ALM2402-Q1_15 TI1 | Alldatasheet

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Technical content

TA(/c71C) Allowable Power Dissipation (W) -40 -20 0 20 40 60 80 100 120 140 0.5 1.5 2.5 3.5 4.5 VCC VCC_OUT VCC GND IN1+ IN1- OUT1 OTF1 VCC_ O1 ALM2402OP AMP Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community ALM2402-Q1 SLOS912D –FEBRUARY 2015–REVISED JULY 2015 ALM2402-Q1DualOp-ampwithHighCurrentOutput

1 Features 3 Description

The ALM2402-Q1 is a dual high voltage, high current 1• High Output Current Drive: 400 mA Continuous op-amp with protection features that are optimal for(Per Channel) driving low impedances and/or high ESR capacitive– Op-amp With Discrete Power Boost Buffer loads. ALM2402-Q1 operates with single or split Replacement power supplies from 5.0 V to 16 V and can output up to 400 mA DC.• Wide Supply Range for Both Supplies (up to 16 V)

  • Over Temperature Shutdown Each op-amp includes over-temperature flag/shut- down. It also includes separate supply pins for each• Current Limit output stage that allow the user to apply a lower• Shutdown Pin for Low Iq Applications voltage on the output to limit the Voh and henceforth• Stable with Large Capacitive Loads (up to 3 µF) the on-chip power dissipation.
  • Zero Crossover Distortion The ALM2402 is packaged in a 12 pin leadless DRR• Qualified for Automotive Applications package and 14 pin leaded HTSSOP (preview). Both include a thermally conductive power pad that• AEC-Q100 Qualified With the Following Results: facilitates heat sinking. The very low thermal– Device Temperature Grade 1: –40°C to 125°C impedance of these packages enable optimal currentAmbient Operating Temperature Range drive with minimal die temperature increase.– Device HBM Classification Level H2 (DRR) Providing customers with the ability to drive high currents in harsh temperature conditions. Maximum– Device CDM Classification Level C5 (DRR) power dissipation can be determined in the figure• Low Offset Voltage: 1 mV (typ) below.• Internal RF/EMI Filter
  • Available in 3.00 mm x 3.00 mm 12 Pin WSON Device Information(1) (DRR) With Thermal Pad PART NUMBER PACKAGE BODY SIZE (NOM) SON (12) 3.00 mm x 3.00 mm ALM2402-Q12 Applications HTSSOP (14) 5.00 mm x 4.40 mm
  • Large Capacitive Loads (1) For all available packages, see the orderable addendum at the end of the data sheet.– Cable Shields – Reference Buffers – Power-FET/IGBT Gates – Super Caps
  • Tracking LDO
  • Inductive Loads – Resolvers – Bipolar DC & Servo Motors – Solenoids & Valves

4 Simplified Schematic

Maximum Power Dissipation vs Temperature An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLOS912D –FEBRUARY 2015–REVISED JULY 2015 www.ti.com Table of Contents

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (June 2015) to Revision D Page Changes from Revision B (May 2015) to Revision C Page Changes from Revision A (April 2015) to Revision B Page Changes from Original (February 2015) to Revision A Page

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Product Folder Links: ALM2402-Q1

OTF/SH_DN IN2+ IN2- GND GND OUT1 VCC_O1 VCC VCC_O2 OUT2 HTSSOP Exposed Thermal Pad IN1- IN1+ OTF/SH_DN IN2+ IN2- GND GND OUT1 VCC_O1 VCC VCC_O2 OUT2 NC NC ALM2402-Q1 www.ti.com SLOS912D –FEBRUARY 2015–REVISED JULY 2015

6 Pin Configuration and Functions

It is recommended to connect the Exposed Pad to ground for best thermal performance. Must not be connected to any other pin than ground. However, it can be left floating. Pin Functions PIN DDR PWP I/O DESCRIPTION NAME NO. NO. IN(X)+ 2, 4 2, 4 Input non-inverting op amp input terminal IN(X)- 1, 5 1, 5 Input inverting op amp input terminal OUT(X) 11, 7 13, 9 Output Op amp output OTF/SH_DN 3 3 Input/output Over temperature flag and Shutdown (see Table 1 for truth table) VCC_O(X) 8, 10 10, 12 Input Output stage supply pin VCC 9 11 Input Gain stage supply pin Ground pin (Both ground pins must be used and connectedGND 6, 12 14 Input together on board) NC N/A 7, 8 N/A No Internal Connection (do no connect) Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: ALM2402-Q1

SLOS912D –FEBRUARY 2015–REVISED JULY 2015 www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings(1)

at 25°C free-air temperature (unless otherwise noted) MIN MAX UNIT VCC Supply Voltage -0.3 18 V VCC_(OX) Output supply voltage(2) -0.3 18 V VOUT(X) Opamp voltage(2) -0.3 18 V VIN(X) Positive and negative input to GND voltage (2) -0.3 18 V IOTF Over Temperature Flag pin maximum Current 20 mA VOTF Over Temperature Flag pin maximum Voltage 0 7 V ISC Continuous output short current per opamp Internally mA Limited Figure 6 TA Operating free-air temperature range –40 125 °C TJ Operating virtual junction temperature(3) -40 150 °C Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the GND/substrate terminal, unless otherwise noted. (3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.

7.2 Thermal Information

THERMAL METRIC(1) DRR (SON) PWP (HTSSOP) UNIT

12 Pins 14 Pins

θJA Junction-to-ambient thermal resistance 39.2 46.5 °C/W θJCtop Junction-to-case (top) thermal resistance 34.5 33.0 °C/W θJB Junction-to-board thermal resistance 15.0 27.6 °C/W ψJT Junction-to-top characterization parameter 0.3 1.5 °C/W ψJB Junction-to-board characterization parameter 15.2 27.4 °C/W θJCbot Junction-to-case (bottom) thermal resistance 4.2 2.2 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.3 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge DRR ±750 VCharged-device model (CDM), per JEDEC specification JESD22- C101(2) PWP ±250 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

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Product Folder Links: ALM2402-Q1

www.ti.com SLOS912D –FEBRUARY 2015–REVISED JULY 2015

7.4 Recommended Operating Conditions

TA= 25°C MIN MAX UNIT TJ Junction Temperature -40 150 TA Ambient Temperature -40 125 Continuous output current (sourcing) 400 IOUT (1) mA Continuous output current (sinking) 400 VIH_OTF OTF input high voltage (Opamp "On" or full operation state) 1.0 VIL_OTF OTF input low voltage (Opamp "Off" or shutdown state) 0.35 VIN(X) Positive and negative input to GND voltage 0 7 V VOTF Over Temperature Flag pin maximum Voltage 2 5 VCC Input Vcc 4.5 16 VCC_O(X) Output Vcc 3 16 (1) Current Limit must taken into consideration when choosing maximum output current

7.5 Electrical Characteristics

VOTF = 5 V, VCC = VCC_O1 = VCC_O2 = 5 V and 12 V; TA = –40°C to 125°C; Typical Values at TA = 25°C, unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIO Input Offset Voltage (1) VICM = Vcc/2, RL = 10 kΩ 1 15 mV IIB Input Bias Current (1) VICM = Vcc/2 1.5 100 nA IIOS Input Offset Current (1) VICM = Vcc/2 30 nA Input Common Mode Range (1) VCC = 5.0 0.2 Vcc-1.2 V VICM VCC = 12.0 V 0.2 7 Total Supply Current (both IO = 0 A 5 15 mA ICC amplifiers)(1) VOTF = 0V 0.5(2) Positive Output Swing VCC = VCC_O(X) = 5.0 V; VICM = Vcc/2; ISINK = 200 mA 4.7 4.87 V VID = 100 mV ISINK = 100 mA 4.85 4.94 Vo Negative Output Swing VCC = VCC_O(X) = 5.0 V; VICM = Vcc/2; ISOURCE = 200 mA 200 425 mV VID = 100 mV ISOURCE = 100 mA 100 200 Over Temp. Fault and 157 165 175 °COTF Shutdown(3) VOL_OTF Over Temp. Fault low voltage Rpullup = 2.5 kΩ, Vpullup = 5.0 V 450 mV Short to Supply Limit (low-side 550 mA limit)(4) ILIMIT Short to Ground Limit (high-side 750 limit)(1)(4) PSRR Power Supply Rejection Ratio(1) VCC = 5.0 V to 12 V, RL = 10 kΩ, VICM = Vcc/2, VO = Vcc/2 65 90 dB Common Mode Rejection 45 90CMRR VICM = VICM(min) to VICM(max), RL = 10 kΩ, VO = Vcc/2 dBRatio(1) AVD DC Voltage Gain(1) RL = 10 kΩ, VICM = Vcc/2, VO = 0.3 V to Vcc-1.5 70 90 dB (1) Tested and verified in closed loop negative feedback configuration. (2) Verified by design. (3) Please see refer to Absolute Maximum Ratings table for maximum junction temperature recommendations. (4) This is the static current limit. It can be temporarily higher in applications due to internal propagation delay.

7.6 AC Characteristics

TJ= –40°C to 125°C; Typical Values at TA = TJ = 25°C; VCC = VCC_O1 = VCC_O2 = 5.0 V and 12 V; VICM=VCC/2 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GBW Gain Bandwidth CL=15 pF RL=10 kΩ 600 KHz PM Phase Margin CL=200 nF RL= 50 Ω 50 ° GM Gain Margin CL=200 nF RL= 50 Ω 17 dB SR Slew Rate G = +1; CL=50 pF; 3 V step 0.17 V/us AV = 2 V/V, RL = 100 Ω, Vo = 8 Vpp, Vcc = 12 -80 dBTHD + N Total Harmonic Distortion + Noise V, F = 1 kHz, VICM = Vcc/2 en Input Voltage Noise Density Vcc = 5 V, F = 1kHz, VICM = Vcc/2 110 nV/√HZ Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: ALM2402-Q1

7.7 Typical Characteristics

Figure 1. VOH at VCC = 5 V Figure 2. VOL at VCC = 5 V Figure 3. VOH at VCC = 3.3 V Figure 4. VOL at VCC = 3.3 V Figure 5. Short to Supply Current Limit vs. Temperature Figure 6. Short to Groung Current Limit vs. Temperature

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Figure 13. ICC vs. Temperature Figure 14. Input Bias Current vs. Temperature Figure 15. Slew Rate Figure 16. Slew Rate vs. Temperature Figure 17. THD + Noise (Vcc = 12 V) Figure 18. THD + Noise (Vcc = 5 V)

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8 Detailed Description

8.1 Overview

the PCB and on to wires that are susceptible to faults from the outside world. package with its thermal pad and low θJA also allows users to deliver high currents to loads.

8.2 Functional Block Diagram

Figure 23. Functional Block Diagram

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www.ti.com SLOS912D –FEBRUARY 2015–REVISED JULY 2015

8.3 Feature Description

8.3.1 OTF/SH_DN

The OTF/SH_DN pin is a bidirectional pin that will allow the user to put both opamps in to a low Iq state (< 500 µA) when forced low or below VIL_OTF. Due to this pin being bidirectional and it's Enable/Disable functionality, it must be pulled high or above VIH_OTF through a pull-up resistor in order for the opamp to function properly or within the specifications, see Electrical Characteristics. When the junction temperature of ALM2402Q1 crosses the limits specified in Electrical Characteristics, the OTF/SH_DN pin will go low to alert the application that the both output have turned off due to an over temperature event. Also, the OTF pin will go low if VCC_O1 and VCC_O2 are 0 V. When OTF/SH_DN is pulled low and the opamps are shutdown, the opamps will be in open-loop even when there is negative feedback applied. This is due to the loss of open loop gain in the opamps when the biasing is disabled. Please see Open Loop and Closed Loop for more detail on open and close loop considerations.

8.3.2 Supply Voltage

ALM2402Q1 uses three power rails. VCC powers the opamp signal path (OTA) and protection circuitry and VCC_O1 and VCC_O2 power the output high side driver. Each supply can operate at separate voltages levels (higher or lower). The min and max values listed in Electrical Characteristics table are voltages that will enable ALM2402Q1 to properly function at or near the specification listed in Electrical Characteristics table. The specifications listed in this table are verified by design for 5 V and 12 V.

8.3.3 Current Limit and Short Circuit Protection

Each opamp in ALM2402Q1 has seperate internal current limiting for the PMOS (high-side) and NMOS (low- side) output transistors. If the output is shorted to ground then the PMOS (high-side) current limit is activated and will limit the current to 750 mA nominally (see Electrical Characteristics) or to values shown in Figure 6 over temperature. If the output is shorted to supply then the NMOS (low-side) current limit is activated and will limit the current to 550 mA nominally (see Electrical Characteristics) or to values shown in Figure 5 over temperature. The current limit value decreases with increasing temperature due to the temperature coefficient of a base-emitter junction voltage. Similarly, the current limit value increases at low temperatures. A programmable current limit for short to ground scenarios can be achieved by adding resistance between VCC_O(X) and the supply (or battery). When current is limited, the safe limits for the die temperature (see Recommended Operating Conditions and Absolute Maximum Ratings) must be taken in to account. With too much power dissipation, the die temperature can surpass the thermal shutdown limits and the opamp will shutdown and reactivate once the die has fallen below thermal limits. However, it is not recommended to continuously operate the device in thermal hysteresis for long periods of time (see Absolute Maximum Ratings).

8.3.4 Input Common Mode Range and Overvoltage Clamps

ALM2402Q1's input common mode range is between 0.2 V and VCC-1.2 V (see Electrical Characteristics). Staying withing this range will allow the opamps to perform and operate within the specification listed in Electrical Characteristics. Operating beyond these limits can cause distortion and non-linearities. In order for the inputs to tolerate high voltages in the event of a short to supply, zener diodes have been added (see Figure 24). The current into this zener is limited via internal resistors. When operating near or above the zener voltage (7 V), the additional voltage gain error caused by the mismatch in internal resistors must be taken in to account. In unity gain, the opamp will force both gate voltages to be equal to the zener voltage on the positive input pin and ideally both zeners will sink the same amount of current and force the output voltage to be equal to Vin. In reality, RN and RP and VZ between both zener diodes do not perfectly match and have some % difference between their values. This leads to the output being Vo = Vin × (ΔR + ΔVZ) . Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: ALM2402-Q1

Figure 24. Schematic Including Input Clamps

8.3.5 Thermal Shutdown

If the die temperature exceeds safe limits, all outputs will be disabled, and the OTF/SH_DN pin will be driven low. be released after operation has resumed. thermal hysteresis for long periods of time (see Recommended Operating Conditions).

8.3.6 Output Stage

swing close to the rails; refer to the graphs in Typical Characteristics section. and the reverse diodes are active.

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8.3.7 EMI Susceptibility and Input Filtering

ALM2402Q1 device incorporates an internal input low-pass filter that reduces the amplifiers response to EMI. Both common-mode and differential mode filtering are provided by this filter. of Operational Amplifiers (SBOA128), available for download from www.ti.com.

8.4 Device Functional Modes

8.4.1 Open Loop and Closed Loop

8.4.2 Shutdown

information on OTF/SH_DN pin. Table 1. Shutdown Truth Table

9 Applications and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

applications. As it is an op amp, there are many general design consideration that must taken into account. ALM2402Q1 being used in a motor drive application.

9.1.1 Capacitive Load and Stability

the amplifier at higher voltage gains. Figure 25. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. Figure 25. Capacitive Load Drive MΩ and RL = 100 Ω. Displaying the ALM2402Q1's good stability performance with big capacitive loads. Figure 26. Output Pulse Response (CL = 2.2 µF and RL = Figure 27. Output Pulse Response (CL = 2.2 µF and RL =

10 MΩ) 100 Ω)

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9.2 Typical Application

Figure 28. ALM2402Q1 in Resolver Application vector position read by the resolver to digital converter chip. increase the life of the end product. ALM2402Q1 offers a solution for, see (SLVA696), which is available for download from www.ti.com.

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters. Table 2. Design Parameters

9.2.2 Detailed Design Procedure

  • Resolver Excitation Input Impedance or Resistance and Inductance: ZO= 50 + j188; (R = 50 Ω and L = 3 mH)
  • Resolver Transformation Ration (VEXC/VSINCOS): 0.5 V/V at 10 kHz
  • Package and θJA : DRR, 39.2°C/W
  • Opamp Maximum Junction Temperature: 150ºC
  • Opamp Bandwidth: 600 kHz

9.2.2.1 Resolver Excitation Input (Opamp Output)

desired frequency must be taken in to account.

9.2.2.1.1 Excitation Voltage

enough headroom to measure the secondary side outputs (~3 Vpp).

9.2.2.1.2 Excitation Frequency

kHz to create negligible closed loop gain error.

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9.2.2.1.3 Excitation Impedance

frequency or phase angle. This calculation is a trivial task. Figure 29. Excitation Coil Implementation Figure 29, many times designers will add a resistor in series with a capacitor to eliminate crossover distortion. is rarely needed. This can be seen in the waveforms shown in the Typical Characteristics section. present for many typical CEMC values.

D

3 V 60 mAP 12 V 5 mA 12 V 480 mW

/c230 /c246/c61 /c180 /c43 /c45 /c180 /c61 /c231 /c247 /c232 /c248 /c40 /c41D CC CC CCO(X) OUT OUTP V I V V (RMS) I (RMS)/c61 /c180 /c43 /c45 /c180 /c40 /c41D SS SSO LP P P P/c61 /c43 /c45 Input Supply Power Output Supply Power Load Power /c40 /c41COS R PPV T V sin 2π cos(θ) ft/c61 /c180 /c180 /c180 /c40 /c41SIN R PPV T V sin 2π sin(θ) ft/c61 /c180 /c180 /c180 /c40 /c41EXC PPV V sin 2π ft/c61 /c180 ALM2402-Q1 SLOS912D –FEBRUARY 2015–REVISED JULY 2015 www.ti.com

9.2.2.2 Resolver Output

As mentioned in the Excitation Frequency section, the excitation signal is similar to a sampling pulse in ADCs, with the real information being in the envelope created by the rotor. The equations below show the behavior of the sin and cos outputs. Whereby the excitation signal is attenuated and enveloped by the voltage created from the electromagnetic response of the rotating rotor. The resolver analog output to digital converter will filter out the excitation signal and process the sine and cosine angles produced by the rotor. Hence, signal integrity or the sine and cosine envelope is most important in resolver design and some trade-offs in signal integrity of the excitation signal can be made for cost or convenience. Many times users can use a square wave or sawtooth signal to accomplish excitation, as opposed to a sine wave. (2) (3) (4)

9.2.2.3 Power Dissipation and Thermal Reliability

Very critical aspects to many industrial and automotive applications are operating temperature and power dissipation. Resolvers are typically chosen over other position feedback techniques due to their sustainability and accuracy in harsh conditions and very high temperatures. Along with the resolver, the electronics used in this system must be able to withstand these conditions. ALM2402Q1 is Q100 qualified and is able to operate at temperatures up to 125°C. To ensure that this device can withstand these temperatures, the internal power dissipation must be determined. The total power dissipation from ALM2402Q1 in this application is the sum of the power from the input supply and output supplies. (5) As shown in the equation below. PSS is a function of the internal supply and operating current of both op amps (ICC). With this op amp being CMOS, the ICC will not increase proportionally to the load like a BJT based design. It will stay close to the average value listed in Electrical Characteristics. For more information on this and calculating and measuring power dissipation with complex loads, please refer to (SBOA022), available for download from www.ti.com (6) (7) As shown inFigure 30, the load current will flow out of one op amp, through the load and in to the other. Each opamp shares the same load at 180° phase difference. The PMOS and NMOS output transistors are resistive when driven near supply and ground. Operating the output voltage at a high percentage of the supply voltage will greatly limit the chip power dissipation. The Typical Characteristics section gives more information on the expected voltage drop, that can be used to determine the limits of VOUT.

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Product Folder Links: ALM2402-Q1

Figure 30. ALM2402Q1 Current Flow temperature case must be determined. This can be determined by Equation 9 below or from Figure 31. to less than 150°C. Please see Absolute Maximum Ratings table for further detail. Figure 31. Maximum Power Dissipation vs Temperature (DRR)

9.2.2.3.1 Improving Package Thermal Performance

www.ti.com/thermal for a general guidance on improving device thermal performance.

9.2.3 Application Curves

Below is test data with ALM2402Q1 exciting TE Connectivity (V23401-D1001-B102) Hollow Shaft Resolver. Table 3. Waveform Legend Figure 33. Resolver Excitation VEXC ≈ 6 Vpp at 10 kHzFigure 32. Resolver Excitation VEXC ≈ 6 Vpp 10 kHz Figure 34. Resolver Excitation VEXC ≈ 4 Vpp at 20 kHz

10 Power Supply Recommendations

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11 Layout

11.1 Layout Guidelines

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supply applications.
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to Circuit Board Layout Techniques, (SLOA089).
  • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.

11.2 Layout Example

www.ti.com/thermal for a general guidance on improving device thermal performance. Figure 35. ALM2402Q1 Layout Example

SLOS912D –FEBRUARY 2015–REVISED JULY 2015 www.ti.com

12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.2 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: ALM2402-Q1

www.ti.com 19-Jul-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples ALM2402QDRRRQ1 ACTIVE SON DRR 12 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ALM24Q ALM2402QPWPRQ1 ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 125 ALM24Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 19-Jul-2015 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ALM2402QDRRRQ1 SON DRR 12 3000 367.0 367.0 35.0 ALM2402QPWPRQ1 HTSSOP PWP 14 2000 367.0 367.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 18-Jul-2015 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C A 3.1 2.9 B 3.1 2.9 12X 0.4 0.2 1.7±0.1 2.5 8X 0.5 12X 0.3 0.2

0.8 MAX

0.05 0.00 2.5±0.1 (0.2) TYP WSON - 0.8 mm max heightDRR0012A PLASTIC SMALL OUTLINE - NO LEAD 4221617/A 09/2014 PIN 1 INDEX AREA 0.08 SEATING PLANE 6 7 (OPTIONAL) PIN 1 ID

0.1 C A B

0.05 THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

12X (0.5) 12X (0.25) 10X (0.5) (1.7) (2.5) (1) (2.9) (0.6) ( ) VIA TYP 0.2 WSON - 0.8 mm max heightDRR0012A PLASTIC SMALL OUTLINE - NO LEAD 4221617/A 09/2014 SYMM 6 7 SYMM LAND PATTERN EXAMPLE SCALE:20X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK OPENING SOLDER MASK UNDER METAL SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED)

www.ti.com EXAMPLE STENCIL DESIGN (2.9) 12X (0.5) 12X (0.25) 10X (0.5) (1.55) (1.11) (0.66) WSON - 0.8 mm max heightDRR0012A PLASTIC SMALL OUTLINE - NO LEAD 4221617/A 09/2014 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED SOLDER COVERAGE BY AREA SCALE:20X SYMM 6 7

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