ALED1262ZT STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Pin description
- 2 Absolute maximum ratings
- 3 Thermal characteristics
- 4 Electrical characteristics
- 4.1 Switching characteristics
- 5 Device pin functions
- 6 Driver dropout voltage
- 7 Device functional description
- 8 Error detection
- 9 Gradual output delay
- 10 Thermal warning and protection
- 11 Device local dimming function
- 12 Local dimming non-linear step table
- 13 Register descriptions
- 13.1 BDM_conf_1 / Enable_CH_1 register
- 13.2 BDM_conf_2 / Enable_CH_2 register
- 13.3 BDM_status register
- 13.4 Faulty_ch_1 register
- 13.5 Faulty_ch_2 register
- 13.6 PWM_gain_x register
- 13.7 LDD register (LED driver device versioning)
- 13.8 OTP/SAM_conf_1_2 register
- 13.9 OTP/SAM_conf_1 register
- 13.10 OTP/SAM_conf_2 register
- 13.11 OTP/BA_n_SAM_setting register
- 14 I²C bus operations
- 14.1 I²C main concepts
- 15 I²C addressing for the ALED1262ZT
Features
- Designed for automotive applications
- 12 constant current output channels
- 19 V current generator rated voltage
- Output current: from 6 mA to 60 mA
- Current programmable by a single external resistor
- 7-bit PWM local brightness control
- Slow turn-on/off time, gradual output delay and dithered clock for EMI reduction
- Error detection for open LEDs
- Supply voltage: from 5.5 V to 38 V
- Thermal shutdown and overtemperature alert
- Standalone and bus-driven mode
- Custom configuration by OTP with Redundancy and ECC
- 400 kHz fast I²C interface with selectable extended Hamming encoding
- Wired-OR error flag connection
Applications
- Automotive rear lights
- Automotive interior lighting
Description
The ALED1262ZT is a monolithic 12 output LED driver designed for automotive exterior and interior lighting applications. The ALED1262ZT guarantees 19 V output driving capability allowing users to connect several LEDs in series. In the output stage, twelve regulated current sources provide from 6 mA to 60 mA constant current to drive LEDs. The current is programmed by a single external resistor. In the ALED1262ZT, LED open error detection is available. The brightness can be adjusted separately for each channel through a 7-bit grayscale control. A slow turn-on and turn-off time improves the system low noise generation performance. Moreover the gradual output delay reduces the inrush current. To further increase EMI performance, this device implements an internal clock dithering to have a spread spectrum noise reduction. Thermal management is equipped with overtemperature data alert and the output thermal shutdown (170 °C). The I²C high clock frequency, up to 400 kHz, makes the device suitable for high data rate transmissions. The supply voltage range is between
5.5 V and 38 V avoiding any external pre-regulation or additional load dump
protection on the power supply stage. This device can operate in bus-driven mode (BDM) using I²C interface or in standalone mode (SAM) using internal custom configuration by OTP. Maturity status link ALED1262ZT Device summary Order code ALED1262ZT ALED1262ZTTR Packing 62 parts per tube 2500 parts per reel Automotive-grade 12-channel LED driver with open detection, local dimming, bus driven and standalone operations ALED1262ZT Datasheet DS12631 - Rev 4 - February 2019 For further information contact your local STMicroelectronics sales office.
1 Pin description
Figure 1. HTSSOP24 pinout Table 1. Pin description
1 VDDD Digital supply terminal
2 SDA I²C serial data input terminal
3 SCL I²C clock input terminal
4 VDDA Analog supply terminal and internal LDO input
6 R-EXT Terminal for external resistor for constant current programming
7 GND Ground terminal
8 FLG Fault flag: open-drain PMOS output for wired-OR connection
11 OTP1/2 Digital input for internal OTP register selection
12 CS Chip-select and power supply (15 V) for OTP burning
- The device exposed pad must be connected to GND, moreover it should be soldered directly to a PCB copper area to
maximize thermal dissipation.
2 Absolute maximum ratings
rating conditions for extended periods may affect device reliability. Table 2. Absolute maximum ratings
- If V DDD is not plugged AMR must be decreased to 3.3 V.
3 Thermal characteristics
Table 3. Thermal characteristics
- The exposed pad must be attached to a metal land electrically connected to ground. To get the thermal benefits it should be
soldered directly to a PCB copper area.
- Jedec test conditions on 2S2P board (4 layers).
4 Electrical characteristics
Table 4. Electrical characteristics (VDDA = 12 V, VDDD = 5 V, Tj = -40 to 125 °C, unless otherwise specified)
Electrical characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit ∆IOL1 Output current precision channel to channel (all outputs ON) (1) VOUT = 0.65 V; REXT = 49.9 kΩ; Io ≈ 6 mA; Tj ≤ 90 °C; (outage) ±15 ∆IOL2 VOUT = 1.05 V; REXT = 24.9 kΩ; IO ≈ 12 mA; (outage) ±10 ∆IOL3 VOUT = 1.35 V; REXT = 4.99 kΩ; IO ≈ 60 mA (outage) ±3 ∆IOL2a Output current precision device to device (all outputs ON) (1) VOUT = 1.35 V; REXT = 4.99 KΩ; IO ≈ 60 mA; (outage) %/dVOUT Output current vs output voltage regulation VOUT from 1.35 V to 3.35 V; REXT = 4.99 kΩ; IO ≈ 60 mA 0.1 |%/V| REXT External current set-up resistance 4.99 49.9 kΩ IDDD VDDD supply current no dimming REXT = 4.99 kΩ; No I²C data transfer OUT0 to 11 = ON (outage) 0.7 1.0 mA IDDA(OFF) VDDA supply current (OFF) GPWM = GND REXT = 4.99 kΩ; OUT0 to 11 = OFF 0.3 0.6 IDDA(ON1) VDDA supply current (ON) no dimming REXT = 24.9 kΩ; IO ≈ 12 mA; OUT0 to 11 = ON (outage) 2 2.5 IDDA(ON2) VDDA supply current (ON) no dimming REXT = 4.99 kΩ; IO ≈ 60 mA OUT0 to 11 = ON (outage) 4 5.5 IDDA(REC) VDDA supply current REXT = 4.99 kΩ; SAM recovery condition 1.2 Tflg Thermal flag 140 Tflg-hy Thermal flag hysteresis 10 Tsd Thermal shutdown 170 Tsd-hy Thermal shutdown hysteresis 15 1. Tested with just one output loaded. 2. ((I On – IOavg1-12)/ IOavg1-12) x 100 ∆ % / V = I O n @ V O U T n = 3.35 V − I O n @ V O U T n = 1.35 V I O n @ V O U T n = 1.35 V ∙ 100 3.35 − 1.35 ALED1262ZT
4.1 Switching characteristics
Table 5. Switching characteristics (VDDA = 12 V, VDDD = 5 V, Tj = 25 °C, unless otherwise specified)
- Using prescaler bit (Faulty_ch_1 register bit[7]) local dimming frequency value can be reduced by half (typ. = 110 Hz)
Figure 2. I²C timing definition
Figure 3. Simplified internal block diagram
5 Device pin functions
A detailed description about each pin function as follows: SDA – I²C is the bidirectional data line, it must be pulled up with an external resistor connected to MCU power supply. SCL – clock line, coming from MCU I²C bus, must be pulled up with an external resistor connected to MCU power supply. CS – chip-select pin used exclusively to address each device during one time register programming (OTP). This procedure is carried out at the end of customer production line to set the device default configuration. CS pin has an internal pull-down resistor of about 160 kΩ. This pin is also used to supply 15 V during factory programming to set internal OTP registers. Note: The CS pin cannot be connected to GND, neither directly nor through passive components. The only allowed polarization is floating or positive voltage (up to 15 V). VDDD – digital power supply coming from MCU section together with I²C bus. When VDDD is below a threshold of power supply VDDD only (VDDA not connected), the device I²C bus is active and internal registers can be programmed, the only restriction is related to VDDA impedance to GND that must be higher than 4.7 kΩ. In case of a lower impedance, the device digital interface starts on the first VDDA voltage rising edge. The allowed slew rate for this pin is below 0.17 V/µs (0 to 5 V; 30 µs ≤ trise). Note: Fast VDDD edges can cause internal regulator overvoltage spikes that may provoke electrical stresses in the device. VDDA – analog power supply coming from car body system. This is the main supply voltage for the driver and it can be dimmed to change LED brightness (100 or 200 Hz at 10% as minimum duty cycle, VDDA = 0 to 12 V). Allowed slew rates for this pin are the following: from 0.4 to 1.2 V/µs (0 to 12 V; 10 µs ≤ trise/fall ≤ 30 µs) in normal operation, from 6.8 to 8.4 V/ms for load dump conditions. Note: If the I²C is programmed to only provide the digital power supply V DDD (VDDA not connected), a subsequent VDDA plug or unplug with edges faster than those allowed (trise/fall < 10 µs) may induce the internal register reset. LDO3 – internal regulator output pin to be connected to an external capacitor (minimum value 1 µF). The output voltage is about 3.3 V ±3% and it is used as an external reference voltage and the device internal supply. The capacitor connected on this pin is also used as “tank capacitor” to maintain internal volatile register data during VDDA pulsed dimming function (if required). REXT – this resistor is used to program the regulated output current. The relationship between REXT value and the output current is given by the following equation: I O x = V BG R E X T ∙ K The current gain factor "K" is about 240. The VBG voltage is normally at 1.233 V used to get the reference current trough R-EXT pin; this current is mirrored by a precise circuit to generate the reference for the driver stage. On R- EXT pin, any filter capacitor can be connected. GND – ground pin, it must be connected to a package exposed pad. Exposed pad should be soldered directly to the PCB to see the thermal benefits (see the device thermal management section). GPWM – a variable duty cycle square wave on this pin allows all channels brightness to be fixed simultaneously (PWM global dimming). If this pin is not used, it must be connected to LDO3. GPWM control requires a square wave with a HIGH level longer than 20 µs caused by a 15 µs delay needed to power on all internal blocks before the channel activation. With 20 µs HIGH level, the real output activation is around 5 µs. The maximum allowed slew-rate on this pin is 1.9 V/µs. OUTx – the ALED1262ZT has 12 current regulated low-side outputs. The output stage is a sinker, which is able to stand till 19 V, this is to use more than one LED series connected. The internal current generator turn-on and turn- off time has been slowed down to decrease as much as possible EMI noise. FLG – this is the fault flag I/O pin used in wired-OR among those devices sharing the same application. In wired- OR connection, all FLG pins are connected together to a single pull-down resistor, this signal can also be read by an MCU to detect any fault condition. If the device receives an external error status, it reacts according to the internal configuration (see Section 13.1 BDM_conf_1 / Enable_CH_1 register, Section 13.2 BDM_conf_2 / ALED1262ZT Device pin functions DS12631 - Rev 4 page 10/69
need to be managed externally according to the used voltage level (i.e., level shifter).
- VDDD is plugged: an internal high-side transistor is connected to the VDDD (5 V). In this case the high level on FLG pin/bus is forced to VDDD and it is compliant to fault information coming directly from the MCU as well.
- VDDD is not plugged: a high-side transistor is connected to the internal regulated voltage 3V3 (LDO3). In this case there is not any external interrupt coming from MCU to be managed (5 V VDDD is not available). The voltage level is among chips connected to the same power domain. The power line selection for the FLG analog MUX is a matter of VDDD comparator used to detect the VDDD plug- in.
Figure 4. FLG pin connection
- Faulty channel, dimming by GPWM pin: FLG blinks according to GPWM external square wave and error detection conditions.
- Faulty channel, dimming by PWM register (BDM): FLG is constantly high according to the error detection conditions. PG – this pin is the LED driver Power Good, it must be connected by a proper resistor divider to the main voltage coming from car body system (VDDA) or to LED power supply. Starting from the internal threshold overcoming (above 1.95 V), the ALED1262ZT has a valid detection available in less than 70 µs. The maximum allowed slew- rate on this pin is 1.9 V/µs. OTP1/2 – in standalone mode, it is possible to select two possible output configurations. Each configuration is stored in non-volatile cells (shadowed by SAM_conf_* registers). This pin can be also connected to a switched voltage coming from car body system (VDDA3) by a resistor divider. When OTP1/2 is at logic level LOW, output configurations are related to SAM_conf_1 register. Conversely, when OTP1/2 is at logic level HIGH, output configurations are related to SAM_conf_2 register (see register description for more details). The maximum allowed slew-rate on this pin is 1.9 V/µs. ALED1262ZT Device pin functions DS12631 - Rev 4 page 11/69
6 Driver dropout voltage
generator must be guaranteed. Figure 5. Channel dropout voltage vs output current (Tj = 25 °C), Table 6. Minimum dropout voltage for certain Figure 5. Channel dropout voltage vs output current (Tj = 25 °C) Table 6. Minimum dropout voltage for certain current values (Tj = 25 °C; worst case simulated at target
Table 7. Minimum dropout voltage at 60 mA (worst case simulated at target minus 3%) Table 8. Typical output current vs REXT value
7 Device functional description
not used (to LDO3) and output channels connected to external LED cathodes. Figure 6. ALED1262ZT typical connection scheme necessary, as external reference voltage. in case of bus accidental disconnection (see the following diagram).
Figure 7. The ALED1262ZT full connection to set properly the device and to release the I²C bus. (CS – see OTP programming section).
- Non-volatile – BA_n_SAM_setting register, it is programmed during one time programming phase, using chip-select pin (CS – see OTP programming section).
- Volatile – BDM_conf 1 and 2, BDM_status, Faulty_ch 1 and 2, PWM_gain registers. BA_n_SAM_setting register sets the device I²C address on 31 possible selections (all zeros is valid only for fresh devices) and the communication protection mode; BDM_conf 1 and 2 set the output ON/OFF status; BDM_conf 1 also contains information about the error detection device behavior, diagnostic function and local dimming activation; BDM_status contains information about the diagnostic results, thermal protection and general driver status; Faulty_ch 1 and 2 contain indications about branches in which a fault is detected; PWM_gain represents the dimming value for each of 12 outputs (for more details see register description paragraph). Through bit BDM_Flag of the BDM_conf_1 register, we can force the device from SAM to BDM according to the following table:
Table 9. Operative status
Figure 8. Power supply internal signal behavior
8 Error detection
on time is less than 15 µs (delay mask + detection delay), no output detection can be available. power-ON in normal regulation. depends on number of active channels and junction temperature) an internal comparator warns the REXT failure. Table 10. Type of fault and device behavior
- If PG is not asserted, FLG and/or load diagnosis are ignored.
9 Gradual output delay
Table 11. Gradual output delay dimming condition (BDM) only.
10 Thermal warning and protection
The device has a thermal control logic providing a digital flag status (warning) when the internal temperature exceeds 140 °C. If thermal alert is asserted, error data is uploaded into BDM_status register and this error notification is ready to stream through I²C bus. If temperature increases over 170 °C a thermal shutdown protects the device (all 12 channels OFF) and external fault flag (FLG) drives high. ALED1262ZT Thermal warning and protection DS12631 - Rev 4 page 20/69
11 Device local dimming function
local dimming register PWM_gain_x. Figure 9. Device local dimming function logic of the brightness register to a 7-bit counter. The counter’s clock source is provided by 3.3 MHz internal oscillator. Brightness register default configuration is all “0” (0x00) this means minimum LED brightness. The schematic below summarizes this functionality. Figure 10. Channel dimming feature
The ALED1262ZT implements 128 non-linear dimming steps to adequate LED brightness change to human eye light perception, giving in this way the impression of brightness linear variation. The exponential law used to calculate the dimming steps is the following: to n i = P WM _ p erio d ∙ α N – i Where toni is the LED ON-time during step number "i", PWM_period = 5 ms or 10 ms (max. values), this means that minimum dimming frequency can be 200 Hz or 100 Hz according to Faulty_ch_1 register bit[7] (see register description), N = 127 (7-bit resolution), 0 ≤ i ≤ 127, α ≈ 0.9471. ALED1262ZT Device local dimming function DS12631 - Rev 4 page 22/69
12 Local dimming non-linear step table
different respect to tabulated numbers. Values are referred to minimum high range frequency: fPWM = 200 Hz). Table 12. Local dimming step
Figure 11. Local dimming duty cycle vs dimming steps
13 Register descriptions
Table 13. Embedded register list and direct address table
18 LDD (LED driver device) R Versioning: driver ID and revision ID -
(standalone mode out config.
- Direct address can be used with 0x81 command (see the command table). Please note that register address must be
these intervals, all other addresses are forbidden.
- Accessing read only registers (BDM_status and Faulty_ch_2) in write mode with direct address command could affect the register content.
- Safer way to address registers is using the specific commands reported in Table 29. Command representation and description, they are fully controlled by internal state machine. ALED1262ZT Register descriptions DS12631 - Rev 4 page 25/69
13.1 BDM_conf_1 / Enable_CH_1 register
Table 14. BDM_conf_1 field descriptions the FLG pin is triggered externally, no action is taken. have a residual random low light emission. remaining active channels could have a flicker. enough to toggle the output activation (OFF/ON) or recover the open channels.
- Each time the LED driver passes from BDM to SAM mode, this bit is reset.
dedicated commands, such as ID_FW_BDM, as well as direct register access ID_DR_ACS.
13.2 BDM_conf_2 / Enable_CH_2 register
Table 15. BDM_conf_2 field descriptions
13.3 BDM_status register
Table 16. BDM_status field descriptions active channels could randomly flicker. is reported only after Rext_fault solution. Reset by HW on global_en deassertion. Set on rising PG threshold exceeded. Set on temperature exceeding Tflg. Set on temperature exceeding Tsd. Reset on the register reading.
detected permanently for at least 10 µs. is reported only after Rext_fault solution.
13.4 Faulty_ch_1 register
Table 17. Faulty_ch_1 field descriptions
13.5 Faulty_ch_2 register
Table 18. Faulty_ch_2 field descriptions
13.6 PWM_gain_x register
Table 19. PWM_gain_x field descriptions desired channel behavior whenever I²C transaction falls in the edge between two dimming cycles.
13.7 LDD register (LED driver device versioning)
Table 20. LDD field descriptions
13.8 OTP/SAM_conf_1_2 register
Table 21. OTP / SAM_conf_1_2 field descriptions
13.9 OTP/SAM_conf_1 register
Table 22. OTP / SAM_conf_1 field descriptions
13.10 OTP/SAM_conf_2 register
Table 23. SAM_conf_2 field description
13.11 OTP/BA_n_SAM_setting register
Table 24. OTP / BA_n_SAM_setting field descriptions and/or load diagnosis are ignored. no action is taken on the current regulation. If the FLG pin is triggered externally, no action is taken. could have a residual random low light emission. remaining active channels could have a very light flicker. fixed at 01 so: 01xxxxx) allowing 32 possible slave addresses only. Table 25. Enable_CH[x] register content
- '0' if channel is ON; '1' if channel is OFF
- '0' if channel is OFF; '1' if channel is controlled by PWM_gain_x
Figure 12. LED open circuit diagnosis response table
14 I²C bus operations
application, it can drive communication following the I²C bus protocol (the bus is active 80 µs after VDDD plug). parasitic and/or connected capacity (typ. ≈ 100 ns; see the following charts). Figure 13. Slave SDA falling time vs CBus Rup = 1.8 kΩ, VDDD = 5 V Figure 14. Slave SDA rising time vs CBus Rup = 1.8 kΩ, VDDD = 5 V, -40 < TJ < 125 °C
14.1 I²C main concepts
I²C communication, performed on a two signal basis, is a synchronous half duplex protocol. Signals are conveniently named as SCL (synchronization signal from MASTER to SLAVE) and SDA (data signal which can be either MASTER to SLAVE, or SLAVE to MASTER). The multi-MASTER application configuration, which is a MASTER specific property, is supported by the ALED1262ZT. I²C communication is driven by specific events on the bus:
- START condition - it is a falling edge of SDA while SCL is HIGH level
- Slave addressing - it is the transmission (M→S) of the ID of the slave to be addressed (7-bit)
- Communication direction - it is one bit immediately following the slave ID: 0 for writing (M→S) or 1 for reading (S→M)
- Acknowledge - it is a LOW level on SDA line; driven by either SLAVE or MASTER depending on the communication moment
- Data bit - data are 8-bit per word driven either by MASTER or SLAVE depending on the communication moment
- STOP condition – it is a rising edge of SDA while SCL is HIGH level
- Restart condition - it is a new START condition which happens before a STOP condition: it normally implies a change in the direction of the communication ALED1262ZT I²C main concepts DS12631 - Rev 4 page 37/69
15 I²C addressing for the ALED1262ZT
Since having more than a single ALED1262ZT device is allowed in this application, a method to differentiate each of them has been put in place. Five OTPs (one time programmable) memory cells are dedicated to differentiate LSB bit of the ALED1262ZT address; this leads up to 31 devices valid addresses usable in the final application. When OTP has not been programmed yet to address one specific SLAVE in the application board, an extra signal named CS is used (which is not part of I²C standard). CS pin is a chip select signal (active HIGH), it is internally pulled down by a resistor. Hence the recommended application scheme should connect all the ALED1262ZT devices CS pin to a corresponding output pin in the programmer. When in the end factory line programming, the testing/set-up system has to leave floating CS pin on all the devices except the one meant to be programmed at that specific time, on this specific device, CS must be polarized at 15 V. For ‘fresh device’, the address is “0100000” (0x40 including the writing bit or 0x41 including the reading bit). Once the programming of all devices is over, all CS pins must be left floating (fixed low by internal pull-down), the addressing, by MCU in application, is performed by each programmed address as a traditional I²C bus. ALED1262ZT I²C addressing for the ALED1262ZT DS12631 - Rev 4 page 38/69
16 I²C selectable Hamming (8, 4) encoding
Table 26. Excerpt from table "OTP / BA_n_SAM_setting field descriptions"
Figure 15. Graphic view of encoding Table 27. Datawords and corresponding codewords
Figure 16. Excerpt of communication scheme in application Table 28. Not encoded nibbles and equivalent Hamming bytes
17 Message structure
17.1 Available commands
A set of commands has been implemented to recall the functions made available by I²C communication. following pages where the structure of messages is presented. Table 29. Command representation and description acknowledged, then the first one is not updated. 11] registers write to LED driver. registers write to LED driver (OTP emulation). registers are burnt on OTPs (OTP burn).
- slave address + write bit (as per I²C protocol)
- slave address repeating (slave replies ACK or NACK according to own I²C actual address)
- command ID (according to the table above, a wrong command ID results in a slave NACK)
- read or write sequence as described on the following sections (see write and read operations)
17.2 Pattern symbols
Figure 17. Pattern symbols
17.3 Write operations
- Without parity detection – BDM_conf_1 + BDM_conf_2, registers updated at the end of the second byte – All remaining registers are updated at the end of the byte
- With parity detection – BDM_conf_1 + BDM_conf_2, registers updated at the end of the fourth byte (if correctly received) – All remaining registers are updated at the end of the second byte (if correctly received) ALED1262ZT Pattern symbols DS12631 - Rev 4 page 43/69
17.3.1 BDM configuration register write
Figure 18. Without parity detection (4 bytes) Figure 19. With parity detection (8 bytes)
17.3.2 FAULTY_ch1[7] bit register write (prescaler)
Figure 20. Without parity detection (3 bytes) Figure 21. With parity detection (6 bytes)
17.3.3 PWM_gain_x register write
Figure 22. Without parity detection (14 bytes) Figure 23. With parity detection (28 bytes)
17.3.4 BDM_conf and PWM_gain_x register write
Figure 24. Without parity detection (16 bytes) Figure 25. With parity detection (32 bytes) (dimming enabled or disabled) ignoring PWM counter progression. In case of writing additional bytes beyond those expected by the specific command, extra data are ignored.
17.3.5 Direct write on registers
Figure 26. Without parity detection (16 bytes)
Figure 27. With parity detection (32 bytes) (BDM) and 0x20 ≤ PP+n ≤ 0x23 (SAM). Outside these intervals all other addresses are forbidden. See also the register address table.
17.4 Read operations
17.4.1 Status register
Figure 28. Without parity detection (4 bytes) Figure 29. With parity detection (7 bytes)
17.4.2 Faulty_ch registers
Figure 30. Without parity detection (5 bytes) Figure 31. With parity detection (9 bytes)
17.4.3 PWM_gain_x registers
Figure 32. Without parity detection (15 bytes) Figure 33. With parity detection (29 bytes)
17.4.4 BDM_conf, status, Faulty_ch, PWM_gain_x registers
Figure 34. Without parity detection (20 bytes) Figure 35. With parity detection (39 bytes) In case of reading additional bytes beyond those provided by the specific command, the extra bit is zeroed.
17.4.5 Direct read from registers
Figure 36. Without parity detection
Figure 37. With parity detection position PP+1 and so on. If PP+n position has not the corresponding register location, read data must be ignored. See also the register address table. be ignored. Normal communication is resumed with a stop transition.
18 OTP operations
description for further information. paired cells are ORed, the resulting data is controlled by ECC word and copied into the four registers.
- V DDD to 5 V
- SDA and SCL connected to 100 or 400 kHz I²C bus (W/O or W parity check according to OTP/ BA_n_SAM_setting [bit 7] programmed 0 or 1)
- CS used to address on application board device to be programmed (I²C address is not yet available because itself is to be programmed). CS pin must be supplied at 15 V with current capability ICS > 100 mA.
- GND to power supply and I²C controller ground (general ground connection) To program OTPs, the user needs to address the device; in case of ‘fresh device’, the address is “0100000” (0x40 including the writing bit or 0x41 including the reading bit); and drives HIGH to 15 V the CS pin. In this condition, the user can proceed with the OTP message to program the fuses. In case of several devices on same I²C bus, programming functions must be performed on a single device by time. This means that all others CS pin must be floating (it means LOW by internal pull-down resistor). After the device power supply and 15 V as CS polarization, OTP operation message must be sent by I²C bus master. Three operations are available on OTP cells: EMULATE, BURN and READ. EMULATE and READ are possible at any time without special care. While BURN execution need a special attention because of ECC; the complete full procedure, based on a double zap, must be executed in a single run (meaning using same data configuration) since ECC is computed for the data actually present into non-volatile registers and once stored into OTP, cells cannot be modified any longer. To invoke such operations, see related message structure and commands.
18.1 OTP emulate
from default if the emulation/burning on BA_n_SAM_setting[4:0] bits has been performed sometimes in the past). Emulated bits are reset at their original status after an electrical HW reset that force an OTP load. changes immediately and so the following commands have to use the new set address. Figure 38. Emulate OTP bit without parity detection
Figure 39. Emulate OTP bit with parity detection
18.2 OTP burn
writes permanently the emulated configuration on the device OTP banks. OTP burn command twice without any change in the emulated configuration. ALED1262ZT generates sequentially the burning signals for zapping all the 80 OTP cells. after the latest I²C 'acknowledge' sent by SLAVE. to add a "fake" byte before the Stop, if needed to know the real burning process duration. Figure 40. Burn OTP bit without parity detection Figure 41. Burn OTP bit with parity detection
18.3 OTP read
BA_n_SAM_setting [4:0] as LSB. Figure 42. Read back OTP bit without parity detection Figure 43. Read back OTP bit with parity detection
19 I²C communication examples
19.1 Communication without parity detection
19.1.1 OTP burning with double zap and read back
To emulate as example the address 0100001 the following sequence is needed:
- CS = 15 V
- VDDD = 5 V
- 0x40 0x40 0x20 0x00 0x00 0x00 0x01 Based on the new emulated address (0100001) the burning communication sequence is:
- 0x42 0x42 0x21
- wait > 80ms
- 0x42 0x42 0x21 Switch OFF the supply to be sure about the real burning before read back check using the following pattern:
- 0x42 0x42 0x28 R 0x43 0x07 0x00 0x00 0x00 0x01 (R means the restart condition; in bold the expected read back data, 0x07 is the current LDD value) From now on, the device answers to 0x42 for writing and to 0x43 for reading operations; CS at 18 V for I²C communication is no more needed.
19.1.2 All LEDs with power-ON
To power on all the device output channels, in case of 0100001 I²C address, the following sequence is needed:
- CS = floating
- VDDD = 5 V
- VDDA = 12 V
- VLED according to number of LEDs in series per channel
- 0x42 0x42 0x00 0xA0 0x00 (0xA0 0x00 means: BDM_Flag = 1, detection = recovery, FLG = driven, PWM_En = OFF, channels from 11 to 0 = ON) 19.1.3 110 Hz dimming prescaler bit For prescaler bit setting, 0100001 I²C address, the following sequence is needed:
- CS = floating
- VDDD = 5 V
- 0x42 0x42 0x03 0x80 (0x80 means: prescaler bit = 1)
19.1.4 All LEDs with PWM dimming at 50% (full configuration)
For PWM dimming setting, 0100001 I²C address, the following sequence is needed:
- CS = floating
- VDDD = 5 V
- VDDA = 12 V
- VLED according to number of LEDs per channel
- 0x42 0x42 0x02 0xB0 0x00 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 0xF2 (0xB0 0x00 means: BDM_Flag=1, detection=recovery, FLG=driven, PWM_En=ON, channels from 11 to 0=ON; 0xF2 means dimming step #114) ALED1262ZT I²C communication examples DS12631 - Rev 4 page 53/69
19.1.5 Device status read back
For status read back, 0100001 I²C address, the following sequence is needed:
- CS = floating
- VDDD = 5 V
- 0x42 0x42 0x08 R 0x43 0x?? (R means the restart condition; in bold the read back data)
19.1.6 Device full status read back
For full status read back, 0100001 I²C address, the following sequence is needed:
- CS = floating
- VDDD = 5 V (R means the restart condition; in bold the read back data) To read the status up to faulty channels only it is matter to send a STOP condition after the fifth received byte, as shown in the following sequence:
- CS = floating
- VDDD = 5 V (R means the restart condition; P means the STOP condition; in bold the read back data).
19.1.7 LDD read back (device identifier)
For LDD read back, 0100001 I²C address, the following sequence is needed:
- CS = floating
- VDDD = 5 V
- 0x42 0x42 0x28 R 0x43 0x07 P (R means the restart condition; P means the STOP condition; in bold the read back data; 0x07 is current LDD value)
19.2 Communication with parity detection
19.2.1 All LEDs with power-ON
To power on all the device output channels, in case of 0100001 I²C address, the following sequence is needed:
- CS = floating
- VDDD = 5 V
- VDDA = 12 V
- VLED according to number of LEDs in series per channel without parity detection pattern was:
- 0x42 0x42 0x00 0xA0 0x00 (0xA0 0x00 means: BDM_Flag=1, detection=recovery, FLG = driven, PWM_En = OFF, channels from 11 to 0 = ON) With parity detection, we need to codify all words beyond the first address (0x42): 0x42, the repeated address, with Hamming encoding is 0x55 + 0x27 (see nibbles encoding table); byte 0x00 encoded is 0x00 + 0x00; byte 0xA0 encoded is 0xB4 + 0x00. So full pattern with Hamming (8, 4) is:
- 0x42 0x55 0x27 0x00 0x00 0xB4 0x00 0x00 0x00 This sequence powers on all the device output channels. ALED1262ZT Communication with parity detection DS12631 - Rev 4 page 54/69
20 LED supply voltage
LED supply voltage (VLED) must be chosen by taking into account several parameters:
- The voltage drop across each current generators (V DROP) must be enough to guarantee the current regulation (see dedicated section in the datasheet)
- The maximum LED forward voltage (V F,max)
- The maximum power that can be dissipated by the package under the application ambient conditions
- The accuracy of the supply voltage itself (V LED can vary in a range and the minimum and maximum values must be considered) Therefore the minimum LED supply voltage can be calculated as: V LE D , m in = V D RO P , mi n + V F , m a x The worst case for power dissipation is to consider all channels connected to LEDs at minimum VF and maximum VLED: V D R O P , m a x = V LE D , m ax − V F , m in The LED supply voltage should be higher than VLED,min (to consider any fluctuation of the involved parameters) but not too high in order to keep low the power dissipation: P D = V D D D ∙ I D D D + V D D A . I D D A + ∑ i = 0 11 V D R O P _ m a x _ i ∙ I CHi where VDDA and VDDD are the device voltage supplies, IDDA and IDDD are the device supply currents, VDROP_max_i and ICHi are respectively the maximum voltage drop across the current generator "i" and the channel "i" current. The simplified equation is the following: P D ≅ ∑ i = 0 11 V D R O P _ m a x _ i ∙ I CHi The power dissipation should be kept below the maximum power dissipation, defined as: P D , ma x = T j − T a θ ja where Tj and Ta are respectively the maximum junction and ambient temperature, whereas θja is the junction-to- ambient thermal resistance (Rthj-amb). Junction temperature should be maintained below 150 °C. To summarize, the proper power supply choice must be a trade-off between the correct value assuring the desired LED current and the lowest power dissipation. In multi-type LED applications, there can be a significant variability of the LED forward voltage (e.g. red LEDs have a lower forward voltage than white, green or blue LEDs). In this case, the supply voltage must be chosen so to correctly switch on the LEDs with the highest forward voltage. At the same time, the excess of voltage in the lines with the lowest forward voltage LEDs drops on the current generators, increasing the power dissipation and the loss of efficiency. To avoid these drawbacks, two different approaches are possible: 1. Adding a resistor in series to each low forward voltage LEDs. In this way, the voltage excess drops across the resistor instead of dropping across the current generators. This solution implies a significant reduction of the power dissipated by the chip (lower Tj). However the total power dissipation does not change and a remarkable part of the power is still wasted on the series resistor. This not only affects the efficiency, but also raises the cost of the system due to the need to dissipate the generated heat. 2. Another solution is to split the LED voltage rail: one for high forward voltage LEDs and one for low forward voltage LEDs, which can be derived from the former using a switching regulator. This solution is by far the most advantageous in terms of power dissipation. Voltage rails are tailored to the type of LEDs they drive and the wasted power is significantly reduced as well as the heat produced. ALED1262ZT LED supply voltage DS12631 - Rev 4 page 55/69
21 Higher current requests (outputs in parallel)
When the application requires driving high power LEDs, the current demand could be higher than the current provided by a single channel. In this case a higher current capability can be achieved by connecting together two or more channels (in accordance with the current value, it must be regulated). Normally no stability issues are shown using this output connection but, in any case, a bypass capacitor on driver power supplies (of about 1 µF on VDDA and VDDD) and in particular a bypass capacitor near LED anodes on VLED power supply rail (2.2 µF or higher) are strongly recommend. ALED1262ZT Higher current requests (outputs in parallel) DS12631 - Rev 4 page 56/69
22 PCB layout and external component guidelines
The aim of this paragraph is to provide some recommendations about the design of the application PCB designing. Routing general rules are always valid, however there are some other considerations tailored for this device family focused to reduce as much as possible EMI effects and maintain good signal integrity.
22.1 Signal integrity and EMI radiated/conducted immunity
- The external programming resistor between R-EXT and GND should be connected as close as possible to the device.
- The I²C bus should move unitarily on the board and should be shielded.
- Try to widen the spacing among signal lines as much as routing restrictions allow. Try not to bring traces closer than three times the dielectric height; the distance between the centers of two adjacent traces should be at least four times the trace width.
- Design the transmission line so that the conductor is as close to the ground plane as possible. This technique couples the transmission line tightly to the ground plane and help decouple it from adjacent signals.
- All I²C signals should proceed to the same board direction by a data bus.
- Regarding I²C bus, vias should be avoided, all strips should be traced on a single layer, if it is possible a ground plane has to be provided close to this layer. If it is an inner layer, insert the strips sandwiched between two GND surfaces. Reduce as much as possible the length of connections from the main bus to the device chain (derived traces ≡ stubs). Keep traces as straight as possible (corners should be rounded). Avoid crossing among SCL/SDA strips and power supply lines or fault flag connections (VDDA, VDDD and FLG).
- Filter capacitors (1 µF) must be connected as close as possible to the device on pins: V DDA, VDDD and LDO3. In parallel to each filter capacitor, it’s suggested to add 10 nF compensation for EMC/EMI improvement. The same additional capacitor (10 nF X7R) must be connected in parallel on FLG pull-down resistor. On VDDA line, a serial resistor of about 10 Ω can be also added to constitute an RC low-pass filter to improve the external conducted disturbance immunity. As electromagnetic very noisy environment, to avoid resonant effects on internal digital supply, causing the device internal electrical stress, it’s suggested to add a 10 Ω resistor between the external filter capacitor and VDDD pin. The following figure shows the placement of the 10 Ω supplementary resistors. ALED1262ZT PCB layout and external component guidelines DS12631 - Rev 4 page 57/69
Figure 44. Additional filter connection
22.2 Radiated emission reduction (EMI)
- To decrease the electromagnetic noise during LED power-on/off, the driver output lines should follow the shortest path “VLED power-rail/LED/driver”. Besides, as the system stability, a capacitor should be connected on the LED power supply rail (2.2 µF) as near as possible to LED anodes (the inductive LED power supply rail component should be compensated by the added capacitor, while regarding to a wider PCB, more distributed capacitors have to be placed). Another filter capacitor must be added to each driver power supply pins (VDDD and VDDA) and on linear regulator output (LDO3), see the previous section
- GND connection must be enlarged as much as possible
- I²C connection strips from controller to LED driver have to be as short as possible, and a ground plane should be provided close to bus lines and layer, see the previous section
22.3 Device thermal management
- For a better power dissipation (to decrease the device working temperature) it is necessary for the package exposed pad to be soldered to the board
- To guarantee a better thermal performance at least a 4-layer (e.g. 2S2P) PCB should be used
- The copper area below the package thermal pad should be enlarged as much as possible also outside the package perimeter using internal and copper side layers and/or extending the copper area using the no-pin package sides
- A reasonable number of vias must connect the copper area below the package to all available PCB layers (e.g. 3x4 or 3x5 via array). Smaller and closely spaced vias is the best solution. The best implementation is represented by copper filled vias
- On each inner layer a copper area must be provided for dissipation (the wider the better, at least 4 times or more the package dimensions). A good condition is to have at least a power layer as an entire copper area (e.g. GND layer)
- Traces for pin connection must be enlarged as much as layout constrains allow
- Several devices in power dissipation conditions on the same board must be adequately spaced ALED1262ZT Radiated emission reduction (EMI) DS12631 - Rev 4 page 58/69
22.4 PCB layout example
- C1 and C2 are the V DDD filter capacitors, very important for power supply noise reduction and internal regulator stability (C1 = 10 nF, C2 = 1 µF, X7R type)
- C3 and C4 are the V DDA filter capacitors, very important for power supply noise reduction and internal regulator stability (C3=10 nF, C4=1 µF, X7R type)
- C5 and C6 are the LDO3 filter capacitors, very important for linear regulator stability (C5 = 10 nF, C6 = 1 µF, X7R type)
- C7 is the fault flag (FLG) filter capacitor, very useful for the device noise immunity (C7 = 10 nF, X7R type). R4 is the fault flag pull-down resistor
- R3 is the current programming resistor to be placed as close as possible to R-EXT pin and the device GND connection
- R2 and R1 are the I²C pull-up resistors
- R5 is the low-side resistor divider related to Power Good pin (PG) To be noticed vias near GND terminal for C1, C2, C3, C4 and C7 capacitors for a low ground impedance connection. I²C bus is mainly on a single layer, GND shielded and without crossing with the supply lines.
Figure 45. PCB routing example power supply pin (VDDD) after C1 and C2 to avoid internal resonant effects (EMI conducted immunity section). These resistors are not placed on the following PCB example.
Figure 46. PCB routing example (components and copper side)
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
23.1 HTSSOP24 exposed pad package information
Figure 47. HTSSOP24 exposed pad package outline
Package information
DS12631 - Rev 4 page 61/69
Table 30. HTSSOP24 exposed pad mechanical data Figure 48. HTSSOP24 exposed pad recommended footprint
Revision history
Table 31. Document revision history Section Enable_CH registers. 25-Feb-2019 4 Updated: Figure 4. FLG pin connection.
Contents
DS12631 - Rev 4 page 65/69
DS12631 - Rev 4 page 66/69