ALD523D ALD | Alldatasheet
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© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 1 of 20 ALD523D MULTIFUNCTION 7-DIGIT SERIAL INPUT DISPLAY MODULE CONTROLLER PRODUCT FEATURES AND BENEFITS Up to 7 full digit plus sign (± 9999999) display Built-in 21 bit serial binary to ± 6½ digit decimal converter Compatible with industry standard 1-line x 16 and 2-line x 16 Character Display Modules User defined 16-alphanumeric character TITLE field and up to three 8-alphanumeric character UNIT fields Wide range of alphanumeric display characters Functional with either LCD or VFD display modules with column drivers Designed to operate optionally with ALD500/ALD500R Precision Analog Signal Processors or directly with serial inputs User selected integration time and conversion speed Cost effective and multipurpose stand alone operation 3 optional modes of operation: - Mode A, calibrated reference mode - Mode B, ratiometric mode - Mode C, display only mode Support external serial binary input (up to 32 bits) 3-wire serial interface to microprocessors or microcontrollers Electrical programmable memory interface Crystal oscillator frequency up to 8 MHz Single 3V to 5V power supply Up to 3 separate sets of 7-DIGIT Display Sets 3 sets of user defined 64-bit arithmetic multiplication factor Software programmable serial data bit mask and sign polarity mask 3 different sets of user selected data sample averaging with up to maximum of 128X sampling Optional 13-function user configurable hardware selection switches Automatic zero level shifting during power-on-reset Automatic zero level overwrite feature Adjustable decimal point placement with trailing digit blanking External 1K EEPROM memory for easy change of factory settings Sleep mode with Auto Power-On-Reset. Easy setup of calibration and system setup parameters No software programming required PC Interface Software provided for Calibration and Setup modes EEPROM MEMORY CONTROLLER DUAL SLOPE A/D 4-PHASE CONTROLLER SERIAL BINARY TO 6½ -DIGIT DECIMAL CONVERTER DISPLAY MODULE CONTROLLER SERIAL I/O INTERFACE LOGIC CONTROL LOGIC CHARACTER DISPLAY MODULE FUNCTIONS SELECTORS EEPROM ALD523D BLOCK DIAGRAM ALD500 ANALOG INPUT EXTERNAL SERIAL BINARY INPUT PC
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 2 of 20 PRODUCT APPLICATIONS Embedded (up to ± 6½ -digit) digital panel meter Customized/specialized instrument display High precision DC voltage meters Dedicated precision monitors High resolution A/D converter with display High accuracy and low noise weigh scale systems Multifunction precision measurement instruments Serial binary input to decimal/character display converter Portable battery operated display systems. ALD523D PIN CONFIGURATIONS PRODUCT ORDERING INFORMATION OPERATING TEMPERATURE RANGE* 0oC to +70oC 0oC to +70oC 28-Pin Plastic DIP Package (PDIP) 28-Pin Small Outline Package (SOIC) ALD523DPH ALD523DSH *: Contact factory for industrial temperature range CALIBRATED REFERENCE (MODE-A) ALD523D S1/SCL DSA1/D6 DSA2/D7 PWRCS SDA B1/D4 B2/D5 V XTAL2 XTAL1 DVCS CAL CS B WP A COUT COUT SEL0/D0 SEL1/D1 DEC1/D2 DGND DATIN SCLK DATOUT S2/EN S3/RS DEC2/D3 PH, SH PACKAGE RATIOMETRIC (MODE-B) ALD523D S1/SCL DSA1/D6 DSA2/D7 PWRCS SDA B1/D4 B2/D5 V XTAL2 XTAL1 DVCS CAL CS B WP A COUT COUT SEL0/D0 SEL1/D1 M/D2 DGND DATIN SCLK DATOUT S2/EN S3/RS Z/D3 PH, SH PACKAGE DISPLAY ONLY (MODE-C) ALD523D SCL DSA1/D6 DSA2/D7 PWRCS SDA B1/D4 B2/D5 V XTAL2 XTAL1 DVCS CAL N/C N/C WP N/C N/C N/C SEL0/D0 SEL1/D1 DEC1/D2 DGND DATIN SCLK DATOUT EN RS DEC2/D3 PH, SH PACKAGE
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 3 of 20 GENERAL DESCRIPTION The ALD523D is a Multifunction 7-Digit Serial Input Display Module Controller designed to interface directly to ALD500 or ALD500R integrating dual slope precision analog processors as a chip set for building a high precision and high accuracy analog-to-digital converter system with auto zero and auto-polarity. The ALD523D also functions as an universal serial input 7-digit display module controller that interfaces to most popular industry standard serial data formats from other microprocessors or data converters. It is designed for easy setting of industry standard Character Display Modules (CDM) such as 1-line by 16-character or 2-line by 16-character LCD or VFD display modules. The ALD523D is an enhanced version of the ALD521D digital controller. The ALD523D functions in three separate operating modes, namely calibrated reference (mode-A), ratiometric (mode-B), and display only (mode-C). The ALD523D digital controller operates as a master display module controller in either a stand-alone mode or in an external microprocessor control mode. In the external microprocessor control mode, the ALD523D can directly interface with a PC under PC software control via a standard parallel printer port. This external control mode is managed by the Serial I/O Interface Logic inside the ALD523D. In the stand-alone mode, the ALD523D makes continuous measurements, and includes all the necessary functions to fully control a CDM. In the stand-alone mode, ALD523D operates in conjunction with a 1K EEPROM chip to preserve the setup parameters and arithmetic (calibration) parameters of the ALD523D. The setup and arithmetic parameters are uploaded to the EEPROM via ALD523D Setup and Calibration PC software (DVM523). The ALD523D communicates to the EEPROM on a handshake protocol governed by the EEPROM Memory Controller inside the ALD523D. The ALD500/ALD500R dual slope precision analog processors consist of on-chip digital control circuitry to accept control inputs, integrating buffer amplifiers, analog switches, and voltage comparators. It functions in four operating phases, namely auto zero, integrate, de-integrate, and integrator zero phases. At the end of a conversion, the comparator output goes from high to low when the integrator crosses zero during de-integration. ALD500/ALD500R dual slope precision analog processors also provide direct logic interface to ALD523D. The ALD523D implements the logic and timing for all the four phases of the ALD500/ALD500R, namely auto zero, integrate, de-integrate, and integrator zero phases in mode- A and mode-B operations. These four phases are governed by the Dual Slope A/D 4-Phase Controller inside the ALD523D. The ALD523D operates from an external clock or its internal oscillator circuit along with an external crystal. The internal system clock of the ALD523D runs at a frequency which can be selected at divide-by N (4, 8, or 64) rate of the crystal (or external) clock frequency. The ALD523D offers up to 3 display settings, known as display sets, namely “DGS1”, “DGS2” and “DGS3”. “DGS1” also has an optional hardware decimal point setting mode, known as “DGS0”, which allows the user to use hardware jumper switches to set decimal point position. Each display set allows a full 7-digit decimal number to be converted from a 16-bit to 32-bit serial binary number using the Serial Binary To 6½-Digit Decimal Converter inside the ALD523D. This 6½-digit decimal number can also be scaled by a MULTIPLIER number, and the result of the scaled number displayed on the CDM through the Display Module Controller within the ALD523D. Additional display parameters that can be manipulated are: Digit Blanking, which allows user selection of number of digits to display; Decimal Point placement, which controls placement of decimal point, if any. Up to 3 sets of display UNIT fields are available, each with a combination of alphanumeric characters up to 8 characters long. The ALD523D also features hardware control-input pins for power down (PWRCS), integration time selection (S1, S2 and S3), data sample averaging (DSA1 and DSA2), digit blanking (B1 and B2), decimal point placement (DEC1 and DEC2), zero offset (M and Z), and display set selection (SEL0 and SEL1). When not used, or if no control is desired, each of these optional pins are wired to their respective desired logic state, either V+ or Ground (DGND), through pull-up or pull-down resistors. The functions of the control-input pins are managed by the Control Logic section in the ALD523D. MODES OF OPERATIONS The ALD523D functions in either single operating mode or multiple operating modes, namely calibrated reference (mode-A), ratiometric (mode-B), and display only (mode- C). In the single operating mode, ALD523D operates in one of the three modes of operation, either mode-A, mode- B or mode-C. In the multiple operating modes, the ALD523D can operate interchangeably in each of the three
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 5 of 20 ALD523 SETUP AND CALIBRATION SOFTWARE In the stand-alone mode, ALD523D operates in conjunction with a 1K EEPROM chip to preserve the setup and arithmetic (calibration) parameters of the ALD523D. These parameters are utilized to fully control the CDM and measurement functions. The parameters are preset by the user through the ALD523D Setup and Calibration PC software known as DVM523.EXE, and later uploaded to the EEPROM via a standard parallel printer port. See the ALD523D Setup and Calibration User Guide (DVM523) for more details. SELECTING AND CONFIGURING MODES OF OPERATIONS The three ALD523D modes of operations, namely mode- A, mode-B, and mode-C are configured in the .CDS file (see Table 1 of the ALD523D Setup and Calibration Software User Guide), and are selected by means of user selection of SEL0 and SEL1 control inputs of the ALD523D. Each display set “DGSx” has an associated mode parameter “Mx” which specifies the mode of operation. Hence, “DGS1”, “DGS2”, and “DGS3” have 3 associated mode specifying parameters “M1”, “M2”, and “M3”, respectively. Each “Mx” parameter can be preset to either “Mode-A”, “Mode-B”, or “Mode-C”. I. CALIBRATED REFERENCE MODE (MODE-A) Mode-A can be selected by setting the nibble “M1” parameter, or “M2” or “M3” of the byte “M2-M3” parameter to an “A” (HEX) in the .CDS file. “M1”, “M2”, and “M3” are the mode selection parameters associated with “DGS1”, “DGS2”, and “DGS3” display sets, respectively. In mode-A or mode-B operation, the bit masking “SMSK1” to “SMSK4” and the polarity bit masking “SMSK5” to “SMSK8” parameters are not utilized. However, this mode transmits a 24-bit serial word on pin 26, DATOUT. This 24-bit serial word consists of 23-bit binary data with MSB as the first bit, LSB the 23rd bit, followed by a sign bit as the last bit. The sign bit is a logical “1” as a positive sign, and logical “0” as a negative sign. II. RATIOMETRIC MODE (MODE-B) Mode-B can be selected by setting the nibble “M1” parameter, or “M2” or “M3” of the byte “M2-M3” parameter to an “B” (HEX) in the .CDS file. When the ALD523D is powered up the first time or after power-on-reset, a zero correction is automatically set by zeroing out the reading. This automatic zero correction feature can be manually overwritten by the Z switch (see Table 5) at any time. The overwrite feature is embedded to eliminate the long wait time at long integration time, and add flexibility to perform zero correction at any time. However, the faster the integration time set, the less the wait time is needed to perform the automatic zero correction (i.e. it takes typically from about 1 to 14 seconds to automatically zero out a reading for integration time of 16.66 ms to 300 ms, respectively). III. DISPLAY ONLY MODE (MODE-C) Mode-C can be selected by setting the nibble “M1” parameter, or “M2” or “M3” of the byte “M2-M3” parameter to an “C” (HEX) in the .CDS file. In mode-C operation, switches “S1”, “S2”, and “S3” are internally disabled. In mode-C operation, the ALD523D receives a maximum serial word length of 32 bits in accordance to 32 serial clock pulses, and processes a maximum of 21-bit serial word plus 1 sign bit within this 32-bit serial word. This 21-bit serial word can be any 21-bit consecutive serial data stream segment within the 32-bit serial clocks, as selected by programming of the bit masks “SMSK1” through “SMSK4”. The length of the received serial word is governed by a DVCS signal. A transition of DVCS from high to low state signals the start of the serial input data bit stream clocking. A transition of DVCS from low to high state stops the serial input data bit stream clocking. After an external instrument or processor sets the DVCS to logic 0, the DATIN terminal of the ALD523D is ready for serial input data stream. The ALD523D reads the first bit of the serial input data stream on DATIN and sends a serial clock pulse on the SCLK as an acknowledge signal to the external instrument or processor. Then the ALD523D reads the second bit of the serial input data stream and sends out a second SCLK clock pulse. This serial data reading and clocking process continues until DVCS is set to high state or until a maximum of 32 serial input data bits have been read. The serial clock SCLK consists of a low to high transition followed by a high to low transition. The maximum converted decimal number from this 21-bit binary data plus sign bit is ± 9999999, when a suitable multiplier and an appropriate conversion factor are used. The sign bit is defined as logic “0” as a positive sign, and logic “1” as a negative sign. Alternatively, the sign bit
inverted, as described in the next section.
- Maximum serial word length that the ALD523D can
stops the data word counter.
- Maximum serial data bits that the ALD523D can
process are 21 bits plus 1 sign bit for a total of 22 bits.
- Minimum serial data bits that the ALD523D can
0 of the 32 bit input mask register.
- The input serial data bits must be in a consecutive
order, from MSB bit first to LSB bit last.
- The sign bit can be anywhere outside the serial data
bits stream but within the serial data word. through SMSK4 from memory address 60H to 63H. Table 1. Serial data bit masking technique. consecutive “1” in the masking bits, which is 16 bits. through SMSK8 from memory address map 64H to 67H. Initially, all 32 bits from SMSK5 to SMSK8 are set to 0. example, the data word has 23 clock cycles. of the input data word, while DVCS is low. Table 2. Sign bit masking technique.
factors “±CALx”, where x=0, 1, 2 or 3. scale factors, decimal point location, and mode selections. when either SEL0 or SEL1 are set to logical “1”. content of the “L1DEC” parameter. content of the “L2DEC” parameter. content of the “L3DEC” parameter. sign bit inverted polarity mode, respectively. Table 3. Display setting switch configurations and operations.
implement these “N1”, “N2”, and “N3” scale factors. User Guide for implementation details. combinations are described in Table 4. Table 4. Decimal Point setting switch combination for functional when display set “DGS0” is selected. number with a decimal point placed after the first digit. placed after the second digit. display set of the same range.
display set “DGS1”, “DGS2”, and “DGS3”, respectively. Table 5. Zero level switch configurations and operations for button in many weigh scales. Table 6. Each logical state combination selects the numbers of digits to be displayed. Table 6. Blanking switch combination for mode-A, mode-B, only the first 4 digits of the number. tradeoff between conversion time and noise rejection.
selects a pre-defined averaging/sampling. Table 7. Averaging selection switch combination for mode- utilizes “AVG3” at address 04H of the EEPROM.
- These values correspond to the number of data
as a multiple of the period of the power line frequency. 300msec maximize 50Hz power line noise rejection. logical state combinations are listed in Table 8. Table 8. Integration time selection switch combination for mode-A and mode-B.
instructions preset by the user in the EEPROM memory. CDM. Next, it checks the status of the PWRCS pin. Setup and Calibration Software User Guide). Figure 6. Reference calibration mode block diagram. and logical “0” as a negative sign. SCLK, DATOUT, and DVCS pins.
calibration process and/or conversion factor scaling. Figure 7. Data transfer mode block diagram. indicate the ALD523D is in data transfer mode.
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 15 of 20 ABSOLUTE MAXIMUM RATINGS3 DC OPERATING ELECTRICAL CHARACTERISTICS TA = 0oC - 70oC, V+ = +5V, fXTL = 3.6864 MHz unless otherwise specified Parameter Symbol Min Typ Max Unit Test Conditions Supply Operating Voltage Range 5.5 V Supply Current IDD 6.5 8.0 mA Supply Current IDD mA V+ = 3.5V Shutdown Mode Supply Current ISDD µA PWRCS = +5V, VIN = 0V Input Characteristics Low Input Voltage VIL -0.3 1.0 V High Input Voltage VIH 3.5 5.3 V Input Leakage Current IIL µA Output Characteristics Low Output Voltage VOL 0.2 0.4 V Iout = 4 mA High Output Voltage VOH 4.6 4.8 V Iout = -2 mA
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 16 of 20 TIMING CHARACTERISTICS TA = 0oC - 70oC, V+ = +5V, fXTL = 3.6864 MHz, internal system clock = fXTL/4 unless otherwise specified Parameter Symbol Min Typ Max Unit Test Conditions Display Only (Mode-C) Timing DATIN Setup Time tDS 3.7 µs Serial Clock Low Time tSCL 16.2 µs Serial Clock High Time tSCH 67.6 µs DVCS to DATIN Valid Time tDIV 67.62 µs Serial Clock to DVCS High Time tDVCSH 22.22 µs Power Timing Power-On-Reset Time tPOR sec Data Transfer From PC Timing4 Calibration to Data Valid Time tCALDV 1.9 µs Serial Clock High Time tSCLKH µs Serial Clock Low Time tSCLKL µs Data Valid to Serial Clock Delay Time tDSdelay 0.271 500,000 µs Serial Clock to Data Valid High Time tSCDVH DC ns Serial Clock to Data Valid Low Time tSCDVL DC ns DATIN Setup Time tDS 2.4 µs Data Valid High Time tDVH µs Serial Clock to Calibration Time tSCCAL ms Reference Calibration Timing Auto Zero Time tAZ tINT ms Integration Time1, 2 tINT 16.667 300 ms Integrator Zero Time tINTZ ms Calibration Setup Time tCS 1.1 µs Calibration Delay Time5 tCD Conv. Cycle DATOUT Valid Setup Time tDVS µs DATOUT Not Valid Time tDNV µs DATOUT Valid Time tDV µs DATOUT Valid Time Out Time tTO 5.5 ms DATOUT Out Time tDATOUT 500 ns Input / Output Characteristic Timing Input Interrupt Low Time tIL ns CAL, PWRCS, COUT, DVCS Rise/Fall Times (CL = 10pF) tR, tF 125 ns Oscillator (OSCIN, OSCOUT) Crystal Frequency fXTL 3.6864 MHz External Frequency (OSCIN) fOSC MHz Rise time/Fall time ≤ 15 ns 1 Apply only for calibrated reference (mode-A) and ratiometric (mode-B) operations. 2 Extendible from S1, S2, and S3 hardware switches through “SETF” parameter in the .CDS file. Lower integration time than the minimum allows more conversion cycles per second at reduced count resolution. Higher integration time increases count resolution, but requires increased capacitor value and lowered number of conversion cycles per second. De-integration time depends on selection of full scale input range, integration capacitor value and voltage reference. 3 ESD Sensitive Device. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to device, and may affect device reliability and performance. 4 PC to ALD523D handshake using page write mode. 5 Calibration delay time (tCD) may be as short as 7 µs, if start of auto zero phase cycle time could be determined. For asynchronous operation, tCD must be for a minimum of one complete conversion cycle to assure synchronization to start of auto zero phase cycle time.
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 17 of 20 DISPLAY ONLY (MODE-C) TIMING *Note: Default mode is SCLK, which can be inverted to produce SCLK by software setup. DATA TRANSFER FROM PC TIMING
- n is the number of serial data bits, and m is the integer of 1, 2, …, n. DATIN IN FROM SERIAL SOURCE tDS tSCH tDIV DVCS IN FROM SERIAL SOURCE SCLK* OUT TO SERIAL SOURCE tDS tSCL S S S S tDVCSH S S MSB BIT BIT n-2 LSB BIT SIGN BIT NOT VALID S S BIT n-m NOT VALID DVCS IN FROM PC CAL IN FROM PC S S tDVH tCALDV tSCDVL tSCLKH SCLK OUT TO PC tSCLKL tDSdelay tSCDVH S S S S DATIN IN FROM PC BIT 63 BIT 62 NOT VALID BIT 0 tDS tDS S S S S NOT VALID BIT n-m NOT VALID tSCCAL tCALDV
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 18 of 20 ALD523D TO PC MODE-A REFERENCE CALIBRATION TIMING EXPANDED VIEW DATOUT OUT TO PC tAZ tINT A OUT TO ALD500 B OUT TO ALD500 COUT IN FROM ALD500 tDINT tINTZ tAZ SCLK OUT TO PC tDNV tDV tTO CAL IN FROM PC tCS tDVS DVCS IN FROM PC SIGN BIT NOT VALID BIT 0 (LSB) BIT 22 (MSB) tDATOUT NOT VALID NOT VALID NOT VALID NOT VALID S S S S S S S S S S S S S S S S S S S S S S DATOUT OUT TO PC SCLK OUT TO PC tDNV tDV DVCS IN FROM PC tTO SIGN BIT NOT VALID BIT 0 (LSB) BIT 22 (MSB) tDATOUT NOT VALID NOT VALID NOT VALID NOT VALID S S S S S S S S
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 19 of 20 ALD523D PIN IDENTIFICATION FOR CALIBRATED REFERENCE MODE (MODE-A) PIN # SYMBOL FUNCTION SIGNAL PROPAGATION COUT COMPARATOR OUTPUT INPUT SDA MEMORY SERIAL ADDRESS/DATA INPUT/OUTPUT S1, SCL INTEGRATION TIME SWITCH, MEMORY SERIAL CLOCK INPUT/ OUTPUT B1, D4 BLANK SWITCH, DISPLAY DATA BIT INPUT/OUTPUT B2, D5 BLANK SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DSA1, D6 AVERAGING SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DSA2, D7 AVERAGING SWITCH, DISPLAY DATA BIT INPUT/OUTPUT POWER SUPPLY XTAL2 CRYSTAL OSCILLATOR OUTPUT XTAL1 CRYSTAL OSCILLATOR INPUT COUT COMPARATOR OUTPUT INPUT INTERRUPT CAL CALIBRATION SIGNAL INPUT PWRCS POWER UP CHIP SELECT INPUT CS CHIP SELECT OUTPUT B A/D INPUT OUTPUT WP MEMORY WRITE PROTECT OUTPUT A A/D INPUT OUTPUT DVCS DATA VALID CHIP SELECT INPUT SEL0, D0 MODE SWITCH, DISPLAY DATA BIT INPUT/OUTPUT SEL1, D1 MODE SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DEC1, D2 DECIMAL POSITION SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DGND DIGITAL GROUND DEC2, D3 DECIMAL POSITION SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DATIN DATA IN INPUT SCLK SERIAL CLOCK OUTPUT DATOUT DATA OUT OUTPUT S2, EN INTEGRATION TIME SWITCH, DISPLAY ENABLE INPUT/OUTPUT S3, RS INTEGRATION TIME SWITCH, DISPLAY REGISTER SELECT INPUT/OUTPUT ALD523D PIN IDENTIFICATION FOR RATIOMETRIC MODE (MODE-B) PIN # SYMBOL FUNCTION SIGNAL PROPAGATION COUT COMPARATOR OUTPUT INPUT SDA MEMORY SERIAL ADDRESS/DATA INPUT/OUTPUT S1, SCL INTEGRATION TIME SWITCH, MEMORY SERIAL CLOCK INPUT/ OUTPUT B1, D4 BLANK SWITCH, DISPLAY DATA BIT INPUT/OUTPUT B2, D5 BLANK SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DSA1, D6 AVERAGING SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DSA2, D7 AVERAGING SWITCH, DISPLAY DATA BIT INPUT/OUTPUT POWER SUPPLY XTAL2 CRYSTAL OSCILLATOR OUTPUT XTAL1 CRYSTAL OSCILLATOR INPUT COUT COMPARATOR OUTPUT INPUT INTERRUPT CAL CALIBRATION SIGNAL INPUT PWRCS POWER UP CHIP SELECT INPUT CS CHIP SELECT OUTPUT B A/D INPUT OUTPUT WP MEMORY WRITE PROTECT OUTPUT A A/D INPUT OUTPUT DVCS DATA VALID CHIP SELECT INPUT SEL0, D0 MODE SWITCH, DISPLAY DATA BIT INPUT/OUTPUT SEL1, D1 MODE SWITCH, DISPLAY DATA BIT INPUT/OUTPUT M, D2 ZERO MASTER SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DGND DIGITAL GROUND Z, D3 ZERO SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DATIN DATA IN INPUT SCLK SERIAL CLOCK OUTPUT DATOUT DATA OUT OUTPUT S2, EN INTEGRATION TIME SWITCH, DISPLAY ENABLE INPUT/OUTPUT S3, RS INTEGRATION TIME SWITCH, DISPLAY REGISTER SELECT INPUT/OUTPUT
© 2001 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706, Tel: (408) 747-1155, Fax: (408) 747-1286 ALD523D 12/01 http://www.aldinc.com 20 of 20 ALD523D PIN IDENTIFICATION FOR DISPLAY ONLY MODE (MODE-C) PIN # SYMBOL FUNCTION SIGNAL PROPAGATION SDA MEMORY SERIAL ADDRESS/DATA INPUT/OUTPUT SCL MEMORY SERIAL CLOCK OUTPUT B1, D4 BLANK SWITCH, DISPLAY DATA BIT INPUT/OUTPUT B2, D5 BLANK SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DSA1, D6 AVERAGING SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DSA2, D7 AVERAGING SWITCH, DISPLAY DATA BIT INPUT/OUTPUT POWER SUPPLY XTAL2 CRYSTAL OSCILLATOR OUTPUT XTAL1 CRYSTAL OSCILLATOR INPUT CAL CALIBRATION SIGNAL INPUT PWRCS POWER UP CHIP SELECT INPUT WP MEMORY WRITE PROTECT OUTPUT DVCS DATA VALID CHIP SELECT INPUT SEL0, D0 MODE SWITCH, DISPLAY DATA BIT INPUT/OUTPUT SEL1, D1 MODE SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DEC1, D2 DECIMAL POSITION SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DGND DIGITAL GROUND DEC2, D3 DECIMAL POSITION SWITCH, DISPLAY DATA BIT INPUT/OUTPUT DATIN DATA IN INPUT SCLK SERIAL CLOCK OUTPUT DATOUT DATA OUT OUTPUT EN DISPLAY ENABLE OUTPUT RS DISPLAY REGISTER SELECT OUTPUT