ALD500R

ALD500RAU ADL | Alldatasheet

Document overview

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Technical content

APPLICATIONS

• 4 1/2 digits to 5 1/2 digits plus sign measurements
• Precision analog signal processor
• Precision sensor interface
• High accuracy DC measurement functions
• Portable battery operated instruments
• Computer peripheral
• PCMCIA

FEATURES

• Resolution up to 18 bits plus sign bit and over-range bit
• Accuracy independent of input source impedances
• Accurate on-chip voltage reference
• Tempco as low as 10 ppm/°C guaranteed
• Chip select - power down mode
• High input impedance of 10 12 Ω
• Inherently filters and integrates any external noise spikes
• Differential analog input
• Wide bipolar analog input voltage range ±3.5V
• Automatic zero offset compensation
• Low linearity error - as low as 0.001% typical
• Fast zero-crossing comparator - 1µs
• Low power dissipation - 6mW typical
• Automatic internal polarity detection
• Low input current - 2pA typical
• Optional digital control from a microcontroller, an ASIC, or a dedicated digital circuit
• Flexible conversion speed vs. resolution trade-off ALD500RAU/ALD500RA/ALD500R ADVANCED LINEAR D EVICES, INC. PRECISION INTEGRATING ANALOG PROCESSOR WITH PRECISION VOLTAGE REFERENCE Rev. 1.01 © 1999 Advanced Linear Devices, Inc., 415 Tasman Drive, Sunnyvale, California 94089-1706 Tel: (408) 747-1155, Fax: (408) 747-1286 http://www.aldinc.com * Contact factory for customized voltage reference voltage levels, accuracy and tempco specifications. PIN CONFIGURATION Resolution Endpoint Voltage Reference Package Type Operating Linearity Accuracy/Tempco Temperature 20L PDIP 20L SOIC 20L QSOP 20LCDIP 16 bit 0.015% 0.5% 50ppm/C ALD500R-50PE ALD500R-50SE ALD500R-50QE 0 °C to 70°C 17 bit 0.01% 0.3% 20ppm/C ALD500RA-20PE ALD500RA-20SE ALD500RA-20QE 0 °C to 70°C 18 bit 0.005% ALD500RAU-20PE ALD500RAU-20SE ALD500RAU-20QE 17 bit 0.01% 0.2% 10ppm/C ALD500RA-10PE ALD500RA-10SE ALD500RA-10QE 0 °C to 70°C 18 bit 0.005% ALD500RAU-10PE ALD500RAU-10SE ALD500RAU-10QE 17 bit 0.01% 0.3% 20ppm/C ALD500RA-20PEI ALD500RA-20SEI ALD500RA-20QEI -40 °C to +85°C 18 bit 0.005% ALD500RAU-20PEI ALD500RAU-20SEI ALD500RAU-20QEI 18 bit 0.005% 0.3% 20ppm/C ALD500RAU-20DE -55 °C to +125°C

Ordering Information

• Low cost, simple functionality
• Wide dynamic signal range
• Very high noise immunity
• Automatic compensation and cancellation of error sources
• Easy to use to acquire bipolar signals
• Up to 19 bit (18 bit + sign bit) single conversion or 21 bit (20 bit + sign bit) multiple conversion and noise performance
• Inherently linear and stable with temperature and component variations V+ A V+REF 10 11 C AZ C INT B UF AGND N/C C +REF V-IN V+IN C OUT DGND QE, PE, SE PACKAGE C -REF ALD500R V-REF C SIB N/C * N/C pin is connected internally. Connect to V-.

2 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R

unknown input voltage, which is the subject of measurement. as VX, are cancelled out and do not affect accuracy. and the stability of the voltage reference value. FIGURE 1. ALD500R Functional Block Diagram with an appropriate digital controller and software. zero, integrate, deintegrate, and integrator zero phases. direct logic interface to CMOS logic families.

can be achieved simply and at very low cost. converters and perform very well in high-noise environments. of the integration period are, theoretically, completely removed. reject 50/60Hz line frequency interference signals. Figure 2. Basic Dual-Slope Converter proportional to the magnitude of the applied input voltage. is handled by a microprocessor or a dedicated logic controller. microprocessor or a display adapter when desired.

4 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R

OPERATING ELECTRICAL CHARACTERISTICS TA = 25°C V+ = +5V V- = -5V (V supply ± 5V) unless otherwise specified; CAZ = CREF = 0.47µf 500RAU 500RA 500R Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Unit Test Conditions Resolution 15 30 60 µV Notes 1, 7 Zero-Scale Z SE 0.0025 0.003 0.005 % 0 °C to 70°C Error 0.003 0.005 0.008 % Linearity 0.007 0.015 0.020 0 °C to +70°C Straight Line Linearity 0.004 0.008 0.015 0 °C to +70°C Zero-Scale TC Temperature Full-Scale S YE 0.005 0.008 0.01 % 0 °C to 70°C Symmetry Error (Rollover Error) 0.008 0.010 0.012 % Full-Scale TC FS 1.3 1.3 1.3 ppm/ °C0 °C to +70°C Temperature Note 7 Coefficient Input I IN 22 2 p A V IN = 0V Current Voltage Range Output Swing Signal Range Voltage V REF VSS +1 VDD -1 VSS +1 VDD -1 VSS + 1 VDD -1 V Reference Range ABSOLUTE MAXIMUM RATINGS Supply voltage, V+ 13.2V Differential input voltage range -0.3V to V + +0.3V Power dissipation 600 mW Operating temperature range PE, SE package 0 °C to +70°C Operating temperature range QE package -55 °C to +125°C Storage temperature range -65°C to +150°C Lead temperature, 10 seconds +260°C

Figure 3. ALD500R TIMING DIAGRAM

1.8432 MHz Clock

1 Conversion Cycle

6 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R

DC ELECTRICAL CHARACTERISTICS TA = 25°C V supply = +5.0V unless otherwise specified; CAZ = CREF = 0.47µf, RREF = 100KΩ (1% metal film) Parameter Symbol 500RAU-10 500RAU-20 500RAU-50 Unit Test Conditions 500RA-10 500RA-20 500RA-50 500R-50 Min Typ Max Min Typ Max Min Typ Max Supply Voltage V RSR 95 95 95 dB Rejection Ratio Temperature V RTC 3 10 7 20 15 50 ppm/C ° Coefficient Long Term Drift Δ VREF / -0.08 -0.08 -0.08 ppm/ Note 7 Δ t 1000hrs Warm Up Time 10 10 10 min. Note 7 Operating Voltage Range Operating Voltage Range Power Down Supply I PD 25 25 25 µA Note 7 Current NOTES: 1. Integrate time ≥ 66 msec., Auto Zero time ≥ 66 msec., VINT = 4V, VIN = 2.0V Full Scale Resolution = VINT /integrate time/clock period 2. End point linearity at ± 1/4, ±1/2, ± 3/4 Full Scale after Full Scale adjustment. 3. Rollover Error also depends on CINT, CREF , CAZ characteristics. 4. Contact factory for other power supply operating voltage ranges, including Vsupply = ±3V or Vsupply = ± 2.5V. 5. Recommended selection of clock periods of one of the following: t clk = 0.27µsec, 0.54µsec, or 1.09µsec which corresponds to clock frequencies of 3.6864 MHz, 1.8432 MHz, 0.9216 MHz respectively. 6. RREF is 100K Ω 1% metal film, 50 ppm/C. 7. Sample tested parameter.

1I B Bias circuit pin. Connect a 0.1µF capacitor from this pin to V- to minimize noise. 2C INT Integrator capacitor connection. 4C AZ The Auto-zero capacitor connection. 5 BUF The Integrator resistor buffer connection. 6 AGND This pin is analog ground. -REF Negative reference capacitor connection. 8C +REF Positive reference capacitor connection. 9 N/C Internally connected. Connect to V - for normal operation. 10 N/C Internally connected. Connect to V - for normal operation. 11 V -REF External voltage reference (-) connection. High impedance load (≥100M Ω ) only. 12 V +REF External voltage reference (+) connection. High impedance load (≥100M Ω ) only. 13 V -IN Negative analog input. 14 V +IN Positive analog input. 15 A Converter phase control MSB Input. 16 B Converter phase control LSB Input. time the Integrator Zero phase. 20 C S Chip select - power down pin. Logic 1 = power on. Logic 0 = power down. *SW +R would be closed for a positive input signal. SW-R would be closed for a negative input signal. Table 1. Conversion Phase and Control Logic Internal Analog Switch Functions

8 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R

ALD500RAU/ALD500RA/ALD500R CONVERSION CYCLE The ALD500RAU/ALD500RA/ALD500R conversion cycle takes place in four distinct phases, the Auto Zero Phase, the Input Signal Integration Phase, the Reference Voltage Deintegration Phase, and the Integrator Zero Phase. A typical measurement cycle uses all four phases in an order sequence as mentioned above. The internal analog switch status for each of these phases is summarized in Table 1. The following is a detailed description of each one of the four phases of the conversion cycle. Auto Zero Phase (AZ Phase) The analog-to-digital conversion cycle begins with the Auto Zero Phase, when the digital controller applies low logic level to input A and high logic level to input B of the analog processor. During this phase, the reference voltage is stored on reference capacitor C REF , comparator offset voltage and the sum of the buffer and integrator offset voltages are stored on auto zero capacitor CAZ. During the Auto Zero Phase, the comparator output is characterized by an indeterminate waveform. During the Auto Zero Phase, the external input signal is disconnected from the internal circuitry of the ALD500RAU/ ALD500RA/ALD500R by opening the two SW IN analog switches and connecting the internal input nodes internally to analog ground. A feedback loop, closed around the integrator and comparator, charges the C AZ capacitor with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. This is the system initialization phase, when a conversion is ready to be initiated at system turn-on. In practice the converter can be operated in continuous conversion mode, where AZ phase must be long enough for the circuit conditions to settle out any system errors. Typically this phase is set to be equal to t INT. Input Signal Integration Phase (INT Phase) During the Input Signal Integration Phase (INT), the ALD500RAU/ALD500RA/ALD500R integrates the differential voltage across the (V+IN) and (V-IN) inputs. The differential voltage must be within the device's common-mode voltage range CMVR. The integrator charges C INT for a fixed period of time, or counts a fixed number of clock pulses, at a rate determined by the magnitude of the input voltage. During this phase, the analog inputs see only the high impedance of the noninverting operational amplifier input of the buffer. The integrator responds only to the voltage difference between the analog input terminals, thus providing true differential analog inputs. The input signal polarity is determined by software control at the end of this phase: C OUT = 1 for positive input polarity; C OUT = 0 for negative input polarity. The value is, in effect, the sign bit for the overall conversion result. The duration of this phase is selected by design to be a fixed time and depends on system parameters and component value selections. The total number of clock pulses or clock counts, during integration phase determine the resolution of the conversion. For high resolution applications, this total number of clock pulses should be maximized. The basic unit of resolution is in µV/count. Before the end of this phase, comparator output is sampled by the microcontroller. This phase is terminated by changing logic inputs AB from 10 to 11. Reference Voltage Deintegration Phase (D INT Phase) At the end of the Input Signal Integration Phase, Reference Voltage Deintegration Phase begins. The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. The ALD500RAU/ ALD500RA/ALD500R analog processors automatically selects the proper logic state to cause the integrator to ramp back toward zero at a rate proportional to the reference voltage stored on the reference capacitor. The time required to return to zero is measured by the counter in the digital processor using the same crystal oscillator. The phase is terminated by the comparator output after the comparator senses when the integrator output crosses zero. The counter contents are then transferred to the register. The resulting time measurement is proportional to the magnitude of the applied input voltage. The duration of this phase is precisely measured from the transition of AB from 10 to 11 to the falling edge of the comparator output, usually with a crystal controlled digital counter chain. The comparator delay contributes some error in this phase. The typical comparator delay is 1µ sec. The comparator delay and overshoot will result in error timing, which translates into error voltages. This error can be zeroed and minimized during Integrator Output Zero Phase and corrected in software, to within ±1 count of the crystal clock (which is equivalent to within ± 1 LSB, when 1 clock pulse = 1 LSB). Integrator Zero Phase ( I NTZ Phase) This phase guarantees the integrator output is at 0V when the Auto Zero phase is entered, and that only system offset voltages are compensated. This phase is used at the end of the reference voltage deintegration and is used for applications with high resolutions. If this phase is not used, the value of the Auto-Zero capacitor (C AZ) must be much greater than the value of the integration capacitor (CINT) to reduce the effects of charge-sharing. The Integrator Zero phase should be programmed to operate until the Output of the Comparator returns "HIGH". A typical Integrator Zero Phase lasts 1msec. The comparator delay and the controller's response latency may result in Overshoot causing charge buildup on the integrator at the end of a conversion. This charge must be removed or performance will degrade. The Integrator Output Zero phase should be activated (AB = 00) until C OUT goes high. At this point, the integrator output is near zero. Auto Zero Phase should be entered (AB = 01) and the ALD500RAU/ ALD500RA/ALD500R is held in this state until the next conversion cycle.

mode rejection is typically 95dB. The integrator output also follows the common-mode voltage. ground in order to minimize noise at the inputs. comparison to the stray capacitance. output state to toggle between positive and negative states. been minimized to typically within one count. pulse count. The internal comparator delay is 1µsec, typically. Figure 4. Comparator Output

10 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R

APPLICATIONS AND DESIGN NOTES Determination and Selection of System Variables The procedure outlined below allows the user to determine the values for the following ALD500RAU/ALD500RA/ALD500R system design variables: (1) Determine Input Voltage Range (2) Clock Frequency and Resolution Selection (3) Input Integration Phase Timing (4) Integrator Timing Components (R INT, CINT) (5) Auto Zero and Reference Capacitors (6) Voltage Reference System Timing Figure 3 and Figure 4 show the overall timing for a typical system in which ALD500RAU/ALD500RA/ALD500R is interfaced to a microcontroller. The microcontroller drives the A, B inputs with I/O lines and monitors the comparator output, C OUT , using an I/O line or dedicated timer-capture control pin. It may be necessary to monitor the state of the comparator output in addition to having it control a timer directly during the Reference Deintegration Phase. There are four critical timing events: sampling the input polarity; capturing the deintegration time; minimizing overshoot and properly executing the Integrator Output Zero Phase. Selecting Input Integration Time For maximum 50/60 cycle noise rejection, Input Integration Time must be picked as a multiple of the period of line frequency. For example, t INT times of 33msec, 66msec and 100 msec maximize 60Hz line rejection, and 20msec, 40 msec, 80msec, and 100 msec maximize 50Hz line rejection. Note that tINT of 100 msec maximizes both 60 Hz and 50Hz line rejection. INT and DINT Phase Timing The duration of the Reference Deintegrate Phase (DINT) is a function of the amount of voltage charge stored on the integrator capacitor during INT phase, and the value of V REF . The DINT phase must be initiated immediately following INT phase and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for D INT phase is twice to three times that of INT phase with VREF chosen as a maximum voltage relative to VIN. For example, VREF = VIN(max)/2 would be a good reference voltage. Integrating Resistor (RINT ) The desired full-scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a full-scale current of 20µA. The value of RINT is therefore directly calculated as follows: R INT =V IN MAX / 20 µA where: VIN MAX = Maximum input voltage desired (full count voltage) R INT = Integrating Resistor value For minimum noise and maximum linearity, RINT should be in the range of between 50kΩ to 150kΩ . Integrating Capacitor (CINT) The integrating capacitor should be selected to maximize integrator output voltage swing VINT, for a given integration time, without output level saturation. For +/-5V supplies, recommended V INT range is between +/- 3 Volt to +/-4 Volt. Using the 20µA buffer maximum output current, the value of the integrating capacitor is calculated as follows: C INT = (tINT) . (20 x 10-6) / VINT where: tINT = Input Integration Phase Period VINT = Maximum integrator output voltage swing It is critical that the integrating capacitor must have a very low dielectric absorption, as charge loss or gain during conversion directly converts into an error voltage. Polypropylene capacitors are recommended while Polyester and Polybicarbonate capacitors may also be used in less critical applications. Reference (C REF ) and Auto Zero (CAZ ) Capacitors C REF and C AZ must be low leakage capacitors (e.g. polypropylene types). The slower the conversion rate, the larger the value C REF must be. Recommended capacitor values for CREF and CAZ are equal to CINT. Larger values for C AZ and CREF may also be used to limit roll-over errors. Calculate VREF The reference deintegration voltage is calculated using: VREF = (VINT) . (CINT) . (RINT) / 2(tINT) The ALD500RAU/ALD500RA/ALD500R requires an external R REF in order to operate properly. This RREF should be a 1% metal film 100KΩ resistor, 50 ppm/C. Any other loading must be high impedance (≥100M Ω ). Converter Noise The converter noise is the total algebraic sum of the integrator noise and the comparator noise. This value is typically 14 µV peak to peak. The higher the value of the reference voltage, the lower the converter noise. Such sources of noise errors can be reduced by increased integration times, which effectively filter out any such noise. If the integration time periods are selected as multiples of 50/60Hz frequencies, then 50/60Hz noise is also rejected, or averaged out. The signal-to-noise ratio is related to the integration time (t INT) and the integration time constant (RINT) (CINT) as follows: S/N (dB) = 20 Log ((VINT / 14 x 10-6) . tINT /(RINT . CINT)) This converter noise can also be reduced by using multiple samples and mathematically averaged. For example, taking 16 samples and averaging the readings result in a mathematical (by software) filtering of noise to less than 4µV.

ALD500RAU/ALD500RA/ALD500R Advanced Linear Devices 11 EQUATIONS AND DERIVATIONS Dual Slope Analog Processor equations and derivations are as follows: 60Hz 2.0 20x10-6 DESIGN EXAMPLES We now apply these equations in the following design examples. Design Example 1: 1. Pick resolution = 16 bit. 2. Pick t INT = 4x = 4 x 16.6667 msec. 3. Pick clock period = 1.08507 µs and number of counts 4. Pick V INMAX value, e.g., VINMAX = 2.0 V I BMAX = 20µA RINT = = 100 kΩ 5. Applying equation (3) to calculate C INT: 6. Pick C REF and CAZ ‡ CINT: CREF CAZ 0.33 µF 7. Pick t DINT = 2 x tINT = 133.3333 msec 8. Calculate V REF VINTMAX . CINT . RINT tDINT MAX 4 x 0.33 x 10-6 x 100 x 103 133.3333 x 10-3 1.00V = 0.0666667 sec. V V R INT . CINT VIN(t)dt = ∫0 tINT tDINTVIN = VREF . tINT 1 tINT . VIN = VREF . tDINT (2a) (2) (1) C INT = VINT tINT . IB (3) R INT = VINMAX IBMAX (4) For VIN(t) = VIN (constant): From equation (2a), OR Rearranging equations (3) and (4): At V INT = VINT MAX, equation (6) becomes: Combining (6a) and (7): In equation (5b), substituting equation (8) for t INT: For t DINT MAX = 2 x tINT, equation (9) becomes: VIN MAX . tINT tDINT MAX VIN . tINT tDINT (5a) (5b) tINT = C INT . VINT IB (6) IBMAX = VINMAX R INT (7) VREF = VREF = VINMAX (8) VIN MAX . tDINT MAX VREF = C INT . VINTMAX . R INT VIN MAX = C INT . VINTMAX . RINT tDINT MAX (9) VREF = C INT . VINTMAX . RINT 2tINT (10) R INT . CINT R INT . CINT VREF . tDINT R INT . CINT ... tINT = C INT . VINTMAX IBMAX and At VINMAX, the current IB is also at a maximum level, for a given RINT value: VIN IB (6a) C INT = (0.0666667)(20x10-6)/4 where VINT = 4.0V 0.33 µF Design Example 2: 1. Select resolution of 17 bit. Total number of counts during t INT is131,072. 2. We can pick t INT of 16.6667 msec. x 5 = 83.3333 msec. or alternately, pick tINT equal 16.6667 msec. x 6 = 100.00 msec. (for 60 Hz rejection) which is t INT = 20.00 msec. x 5 Therefore, using t INT = 100 msec. would achieve both 50 Hz and 60 Hz cycle noise rejection. For this example, the following calculations would assume t INT of 100 msec. Now select period equal to 0.5425 µsec. (clock frequency of 1.8432 MHz) = 66.6667ms = 100.00 msec. (for 50 Hz rejection) 0.0666667 1.08507x10-6 over tINT = = 61440

12 Advanced Linear Devices ALD500RAU/ALD500RA/ALD500R

1. Pick VINMAX = –2V For I BMAX = 20µA, applying equation (4), 4. Calculate, using equation (3) for CINT: Use CINT 0.47µF as the closest practical value. 5. Pick CREF and CAZ = 0.47 µF 6. Pick tDINT = 2 x tINT = 200 msec. 7. Calculate the value for VREF , from equation (10): V REF = 20x10-6 = 0.83 µF 20x10-6 = 0.5 µF C INT . VINTMAX . RINT tDINT MAX = 1.00V = 0.1666667 sec. 0.5 x 10-6 x 4 x 100 x 103 200 x 10-3 Design Example 3: 1. Pick resolution of 18 bit. Total number of counts during tINT is 262,144. 2. Pick tINT = 16.66667 msec. x 10 cycles This t INT allows clock period of 0.5425 µsec. and still achieve 18 bits resolution. 3. Again, as shown from previous example, pick V INMAX = –2V For I BMAX = 20 µA, RINT = = 100 KΩ 4. Next, we calculate CINT: C INT = (0.1666667) x (20 x 10-6)/4 In this case, use CINT = 1.0 µF to keep V INT < 4.0V 5. Pick CREF and CAZ = 1.0 µF 6. Select tDINT = 2 x tINT = 333.333 msec. 7. Calculate VREF as shown in the previous examples and VREF = 1.00V 245776 or 16.276 µV/count 16.276 x VINTMAX VINMAX = 8.138 µV/count 20 x 10-6 2 = 100 KΩ Design Example 4: Objective: 5 1/2 digit + sign +over-range measurement. 1. Pick tINT = 133.333 msec. for 60Hz noise rejection. (16.6667 msec. x 8 cycles) Frequency = 1.8432 MHz clock period = 0.5425 µsec. During Input Integrate Phase, For V INT = 4.0V, the basic resolution is For VINMAX = 2.00V, the input resolution is 2. Pick VIN range = – 2V For I B = 20 µA, RINT = 3. Calculate CINT = (0.133333) x (20 x 10-6)/4 = 0.67 µF 4. Pick CREF = CAZ = 0.67 µF 5. Select tDINT = 2 x tINT = 266.667 msec. 6. Calculate VREF as shown in Design Example 1, substituting the appropriate values: C INT . VINTMAX . RINT tDINT MAX VREF = ~= 1.005V R INT = = 100 K Ω 133.333 x 10-3 0.5425 x 10-6 (assume VINTMAX = 4V) (VINTMAX = 4.0V) total count = = 245776