AL4CX263 AVERLOGIC | Alldatasheet

Document overview

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Technical content

Features

  • 8,192 x 18/16, 384 x 9 - bit (AL4CX263)
  • 16,384 x 18/32, 768 x 9 - bit (AL4CX273)
  • 32,768 x 18/65, 536 x 9 - bit (AL4CX283)
  • 65,536 x 18/131, 072 x 9 - b it (AL4CX293)
  • Maximum 166 MHz Operation
  • 6 ns read/write cycle time
  • Independent Read and Write operations Standard or First Word Fall Through mode
  • Bus - Matching and Endian selection
  • Empty, Full, Half - Full and Programmable Almost - Empty, Almost - Full Flags
  • Dept h and width expandable
  • Output enable (data skipping)
  • Master Reset clears entire FIFO
  • Partial Reset, clears data
  • Zero Latency Retransmit
  • 3.3V power supply with 5V tolerant inputs
  • Available in a 80 - pin thin quad flat pack (TQFP)

A VER L OGIC T ECHNOLOGIES , I NC . TEL : 1 408 361 - 0400 e - mail: sales@averlogic.com URL: www.averlogic.com 11/6/2002 ( 8k,16k,32k,64k) x18/ (16k,32k, 64k,128k) x9 Memory Array Input Buffer Output Buffer Write Control Logic Read Control Logic Flag Logic Expansion Logic Write Pointer Read Pointer Offset Regissers Reset Logic Input data bus Output data bus /OE WCLK /WEN /LD /RST RCLK /REN /FF /EF /HF /PAF /PAE /WXO /RXO /WXI /RXI AL4CX2x3 FIFO Block Diagram AL4CX2x3 FIFO memory is AverLogic Technologies, latest products that is designed to buffer high - speed data for a wide range of application such as optical storage controllers, Networking Switc hes and various communication applications. The embedded memory array with built - in address decoder, pointer manager and state - of - the - art circuits provide an easy - to - use interface to serial read/write memory and offer a flexible way to manage memory in th e system design. The input port of the FIFO is controlled by a free running clock (WCLK), and an input enable (/WEN). The output port is controlled by another clock (RCLK) and an output enable (/REN). Data is read into or output from FIFO synchronous o n every individual WRCK or RCLK clock cycle when /WEN or /REN is asserted respectively. These FIFOs support selectable bus width up to 18bit for both input and output ports and can be configured as x18 to x18, x18 to x9, x9 to x18 and x9 to x9 multiple in put and output port bus width. This allows for easy conversion of the bus width between the input flow and output flow. There are two fixed flags, Empty Flag/Output Ready and Full Flag/Input Ready, and two programmable flags, Almost - Empty and Almost - Full . The flags enable further manipulation of the synchronous control. Multiple AL4CX2x3s can be cascaded to expand the storage depth or can be used in parallel to expand bus width. The FIFOs are 3.3 - volt devices with 5 - volt input tolerance. And are avai lable in the 80 - pin thin quad flat Pack (TQFP Package). D ISTRIBUTED BY :