AL4CS211_1 AVERLOGIC | Alldatasheet

Document overview

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Technical content

Features

  • High performance, low - power, FIFO(First - In First - Out) memory
  • 512 x9 bit I/O port (AL4CS211)
  • 1K x9 bit 1/O port (AL4CS221)
  • 2K x9 bit I/O port (AL4CS231)
  • 4K x9 bit I/O port (AL4CS241)
  • 8K x9 bit I/O po rt (AL4CS251)
  • High clock speed ( 133MHz)
  • Fully independent read/write access
  • Empty, Full, and programmable Almost Empty, Almost Full flags
  • Output enable control (data skipping)
  • 3.3V power with 5V signal toleran t input
  • Standard 32 - pin TQFP and PLCC

A VER L OGIC T ECHNOLOGIES , I NC . TEL : 1 408 361 - 0400 e - mail: sales@averlogic.com URL: www.averlogic.com April 5, 200 2 (512, 1k ,2k, 4k, 8k) x9 Memory Array Input Buffer Output Buffer Write Control Logic Read Control Logic Flag Logic Write Pointer Read Pointer Offset Regissers Reset Logic Input data bus Output data bus /OE WCLK /WEN1 /LD /RS RCLK /REN1 /FF /EF /PAF /PAE AL4CS2x1 FIFO Block Diagram WEN2 /REN2 The 9bit input and output ports operate independently at a maximum speed of 133 MHz. The built - in address decoder and pointer managing circuits provide a straightforward bus interface to se rially read/write memory that reduces inter - chip design efforts. The AL4CS2x1 embedded memory array and high performance process technologies with extended controller functions (read skip, fixed and programmable status flags.. etc.) offer flexible memory m anagement. The input data is synchronous with a free - running clock (WCLK), and input - enable pins (/WEN1, /WEN2). Data is written into the FIFO on every clock when enable pins are asserted. The output is synchronous with the other free - running clock (RC LK) and enables (/REN1, /REN2). An Output Enable pin (/OE) is provided at the read port for tri - state control of the output port. The FIFOs can output two fixed flags, Empty Flag( /EF) and Full Flag (/FF), and two programmable flags, Almost - Empty (/PAE ) and Almost - Full (/PAF). The offsets of the /PAE and /PAF flags are loaded when Load pin (/LD) goes low. These chips are available as a 32 - pin TQFP and PLCC Package. D ISTRIBUTED BY :