AL4CS205 AVERLOGIC | Alldatasheet
Document overview
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Technical content
Features
- High performance, low - power, FIFO(First - In First - Out) memory
- 256 x 18 bit I/O port (AL4CS205)
- 512 x 18 bit I/O port (AL4CS215)
- 1K x18 bit 1/O port (AL4CS225)
- 2K x18 bit I/O port (AL4CS235)
- 4K x18 bit I/O port (AL4CS245)
- High clock speed ( 133MHz)
- Fully independent read/write access
- Empty, Full, Half Full and programmable Almost Empty, Almost Full flags
- Output enable control (data skipping)
- Cascadable expansion in depth and width
- 3.3V ±10% power s upply with 5V signal tolerant input
- Standard 64 - pin TQFP and STQFP
A VER L OGIC T ECHNOLOGIES , I NC . TEL : 1 408 361 - 0400 e - mail: sales@averlogic.com URL: www.averlogic.com April 5, 2002 The 18bit input and output ports operate independently at a maximum speed of 133 MHz. The built - in address decoder and pointer managing circuits provide a straightforward bus interf ace to serially read/write memory that reduces inter - chip design efforts. The AL4CS2x5 embedded memory array and high performance process technologies with extended controller functions (read skip, fixed and programmable status flags.. etc.) offer flexible memory management. These FIFOs support up to 18bit input and output data bus - width that is controlled by separate clock and enable signals respectively. The input data is acquired at each rising edge of a free running write clock while a write enable control pin is asserted. The output data is available after each rising edge of a free running read clock while a read enable and output enable control pins are asserted. When output enable (/OE) is LOW, the data output bus is active. If /OE is HIGH, th e output data bus will be in a high - impedance. This signal can control whether the data is going to be skipped during the read operation. The FIFO Full/Empty, Half - Full and programmable Almost Full/Almost Empty flags are powerful functions that can help controlling software to manipulate the FIFO more easily or to do retransmit operation. Multiple AL4CS2x5s can cascade to expand the storage depth or provide a longer delay. The FIFOs can be chained by looping connect /WXO, /RXO pins of the first FIFO chi p to /WXI, /RXI pins of successive chips respectively and connect /WXO, /RXO pins of last cascading chip to /WXI, /RXI pins of the first FIFO chip. Expanding AL4CS2x5 data bus width is also possible by using multiple AL4CS2x5 chips in parallel. These chips are available as a 64pin TQFP and D ISTRIBUT ED BY : RAM ARRAY 256 x18, 512 x18 1024 x18, 2048 x18 4096 x18 Input Buffer Output Buffer Write Control Logic Read Control Logic Flag Logic Expansion Logic Write Pointer Read Pointer Offset Regissers Reset Logic Input data bus Output data bus /OE WCLK /WEN /LD /RS RCLK /REN /FF /EF /HF /PAF /PAE /WXO /RXO /WXI /RXI AL4CS205/215/225/235/245 FIFO Block Diagram