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AL422B_V01 AVERLOGIC | Alldatasheet

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Technical content

© 1999~2006 by AverLogic Technologies, Corp. Version 1.5 2 Amendments (Since April 2, 1999) 05-13-99 DC/AC characteristics (including current consumption) updated. 07-02-99 Pinout diagram (5.0) and DC external load (7.4) modified. 08-03-99 Description about TST pin added in sections 6.0 & 8.1. 09-02-99 8.3.2 Rewritten. 10-26-99 Capacitance provided in the AC characteristics section. 12-15-99 Remove TST pin restriction. Manipulation of FIFO Access”. 2. Add section “8.3.3 Single Field Write with Multiple Read Operation” 3. Add section “8.3.4 One Field Delay Line (The Old Data Read)” 02-28-02 Address and version update 03-20-02 Correct Pin-out diagram 02-20-03 Company Contact Information updated 04-27-04 1. Revised “5V or 3.3V power supply” in section “2.0 Features” 2. Revised “+5V/+3.3 volt” in section “4.0 Ordering Information” 3. Revised “5V or 3.3V” in section “6.0 Pin Description” 4. Revised section “7.0 Electrical Characteristics” 5. Revised section “8.2 5V and 3.3V application” 05-11-04 Include PB-free package “AL422B-PBF”

1.0 Description

The AL422 consists of 3M-bits of DRAM, and is configured as 393,216 words x 8 bit FIFO (first in first out). The interface is very user-friendly since all complicated DRAM operations are already managed by the internal DRAM controller. Current sources of similar memory (field memory) in the market provide limited memory size which is only enough for holding one TV field, but not enough to hold a whole PC video frame which normally contains 640x480 or 720x480 bytes. The AverLogic AL422 provides 50% more memory to support high resolution for digital PC graphics or video applications. The 50% increase in speed also expands the range of applications.

2.0 Features

384K (393,216) x 8 bits FIFO organization
Support VGA, CCIR, NTSC, PAL and HDTV resolutions
Independent read/write operations (different I/O data rates acceptable)
High speed asynchronous serial access
Read/write cycle time: 20ns
Access time: 15ns
Output enable control (data skipping)
Self refresh
5V or 3.3V power supply
Standard 28-pin SOP package

3.0 Applications

Multimedia systems
Video capture systems
Video editing systems
Scan rate converters
TV’s picture in picture feature
Time base correction (TBC)
Frame synchronizer
Digital video camera
Buffer for communications systems

4.0 Ordering Information

Part number Package Power Supply Status AL422B 28-pin plastic SOP +5/+3.3 volt Shipping AL422B-PBF 28-pin plastic SOP +5/+3.3 volt Shipping

5.0 Pinout Diagram

1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DI0 DI1 DI2 DI3 /WE GND TST /WRST WCK VDD DI4 DI5 DI6 DI7 DO0 DO1 DO2 DO3 /RE GND /OE /RRST RCK DEC DO4 DO5 DO6 DO7 AL422B-PBF pinout diagram AVERLOGIC AL422B XXXXX XXXX Lot Number Date Code Note: “PBF” to indicate it is Pb free package. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DI0 DI1 DI2 DI3 /WE GND TST /WRST WCK VDD DI4 DI5 DI6 DI7 DO0 DO1 DO2 DO3 /RE GND /OE /RRST RCK DEC DO4 DO5 DO6 DO7 AL422-04 422B pinout diagram AVERLOGIC AL422B XXXXX XXXX Lot Number Date Code

6.0 Pin Description

Pin name Pin # I/O type Function DI0~DI7 1~4, 11~14 input Data input WCK 9 Input Write clock /WE 5 Input (active low) Write enable /WRST 8 Input (active low) Write reset DO0~DO7 15~18, 25~28 Output (tristate) Data output RCK 20 Input Read clock /RE 24 Input (active low) Read enable /RRST 21 Input (active low) Read reset /OE 22 Input (active low) Output enable TST 7 Input Test pin (pulled-down)* VDD 10 5V or 3.3V DEC/VDD 19 Decoupling cap input GND 6, 23 Ground

7.0 Electrical Characteristics

7.1 Absolute Maximum Ratings

3.3V application 5V application Unit VDD Supply Voltage -1.0 ~ +4.5 -1.0 ~ +7.0 V VP Pin Voltage -1.0 ~ +5.5 -1.0 ~ VDD +0.5 V IO Output Current -20 ~ +20 -20 ~ +20 mA TAMB Ambient Op. Temperature 0 ~ +70 0 ~ +70 °C Tstg Storage temperature -55 ~ +125 -55 ~ +125 °C

7.2 Recommended Operating Conditions

3.3V application 5V application Parameter Min Max Min Max Unit VDD Supply Voltage +3.0 +3.6 +4.5 +5.25 V VIH High Level Input Voltage +2.0 +5.5 +3.0 VDD +0.5 V VIL Low Level Input Voltage -1.0 +0.8 -1.0 +0.8 V

7.3 DC Characteristics

(VDD =5V or 3.3V, Vss=0V. TAMB = 0 to 70°C) 3.3V application 5V application Parameter Min Typ Max Min Typ Max Unit IDD Operating Current @20MHz - 33 - - 50 - mA IDD Operating Current @30MHz - 45 - - 66 - mA IDD Operating Current @40MHz - 57 - - 82 - mA IDD Operating Current @50MHz - 68 - - 97 - mA IDDS Standby Current - 7 - - 12 - mA VOH Hi-level Output Voltage 0.7VDD - VDD +3.0 - VDD V VOL Lo-level Output Voltage - - +0.4 - - +0.4 V ILI Input Leakage Current -10 - +10 -10 - +10 µA ILO Output Leakage Current -10 - +10 -10 - +10 µA

7.4 AC Characteristics

(VDD =5V or 3.3V, Vss=0V, TAMB = 0 to 70°C) 3.3V application 5V application Parameter Min Max Min Max Unit TWC WCK Cycle Time 20 1000 20 1000 ns TWPH WCK High Pulse Width 7 - 7 - ns TWPL WCK Low Pulse Width 7 - 7 - ns TRC RCK Cycle Time 20 1000 20 1000 ns TRPH RCK High Pulse Width 7 - 7 - ns TRPL RCK Low Pulse Width 7 - 7 - ns

© 1999~2006 by AverLogic Technologies, Corp. Version 1.5 8 TAC Access Time - 15 - 15 ns TOH Output Hold Time 4 - 4 - ns THZ Output High-Z Setup Time 3 15 4 15 ns TLZ Output Low-Z Setup Time 3 15 4 15 ns TWRS /WRST Setup Time 5 - 6 - ns TWRH /WRST Hold Time 2 - 3 - ns TRRS /RRST Setup Time 5 - 6 - ns TRRH /RRST Hold Time 2 - 3 - ns TDS Input Data Setup Time 5 - 6 - ns TDH Input Data Hold Time 2 - 3 - ns TWES /WE Setup Time 5 - 6 - ns TWEH /WE Hold Time 2 - 3 - ns TWPW /WE Pulse Width 10 - 10 - ns TRES /RE Setup Time 5 - 6 - ns TREH /RE Hold Time 2 - 3 - ns TRPW /RE Pulse Width 10 - 10 - ns TOES /OE Setup Time 5 - 6 - ns TOEH /OE Hold Time 2 - 3 - ns TOPW /OE Pulse Width 10 - 10 - ns TTR Transition Time 2 20 3 20 ns CI Input Capacitance - 7 - 7 pF CO Output Capacitance - 7 - 7 pF

Input voltage levels are defined as VIH=3.0V and VIL=0.4V.
The read address needs to be at least 128 cycles after the write address. DO external load:

7.5 Timing Diagrams

cycle (s) cycle 0 cycle 1 WCK /WRST DI7~0 AL422-05 Write Cycle Timing (Write Reset) TTR TWRS TWRH n-1 n 0 1 TDS TDH RCK /RRST DO7~0 n-1 n TOH AL422-07 Read Cycle Timing (Read Reset) TRPH TRPL 0 1 cycle n Reset cycle (s) cycle 0 cycle 1 TRRS TRRH TAC

© 1999~2006 by AverLogic Technologies, Corp. Version 1.5 11 cycle n cycle n+1 cycle n+3 RCK /OE DO7~0 n-1 n AL422-09 Read Cycle Timing (Output Enable) TRPH TRPL TOES TOEHTRC n+1 TOPW TOH TAC cycle n+2 Hi-Z cycle n+4 n+4 THZ TLZ cycle n cycle n+1 Disable cycle (s) RCK /RE DO7~0 n-1 n AL422-08 Read Cycle Timing (Read Enable) TRPH TRPL TRES TREHTRC n+1 TRPW TOH TAC n+2 cycle n+2

© 1999~2006 by AverLogic Technologies, Corp. Version 1.5 12 cycle n cycle n+1 Disable cycle (s) WCK /WE DI7~0 n-1 n TDS TDH AL422-06 Write Cycle Timing (Write Enable) TWPH TWPL TWES TWEHTWC n+1 n+2 TWPW cycle n+2 cycle n cycle n+1 Disable cycle (s) RCK /RE DO7~0 n-1 n AL422-14 Read Cycle Timing (RE, RRST) TRPH TRPL TRES TREH TRC n+1 TRPW TOH TAC TRRS TRRH /RRST cycle 0

© 1999~2006 by AverLogic Technologies, Corp. Version 1.5 13 cycle n cycle n+1 Disable cycle (s) WCK /WE DI7~0 n-1 n TDS TDH AL422-15 Write Cycle Timing (WE, WRST) TWPH TWPL TWES TWEH TWC n+1 1 TWPW cycle 0 TWRS TWRH /WRST cycle 1

8.0 Functional Description

The AL422 is a video frame buffer consisting of DRAM that works like a FIFO which is long enough to hold up to 819x480 bytes of picture information and fast enough to operate at 50MHz. The functional block diagram is as follows: The I/O pinouts and functions are described as follows: DI7~DI0 Data Input : Data is input on the rising edge of the cycle of WCK when /WE is pulled low (enabled). DO7~DO0 Data Output: Data output is synchronized with the RCK clock. Data is obtained at the rising edge of the RCK clock when /RE is pulled low. The access time is defined from the rising edge of the RCK cycle. WCK Write Clock Input: The write data input is synchronized with this clock. Write data is input at the rising edge of the WCK cycle when /WE is pulled low (enabled). The internal write address pointer is incremented automatically with this clock input. RCK Read Clock Input: The read data output is synchronized with this clock. Read data output at the rising edge of the RCK cycle when /OE is pulled low (enabled). The internal re ad address pointer is incremented with this clock input. /WE Write Enable Input: /WE controls the enabling/disabling of the data input. When /WE is pulled low, input data is acquired at the rising edge of the WCK cycle. When /WE is pulled high, the memory does not accept data input. The write address pointer is stopped at the current position. /WE signal is fetched at the rising edge of the WCK cycle. 384k x8 Memory Cell Array Write Data Register Input Buffer Read Data Register Output Buffer Timing Generator & Arbiter Write Address Counter Read Address Counter Refresh Address Counter DI7~ DI0 DO7~ DO0 /OE RCK /RRST /RE WCK /WRST /WE AL422-03 Block Diagram

© 1999~2006 by AverLogic Technologies, Corp. Version 1.5 15 /RE Read Enable Input: /RE controls the operation of the data output. When /RE is pulled low, output data is provided at the rising edge of the RCK cycle and the internal read address is incremented automatically. /RE signal is fetched at the rising edge of the RCK cycle. /OE Output Enable Input: /OE controls the enabling/disabling of the data output. When /OE is pulled low, output data is provided at the rising edge of the RCK cycle. When /OE is pulled high, data output is disabled and the output pins remain at high impedance status. /OE signal is fetched at the rising edge of RCK cycle. /WRST Write Reset Input: This reset signal initializes the write address to 0, and is fetched at the rising edge of the WCK input cycle. /RRST Write Reset Input: This reset signal initializes the read address to 0, and is fetched at the rising edge of the RCK input cycle. TST Test Pin: For testing purpose only. It should be pulled low for normal applications. DEC: Decoupling cap pin, should be connected to a 1µF or 2.2µF capacitor to ground for 5V application. For 3.3V application, the DEC pin can be simply connected to the 3.3V power with regular 0.1µF bypass capacitor.

8.1 Memory Operation

Apply /WRST and /RRST 0.1ms after power on, then follow the following instructions for normal operation. Reset Operation The reset signal can be given at any time regardless of the /WE, /RE and /OE status, however, they still need to meet the setup time and hold time requirements with reference to the clock input. When the reset signal is provided during disabled cycles, the reset operation is not executed until cycles are enabled again. After WRST and RRST signals are pulled low, the data output and input start from address 0. Write Operation Data input DI7~DI0 is written into the write register at the WCK input when /WE is pulled low. The write data should meet the setup time and hold time requirements with reference to the WCK input cycle. Write operation is prohibited when /WE is pulled high, and the write address pointer is stopped at the current position. The write address starts from there when the /WE is pulled low again. The /WE signal needs to meet the setup time and hold time requirements with reference to the WCK input cycle.

© 1999~2006 by AverLogic Technologies, Corp. Version 1.5 16 Read Operation Data output DO7~DO0 is written into the read register at the RCK input when both /RE and /OE are pulled low. The output data is ready after TAC (access time) from the rising edge of the RCK input cycle. The read address pointer is stopped at the current position when /RE is pulled high, and starts there when /RE is pulled low again. /OE needs to be pulled low for read operations. When /OE is pulled high, the data outputs will be at high impedance stage. The read address pointer still increases synchronously with RCK regardless of the /OE status. The /RE and /OE signals need to meet the setup time and hold time requirements with reference to the RCK input cycle. When the new data is read, the read address should be between 128 to 393,247 cycles after the write address, otherwise the output may not be new data. 8.2 5V and 3.3V applications The AL422 can accept either 3.3V or 5V power with slightly different external configuration. The internal voltage regulator can convert 5V power to 3.3V for the embedded DRAM and logic circuitry when 5V power is applied to VDD pin (#10) only and leave the DEC pin (#19) decoupled by a capacitor of 1µF or 2.2µF to ground. The regulator can also be bypassed when 3.3V power is applied to both VDD and DEC pins. In either case the AL422 is 5V or 3.3V I/O tolerant. The 3.3V configuration consumes less power and is free from noise interference from the voltage regulator so may be more ideal for high -speed applications. Please note that using the AL422B with 5V configuration can directly replace the previous AL422V5; using it with 3.3V configuration can directly replace the previous AL422V3. No additional modification is required. The 5V configuration (direct replacement of the previous AL422V5) is as follows: VDD DEC AL422B 0.1uF 2.2uF

8.3 Restrictions

8.3.1 Irregular Read/Write

It is recommended that the WCK and RCK are kept running at least 1MHz at all times. The faster one of WCK and RCK is used as the DRAM refresh timing clock and has to be kept free running. When irregular FIFO I/O control is needed, keep the clock free running and use /WE or /RE to control the I/O as follows: The following drawing shows irregular clock and should be avoided: VDD DEC 3.3V AL422B 3.3V 0.1uF 0.1uF 10 19 Data /WE AL422-17 Slow Write - Correct WCK Data /WE AL422-16 Slow Write - Incorrect WCK

8.3.2 Read Enable during Reset Cycles

/RE should never be low at the rising edge of /RRST. The following cases are acceptable: The following cases should always be avoided: Please use the drawing AL422-14, Read Cycle Timing (RE, RRST) as enable/reset timing reference. /RRST /RE These cases are ok /RRST /RE These cases are not ok

9.0 Mechanical Drawing

28 PIN PLASTIC SOP:

Averlogic Technologies , Corp. E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw Averlogic Technologies, Inc. E-mail: sales_usa@averlogic.com URL: http://www.averlogic.com

Product Information

AL422B-PBF specifications and overview.

Summary

3M-Bits FIFO Field Memory

Description

3M-Bits FIFO Field Memory

Source title AL422B-PBF Datasheet(PDF) - AverLogic Technologies Inc

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