AK4413EQP

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CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 1 - GENERAL DESCRIPTION AK4413 is a 24-bit DAC, which corresponds to BD systems. An internal circuit includes newly developed 24bit Digital Filter for better sound quality achiev ing low distortion charac teristics and wide dynamic range. The AK4413 has full differential SCF outputs, removing the need for AC coupling capacitors and increasing performance for systems with excessive clock jitter. The AK4413 accepts 216kHz PCM data, ideal for a wide range of applications including DVD-Audio.

FEATURES

• 128x Over sampling
• Sampling Rate: 30kHz ∼ 216kHz
• 24Bit 8x Digital Filter - Ripple: ±0.005dB, Attenuation: 80dB - High Quality Sound Short Delay Option; GD=7/fs and GD=5.5/fs - Sharp Roll-Off Filter - Slow Roll-Off Filter
• High Tolerance to Clock Jitter
• Low Distortion Differential Output
• Digital De-emphasis for 32, 44.1, 48kHz sampling
• Soft Mute
• Digital Attenuator (255 levels and 0.5dB step)
• Stereo Mode
• THD+N: -102dB
• DR, S/N: 120dB (Stereo mode: 123dB)
• I/F Format: 24-bit MSB justified, 16/20/24bit LSB justified, I 2S, TDM
• Master Clock: 30kHz ~ 32kHz: 1152fs 30kHz ~ 54kHz: 512fs or 768fs 30kHz ~ 108kHz: 256fs or 384fs 108kHz ~ 216kHz: 128fs or 192fs
• Power Supply: DVDD=AVDD=2.7 ∼ 3.6V, VDD1/2=4.75 ∼ 5.25V
• Digital Input Level: CMOS
• Package: 44pin LQFP AK4413 High Performance 120dB 24-Bit 4ch DAC = Preliminary =

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 2 - ■ Block Diagram MCLK SDTI1 CSN/SMUTE BICK CCLK/DEM0 CDTI/DEM1 ACKS/DZF2 VSS VDD1 PDN AVDD Clock Divider DVSSDVDD CAD0/SD CAD1/DIF0 PSN DZF1/DIF1 DIF VSS2 AOUTRN1 VREFH1 VREFL1 AVSS AOUTLP1 AOUTLN1 AOUTRP1 PCM Data Interface Interpolator Control Register SCF SCF AOUTRN VREFH2 VREFL2 AOUTLP2 AOUTLN2 AOUTRP2 ΔΣ Modulator Vref VDD2 VCOM2 VCOM1 TDM0 SDTI2 Interpolator DATT Soft Mute SCF SCF ΔΣ Modulator Vref DATT Soft Mute Bias SLOW TDM1 Block Diagram

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 3 - ■ Ordering Guide AK4413EQ −10 ∼ +70°C 44pin LQFP (0.8mm pitch) AKD4413 Evaluation Board for AK4413 ■ Pin Layout VDD1 VSS1 AOUTL1N AOUTL1P 36 VCM1 37 TSTO1 38 TSTO2 39 AVDD 40 AVSS 41 MCLK 42 DVSS 43 DVDD 44 VREFL1 32 VREFH1 31 AOUTR1N 30 AOUTR1P 29 NC 28 AOUTL2P 27 AOUTL2N 26 VREFH2 25 VREFL2 24 VSS2 23 PDN 1 TDM1

2 BICK

3 SDATA1

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 4 - PIN/FUNCTION No. Pin Name I/O Function

1 PDN I

When at “L”, the AK4413 is in power-down mode and is held in reset. The AK4413 should always be reset upon power-up.

2 BICK I Audio Serial Data Clock in PCM Mode

3 SDATA1 I Audio Serial Data Input in PCM Mode

4 SDATA2 I Audio Serial Data Input in PCM Mode

5 TDM1 I TDM I/F Format Mode in PCM Mode

6 LRCK I L/R Clock in PCM Mode

Soft Mute in Parallel Control Mode When this pin goes to “H”, soft mute cycle is initiated. When returning to “L”, the output mute releases. CSN I Chip Select in Serial Control Mode SD Digital Filter setting pin in Parallel Control mode 8 CAD0 I Chip Address 0 in Serial Control Mode (Internal pull-down pin) DEM0 I De-emphasis Enable 0 in Parallel Control Mode 9 CCLK I Control Data Clock in Serial Control Mode DEM1 I De-emphasis Enable 1 in Parallel Control Mode 10 CDTI I Control Data Input in Serial Control Mode DIF0 I Digital Input Format 0 in PCM Mode 11 CAD1 I Chip Address 1 in Serial Control Mode DIF1 I Digital Input Format 1 in PCM Mode 12 DZF1 O Zero Input Detect in Serial Control Mode

13 DIF2 I Digital Input Format 2 in PCM Mode

14 PSN I Parallel/Serial Select (Internal pull-up pin)

“L”: Serial Control Mode, “H”: Parallel Control Mode ACKS I Auto Clock Setting Mode in Parallel Control mode “L”: Manual Setting Mode, “H”: Auto Setting Mode 15 DZF2 O Zero Input Detect in Serial Control Mode

16 TDM0 I TDM I/F Format Mode in Parallel Control mode

17 SLOW I Digital filter setting pin

18 TEST - No internal bonding. Connect to DVSS.

19 VCM2 - Common Voltage 2

Normally connected to VSS with a 10uF electrolytic cap.

20 AOUTR2P O Right Channel Positive Analog Output 2

21 AOUTR2N O Right Channel Negative Analog Output 2

22 VDD2 - Analog Power Supply, 4.75 to 5.25V

23 VSS2 - Ground (connected to DVSS, AVSS, VSS1 ground)

24 VREFL2 I Low Level Voltage Reference Input 2

25 VREFH2 I High Level Voltage Reference Input 2

26 AOUTL2N O Left Channel Negative Analog Output 2

27 AOUTL2P O Left Channel Positive Analog Output 2

28 NC - No internal bonding. Connect to GND.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 5 - No. Pin Name I/O Function

29 AOUTR1P O Right Channel Positive Analog Output 1

30 AOUTR1N O Right Channel Negative Analog Output 1

31 VREFH1 I High Level Voltage Reference Input 1

32 VREFL1 I Low Level Voltage Reference Input 1

33 VSS1 - Connected to DVSS, AVSS, VSS2 Ground

34 VDD1 - Analog Power Supply Pin, 4.75 ∼ 5.25V

35 AOUTL1N O Left Channel Negative Analog Output 1

36 AOUTL1P O Left Channel Positive Analog Output 1

37 VCM1 - Common Voltage 1

Normally connected to VSS with a 10uF electrolytic cap. 38 TSTO1 I Test Output pin. “Hi-Z” at Normal Operation. Connect to AVSS. 39 TSTO2 I Test Output pin. “Hi-Z” at Normal Operation. Connect to AVSS. 40 AVDD - Analog Power Supply, 2.7 to 3.6V

41 AVSS - Analog Ground Pin

42 MCLK I Master Clock Input

43 DVSS - Digital Ground Pin

44 DVDD - Digital Power Supply, 3.0 ∼ 3.6V Note: All input pins except internal pull-up/down pins should not be left floating.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 6 - ■ Handling of Unused Pin The unused I/O pins should be processed appropriately as below. (1) Parallel Mode Classification Pin Name Setting AOUTL1P, AOUTL1N These pins must be open. AOUTR1P, AOUTR1N These pins must be open. AOUTL2P, AOUTL2N These pins must be open. Analog AOUTR2P, AOUTR2N These pins must be open. Analog TSTO1,TSTO2 This pin must be connected to AVSS Digital TEST This pin must be connected to DVSS (2) Serial Mode Classification Pin Name Setting AOUTL1P, AOUTL1N These pins must be open. AOUTR1P, AOUTR1N These pins must be open. AOUTL2P, AOUTL2N These pins must be open. Analog AOUTR2P, AOUTR2N These pins must be open. Analog TSTO1,TSTO2 This pin must be connected to AVSS DIF2,PSN,TDM0,SLOW,TEST This pin must be connected to DVSS Digital DZF1, DZF2 These pins must be open.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 7 - ABSOLUTE MAXIMUM RATINGS (VSS1-2=AVSS=DVSS=0V; Note 1) Parameter Symbol min max Unit Power Supplies: Analog Analog Digital |AVSS − DVSS| AVDD VDD1/2 DVDD ΔGND −0.3 −0.3 −0.3 4.6 6.0 4.6 0.3 V V V V Input Current, Any Pin Except Supplies IIN - ±10 mA Digital Input Voltage VIND −0.3 DVDD+0.3 V Ambient Temperature (Power applied) Ta −10 70 °C Storage Temperature Tstg −65 150 °C Note 1. All voltages with respect to ground. Note 2. AVSS, VSS1/2, DVSS must be connected to the same analog ground plane. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (VSS1-2=AVSS=DVSS=0V; Note 1) Parameter Symbol min typ max Unit Power Supplies (Note 3) Analog Analog Digital AVDD VDD1/2 DVDD 2.7 4.75 2.7 3.0 5.0 3.0 3.6 5.25 3.6 V V V Voltage Reference (Note 4) “H” voltage reference “H” voltage reference “L” voltage reference “L” voltage reference VREFH1 VREFH2 VREFL1 VREFL2 VDD1−0.5 VDD2-0.5 AVSS AVSS VDD1 VDD2 V V V V Note 1. All voltages with respect to ground. Note 3. The power up sequence between AVDD, VDD1/2 and DVDD is not critical. Note 4. The analog output voltage scales with the voltage of (VREFH1/2 − VREFL1/2). Connect a resistor of 20ohm or less and a capacitor of 100uF or more to the VREFH1/2 pin. ( Figure 19) AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH1/2 − VREFL1/2)/5. * AKM assumes no responsibility for the usage beyond the conditions in this data sheet.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 8 - ANALOG CHARACTERISTICS (Ta=25°C; AVDD=DVDD=3.0V, VDD1/2=5.0V; AVSS=VSS1/2=DVSS=0V; VREFH1/2=VDD1/2, VREFL1/2= AVSS; Input data = 24bit; RL ≥ 1kΩ; BICK=64fs; Signal Frequency = 1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure 22; unless otherwise specified.) Parameter min typ max Unit Resolution - - 24 Bits Dynamic Characteristics (Note 5) fs=44.1kHz BW=20kHz 0dBFS −60dBFS -102 -57 -95 dB dB fs=96kHz BW=40kHz 0dBFS −60dBFS -99 -54 dB dB THD+N fs=192kHz BW=40kHz BW=80kHz 0dBFS −60dBFS −60dBFS -99 -54 -51 dB dB dB Dynamic Range (−60dBFS with A-weighted) (Note 6) TBD 120 dB S/N (A-weighted) (Note 7) TBD 120 dB Interchannel Isolation (1kHz) TBD 110 dB DC Accuracy Interchannel Gain Mismatch - 0.15 0.3 dB Gain Drift (Note 8) - 20 - ppm/ °C Output Voltage (Note 9) TBD ±2.8 TBD Vpp Load Capacitance - - 10 pF Load Resistance (Note 10) 1 - - k Ω Power Supplies Power Supply Current Normal operation (PDN pin = “H”) VDD1+VDD2 AVDD DVDD (fs ≤ 44.1kHz) DVDD (fs=96kHz) DVDD (fs = 192kHz) TBD TBD TBD TBD TBD mA mA mA mA mA Power down (PDN pin = “L”) ( Note 11) AVDD+VDD1/2+DVDD TBD μA Note 5. Measured by Audio Precision, System Two. Averaging mode. Refer to the evaluation board manual. Note 6. Figure 22 External LPF Circuit Example 2. 100dB for 16-bit data. Note 7. Figure 22 External LPF Circuit Example 2. S/N does not depend on input data size. Note 8. The voltage on (VREFH1/2 − VREFL1/2) is held +5V externally. Note 9. Full scale voltage (0dB). Output voltage scales with the voltage of (VREFH1/2 − VREFL1/2). AOUT (typ.@0dB) = (AOUT+) − (AOUT−) = ±2.8Vpp × (VREFH1/2 − VREFL1/2)/5. Note 10. Regarding Load Resistance, AC load is 1kΩ (min) with a DC cut capacitor (Figure 22). DC load is 1.5kΩ (min) without a DC cut capacitor (Figure 21). The load resistance value is with respect to ground. Analog characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the capacitive load must be minimized. Note 11. In the power down mode. The PSN pin = DVDD, and all other digital input pins including clock pins (MCLK, BICK and LRCK) are held DVSS.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 9 - SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“0”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 22.05 20.0 kHz kHz Stopband (Note 12) SB 24.1 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 80 dB Group Delay (Note 13) GD - 29 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz - ±0.2 - dB SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“0”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 48.0 43.5 kHz kHz Stopband (Note 12) SB 52.5 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 80 dB Group Delay (Note 13) GD - 29 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz - ±0.3 - dB SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) bit=“0”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 96.0 87.0 kHz kHz Stopband (Note 12) SB 105 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 80 dB Group Delay (Note 13) GD - 29 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz - −1/+0 - dB Note 13. The calculating delay time which occurred by digital filtering. This time is from setting the 16/20/24-bit data of both channels to input register to the output of analog signal.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 10 - SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit=“1”, SD bit = “0”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 14) ±0.04dB −3.0dB PB 18.2 8.1 kHz kHz Stopband (Note 14) SB 39.2 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 73 dB Group Delay (Note 13) GD - 6 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 20.0kHz - −5/+0.1 - dB SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode DEM=OFF; SLOW bit=“1”, SD bit = “0”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 14) ±0.04dB −3.0dB PB 39.6 17.7 kHz kHz Stopband (Note 14) SB 85.3 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 73 dB Group Delay (Note 13) GD - 6 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 40.0kHz - −4/+0.1 - dB SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit=“1”, SD bit = “0”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 14) ±0.04dB −3.0dB PB 79.1 35.5 kHz kHz Stopband (Note 14) SB 171 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 73 dB Group Delay (Note 13) GD - 6 - 1/fs Digital Filter + SCF Frequency Response: 0 ∼ 80.0kHz - −5/+0.1 - dB

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 11 - SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“1”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 22.05 20.0 kHz kHz Stopband (Note 12) SB 24.1 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 80 dB Group Delay (Note 13) GD - 7 - 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 20.0kHz - ±0.2 - dB SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“1”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 48.0 43.5 kHz kHz Stopband (Note 12) SB 52.5 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 80 dB Group Delay (Note 13) GD - 7 - 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 40.0kHz - ±0.3 - dB SHORT DELAY SHARP ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “0”, SD bit=“1”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 96.0 87.0 kHz kHz Stopband (Note 12) SB 105 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 80 dB Group Delay (Note 13) GD - 7 - 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 80.0kHz - −1/+0 - dB

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 12 - SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 44.1kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Normal Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“1”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 22.3 11.1 kHz kHz Stopband (Note 12) SB 38.1 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 82 dB Group Delay (Note 13) GD - 5.5 - 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 20.0kHz - −5/+0.1 - dB SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 96kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Double Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“1”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 44.6 24.2 kHz kHz Stopband (Note 12) SB 83.0 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 82 dB Group Delay (Note 13) GD - 5.5 - 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 40.0kHz - −5/+0.1 - dB SHORT DELAY SLOW ROLL-OFF FILTER CHARACTERISTICS (fs = 192kHz) (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V; Quad Speed Mode; DEM=OFF; SLOW bit = “1”, SD bit=“1”) Parameter Symbol min typ max Unit Digital Filter Passband (Note 12) ±0.01dB −6.0dB PB 89.2 48.4 kHz kHz Stopband (Note 12) SB 165.9 kHz Passband Ripple PR ±0.005 dB Stopband Attenuation SA 82 dB Group Delay (Note 13) GD - 5.5 - 1/fs Digital Filter + SCF Frequency Response : 0 ∼ 80.0kHz - −5/+0.1 - dB

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 13 - DC CHARACTERISTICS (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V) Parameter Symbol min typ max Unit High-Level Input Voltage Low-Level Input Voltage VIH VIL 70%DVDD 30%DVDD V V High-Level Output Voltage (Iout=−100μA) Low-Level Output Voltage (Iout=100μA) VOH VOL DVDD−0.5 0.5 V V Input Leakage Current (Note 15) Iin - - ±10 μA Note 15. The PSN pin has an internal pull-up device nominally 100kΩ. Therefore the PSN pin is not included.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 14 - SWITCHING CHARACTERISTICS (Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V) Parameter Symbol min typ max Unit Master Clock Timing Frequency Duty Cycle fCLK dCLK 2.048 41.472 MHz LRCK Frequency (Note 16) Normal Mode (TDM0= “L”, TDM1= “L”) 1152fs, 512fs or 768fs 256fs or 384fs 128fs or 192fs Duty Cycle fsn fsd fsq Duty 108 108 216 kHz kHz kHz TDM256 mode (TDM0= “H”, TDM1= “L”) Normal Speed Mode High time Low time fsn tLRH tLRL 1/256fs 1/256fs kHz ns ns TDM128 mode (TDM0= “H”, TDM1= “H”) Normal Speed Mode Double Speed Mode Quad Speed Mode High time Low time fsn fsd fsq tLRH tLRL 108 1/128fs 1/128fs 108 216 kHz kHz kHz ns ns PCM Audio Interface Timing Normal Mode (TDM0= “L”, TDM1= “L”) BICK Period 1152fs, 512fs or 768fs 256fs or 384fs 128fs or 192fs BICK Pulse Width Low BICK Pulse Width High BICK “↑” to LRCK Edge ( Note 17) LRCK Edge to BICK “↑” (Note 17) SDATA Hold Time SDATA Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/64fsd 1/64fsq ns ns ns ns ns ns ns ns ns TDM256 mode (TDM0= “H”, TDM1= “L”) BICK Period Normal Speed Mode BICK Pulse Width Low BICK Pulse Width High BICK “↑” to LRCK Edge (Note 17) LRCK Edge to BICK “↑” (Note 17) SDATA1/2 Hold Time SDATA1/2 Setup Time tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/256fsn ns ns ns ns ns ns ns

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 15 - TDM128 mode (TDM0= “H”, TDM1= “H”) BICK Period Normal Speed Mode Double Speed Mode Quad Speed Mode BICK Pulse Width Low BICK Pulse Width High BICK “↑” to LRCK Edge ( Note 17) LRCK Edge to BICK “↑” (Note 17) SDATA1/2 Hold Time SDATA1/2 Setup Time tBCK tBCK tBCK tBCKL tBCKH tBLR tLRB tSDH tSDS 1/128fsn 1/128fsd 1/128fsq ns ns ns ns ns ns ns ns ns Control Interface Timing CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN High Time tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH 200 150 ns ns ns ns ns ns ns ns Reset Timing PDN Pulse Width (Note 18) tPD 150 ns Note 16. When the 1152fs, 512fs or 768fs /256fs or 384fs /128fs or 192fs are switched, the AK4413 should be reset by the PDN pin or RSTN bit. Note 17. BICK rising edge must not occur at the same time as LRCK edge. Note 18. The AK4413 can be reset by bringing the PDN pin “L” to “H” upon power-up.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 16 - ■ Timing Diagram 1/fCLK tCLKL VIH tCLKH MCLK VIL dCLK=tCLKH x fCLK, tCLKL x fCLK 1/fs VIH LRCK VIL tLRLtLRH Duty=tLRH x fs, tLRL x fs tBCK tBCKL VIH tBCKH BICK VIL Clock Timing tLRB LRCK VIH BICK VIL tSDS VIH SDATA1/2 VIL tSDH VIH VIL tBLR Audio Interface Timing (PCM Mode)

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 17 - tCSS CSN VIH CCLK VIL VIH CDTI VIL VIH VIL C1 C0 R/W A4 tCCKL tCCKH tCDS tCDH WRITE Command Input Timing CSN VIH CCLK VIL VIH CDTI VIL VIH VIL D3 D2 D1 D0 tCSW tCSH WRITE Data Input Timing tPD PDN VIL Power Down & Reset Timing

AK4413 is in power-down mode until MCLK and LRCK are supplied. required to be provided as input and are shown in (Table 2). Table 1. Sampling Speed (Manual Setting Mode @Parallel Mode) Table 2. System Clock Example (Manual Setting Mode @Parallel Mode), (N/A: Not available)

1. Auto Setting Mode (ACKS pin = “H”)

the correct frequency according to Table 4. Table 3. Sampling Speed (Auto Setting Mode @Parallel Mode) Table 4. System Clock Example (Auto Setting Mode @Parallel Mode), (N/A: Not available) 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. Table 5. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) Table 6. Digital Filter Setting (Parallel Mode)

1. Manual Setting Mode (ACKS bit = “0”)

Mode at power-up (PDN pin = “L” →“H”). When DFS1-0 bits are changed, the AK4413 should be reset by RSTN bit. Table 7. Sampling Speed (Manual Setting Mode @Serial Mode) Table 8. System Clock Example (Manual Setting Mode @Serial Mode)

1. Auto Setting Mode (ACKS bit = “1”)

frequency corresponding to each sampling speed should be provided externally (Table 10). Table 9. Sampling Speed (Auto Setting Mode @Serial Mode) Table 10. System Clock Example (Auto Setting Mode @Serial Mode)

32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs. Table 11. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz) Table 12. Digital Filter Setting (Serial Mode)

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 22 - ■ Audio Interface Format [1] PCM Mode (1) Parallel Control Mode (PSN pin = “H”) Ten formats are selectable by DIF2-0 and TDM1-0 pins (Table 13). In this mode, register settings are ignored. In all formats the serial data is MSB-first, 2's compliment format and is latched on the rising edge of BICK. Mode 2 can be used for 20 and 16 MSB justified formats by zeroing the unused LSBs. If TDM1-0 pins = “LH” the audio interface is TDM256 mode (Table 13) and all eight channels of DAC data are input to the SDTI1 pin (Figure 15). The input data to the SDTI2 pin is ignored. BICK is fixed to 256fs, “H” time and “L” time of LRCK should be 1/256fs at least. The data format is MSB first, 2’s complement and the SDTI1 is latched on the rising edge of BICK. Only the first four channels of DAC data may be selected to be converted into four channels of DAC analog output. If TDM1-0 pins = “HH” the audio interface is TDM128 mode (Table 13) and the serial data of DAC (four channels: L1, R1, L2, R2) is input to the SDTI1 pin (Figure 14). The input data to the SDTI2 pin is ignored. (2) Serial Control Mode (PSN pin = “L”) Ten formats are selected by setting DIF2-0 and TDM1-0 bits (Table 13). The initial setting of DIF2-0 bits is “010”. In this mode, the DIF1 pin setting is ignored. If TDM1-0 bits = “01b” the audio I/F format is TDM256 mode (Table 13) and all the serial data of eight DAC channels are input to the SDTI1 pin (Figure 15). The input data to the SDTI2 pin is ignored. BICK is fixed to 256fs, high and low amplitude of LRCK is 1/256fs (min). The data format is MSB first, 2’s complement and the SDTI1 is latched on the rising edge of BICK. The eight channels of DAC data may be mapped to two pieces of AK4413 (Table 14). If TDM1-0 bits = “11b” the audio I/F format is TDM128 mode (Table 13) and the serial data of DAC (four channels: L1, R1, L2, R2) is input to the SDTI1 pin and other serial data of DAC (four channels: L3, R3, L4, R4) are input to the SDTI2 pin ( Figure 14). BICK is fixed to 128fs. The data format is MSB first and 2’s complement and the input data to SDTI1-2 pins are latched on the rising edge of BICK. The eight channels of DAC data may be mapped to two pieces of AK4413 (Table 14).

1 X X 24-bit LSB justified H/L ≥48fs

1 X X 24-bit LSB justified ↑ 256fs

1 X X 24-bit LSB justified ↑ 128fs

Table 13. Audio Interface Format

Figure 4. Mode 3 Timing

32 BICK

256 BICK

Figure 5. Mode 8 Timing Figure 6. Mode 9 Timing

Figure 7. Mode 10 Timing

128 BICK

Figure 8. Mode 14 Timing Figure 9. Mode 15/19 Timing

Figure 10. Mode 16 Timing

Figure 11. Data Slot in Normal Mode Figure 12. Data Slot in TDM128 Mode Figure 13. Data Slot in TDM256 Mode Table 14. Data Select

The DEM1 and DEM0 pins control de-emphasis mode of DAC1 and DAC2. This setting is common for both of DAC’s. In parallel mode, the filter setting cannot be applied independently. Table 15. De-emphasis Control (Parallel Mode) DEM1-0 bits and DEM3-2 bits control de-emphasis mode of DAC1 and DAC2, respectively. Table 16. DAC1 De-emphasis Control (Serial Mode) Table 17. DAC2 De-emphasis Control (Serial Mode) The AK4413 includes channel independent digital output volumes (ATT) with 255 levels at 0.5dB step including MUTE. “0”, the attenuation level is initialized to FFH, and the attenuation level returns to the setting value by RSTN bit = “1”. Table 18. ATT Transition Time

“L”. The DZFB bit can invert the polarity of the DZF pin. In parallel control mode, the zero detect function is unavailable. DZF1 Zero Detection flag output of the channels set by register 08H. DZF2 Zero Detection flag output of the channels set by register 09H. Table 19. DZF pin function are available for any audio format. Table 20. Output Select for DAC1

Table 21. Output Select for DAC2

changing the signal source without stopping the signal transmission. (2) The analog output corresponding to the digital input has group delay (GD). and returned to ATT level by the same cycle. goes to “H”. The DZF pin immediately returns to “L” if input data are not zero. Figure 14. Soft Mute Function exits power-down mode. The digital block exits power-down mode after the internal counter counts MCLK for 4/fs.

muted externally if the click noise influences system application. externally if click noise aversely affect system performance. (1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns. (2) The analog output corresponding to digital input has group delay (GD). (3) Analog outputs are floating (Hi-Z) in power-down mode. (4) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input. (5) MCLK, BICK and LRCK clocks can be stopped in power-down mode (PDN pin= “L”). The timing example is shown in this figure. (7) DZF1/2 pins are “L” in the power-down mode (PDN pin = “L”). Figure 15. Power-down/up Sequence Example

When the RSTN bit = “0”, the AK4413’s digital block is powered down, but the internal register values are not initialized. (1) The analog output corresponding to digital input has group delay (GD). (2) Analog outputs settle to VCOM voltage. Figure 16. Reset Sequence Example 1

and starts the operation. Zero detect function is disable when MCLK or LRCK is stopped. (1) After AVDD and DVDD are powered-up, the PDN pin should be “L” for 150ns. (2) The analog output corresponding to digital input has group delay (GD). “0” data during this period. noise occurs even when “0” data is input. (5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset state (MCLK or LRCK is stopped). Figure 17. Reset Sequence Example 2

mode, the register setting is ignored, and in serial control mode the pin settings are ORed if the pin is not repurposed. is valid when CSN “↑”. The clock speed of CCLK is 5MHz (max). Table 22. Function List 1 (Y: Available, -: Not available) reset by the RSTN bit, but the registers are not initialized. Figure 18. Control I/F Timing

• The AK4413 does not support the read command.

Table 23. Function List 2

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 38 - ■ Register Map Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN 01H Control 2 0 0 SD DFS1 DFS0 DEM1 DEM0 SMUTE 02H Control 3 0 0 0 0 MONO DZFB SELLR1 SLOW 03H L1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H R1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 0 0 06H L2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H R2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 08H DZF1 Control L1 R1 L2 R2 0 0 0 0 09H DZF2 Control L1 R1 L2 R2 0 0 0 0 0AH Control 5 TDM1 TDM0 SDS1 SDS2 PW2 PW1 DEM3 DEM2 Notes: Data must not be written into addresses from 0BH to 1FH. When the PDN pin goes to “L”, the registers are initialized to their default values. When RSTN bit is set to “0”, only the internal timing is reset, and the registers are not initialized to their default values. When the state of the PSN pin is changed, the AK4413 should be reset by the PDN pin. ■ Register Definitions Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 00H Control 1 ACKS 0 0 0 DIF2 DIF1 DIF0 RSTN Default 0 0 0 0 0 1 0 1 RSTN: Internal Timing Reset 0: Reset. All registers are not initialized. 1: Normal Operation (default) Internal clock timings are reset but registers are not reset. DIF2-0: Audio Data Interface Modes (Table 13) Initial value is “010” (Mode 2: 24-bit MSB justified). ACKS: Master Clock Frequency Auto Setting Mode Enable (PCM only) 0: Disable : Manual Setting Mode (default) 1: Enable : Auto Setting Mode When ACKS bit = “1”, the sampling frequency and MCLK frequency are detected automatically.

Initial value is “01” (OFF). SD: Short delay Filter Enable. Table 24. Digital Filter setting The default values are “00”. A click noise occurs when changing DFS1-0 bits.

SLOW: Slow Roll-off Filter Enable. This setting is ORed with the pin setting. Table 25. Digital Filter setting 1: All channel output R channel data, when MONO mode. When MONO bit is “1”, MONO mode is enabled.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 41 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 03H L1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 04H R1ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Default 1 1 1 1 1 1 1 1 ATT7-0: Attenuation Level 255 levels, 0.5dB step Data Attenuation FFH 0dB FEH -0.5dB FDH -1.0dB : : : : 02H -126.5dB 01H -127.0dB 00H MUTE (- ∞) The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is independent of soft mute function. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 05H Control 4 INVL1 INVR1 INVL2 INVR2 SELLR2 0 0 0 Default 0 0 0 0 0 0 0 0 SELLR2: The data selection of AOUTL2-R2, when MONO mode 0: AOUTL2-R2 output L channel data, when MONO mode. (default) 1: AOUTL2-R2 output R channel data, when MONO mode. When MONO bit is set to “1”, Lch data is output by SELLR2 bit = “0” and Rch data is output by SELLR2 bit = “1”. INVR2: AOUTR2 output phase invert bit 0: Disable (default) 1 : E n a b l e INVL2: AOUTL2 output phase invert bit 0: Disable (default) 1 : E n a b l e INVR1: AOUTR1 output phase invert bit 0: Disable (default) 1 : E n a b l e INVL1: AOUTL1 output phase invert bit 0: Disable (default) 1 : E n a b l e

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 42 - Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 06H L2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 07H R2ch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0 Default 1 1 1 1 1 1 1 1 ATT7-0: Attenuation Level 255 levels, 0.5dB step Data Attenuation FFH 0dB FEH -0.5dB FDH -1.0dB : : : : 02H -126.5dB 01H -127.0dB 00H MUTE (- ∞) The transition between set values is soft transition of 7425 levels. It takes 7424/fs (168ms@fs=44.1kHz) from FFH (0dB) to 00H (MUTE). If the PDN pin goes to “L”, the ATTs are initialized to FFH. The ATTs are FFH when RSTN bit= “0”. When RSTN return to “1”, the ATTs fade to their current value. This digital attenuator is independent of soft mute function. Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 08H DZF1 Control L1 R1 L2 R2 0 0 0 0 09H DZF2 Control L1 R1 L2 R2 0 0 0 0 Default 0 0 0 0 0 0 0 0 L1-2, R1-2: Zero Detect Flag Enable Bit for the DZF1-2 pins 0: Disable 1: Enable Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0 0AH Control 5 TDM1 TDM0 SDS1 SDS2 PW2 PW1 DEM3 DEM2 Default 0 0 0 0 0 1 0 0 DEM3-2: De-emphasis control for the DAC2-1 0: Disable 1: Enable PW2-1: Power Down control for DAC PW2: Power management for DAC2 PW1: Power management for DAC1 SDS1-2: DAC1and DAC2 data select 0: Normal Operation 1: Outputs other slot data Refer to Table 14 for details. TDM0-1: TDM Mode Select Mode TDM1 TDM0 BICK SDTI Sampling Speed Normal 0 0 32fs∼ 1-2 Normal, Double, Quad Speed TDM256 0 1 256fs fixed 1 Normal Speed TDM128 1 1 128fs fixed 1-2 Normal, Double, Quad Speed

33 VSS1

32 VREFL1

31 VREFH1

30 AOUTR1N

29 AOUTR1P

27 AOUTL2P

26 AOUTL2N

25 VREFH2

24 VREFL2

23 VSS2

Figure 20. Ground Layout

1. Grounding and Power Supply Decoupling

as near as possible to the supply pin. VREFH1/2 and VREFL1/2 pins in order to avoid unwanted noise coupling into the AK4413. The analog outputs are full differential outputs and 2.8Vpp (typ, VREFH1/2 − VREFL1/2 = 5V) centered around AVDD/2. Figure 21 shows an example of external LPF circuit summing the differential outputs by an op-amp. Figure 22 shows an example of differential outputs and LPF circuit example by three op-amps.

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 46 - PACKAGE 0.10 0.145±0.0550.37 10.0 1.60max 1 11 2333 44pin LQFP (Unit: mm) 10.0 12.0 0.80 12.0 0.10±0.05 0°∼7° 0.6±0.15 1.40 ±0.05 0.20 M +0.08 –0.07 S S 1.00 ■ Material & Lead finish Package molding compound: Epoxy, Halogen (bromine and chlorine) free L e a d f r a m e m a t e r i a l : C u Lead frame surface treatment: Solder (Pb free) plate

CONFIDENTIAL [AK4413] Rev. 0.3 2012/07 - 47 - MARKING AK4413EQ XXXXXXX AKM 1) Pin #1 indication 2) AKM Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK4413 5) Audio 4 pro Logo IMPORTANT NOTICE z These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status of the products. z Descriptions of external circuits, a pplication circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. You are fully responsible for the in corporation of these external circuits, app lication circuits, software and other related information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z Any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z AKM products are neither intended nor au thorized for use as critical components Note1) in any safety, life support, or other hazard related device or system Note2), and AKM assumes no resp onsibility for such use, except for the use approved with the express written consent by Representative Director of AKM. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.