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AGLP125V2-CS281I

Microsemi Corporation

IGLOO PLUS Low Power Flash FPGAs

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1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
5 µW Power Consumption in Flash*Freeze Mode
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content
Configurable Hold Previous State, Tristate, HIGH, or LOW State per I/O in Flash*Freeze Mode
Easy Entry To / Exit From Ultra-Low Power Flash*Freeze Mode Feature Rich
30 k to 125 k System Gates
Up to 36 kbits of True Dual-Port SRAM
Up to 212 User I/Os Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)†
FlashLock ® Designed to Secure FPGA Contents High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure Advanced I/O
Bank-Selectable I/O Voltages—4 Banks per Chip on All IGLOO® PLUS Devices
Single-Ended I/O Standards: LVTTL, LVCMOS
Selectable Schmitt Trigger Inputs
Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Small-Footprint Packages across the IGLOO PLUS Family Clock Conditioning Circuit (CCC) and PLL†
Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
True Dual-Port SRAM (except ×18) † † The AGLP030 device does not support this feature. Table 1 • IGLOO PLUS Product Family IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 System Gates 30,000 60,000 125,000 Typical Equivalent Macrocells 256 512 1,024 VersaTiles (D-flip-flops) 792 1,584 3,120 Flash*Freeze Mode (typical, µW) 5 10 16 RAM Kbits (1,024 bits) – 18 36 4,608-Bit Blocks – 4 8 Secure (AES) ISP – Yes Yes FlashROM Kbits 1 1 1 Integrated PLL in CCCs 1 – 1 1 VersaNet Globals 2 61 8 1 8 I/O Banks 4 4 4 Maximum User I/Os 120 157 212 Package Pins CS VQ CS201, CS289 VQ128 CS201, CS289 VQ176 CS281, CS289 Notes: 1. AGLP060 in CS201 does not support the PLL. 2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125. Revision 16

IGLOO PLUS Low Power Flash FPGAs I/Os Per Package 1 IGLOO PLUS Device Status IGLOO PLUS Devices AGLP030 AGLP060 AGLP125 Package Single-Ended I/Os CS201 120 157 – CS281 – – 212 CS289 120 157 212 VQ128 101 – – VQ176 – 137 – Note: When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single- ended user I/Os available is reduced by one. Table 2 • IGLOO PLUS FPGAs Package Size Dimensions Length × Width (mm/mm) 8 × 8 10 × 10 14 × 14 14 × 14 20 × 20 Nominal Area (mm2) 64 100 196 196 400 IGLOO PLUS Device Status AGLP030 Production AGLP060 Production AGLP125 Production

IGLOO PLUS Low Power Flash FPGAs Revision 16 III Notes: 1. Marking information: IGLOO PLUS V2 devices do not have a V2 marking, but IGLOO PLUS V5 devices are marked accordingly. 2. "G" indicates RoHS-compliant packages. Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only AGLP125 V2 CS _ Part Number Package Type

289 I Y

G Lead-Free Packaging Application (Temperature Range) Blank = Commercial (0°C to +70°C ambient temperature) I = Industrial ( –40°C to +85°C ambient temperature) Blank = Standard Packaging G= RoHS-Compliant Packaging PP= Pre-Production ES= Engineering Sample (room temperature only) 30,000 System GatesAGLP030 = 60,000 System GatesAGLP060 = 125,000 System GatesAGLP125 = CS = Chip Scale Package (0.5 mm and 0.8 mm pitches) VQ = Very Thin Quad Flat Pack (0.4 mm pitch) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio

IGLOO PLUS Low Power Flash FPGAs Temperature Grade Offerings Contact your local Microsemi SoC Products Group representative for device availability: http://www.microsemi.com/soc/company/contact/default.aspx. CS201 C, I C, I – CS281 –– C , I CS289 C , IC , IC , I VQ128 C, I – – VQ176 –C , I– Notes: 1. C = Commercial temperature range: 0°C to 70°C ambient temperature. 2. I = Industrial temperature range: –40°C to 85°C ambient temperature.

IGLOO PLUS Low Power Flash FPGAs Revision 16 V Table of Contents IGLOO PLUS Device Family Overview IGLOO PLUS DC and Switching Characteristics Pin Descriptions and Packaging Package Pin Assignments Datasheet Information

1 – IGLOO PLUS Device Family Overview General Description The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultra-low power mode that consumes as little as 5 µW whil e retaining the design information, SRAM content, registers, and I/O states. Flash*Freeze technolog y simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allo ws for ultra-low power c onsumption while the IGLOO PLUS device is completely functional in the syste m. This allows the IGLOO PLUS device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO PLUS dev ices the advantage of being a secure, low power, single-chip solution that is In stant On. IGLOO PLUS is reprogra mmable and offers time-to-market benefits at an ASIC-level unit cost. These features e nable designers to create high -density systems using existing ASIC or FPGA design flows and tools. IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212 user I/Os. The AGLP030 devices have no PLL or RAM support. Flash*Freeze Technology The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode. IGLOO PLUS devices do not need additional components to turn off I/Os or clocks while retaining t he design information, SRAM cont ent, registers, and I/O states. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the fi nal stages of manufacturing or in the field. The ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state, tristate, or set as HIGH or LOW. The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high- pin-count packages, make IGLOO PLUS devices the best fit for portable electronics. Flash Advantages Low Power IGLOO PLUS devices exhibit power characteristics sim ilar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA.

IGLOO PLUS Device Family Overview Security Nonvolatile, flash-based IGLOO PLUS devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO PLUS devices inco rporate FlashLock, which provides a unique combination of reprogrammabilit y and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO PLUS devices (except AGLP030) utilize a 128- bit flash-based lock and a separate AES key to provide the highest level of security in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO PLUS devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS1 92) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO PLUS devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programm able logic device security solution available today. IGLOO PLUS devices with AES-based security provide a high level of protection for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. Security, built into the FPGA fabric, is an inherent component of the IGLOO PLUS family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO PLUS family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. An IGLOO PLUS device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration informati on in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power -up (unlike SRAM-based FPGAs). Th erefore, flash-based IGLOO PLUS FPGAs do not require system configuration compo nents such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. The IGLOO PLUS devices can be operated with a 1.2 V or 1.5 V single-voltage supply for core and I/Os, eliminating the need for additional supplies while minimizing total power consumption. Instant On Flash-based IGLOO PLUS devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock genera tion, and bus activity management. The Instant On feature of flash-based IGLOO PLUS devices greatly simplifies total system de sign and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In a ddition, glitches and brownouts in system power will not corrupt the IGLO O PLUS device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system pow er is restored. This enables the reduction or complete removal of t he configuration PROM, expensive voltage monitor, brownout detection, and clock generator device s from the PCB design. Flash-based IGLOO PLUS devices simplify total system design and reduce cost and des ign risk while increasin g system reliability and improving system initialization time. IGLOO PLUS flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 µs), and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from external memory components; instead, it retains all necessary information to resume operation immediately. Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM- based FPGAs, flash-based IGLOO PLUS devices allow all functionality to be Instant On; no external boot PROM is required. On-boa rd security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry- standard AES algorithm.

IGLOO PLUS Low Power Flash FPGAs Revision 16 1-3 The IGLOO PLUS family device architecture miti gates the need for ASIC migration at higher user volumes. This makes the IGLOO PLUS family a cost -effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energ y of the collision can ch ange the state of the configuration cell and thus change t he logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO PLUS flash- based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO PLUS FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO PLUS family offers many benefits, incl uding nonvolatility and reprogrammability, through an advanced flash-based, 130 nm LVCM OS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and contro l functions. The combination of fine granularity, enhanced flexible routing resources, and abundant fl ash switches allows for very high logic utilization without compromising device routability or perform ance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO PLUS family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOO PLUS architecture provides granularity comparable to standard-cell ASICs. The IGLOO PLUS device consists of five distinct and programmable arch itectural features ( Figure 1-1 on page 1-4):

Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM
Dedicated SRAM/FIFO memory
Extensive CCCs and PLLs †
Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by progr amming the appropriate flash switch interconnections. The versatility of the IGLOO PLUS co re tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows fo r efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC ® family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four leve ls of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable inte rconnect programming. Maximum core utilization is possible for virtually any design. † The AGLP030 device does not support PLL or SRAM.

IGLOO PLUS Low Power Flash FPGAs Revision 16 1-5 VersaTiles The IGLOO PLUS core consists of VersaTiles, which have been enhanced beyond the ProASIC PLUS® core tiles. The IGLOO PLUS VersaTile supports the following:

All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. User Nonvolatile FlashROM IGLOO PLUS devices have 1 kbit of on-chip, use r-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications:
Internet protocol addressing (wireless or fixed)
System calibration settings
Device serialization and/or inventory control
Subscription-based business models (for example, set-top boxes)
Secure key storage for secure communications algorithms
Asset management/tracking
Date stamping
Version management The FlashROM is written using the standard IGLOO PLUS IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networ ks (except in AGLP030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG progr amming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits ; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address fr om the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The IGLOO PLUS development software solutions, Libero ® System-on-Chip (SoC) and Designer, have extensive support for the FlashROM. One such feat ure is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehe nsive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. Figure 1-3 • VersaTile Configurations YX2 LUT-3 Data Y CLK Enable CLR D-FF Data Y CLK CLR D-FF LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

IGLOO PLUS Device Family Overview SRAM and FIFO IGLOO PLUS devices (except AGLP030 devices) ha ve embedded SRAM blocks along their north side. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The emb edded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices). In addition, every SRAM block has an embedded FI FO control unit. The contro l unit allows the SRAM block to be configured as a synchronous FIFO with out using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also feat ures programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the norma l Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generati on of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOO PLUS devices provide designers with very fl exible clock conditioning circuit (CCC) capabilities. Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL. The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features:

Wide input frequency range (f IN_CCC) = 1.5 MHz up to 250 MHz
Output frequency range (f OUT_CCC) = 0.75 MHz up to 250 MHz
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only) Additional CCC specifications:
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock per iod peak-to-peak period jitter when single global network used (for PLL only)
Maximum acquisition time is 300 µs (for PLL only)
Exceptional tolerance to input period jitter—allowabl e input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases (for PLL only) is 40 ps ×

250 MHz / fOUT_CCC

IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The IGLOO PLUS family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 standards. The I/Os are organized into four banks. All devices in IGLOO PLUS have four banks. The configuration of these banks determines the I/O standards supported.

IGLOO PLUS Low Power Flash FPGAs Revision 16 1-7 Each I/O module contains several input, output, and output enable registers. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support IGLOO PLUS devices support JEDEC-defined wide ra nge I/O operation. IGLOO PLUS devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components wit h greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configurat ion. A FlashPoint – Pr ogramming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-4 on page 1-8). 5. Set the I/O Output State. You can set Basic I/O se ttings if you want to use the default I/O settings for your pins, or use Custom I/O settings to cust omize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated

IGLOO PLUS Device Family Overview 6. Click OK to return to the FlashPoi nt – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. Figure 1-4 • I/O States During Programming Window

2 – IGLOO PLUS DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of th e device at these or any other conditions beyond those listed under the Recommended O perating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI DC I/O buffer supply voltage –0.3 to 3.75 V VI 1 I/O input voltage –0.3 V to 3.6 V V TSTG

2 Storage temperature –65 to +150 °C

2 Junction temperature +125 °C

Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2.

IGLOO PLUS DC and Switching Characteristics Table 2-2 • Recommended Operating Conditions1,2 Symbol Parameter Commercial Industrial Units TA Ambient temperature 0 to +70 –40 to +85 °C TJ Junction temperature2 0 to + 85 –40 to +100 °C VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V VPUMP7 Programming voltage Programming mo de 3.15 to 3.45 3.15 to 3.45 V Operation 0 to 3.6 0 to 3.6 V 1.2 V–1.5 V wide range core voltage5 1.14 to 1.575 1.14 to 1.575 V

3.3 V wide range DC supply voltage

9 2.7 to 3.6 2.7 to 3.6 V Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank. 4. For IGLOO ® PLUS V5 devices 5. For IGLOO PLUS V2 devices only, operating at VCCI  VCC. 6. All IGLOO PLUS devices (V5 and V2) must be programmed wi th the VCC core voltage at 1.5 V. Applications using V2 devices powered by a 1.2 V supply must switch the core supply to 1.5 V for in-system programming. 7. VPUMP can be left floating during operation (not programming mode). 8. VCCPLL pins should be tied to VCC pins. See the Pin Descriptions chapter of the IGLOO PLUS FPGA Fabric User’s Guide for further information. 9. 3.3 V wide range is compliant to the JDEC8b specification and supports 3.0 V VCCI operation. Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature 1 Product Grade Programming Cycles Program Retention (biased/unbiased) Maximum Storage Temperature TSTG (°C) 2 Maximum Operating Junction Temperature TJ (°C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-3 I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every IGLOO PLUS device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequ ence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. IGLOO PLUS I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the mi nimum specified trip points ( Figure 2-1 and Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V VCC Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:

During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. Table 2-4 • Overshoot and Undershoot Limits VCCI Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 2.7 V or less 10% 1.4 V 5% 1.49 V 3 V 10% 1.1 V 5% 1.19 V 3.3 V 10% 0.79 V 5% 0.88 V 3.6 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of si x clock cycles. If the overshoot/unders hoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

IGLOO PLUS DC and Switching Characteristics PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplie s or voltage regulators to ensure proper power- up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes Low and/or the output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the IGLOO PLUS Device Family User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation To make sure the transition from input buffers to output buffers is clean, en sure that there is no path longer than 100 ns from input buffer to output buffer in your design. Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCC VCC = 1.425 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. VCC = VCCI + VT

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-5 Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Region 1: I/O buffers are OFF Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Min VCCI datasheet specification voltage at a selected I/O 2.3 V, or 3.0 V VCC VCC = 1.14 V Region 1: I/O Buffers are OFF Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V VCC = 1.575 V Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCCI Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. VCC = VCCI + VT

IGLOO PLUS DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient temperature. This is an important distin ction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = T + TA EQ 1 where: T A = Ambient temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Figure 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. The maximum operating junction temperature is 100°C. EQ 2 shows a sample calculation of th e maximum operating power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. EQ 2 Temperature and Voltage Derating Factors Maximum Power Allowed Max. junction temp. (C) Max. ambient temp. ( C)– Table 2-5 • Package Thermal Resistivities Package Type Pin Count jc ja UnitsStill Air 200 ft./ min. 500 ft./ min. Chip Scale Package (CSP) CS201 TBD TBD TBD TBD C/W CS281 TBD TBD TBD TBD C/W CS289 TBD TBD TBD TBD C/W Very Thin Quad Flat Package (VQFP) VQ128 TBD TBD TBD TBD C/W VQ176 TBD TBD TBD TBD C/W Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Array Voltage VCC (V) Junction Temperature (°C) –40°C 0°C 25°C 70°C 85°C 100°C

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-7 Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (I DD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operati ng temperature, system clock frequency, and power mode usage. Microsemi recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power bas ed on the user design, pow er mode usage, operating voltage, and temperature. Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) For IGLOO PLUS V2, 1.2 V DC Core Supply Voltage Array Voltage VCC (V) Junction Temperature (°C) –40°C 0°C 25°C 70°C 85°C 100°C Table 2-8 • Power Supply State per Mode Modes/Power Supplies Power Supply Configurations VCC VCCPLL VCCI VJTAG VPUMP Flash*Freeze On On On On On/off/floating Sleep Off Off On Off Off Shutdown Off Off Off Off Off No Flash*Freeze On On On On On/off/floating Note: Off: Power Supply level = 0 V Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* Core Voltage AGLP030 AGLP060 AGLP125 Units Typical (25°C) 1.2 V 4 8 13 µA

1.5 V 6 10 18 µA

Note: *IDD includes VCC, VPUMP, VCCI, VJTAG, and VCCPLL currents. Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode* ICCI Current Core Voltage AGLP030 AGLP060 AGLP125 Units Note: *IDD = N BANKS * ICCI

IGLOO PLUS DC and Switching Characteristics Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode Core Voltage AGLP030 AGLP060 AGLP125 Units Typical (25°C) 1.2 V / 1.5 V 0 0 0 µA Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 Core Voltage AGLP030 AGLP060 AGLP125 Units ICCA Current 2 Typical (25°C) 1.2 V 6 10 13 µA

1.5 V 16 20 28 µA

VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) 1.2 V 1.7 1.7 1.7 µA VCCI / VJTAG = 1.5 V (per bank) Typical (25°C) VCCI / VJTAG = 1.8 V (per bank) Typical (25°C) VCCI / VJTAG = 2.5 V (per bank) Typical (25°C) VCCI / VJTAG = 3.3 V (per bank) Typical (25°C) Notes: 1. IDD = N BANKS * ICCI + ICCA. JTAG counts as one bank when powered. 2. Includes VCC, VCCPLL, and VPUMP currents.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-9 Power per I/O Pin Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings VCCI (V) Dynamic Power PAC9 (µW/MHz) 1 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.26 3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.95

3.3 V LVCMOS Wide Range

2 3.3 16.26 3.3 V LVCMOS Wide Range2 – Schmitt Trigger 3.3 18.95 2.5 V LVCMOS 2.5 4.59 2.5 V LVCMOS – Schmitt Trigger 2.5 6.01 1.8 V LVCMOS 1.8 1.61 1.8 V LVCMOS – Schmitt Trigger 1.8 1.70 1.5 V LVCMOS (JESD8-11) 1.5 0.96 1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.90

1.2 V LVCMOS

3 1.2 0.55 1.2 V LVCMOS3 – Schmitt Trigger 1.2 0.47 1.2 V LVCMOS Wide Range3 1.2 0.55 1.2 V LVCMOS Wide Range3 – Schmitt Trigger 1.2 0.47 Notes: 1. PAC9 is the total dynamic power measured on VCCI. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC. Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 CLOAD (pF) VCCI (V) Dynamic Power PAC10 (µW/MHz)2 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 127.11 3.3 V LVCMOS Wide Range3 5 3.3 127.11 2.5 V LVCMOS 5 2.5 70.71 1.8 V LVCMOS 5 1.8 35.57 1.5 V LVCMOS (JESD8-11) 5 1.5 24.30 4 51 . 2 1 5 . 2 2 1.2 V LVCMOS Wide Range4 51 . 2 1 5 . 2 2 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PAC10 is the total dynamic power measured on VCCI. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. Applicable for IGLOO PLUS V2 devices only, operating at VCCI VCC.

IGLOO PLUS DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Parameter Definition Device Specific Dynamic Power (µW/MHz) AGLP125 AGLP060 AGLP030 PAC1 Clock contribution of a Global Rib 4.489 2.696 0.000 1 PAC2 Clock contribution of a Global Spine 1.991 1.962 3.499 PAC3 Clock contribution of a VersaTile row 1.510 1.523 1.537 PAC4 Clock contribution of a VersaTile us ed as a sequential module 0.153 0.151 0.151 PAC5 First contribution of a VersaTile used as a sequential module 0.029 0.029 0.029 PAC6 Second contribution of a VersaTile us ed as a sequential module 0.323 0.323 0.323 PAC7 Contribution of a VersaTile used as a combinatorial module 0.280 0.300 0.278 PAC8 Average contribution of a routing net 1.097 1.081 1.130 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-13 on page 2-9. PAC10 Contribution of an I/O out put pin (standard-dependent) See Table 2-14 on page 2-9. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.70 Note: 1. There is no Center Global Rib present in AGLP030, and thus it starts directly at the spine resulting in 0µW/MHz.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-11 Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage Parameter Definition Device-Specific Static Power (mW) AGLP125 AGLP060 AGLP030 PDC1 Array static power in Active mode See Table 2-12 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-11 on page 2-8 PDC3 Array static power in Flash*Freeze mode See Table 2-9 on page 2-7 PDC4 Static PLL contribution 1.84 1 PDC5 Bank quiescent power (VCCI-dependent) See Table 2-12 on page 2-8 Notes: 1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in Libero SoC software. Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Parameter Definition Device-Specific Dynamic Power (µW/MHz) AGLP125 AGLP060 AGLP030 PAC1 Clock contribution of a Global Rib 2.874 1.727 0.000 1 PAC2 Clock contribution of a Global Spine 1.264 1.244 2.241 PAC3 Clock contribution of a VersaTile row 0.963 0.975 0.981 PAC4 Clock contribution of a VersaTile used as a sequential module 0.098 0.096 0.096 PAC5 First contribution of a VersaTile us ed as a sequential module 0.018 0.018 0.018 PAC6 Second contribution of a VersaTile us ed as a sequential module 0.203 0.203 0.203 PAC7 Contribution of a VersaTile used as a combinatorial module 0.160 0.170 0.158 PAC8 Average contribution of a routing net 0.679 0.686 0.748 PAC9 Contribution of an I/O in put pin (standard-dependent) See Table 2-13 on page 2-9 PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-14 on page 2-9 PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.10 Note: 1. There is no Center Global Rib pr esent in AGLP030, and thus it starts directly at the spine resulting in 0µW/MHz.

IGLOO PLUS DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estima te power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software. The power calculation methodology described below uses the following variables:

The number of PLLs as well as the number a nd the frequency of each output clock generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on page 2-14.
Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on page 2-14.
Read rate and write rate to the memory—guidel ines are provided for typical applications in Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—P TOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—P STAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption—P DYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—P CLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric User's Guide. Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage Parameter Definition Device-Specific Static Power (mW) AGLP125 AGLP060 AGLP030 PDC1 Array static power in Active mode See Table 2-12 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-11 on page 2-8 PDC3 Array static power in Flash*Freeze mode See Table 2-9 on page 2-7 PDC4 Static PLL contribution 0.90 1 PDC5 Bank quiescent power (VCCI-dependent) See Table 2-12 on page 2-8 Notes: 1. This is the minimum contribution of the PLL when operating at lowest frequency. 2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in Libero SoC software.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-13 NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric User's Guide. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—P S-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. Combinatorial Cells Contribution—P C-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. Routing Net Contribution—P NET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—P INPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—P OUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14. 1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14. FCLK is the global clock signal frequency. RAM Contribution—P MEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on page 2-14.

IGLOO PLUS DC and Switching Characteristics PLL Contribution—P PLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic elem ent relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples:

The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency.
The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – Bit 7 (MSB) = 0.78125% Enable Rate Definition Output enable rate is the average percentage of ti me during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. Table 2-19 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 Toggle rate of VersaTile outputs 10% 2 I/O buffer toggle rate 10% Table 2-20 • Enable Rate Guidelines Recommended for Power Calculation Component Definition Guideline 1 I/O output buffer enable rate 100% 2 RAM enable rate for read operations 12.5% 3 RAM enable rate for write operations 12.5%

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-15 User I/O Characteristics Timing Model Figure 2-3 • Timing Model Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices DQ Y Y DQDQ DQY Combinational Cell Combinational Cell Combinational Cell I/O Module (Registered) I/O Module (Non-Registered) Register Cell Register Cell I/O Module (Registered) I/O Module (Non-Registered) LVCMOS 2.5 V Output Drive Strength = 12 mA High Slew Rate Input LVCMOS 2.5 V LVCMOS 1.5 V LVTTL 3.3 V Output drive strength = 12 mA High slew rate Y Combinational Cell Y Combinational Cell Y Combinational Cell I/O Module (Non-Registered) LVTTLOutput drive strength = 8 mA High slew rate I/O Module (Non-Registered) LVCMOS 1.5 VOutput drive strength = 4 mA High slew rate LVTTLOutput drive strength = 12 mA High slew rate I/O Module (Non-Registered) Input LVTTL Clock Input LVTTL Clock Input LVTTL Clock tPD = 1.40 ns tPD = 0.89 ns tDP = 1.62 ns tPD = 1.98 ns tDP = 1.62 ns tPD = 1.24 ns tDP = 1.70 ns tPD = 0.86 ns tDP = 2.07 ns tPD = 0.87 ns tPY = 0.85 ns tCLKQ = 0.80 ns tOCLKQ = 0.89 ns tSUD = 0.84 ns tOSUD = 0.18 ns tDP = 1.62 ns tPY = 0.85 ns tPY = 1.15 ns tCLKQ = 0.80 ns tSUD = 0.84 ns tPY = 0.85 ns tICLKQ = 0.63 ns tISUD = 0.18 ns tPY = 1.06 ns

IGLOO PLUS DC and Switching Characteristics Figure 2-4 • Input Buffer Timing Model and Delays (example) tPY (R) PAD Y Vtrip GND tPY (F) Vtrip 50%50% VIH VCC VIL tDIN (R) DIN GND tDIN (F) 50%50% VCC PAD Y tPY D CLK Q I/O Interface DIN tDIN To Array tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-17 Figure 2-5 • Output Buffer Model and Delays (example) tDP (R) PAD VOL tDP (F) VtripVtrip VOH VCC D 50% 50% VCC 0 V DOUT 50% 50% 0 V tDOUT (R) tDOUT (F) From Array PAD tDP Std Load D CLK Q I/O Interface DOUT D tDOUT tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F))

IGLOO PLUS DC and Switching Characteristics Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example) D CLK Q D CLK Q 10% VCCI tZL Vtrip 50% tHZ 90% VCCI tZH Vtrip 50% 50% tLZ 50% EOUT PAD D E 50% tEOUT (R) 50% tEOUT (F) PAD DOUT EOUT D I/O Interface E tEOUT tZLS Vtrip 50% tZHS Vtrip 50%EOUT PAD D E 50% 50%tEOUT (R) tEOUT (F) 50% VCC VCC VCC VCCI VCC VCC VCC VOH VOL VOL tZL, tZH, tHZ, tLZ, tZLS, tZHS tEOUT = MAX(tEOUT(r), tEOUT(f))

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-19 Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—S oftware Default Settings I/O Standard Drive Strength Equiv. Software Default Drive Strength Option2 Slew Rate VIL VIH VOL VOH IOL 1 IOH1 Min. V Max. V Min. V Max. V Max. V Min. Vm A m A

3.3 V LVTTL /

3.3 V LVCMOS

1.2 V LVCMOS4 Wide Range4,5 Notes: 1. Currents are measured at 85°C junction temperature. 2. Note that 1.2 V LVCMOS and 3.3 V LVCMOS wide range are ap plicable to 100 µA drive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 3. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. 4. Applicable to IGLOO PLUS V2 devices operating at VCC I VCC. 5. All LVCMOS 1.2 V software macros support LVCMOS 1. 2 V wide range as specified in the JESD8-12 specification.

IGLOO PLUS DC and Switching Characteristics Table 2-22 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standards Commercial1 Industrial2 IIL3 IIH4 IIL3 IIH4 µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

3.3 V LVCMOS Wide Range 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

1.2 V LVCMOS Wide Range5 10 10 15 15

Notes: 1. Commercial range (0°C < T A < 70°C) 2. Industrial range (–40°C < T A < 85°C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 4. IIH is the input leakage current per I/O pin over reco mmended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to IGLOO PLUS V2 devices operating at VCCI ³ VCC.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-21 Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-23 • Summary of AC Measuring Points Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 3.3 V LVCMOS Wide Range 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 1.2 V LVCMOS 0.60 V 1.2 V LVCMOS Wide Range 0.60 V Table 2-24 • I/O AC Parameter Definitions Parameter Parameter Definition t DP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer—High to Z tZH Enable to Pad delay through the Output Buffer—Z to High tLZ Enable to Pad delay through the Output Buffer—Low to Z tZL Enable to Pad delay through the Output Buffer—Z to Low tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to High tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to Low

IGLOO PLUS DC and Switching Characteristics Table 2-25 • Summary of I/O Timing Characteristics—So ftware Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V I/O Standard Drive Strength Equivalent Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA dr ive strength only. The configuration will not operate at the equivalent software default drive strength. These values are for normal ranges only. 2. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-23 Table 2-26 • Summary of I/O Timing Characteristics—So ftware Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V I/O Standard Drive Strength Equivalent Software Default Drive Strength Option1 Slew Rate Capacitive Load (pF) External Resistor () tDOUT tDP tDIN tPY) tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3. 3 V wide range as specified in the JESD-8B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1. 2 V wide range as specified in the JESD8-12 specification. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-27 • Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Table 2-28 • I/O Output Buffer Maximum Resistances 1 Standard Drive Strength RPULL-DOWN () 2 RPULL-UP () 3 3.3 V LVTTL / 3.3V LVCMOS 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 12 mA 25 75 16 mA 25 75

3.3 V LVCMOS Wide Range 100 µA Same as equivalent software default drive

2.5 V LVCMOS 2 mA 100 200

1.8 V LVCMOS 2 mA 200 225

1.5 V LVCMOS 2 mA 200 224

1.2 V LVCMOS 2 mA 157.5 163.8

1.2 V LVCMOS Wide Range

4 100 µA 157.5 163.8 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS model on the Microsemi SoC Products Group website at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R (PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R (PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec 4. Applicable to IGLOO PLUS V2 devices operating at VCCI  VCC.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-25 Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values VCCI R(WEAK PULL-UP) () R(WEAK PULL-DOWN) () Min. Max. Min. Max.

3.3 V 10 K 45 K 10 K 45 K

3.3 V (wide range I/Os) 10 K 45 K 10 K 45 K

2.5 V 11 K 55 K 12 K 74 K

1.8 V 18 K 70 K 17 K 110 K

1.5 V 19 K 90 K 19 K 140 K

1.2 V 25 K 110 K 25 K 150 K

1.2 V (wide range I/Os) 19 K 110 K 19 K 150 K

Notes: 1. R (WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) 2. R (WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN) Table 2-30 • I/O Short Currents IOSH/IOSL Drive Strength IOSL (mA)* IOSH (mA)* 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 27 25 4 mA 27 25 6 mA 54 51 8 mA 54 51 12 mA 109 103 16 mA 109 103

2.5 V LVCMOS 2 mA 18 16

1.8 V LVCMOS 2 mA 11 9

1.5 V LVCMOS 2 mA 16 13

1.2 V LVCMOS 2 mA 26 20

1.2 V LVCMOS Wide Range 100 µA 26 20

Note: *T J = 100°C

IGLOO PLUS DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junc tion temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-31 • Duration of Short Circuit Event before Failure Temperature Time before Failure –40°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months Table 2-32 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

1.2 V LVCMOS (Schmitt trigger mode) 40 mV

Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns * 20 years (100°C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage cannot exceed Schmitt hysteresis. 20 years (100°C) Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-27 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-34 • Minimum and Maximum DC Input and Output Levels

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2

Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (1 00°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-7 • AC Loading Table 2-35 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 03 . 3 1 . 4 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Applies to 1.2 V DC Core Voltage Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-29 Table 2-40 • Minimum and Maximum DC Input and Output Levels Option1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vµ A µ A Max. µA Max. µA4 µA5 µA5 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < V CCI. Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. Table 2-41 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 03 . 3 1 . 4 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.

IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Applies to 1.2 V DC Core Voltage Table 2-42 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Drive Strength Equivalent Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-43 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Drive Strength Equivalent Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-31 Table 2-44 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Drive Strength Equivalent Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LV CMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-45 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Drive Strength Equivalent Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray.

IGLOO PLUS DC and Switching Characteristics

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 2.5 V applications. Table 2-46 • Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100° C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-8 • AC Loading Table 2-47 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 02 . 5 1 . 2 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-33 Timing Characteristics Applies to 1.5 V DC Core Voltage Applies to 1.2 V DC Core Voltage Table 2-48 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-49 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Table 2-50 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-51 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.

IGLOO PLUS DC and Switching Characteristics

1.8 V LVCMOS

Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standa rd (JESD8-5) used for general- purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-52 • Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-9 • AC Loading Table 2-53 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 8 0 . 9 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-35 Timing Characteristics Applies to 1.5 V DC Core Voltage Applies to 1.2 V DC Core Voltage Table 2-54 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-55 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Table 2-56 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-57 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.

IGLOO PLUS DC and Switching Characteristics

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general- purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-58 • Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH2 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA3 Max. mA3 µA4 µA4 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Figure 2-10 • AC Loading Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 5 0 . 7 5 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-37 Timing Characteristics Applies to 1.5 V DC Core Voltage Applies to 1.2 V DC Core Voltage Table 2-60 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-61 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray. Table 2-62 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-63 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.

IGLOO PLUS DC and Switching Characteristics

1.2 V LVCMOS (JESD8-12A)

Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-64 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 2 IIH3 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA4 Max. mA4 µA5 µA5 Notes: 1. Applicable to IGLOO nano V2 devices operating at VCCI VCC. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. Currents are measured at high temperature (100 °C junction temperature) and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. Figure 2-11 • AC Loading Table 2-65 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 2 0 . 6 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points. Test Point Test Point Enable PathDatapath 5 pF R = 1 k R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Table 2-66 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-67 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: T J = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Software default selection highlighted in gray.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-39 Table 2-68 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS Wide Range1 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 3 IIH4 Drive Strength Equivalent Software Default Drive Strength Option Min. V Max. V Min. V Max. V Max. V Min. Vm A m A Max. mA5 Max mA5 µA6 µA6 Notes: 1. Applicable to V2 devices only. 2. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 4. IIH is the input leakage current per I/O pin over recomm ended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Currents are measured at high temperature (1 00°C junction temperature) and maximum voltage. 6. Currents are measured at 85°C junction temperature. 7. Software default selection highlighted in gray. Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) Input High (V) Measuring Point* (V) C LOAD (pF) 01 . 2 0 . 6 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-21 for a complete table of trip points.

IGLOO PLUS DC and Switching Characteristics Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-70 • 1.2 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength Equivalent Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LV CMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-71 • 1.2 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength Equivalent Software Default Drive Strength Option1 Speed Grade t DOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units Notes: 1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-41 I/O Register Specifications Fully Registered I/O Buffers with Asynchronous Preset Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset INBUF INBUF TRIBUF CLKBUF INBUFCLKBUF Data Input I/O Register with: Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Preset Postive-Edge Triggered Pad Out CLK Preset Data_out Data EOUT DOUT CLK DQ DFN1P1 PRE DQ DFN1P1 PRE DQ DFN1P1 PRE D_Enable A C D E F H I J L Y Core Array

IGLOO PLUS DC and Switching Characteristics Table 2-72 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register H, DOUT tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A Note: *See Figure 2-12 on page 2-41 for more information.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-43 Fully Registered I/O Buffers with Asynchronous Clear Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear CLK Pad Out CLK CLR Data_out Data Y AA EOUT DOUT Core ArrayDQ DFN1C1 CLR DQ DFN1C1 CLR DQ DFN1C1 CLR D_Enable CC DD EE FF LL HH JJ CLKBUF INBUF TRIBUF INBUF CLKBUF INBUF Data Input I/O Register with Active High Clear Positive-Edge Triggered Data Output Register and Enable Output Register with Active High Clear Positive-Edge Triggered

IGLOO PLUS DC and Switching Characteristics Table 2-73 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA Note: *See Figure 2-13 on page 2-43 for more information.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-45 Input Register Timing Characteristics

1.5 V DC Core Voltage

Figure 2-14 • Input Register Timing Diagram 50%Clear Out_1 CLK Data Preset 50% tISUD tIHD 50% 50% tICLKQ 1 0 tIRECPRE tIREMPRE tIRECCLR tIREMCLRtIWCLR tIWPRE tIPRE2Q tICLR2Q tICKMPWH tICKMPWL 50% 50% 50% 50% 50% 50% 50% 50% Table 2-74 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.41 ns tISUD Data Setup Time for the Input Data Register 0.32 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.57 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.57 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics

1.2 V DC Core Voltage

Table 2-75 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.66 ns tISUD Data Setup Time for the Input Data Register 0.43 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.86 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.86 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-47 Output Register Timing Characteristics Figure 2-15 • Output Register Timing Diagram Clear DOUT CLK Data_out Preset 50% tOSUD tOHD 50% 50% tOCLKQ 1 0 tORECPRE tOREMPRE tORECCLR tOREMCLRtOWCLR tOWPRE tOPRE2Q tOCLR2Q tOCKMPWH tOCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-76 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 0.66 ns tOSUD Data Setup Time for the Output Data Register 0.33 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.82 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.88 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics Table 2-77 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 1.03 ns tOSUD Data Setup Time for the Output Data Register 0.52 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.22 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.31 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width High for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width Low for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-49 Output Enable Register Timing Characteristics Figure 2-16 • Output Enable Register Timing Diagram 50% Preset Clear EOUT CLK D_Enable 50% tOESUDtOEHD 50% 50% tOECLKQ 1 0 tOERECPRE tOEREMPRE tOERECCLR tOEREMCLRtOEWCLR tOEWPRE tOEPRE2Q tOECLR2Q tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% 50% Table 2-78 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.68 ns tOESUD Data Setup Time for the Output Enable Register 0.33 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.84 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.91 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics Table 2-79 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 1.06 ns tOESUD Data Setup Time for the Output Enable Register 0.52 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 1.25 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 1.36 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-51 VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOO PLUS library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/ E Macro Library Guide. Figure 2-17 • Sample of Combinatorial Cells MAJ3 A C BY MUX2 B A S Y AY B B A XOR2 Y NOR2 B A Y B A YOR2 INV A YAND2 B A Y NAND3B A C XOR3 YB A C NAND2

IGLOO PLUS DC and Switching Characteristics Figure 2-18 • Timing Model and Waveforms Net A Y B Length = 1 VersaTile Net A Y B Length = 1 VersaTile Net A Y B Length = 1 VersaTile Net A Y B Length = 1 VersaTile NAND2 or Any Combinatorial Logic NAND2 or Any Combinatorial Logic NAND2 or Any Combinatorial Logic NAND2 or Any Combinatorial Logic tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for a particular combinatorial cell Fanout = 4 t PD tPD tPD 50% VCC VCC VCC 50% GNDA, B, C 50% 50% 50% (RR) (RF) GND OUT OUT GND 50% (FF) (FR) tPD tPD

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-53 Timing Characteristics Table 2-80 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter Std. Units INV Y = !A t PD 0.72 ns AND2 Y = A · B t PD 0.86 ns NAND2 Y = !(A · B) t PD 1.00 ns OR2 Y = A + B t PD 1.26 ns NOR2 Y = !(A + B) t PD 1.16 ns XOR2 Y = A Bt PD 1.46 ns MAJ3 Y = MAJ(A, B, C) t PD 1.47 ns XOR3 Y = A  B Ct PD 2.12 ns MUX2 Y = A !S + B S t PD 1.24 ns AND3 Y = A · B · C t PD 1.40 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-81 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Combinatorial Cell Equation Parameter Std. Units INV Y = !A t PD 1.26 ns AND2 Y = A · B t PD 1.46 ns NAND2 Y = !(A · B) t PD 1.78 ns OR2 Y = A + B t PD 2.47 ns NOR2 Y = !(A + B) t PD 2.17 ns XOR2 Y = A Bt PD 2.62 ns MAJ3 Y = MAJ(A, B, C) t PD 2.66 ns XOR3 Y = A  B Ct PD 3.77 ns MUX2 Y = A !S + B S t PD 2.20 ns AND3 Y = A · B · C t PD 2.49 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOO PLUS library offers a wide variety of se quential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. Figure 2-19 • Sample of Sequential Cells DQ DFN1 Data CLK Out D Q DFN1C1 Data CLK Out CLR DQ DFI1E1P1 Data CLK Out En PRE D Q DFN1E1 Data CLK Out En

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-55 Timing Characteristics Figure 2-20 • Timing Model and Waveforms PRE CLR Out CLK Data EN tSUE 50% 50% tSUD tHD 50% 50% tCLKQ tHE tRECPRE tREMPRE tRECCLR tREMCLRtWCLR tWPRE tPRE2Q tCLR2Q tCKMPWH tCKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-82 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tCLKQ Clock-to-Q of the Core Register 0.89 ns tSUD Data Setup Time for the Core Register 0.81 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 0.73 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.60 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.62 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.56 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics Table 2-83 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tCLKQ Clock-to-Q of the Core Register 1.61 ns tSUD Data Setup Time for the Core Register 1.17 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 1.29 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.87 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.89 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.46 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.46 ns tCKMPWH Clock Minimum Pulse Width High for the Core Register 0.95 ns tCKMPWL Clock Minimum Pulse Width Low for the Core Register 0.95 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-57 Global Resource Characteristics AGLP125 Clock Tree Topology Clock delays are device-specific. Figure 2-21 is an example of a global tree used for clock routing. The global tree presented in Figure 2-21 is driven by a CCC located on the west side of the AGLP125 device. It is used to drive all D-flip-flops in the device. Figure 2-21 • Example of Global Tree Use in an AGLP125 Device for Clock Routing Central Global Rib VersaTile Rows Global Spine CCC

IGLOO PLUS DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-61. Table 2-84 to Table 2-89 on page 2-60 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics Table 2-84 • AGLP030 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. UnitsMin.1 Max.2 tRCKL Input Low Delay for Global Clock 1.21 1.42 ns tRCKH Input High Delay for Global Clock 1.23 1.49 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.18 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.15 ns tRCKSW Maximum Skew for Global Clock 0.27 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-85 • AGLP060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. UnitsMin.1 Max.2 tRCKL Input Low Delay for Global Clock 1.32 1.62 ns tRCKH Input High Delay for Global Clock 1.34 1.72 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.18 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.15 ns tRCKSW Maximum Skew for Global Clock 0.38 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-59 Table 2-86 • AGLP125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. UnitsMin.1 Max.2 tRCKL Input Low Delay for Global Clock 1.36 1.71 ns tRCKH Input High Delay for Global Clock 1.39 1.82 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.18 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.15 ns tRCKSW Maximum Skew for Global Clock 0.43 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-87 • AGLP030 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. UnitsMin.1 Max.2 tRCKL Input Low Delay for Global Clock 1.80 2.09 ns tRCKH Input High Delay for Global Clock 1.88 2.27 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.39 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS DC and Switching Characteristics Table 2-88 • AGLP060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. UnitsMin.1 Max.2 tRCKL Input Low Delay for Global Clock 2.02 2.43 ns tRCKH Input High Delay for Global Clock 2.09 2.65 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.56 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-89 • AGLP125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. UnitsMin.1 Max.2 tRCKL Input Low Delay for Global Clock 2.08 2.54 ns tRCKH Input High Delay for Global Clock 2.15 2.77 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.62 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-61 Clock Conditioning Circuits Timing Characteristics Table 2-90 • IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 or V5 devices, 1.5 V DC Core Supply Voltage Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 250 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 250 MHz Delay Increments in Programmable Delay Blocks 1, 2 360 3 ps Number of Programmable Values in Each Programmable Delay Block 32 Serial Clock (SCLK) for Dynamic PLL 4,5 100 MHz Input Cycle-to-Cycle Jitter (peak magnitude) 1 ns Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter LockControl = 0 2.5 ns LockControl = 1 1.5 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 1.25 15.65 ns Delay Range in Block: Programmable Delay 2 1, 2 0.469 15.65 ns Delay Range in Block: Fixed Delay 1, 2 3.5 ns VCO Output Peak-to-Peak Period Jitter FCCC_OUT

7 Maximum Peak-to-Peak Period Jitter7,8,9

SSO  2 SSO  4 SSO  8 SSO  16 50 MHz to 250 MHz 2.50% 4.00% 6.00% 12.00% Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. T J = 25°C, VCC = 1.5 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help associated with the core for more information. 4. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions. For specific junction temperature and voltage supply, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 5. The AGLP030 device does not support a PLL. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 8. Measurements done with LVTTL 3.3 V 8 mA I/O driv e strength and high slew rate, VCC/VCCPLL = 1.425 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 9. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within ±200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout" section in the IGLOO PLUS FPGA Fabric User’s Guide.

IGLOO PLUS DC and Switching Characteristics Table 2-91 • IGLOO PLUS CCC/PLL Specification For IGLOO PLUS V2 Devices, 1.2 V DC Core Supply Voltage Parameter Min. Typ. Max. Units Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 160 MHz Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 160 MHz Delay Increments in Programmable Delay Blocks 1, 2 580 3 ps Number of Programmable Values in Each Programmable Delay Block 32 Serial Clock (SCLK) for Dynamic PLL4,5 60 MHz Input Cycle-to-Cycle Jitter (peak magnitude) .25 ns Acquisition Time LockControl = 0 300 µs LockControl = 1 6.0 ms Tracking Jitter LockControl = 0 4 ns LockControl = 1 3 ns Output Duty Cycle 48.5 51.5 % Delay Range in Block: Programmable Delay 1 1, 2 2.3 20.86 ns Delay Range in Block: Programmable Delay 2 1, 2 0.863 20.86 ns Delay Range in Block: Fixed Delay 1, 2 5.7 ns VCO Output Peak-to-Peak Period Jitter FCCC_OUT SSO  2 SSO  4 SSO  8 SSO  16 50 MHz to 160 MHz 2.50% 5.00% 7.00% 15.00% Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. T J = 25°C, VCC = 1.2 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the online help associated with the core for more information. 4. Maximum value obtained for a STD speed grade device in Worst Case Commercial Conditions.For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 5. The AGLP030 device does not support PLL. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by period jitter parameter. 7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings. 8. Measurements are done with LVTTL 3.3 V, 8 mA, I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 9. SSO are outputs that are synchronous to a single clock domain, and have their clock-to-out times within ±200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout" section in the IGLOO PLUS FPGA Fabric User’s Guide

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-63 Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-22 • Peak-to-Peak Jitter Definition Tperiod_max Tperiod_min Output Signal

IGLOO PLUS DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM Figure 2-23 • RAM Models ADDRA11 DOUTA8 DOUTA7 DOUTA0 DOUTB8 DOUTB7 DOUTB0 ADDRA10 ADDRA0 DINA8 DINA7 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RAM4K9 RADDR8 RD17 RADDR7 RD16 RADDR0 RD0 WD17 WD16 WD0 WW1 WW0 RW1 RW0 PIPE REN RCLK RAM512X18 WADDR8 WADDR7 WADDR0 WEN WCLK RESETRESET

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-67 Figure 2-28 • RAM Reset CLK RESET DOUT|RD Dn tCYC tCKH tCKL tRSTBQ Dm

IGLOO PLUS DC and Switching Characteristics Timing Characteristics Table 2-92 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.69 ns tAH Address hold time 0.13 ns tENS REN, WEN setup time 0.68 ns tENH REN, WEN hold time 0.13 ns tBKS BLK setup time 1.37 ns tBKH BLK hold time 0.13 ns tDS Input data (DIN) setup time 0.59 ns tDH Input data (DIN) hold time 0.30 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 2.94 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 2.55 ns tCKQ2 Clock High to new data valid on DOUT (pipelined) 1.51 ns tC2CWWL

1 Address collision clk-to-clk delay for reliable write after write on same address – applicable

0.29 ns tC2CRWH

1 Address collision clk-to-clk delay for reliable read access after write on same address –

applicable to opening edge 0.24 ns tC2CWRH

1 Address collision clk-to-clk delay for reliable write access after read on same address –

applicable to opening edge 0.40 ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 1.72 ns RESET Low to data out Low on DOUT (pipelined) 1.72 ns tREMRSTB RESET removal 0.51 ns tRECRSTB RESET recovery 2.68 ns tMPWRSTB RESET minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-69 Table 2-93 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.69 ns tAH Address hold time 0.13 ns tENS REN, WEN setup time 0.61 ns tENH REN, WEN hold time 0.07 ns tDS Input data (WD) setup time 0.59 ns tDH Input data (WD) hold time 0.30 ns tCKQ1 Clock High to new data valid on RD (output retained) 3.51 ns tCKQ2 Clock High to new data valid on RD (pipelined) 1.43 ns tC2CRWH applicable to opening edge 0.21 ns tC2CWRH applicable to opening edge 0.25 ns tRSTBQ RESET Low to data out Low on RD (flow-through) 1.72 ns RESET Low to data out Low on RD (pipelined) 1.72 ns tREMRSTB RESET removal 0.51 ns tRECRSTB RESET recovery 2.68 ns tMPWRSTB RESET minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics Table 2-94 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tAS Address setup time 1.28 ns tAH Address hold time 0.25 ns tENS REN, WEN setup time 1.25 ns tENH REN, WEN hold time 0.25 ns tBKS BLK setup time 2.54 ns tBKH BLK hold time 0.25 ns tDS Input data (DIN) setup time 1.10 ns tDH Input data (DIN) hold time 0.55 ns tCKQ1 Clock High to new data valid on DOUT (output retained, WMODE = 0) 5.51 ns Clock High to new data valid on DOUT (flow-through, WMODE = 1) 4.77 ns t CKQ2 Clock High to new data valid on DOUT (pipelined) 2.82 ns tC2CWWL

1 Address collision clk-to-clk delay for re liable write after write on same address –

applicable to closing edge 0.30 ns tC2CRWH applicable to opening edge 0.32 ns tC2CWRH applicable to opening edge 0.44 ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 3.21 ns RESET Low to data out Low on DOUT (pipelined) 3.21 ns tREMRSTB RESET removal 0.93 ns tRECRSTB RESET recovery 4.94 ns tMPWRSTB RESET minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-71 Table 2-95 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tAS Address setup time 1.28 ns tAH Address hold time 0.25 ns tENS REN, WEN setup time 1.13 ns tENH REN, WEN hold time 0.13 ns tDS Input data (WD) setup time 1.10 ns tDH Input data (WD) hold time 0.55 ns tCKQ1 Clock High to new data valid on RD (output retained) 6.56 ns tCKQ2 Clock High to new data valid on RD (pipelined) 2.67 ns tC2CRWH

1 Address collision clk-to-clk delay for relia ble read access after wr ite on same address –

applicable to opening edge 0.29 ns tC2CWRH

1 Address collision clk-to-clk delay for reliabl e write access after r ead on same address –

applicable to opening edge 0.36 ns tRSTBQ RESET Low to data out Low on RD (flow through) 3.21 ns RESET Low to data out Low on RD (pipelined) 3.21 ns tREMRSTB RESET removal 0.93 ns tRECRSTB RESET recovery 4.94 ns tMPWRSTB RESET minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics FIFO Figure 2-29 • FIFO Model FIFO4K18 RW2 RD17 RW1 RD16 RW0 WW2 WW1 WW0 RD0 ESTOP FSTOP FULL AFULL EMPTY AFVAL11 AEMPTY AFVAL10 AFVAL0 AEVAL11 AEVAL10 AEVAL0 REN RBLK RCLK WEN WBLK WCLK RPIPE WD17 WD16 WD0 RESET

IGLOO PLUS DC and Switching Characteristics Timing Characteristics Table 2-96 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. Units tENS REN, WEN Setup Time 1.66 ns tENH REN, WEN Hold Time 0.13 ns tBKS BLK Setup Time 0.30 ns tBKH BLK Hold Time 0.00 ns tDS Input Data (WD) Setup Time 0.63 ns tDH Input Data (WD) Hold Time 0.20 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.77 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 1.50 ns tRCKEF RCLK High to Empty Flag Valid 2.94 ns tWCKFF WCLK High to Full Flag Valid 2.79 ns tCKAF Clock High to Almost Empty/Full Flag Valid 10.71 ns tRSTFG RESET Low to Empty/Full Flag Valid 2.90 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 10.60 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 1.68 ns RESET Low to Data Out Low on RD (pipelined) 1.68 ns t REMRSTB RESET Removal 0.51 ns tRECRSTB RESET Recovery 2.68 ns tMPWRSTB RESET Minimum Pulse Width 0.68 ns tCYC Clock Cycle Time 6.24 ns FMAX Maximum Frequency for FIFO 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-77 Table 2-97 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. Units tENS REN, WEN Setup Time 3.44 ns tENH REN, WEN Hold Time 0.26 ns tBKS BLK Setup Time 0.30 ns tBKH BLK Hold Time 0.00 ns tDS Input Data (WD) Setup Time 1.30 ns tDH Input Data (WD) Hold Time 0.41 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 5.67 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 3.02 ns tRCKEF RCLK High to Empty Flag Valid 6.02 ns tWCKFF WCLK High to Full Flag Valid 5.71 ns tCKAF Clock High to Almost Empty/Full Flag Valid 22.17 ns tRSTFG RESET Low to Empty/Full Flag Valid 5.93 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 21.94 ns tRSTBQ RESET Low to Data Out Low on RD (flow-through) 3.41 ns RESET Low to Data Out Low on RD (pipelined) 3.41 ns t REMRSTB RESET Removal 1.02 ns tRECRSTB RESET Recovery 5.48 ns tMPWRSTB RESET Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency for FIFO 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.

IGLOO PLUS DC and Switching Characteristics Embedded FlashROM Characteristics Timing Characteristics Figure 2-37 • Timing Diagram A0 A1 tSU tHOLD tSU tHOLD tSU tHOLD tCKQ2 tCKQ2 tCKQ2 CLK Address Data D0 D0 D1 Table 2-98 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. Units tSU Address Setup Time 0.57 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 17.58 ns FMAX Maximum Clock Frequency 15 MHz Table 2-99 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. Units tSU Address Setup Time 0.59 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 30.94 ns FMAX Maximum Clock Frequency 10 MHz

IGLOO PLUS Low Power Flash FPGAs Revision 16 2-79 JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-15 for more details. Timing Characteristics Table 2-100 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tDISU Test Data Input Setup Time 1.00 ns tDIHD Test Data Input Hold Time 2.00 ns tTMSSU Test Mode Select Setup Time 1.00 ns tTMDHD Test Mode Select Hold Time 2.00 ns tTCK2Q Clock to Q (data out) 8.00 ns tRSTB2Q Reset to Q (data out) 25.00 ns FTCKMAX TCK Maximum Frequency 15 MHz tTRSTREM ResetB Removal Time 0.58 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-101 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tDISU Test Data Input Setup Time 1.50 ns tDIHD Test Data Input Hold Time 3.00 ns tTMSSU Test Mode Select Setup Time 1.50 ns tTMDHD Test Mode Select Hold Time 3.00 ns tTCK2Q Clock to Q (data out) 11.00 ns tRSTB2Q Reset to Q (data out) 30.00 ns FTCKMAX TCK Maximum Frequency 9.00 MHz tTRSTREM ResetB Removal Time 1.18 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.

IGLOO PLUS DC and Switching Characteristics

3 – Pin Descriptions and Packaging Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise orig inated from the output buffer ground domain. This minimizes the noise transfer within the package and im proves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V fo r IGLOO PLUS V5 devices, and 1.2 V or 1.5 V for IGLOO PLUS V2 devices. VCC is required for powerin g the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. For IGLOO PLUS V2 devices, VCC can be switched dynam ically from 1.2 V to 1.5 V or vice versa. This allows in-system programming (ISP) when VCC is at 1.5 V and the benefit of low power operation when VCC is at 1.2 V. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I /O logic. Bx is the I/O bank number. There are four I/O banks on low power flash devices plus a dedic ated VJTAG bank. Each bank can have a separate 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V, depending on the device.

1.5 V for IGLOO PLUS V5 devices
1.2 V or 1.5 V for IGLOO PLUS V2 devices When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed signal FPGAs " chapter of the IGLOO PLUS FPGA Fabric User’s Guide for a complete board solution for the PLL analog power supply and ground. There is one VCCPLF pin on IGLOO PLUS devices.

Pin Descriptions and Packaging VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There is one VCOMPLF pin on IGLOO PLUS devices. VJTAG JTAG Supply Voltage Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isol ating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and si mplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage IGLOO PLUS devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. Duri ng normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG pow er supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows:

Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed GL Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power Flash Devices and Mixed Signal FPGAs" chapter of the IGLOO PLUS FPGA Fabric User’s Guide . All inputs labeled GC/GF are direct inputs into the quadr ant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available fo r input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the ch ip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the I/O Structure chapter of the IGLOO PLUS FPGA Fabric User’s Guide for an explanation of the naming of global pins.

IGLOO PLUS Low Power Flash FPGAs Revision 16 3-3 FF Flash*Freeze Mode Activation Pin The FF pin is a dedicated input pin used to enter a nd exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single- ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin should be treated as a sensitive asynchronous signa l. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pul l-up. This default config uration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO and ProASIC3L devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to larger or smaller IGLOO devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO PLUS Device Family User’s Guide for more information on I/O states during Flash*Freeze mode. Table 3-1 • Flash*Freeze Pin Location in IGLOO PLUS Devices Package Flash*Freeze Pin CS281 W2 CS201 R4 CS289 U1 VQ128 34 VQ176 47

Pin Descriptions and Packaging JTAG Pins Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VC C must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in s upply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull- up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2 for more information. TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP , and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull- down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-2 and must satisfy the parallel re sistance value requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circui t could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500  to 1 k will satisfy the requirements. Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins VJTAG Tie-Off Resistance VJTAG at 3.3 V 200  to 1 k VJTAG at 2.5 V 200  to 1 k VJTAG at 1.8 V 500  to 1 k VJTAG at 1.5 V 500  to 1 k Notes: 1. Equivalent parallel resistance if more than one device is on the JTAG chain 2. The TCK pin can be pulled up/down. 3. The TRST pin is pulled down.

IGLOO PLUS Low Power Flash FPGAs Revision 16 3-5 Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability an d performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. Related Documents IGLOO PLUS Device Family User’s Guide http://www.microsemi.com/soc/documents/IGLOOPLUS_UG.pdf The following documents provide packaging information and device selection for low power flash devices. Product Catalog http://www.microsemi.com/soc/documents/ProdCat_PIB.pdf Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings http://www.microsemi.com/soc/documents/PckgMechDrwngs.pdf This document contains the package mechanical dr awings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials are available at http://www.microsemi.com/soc/products/solutions/package/docs.aspx.

4 – Package Pin Assignments VQ128 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Pin information is in the "Pin Descriptions" chapter of the IGLOO PLUS FPGA Fabric User’s Guide. Note: This is the bottom view of the package. 128-Pin VQFP 128

1 IO119RSB3

2 IO118RSB3

3 IO117RSB3

4 IO115RSB3

5 IO116RSB3

6 IO113RSB3

7 IO114RSB3

10 IO112RSB3

11 IO111RSB3

12 IO110RSB3

13 IO109RSB3

14 GEC0/IO108RSB3

15 GEA0/IO107RSB3

16 GEB0/IO106RSB3

17 VCC

18 IO104RSB3

19 IO103RSB3

20 IO102RSB3

21 IO101RSB3

22 IO100RSB3

23 IO99RSB3

24 GND

25 VCCIB3

26 IO97RSB3

27 IO98RSB3

28 IO95RSB3

29 IO96RSB3

30 IO94RSB3

31 IO93RSB3

32 IO92RSB3

33 IO91RSB2

34 FF/IO90RSB2

35 IO89RSB2

36 IO88RSB2

37 IO86RSB2

38 IO84RSB2

39 IO83RSB2

40 GND

41 VCCIB2

42 IO82RSB2

43 IO81RSB2

44 IO79RSB2

45 IO78RSB2

46 IO77RSB2

47 IO75RSB2

48 IO74RSB2

49 VCC

50 IO73RSB2

51 IO72RSB2

52 IO70RSB2

53 IO69RSB2

54 IO68RSB2

55 IO66RSB2

56 IO65RSB2

57 GND

58 VCCIB2

59 IO63RSB2

60 IO61RSB2

61 IO59RSB2

62 TCK

63 TDI

64 TMS

65 VPUMP

66 TDO

67 TRST

68 IO58RSB1

69 VJTAG

70 IO56RSB1

71 IO57RSB1

72 VCCIB1

73 GND

74 IO55RSB1

75 IO54RSB1

76 IO53RSB1

77 IO52RSB1

78 IO51RSB1

79 IO50RSB1

80 IO49RSB1

81 VCC

82 GDB0/IO48RSB1

83 GDA0/IO47RSB1

84 GDC0/IO46RSB1

85 IO45RSB1

86 IO44RSB1

87 IO43RSB1

88 IO42RSB1

89 VCCIB1

90 GND

91 IO40RSB1

92 IO41RSB1

93 IO39RSB1

94 IO38RSB1

95 IO37RSB1

96 IO36RSB1

97 IO35RSB0

98 IO34RSB0

99 IO33RSB0

100 IO32RSB0

101 IO30RSB0

102 IO28RSB0

103 IO27RSB0

104 VCCIB0

105 GND

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-3

106 IO26RSB0

107 IO25RSB0

108 IO23RSB0

109 IO22RSB0

110 IO21RSB0

111 IO19RSB0

112 IO18RSB0

113 VCC

114 IO17RSB0

115 IO16RSB0

116 IO14RSB0

117 IO13RSB0

118 IO12RSB0

119 IO10RSB0

120 IO09RSB0

121 VCCIB0

122 GND

123 IO07RSB0

124 IO05RSB0

125 IO03RSB0

126 IO02RSB0

127 IO01RSB0

128 IO00RSB0

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. 176-Pin VQFP 176

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-5 VQ176 Pin Number AGLP060 Function

1 GAA2/IO156RSB3

2 IO155RSB3

3 GAB2/IO154RSB3

4 IO153RSB3

5 GAC2/IO152RSB3

7 VCCIB3

8 IO149RSB3

9 IO147RSB3

10 IO145RSB3

11 IO144RSB3

12 IO143RSB3

13 VCC

14 IO141RSB3

15 GFC1/IO140RSB3

16 GFB1/IO138RSB3

17 GFB0/IO137RSB3

18 VCOMPLF

19 GFA1/IO136RSB3

20 VCCPLF

21 GFA0/IO135RSB3

22 GND

23 VCCIB3

24 GFA2/IO134RSB3

25 GFB2/IO133RSB3

26 GFC2/IO132RSB3

27 IO131RSB3

28 IO130RSB3

29 IO129RSB3

30 IO127RSB3

31 IO126RSB3

32 IO125RSB3

33 IO123RSB3

34 IO122RSB3

35 IO121RSB3

36 IO119RSB3

37 GND

38 VCCIB3

39 GEC1/IO116RSB3

40 GEB1/IO114RSB3

41 GEC0/IO115RSB3

42 GEB0/IO113RSB3

43 GEA1/IO112RSB3

44 GEA0/IO111RSB3

45 GEA2/IO110RSB2

47 FF/GEB2/IO109R

48 GEC2/IO108RSB2

49 IO106RSB2

50 IO107RSB2

51 IO104RSB2

52 IO105RSB2

53 IO102RSB2

54 IO103RSB2

55 GND

56 VCCIB2

57 IO101RSB2

58 IO100RSB2

59 IO99RSB2

60 IO98RSB2

61 IO97RSB2

62 IO96RSB2

63 IO95RSB2

64 IO94RSB2

65 IO93RSB2

66 VCC

67 IO92RSB2

68 IO91RSB2

69 IO90RSB2

70 IO89RSB2

71 IO88RSB2

72 IO87RSB2

73 IO86RSB2

74 IO85RSB2

75 IO84RSB2

76 GND

77 VCCIB2

78 IO83RSB2

79 IO82RSB2

80 GDC2/IO80RSB2

81 IO81RSB2

82 GDA2/IO78RSB2

83 GDB2/IO79RSB2

86 TCK

87 TDI

88 TMS

89 VPUMP

90 TDO

91 TRST

92 VJTAG

93 GDA1/IO76RSB1

94 GDC0/IO73RSB1

95 GDB1/IO74RSB1

96 GDC1/IO72RSB1

97 VCCIB1

98 GND

99 IO70RSB1

100 IO69RSB1

101 IO67RSB1

102 IO66RSB1

103 IO65RSB1

104 IO63RSB1

105 IO62RSB1

106 IO61RSB1

107 GCC2/IO60RSB1

108 GCB2/IO59RSB1

109 GCA2/IO58RSB1

110 GCA0/IO57RSB1

111 GCA1/IO56RSB1

112 VCCIB1

113 GND

114 GCB0/IO55RSB1

115 GCB1/IO54RSB1

116 GCC0/IO53RSB1

117 GCC1/IO52RSB1

118 IO51RSB1

119 IO50RSB1

120 VCC

121 IO48RSB1

122 IO47RSB1

123 IO45RSB1

124 IO44RSB1

125 IO43RSB1

126 VCCIB1

127 GND

128 GBC2/IO40RSB1

129 IO39RSB1

130 GBB2/IO38RSB1

131 IO37RSB1

132 GBA2/IO36RSB1

133 GBA1/IO35RSB0

135 GBA0/IO34RSB0

137 GBB1/IO33RSB0

139 GBC1/IO31RSB0

140 GBB0/IO32RSB0

141 GBC0/IO30RSB0

142 IO29RSB0

143 IO28RSB0

144 IO27RSB0

145 VCCIB0

146 GND

147 IO26RSB0

148 IO25RSB0

149 IO24RSB0

150 IO23RSB0

151 IO22RSB0

152 IO21RSB0

153 IO20RSB0

154 IO19RSB0

155 IO18RSB0

156 VCC

157 IO17RSB0

158 IO16RSB0

159 IO15RSB0

160 IO14RSB0

161 IO13RSB0

162 IO12RSB0

163 IO11RSB0

164 IO10RSB0

165 IO09RSB0

166 VCCIB0

167 GND

168 IO07RSB0

169 IO08RSB0

170 GAC1/IO05RSB0

171 IO06RSB0

172 GAB1/IO03RSB0

173 GAC0/IO04RSB0

174 GAB0/IO02RSB0

175 GAA1/IO01RSB0

176 GAA0/IO00RSB0

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-7 CS201 Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: This is the bottom view of the package. A B C D E F G H J K L M N P R 2345678915 14 13 12 11 10

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-9 H14 IO45RSB1 H15 IO43RSB1 J1 GEA0/IO107RSB3 J2 IO105RSB3 J3 IO104RSB3 J4 IO102RSB3 J6 VCCIB3 J7 GND J8 VCC J9 GND J10 VCCIB1 J12 NC J13 NC J14 IO52RSB1 J15 IO50RSB1 K1 IO103RSB3 K2 IO101RSB3 K3 IO99RSB3 K4 IO100RSB3 K6 GND K7 VCCIB2 K8 VCCIB2 K9 VCCIB2 K10 VCCIB1 K12 NC K13 IO57RSB1 K14 IO49RSB1 K15 IO53RSB1 L1 IO96RSB3 L2 IO98RSB3 L3 IO95RSB3 L4 IO94RSB3 L12 NC L13 NC L14 IO51RSB1 CS201 Pin Number AGLP030 Function L15 IO58RSB1 M1 IO93RSB3 M2 IO92RSB3 M3 IO97RSB3 M4 GND M5 NC M6 IO79RSB2 M7 IO77RSB2 M8 IO72RSB2 M9 IO70RSB2 M10 IO61RSB2 M11 IO59RSB2 M12 GND M13 NC M14 IO55RSB1 M15 IO56RSB1 N1 NC N2 NC N3 GND N4 NC N5 IO88RSB2 N6 IO81RSB2 N7 IO75RSB2 N8 IO68RSB2 N9 IO66RSB2 N10 IO65RSB2 N11 IO71RSB2 N12 IO63RSB2 N13 GND N14 TDO N15 VJTAG P1 NC P2 NC P3 NC P4 NC CS201 Pin Number AGLP030 Function P5 IO87RSB2 P6 IO86RSB2 P7 IO84RSB2 P8 IO80RSB2 P9 IO74RSB2 P10 IO73RSB2 P11 IO76RSB2 P12 IO67RSB2 P13 IO64RSB2 P14 VPUMP P15 TRST R1 NC R2 NC R3 IO91RSB2 R4 FF/IO90RSB2 R5 IO89RSB2 R6 IO83RSB2 R7 IO82RSB2 R8 IO85RSB2 R9 IO78RSB2 R10 IO69RSB2 R11 IO62RSB2 R12 IO60RSB2 R13 TMS R14 TDI R15 TCK CS201 Pin Number AGLP030 Function

G1* VCOMPLF G2 GFB0/IO137RSB3 G3 GFC0/IO139RSB3 G4 IO143RSB3 G6 VCCIB3 G7 GND G8 VCC G9 GND G10 GND G12 IO50RSB1 G13 GCB1/IO54RSB1 G14 GCC2/IO60RSB1 G15 GCA2/IO58RSB1 H1* VCCPLF H2 GFA1/IO136RSB3 H3 GFB1/IO138RSB3 H4 NC H6 VCCIB3 H7 GND H8 VCC H9 GND H10 VCCIB1 H12 GCB2/IO59RSB1 H13 GCA0/IO57RSB1 CS201 Pin Number AGLP060 Function Note: *Pin numbers G1 and H1 must be connected to ground because a PLL is not supported for AGLP060-CS/G201.

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-11 H14 IO64RSB1 H15 IO62RSB1 J1 GFA2/IO134RSB3 J2 GFA0/IO135RSB3 J3 GFB2/IO133RSB3 J4 IO131RSB3 J6 VCCIB3 J7 GND J8 VCC J9 GND J10 VCCIB1 J12 IO61RSB1 J13 IO63RSB1 J14 IO68RSB1 J15 IO66RSB1 K1 IO130RSB3 K2 GFC2/IO132RSB3 K3 IO127RSB3 K4 IO129RSB3 K6 GND K7 VCCIB2 K8 VCCIB2 K9 VCCIB2 K10 VCCIB1 K12 IO65RSB1 K13 IO67RSB1 K14 IO69RSB1 K15 IO70RSB1 L1 IO126RSB3 L2 IO128RSB3 L3 IO121RSB3 L4 IO123RSB3 L12 GDB1/IO74RSB1 L13 GDC1/IO72RSB1 L14 IO71RSB1 CS201 Pin Number AGLP060 Function L15 GDC0/IO73RSB1 M1 IO122RSB3 M2 IO124RSB3 M3 IO119RSB3 M4 GND M5 IO125RSB3 M6 IO98RSB2 M7 IO96RSB2 M8 IO91RSB2 M9 IO89RSB2 M10 IO82RSB2 M11 GDA2/IO78RSB2 M12 GND M13 GDA1/IO76RSB1 M14 GDA0/IO77RSB1 M15 GDB0/IO75RSB1 N1 IO117RSB3 N2 IO120RSB3 N3 GND N4 GEB1/IO114RSB3 N5 IO107RSB2 N6 IO100RSB2 N7 IO94RSB2 N8 IO87RSB2 N9 IO85RSB2 N10 GDC2/IO80RSB2 N11 IO90RSB2 N12 IO84RSB2 N13 GND N14 TDO N15 VJTAG P1 GEC0/IO115RSB3 P2 GEC1/IO116RSB3 P3 GEA0/IO111RSB3 P4 GEA1/IO112RSB3 CS201 Pin Number AGLP060 Function P5 IO106RSB2 P6 IO105RSB2 P7 IO103RSB2 P8 IO99RSB2 P9 IO93RSB2 P10 IO92RSB2 P11 IO95RSB2 P12 IO86RSB2 P13 IO83RSB2 P14 VPUMP P15 TRST R1 IO118RSB3 R2 GEB0/IO113RSB3 R3 GEA2/IO110RSB2 R4 FF/GEB2/IO109RS R5 GEC2/IO108RSB2 R6 IO102RSB2 R7 IO101RSB2 R8 IO104RSB2 R9 IO97RSB2 R10 IO88RSB2 R11 IO81RSB2 R12 GDB2/IO79RSB2 R13 TMS R14 TDI R15 TCK CS201 Pin Number AGLP060 Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx Note: This is the bottom view of the package. 10 9 8 7 6 5 4 3 2 1111213141516171819 M N P R T U V W D E F A B C G H J K L

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-13 CS281 Pin Number AGLP125 Function A1 GND A2 GAB0/IO02RSB0 A3 GAC1/IO05RSB0 A4 IO09RSB0 A5 IO13RSB0 A6 IO15RSB0 A7 IO18RSB0 A8 IO23RSB0 A9 IO25RSB0 A10 VCCIB0 A11 IO33RSB0 A12 IO41RSB0 A13 IO43RSB0 A14 IO46RSB0 A15 IO55RSB0 A16 IO56RSB0 A17 GBC1/IO58RSB0 A18 GBA0/IO61RSB0 A19 GND B1 GAA2/IO211RSB3 B2 VCCIB0 B3 GAB1/IO03RSB0 B4 GAC0/IO04RSB0 B5 IO11RSB0 B6 GND B7 IO21RSB0 B8 IO22RSB0 B9 IO28RSB0 B10 IO32RSB0 B11 IO36RSB0 B12 IO39RSB0 B13 IO42RSB0 B14 GND B15 IO52RSB0 B16 GBC0/IO57RSB0 B17 GBA1/IO62RSB0 B18 VCCIB1 B19 IO64RSB1 C1 GAB2/IO209RSB3 C2 IO210RSB3 C6 IO12RSB0 C14 IO47RSB0 C18 IO54RSB0 C19 GBB2/IO65RSB1 D1 IO206RSB3 D2 IO208RSB3 D4 GAA0/IO00RSB0 D5 GAA1/IO01RSB0 D6 IO10RSB0 D7 IO17RSB0 D8 IO24RSB0 D9 IO27RSB0 D10 GND D11 IO31RSB0 D12 IO40RSB0 D13 IO49RSB0 D14 IO45RSB0 D15 GBB0/IO59RSB0 D16 GBA2/IO63RSB1 D18 GBC2/IO67RSB1 D19 IO66RSB1 E1 IO203RSB3 E2 IO205RSB3 E4 IO07RSB0 E5 IO06RSB0 E6 IO14RSB0 E7 IO20RSB0 E8 IO29RSB0 E9 IO34RSB0 E10 IO30RSB0 E11 IO37RSB0 E12 IO38RSB0 CS281 Pin Number AGLP125 Function E13 IO48RSB0 E14 GBB1/IO60RSB0 E15 IO53RSB0 E16 IO69RSB1 E18 IO68RSB1 E19 IO71RSB1 F1 IO198RSB3 F2 GND F3 IO201RSB3 F4 IO204RSB3 F5 IO16RSB0 F15 IO50RSB0 F16 IO74RSB1 F17 IO72RSB1 F18 GND F19 IO73RSB1 G1 IO195RSB3 G2 IO200RSB3 G4 IO202RSB3 G5 IO08RSB0 G7 GAC2/IO207RSB3 G8 VCCIB0 G9 IO26RSB0 G10 IO35RSB0 G11 IO44RSB0 G12 VCCIB0 G13 IO51RSB0 G15 IO70RSB1 G16 IO75RSB1 G18 GCC0/IO80RSB1 G19 GCB1/IO81RSB1 H1 GFB0/IO191RSB3 H2 IO196RSB3 H4 GFC1/IO194RSB3 H5 GFB1/IO192RSB3 H7 VCCIB3 CS281 Pin Number AGLP125 Function

Pin Number AGLP125 Function K15 IO89RSB1 K16 GND K18 IO88RSB1 K19 VCCIB1 L1 GFB2/IO187RSB3 L2 IO185RSB3 L4 GFC2/IO186RSB3 L5 IO184RSB3 L7 IO199RSB3 L8 VCCIB3 L9 GND L10 GND L11 GND L12 VCCIB1 L13 IO95RSB1 L15 IO91RSB1 L16 NC L18 IO90RSB1 L19 NC M1 IO180RSB3 M2 IO179RSB3 M4 IO181RSB3 M5 IO183RSB3 M7 VCCIB3 M8 VCC M9 VCCIB2 M10 VCC M11 VCCIB2 M12 VCC M13 VCCIB1 M15 IO122RSB2 M16 IO93RSB1 M18 IO92RSB1 M19 NC N1 IO178RSB3 N2 IO175RSB3 CS281 Pin Number AGLP125 Function N4 IO182RSB3 N5 IO161RSB2 N7 GEA2/IO164RSB2 N8 VCCIB2 N9 IO137RSB2 N10 IO135RSB2 N11 IO131RSB2 N12 VCCIB2 N13 VPUMP N15 IO117RSB2 N16 IO96RSB1 N18 IO98RSB1 N19 IO94RSB1 P1 IO174RSB3 P2 GND P3 IO176RSB3 P4 IO177RSB3 P5 GEA0/IO165RSB3 P15 IO111RSB2 P16 IO108RSB2 P17 GDC1/IO99RSB1 P18 GND P19 IO97RSB1 R1 IO173RSB3 R2 IO172RSB3 R4 GEC1/IO170RSB3 R5 GEB1/IO168RSB3 R6 IO154RSB2 R7 IO149RSB2 R8 IO146RSB2 R9 IO138RSB2 R10 IO134RSB2 R11 IO132RSB2 R12 IO130RSB2 R13 IO118RSB2 R14 IO112RSB2 CS281 Pin Number AGLP125 Function

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-15 R15 IO109RSB2 R16 GDA1/IO103RSB1 R18 GDB0/IO102RSB1 R19 GDC0/IO100RSB1 T1 IO171RSB3 T2 GEC0/IO169RSB3 T4 GEB0/IO167RSB3 T5 IO157RSB2 T6 IO158RSB2 T7 IO148RSB2 T8 IO145RSB2 T9 IO143RSB2 T10 GND T11 IO129RSB2 T12 IO126RSB2 T13 IO125RSB2 T14 IO116RSB2 T15 GDC2/IO107RSB2 T16 TMS T18 VJTAG T19 GDB1/IO101RSB1 U1 IO160RSB2 U2 GEA1/IO166RSB3 U6 IO151RSB2 U14 IO121RSB2 U18 TRST U19 GDA0/IO104RSB1 V1 IO159RSB2 V2 VCCIB3 V3 GEC2/IO162RSB2 V4 IO156RSB2 V5 IO153RSB2 V6 GND V7 IO144RSB2 V8 IO141RSB2 V9 IO140RSB2 CS281 Pin Number AGLP125 Function V10 IO133RSB2 V11 IO127RSB2 V12 IO123RSB2 V13 IO120RSB2 V14 GND V15 IO113RSB2 V16 GDA2/IO105RSB2 V17 TDI V18 VCCIB2 V19 TDO W1 GND W2 FF/GEB2/IO163RSB W3 IO155RSB2 W4 IO152RSB2 W5 IO150RSB2 W6 IO147RSB2 W7 IO142RSB2 W8 IO139RSB2 W9 IO136RSB2 W10 VCCIB2 W11 IO128RSB2 W12 IO124RSB2 W13 IO119RSB2 W14 IO115RSB2 W15 IO114RSB2 W16 IO110RSB2 W17 GDB2/IO106RSB2 W18 TCK W19 GND CS281 Pin Number AGLP125 Function

For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx . Note: This is the bottom view of the package. 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U A1 Ball Pad Corner

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-17 CS289 Pin Number AGLP030 Function A1 IO03RSB0 A2 NC A3 NC A4 GND A5 IO10RSB0 A6 IO14RSB0 A7 IO16RSB0 A8 IO18RSB0 A9 GND A10 IO23RSB0 A11 IO27RSB0 A12 NC A13 NC A14 GND A15 NC A16 NC A17 IO30RSB0 B1 IO01RSB0 B2 GND B3 NC B4 NC B5 IO07RSB0 B6 NC B7 VCCIB0 B8 IO17RSB0 B9 IO19RSB0 B10 IO24RSB0 B11 IO28RSB0 B12 VCCIB0 B13 NC B14 NC B15 NC B16 IO31RSB0 B17 GND C1 NC C2 IO00RSB0 C3 IO04RSB0 C4 NC C5 VCCIB0 C6 IO09RSB0 C7 IO13RSB0 C8 IO15RSB0 C9 IO21RSB0 C10 GND C11 IO29RSB0 C12 NC C13 NC C14 NC C15 GND C16 IO34RSB0 C17 NC D1 NC D2 IO119RSB3 D3 GND D4 IO02RSB0 D5 NC D6 NC D7 NC D8 GND D9 IO20RSB0 D10 IO25RSB0 D11 NC D12 NC D13 GND D14 IO32RSB0 D15 IO35RSB0 D16 NC D17 NC E1 VCCIB3 E2 IO114RSB3 E3 IO115RSB3 E4 IO118RSB3 E5 IO05RSB0 E6 NC CS289 Pin Number AGLP030 Function E7 IO06RSB0 E8 IO11RSB0 E9 IO22RSB0 E10 IO26RSB0 E11 VCCIB0 E12 NC E13 IO33RSB0 E14 IO36RSB1 E15 IO38RSB1 E16 VCCIB1 E17 NC F1 IO111RSB3 F2 NC F3 IO116RSB3 F4 VCCIB3 F5 IO117RSB3 F6 NC F7 NC F8 IO08RSB0 F9 IO12RSB0 F10 NC F11 NC F12 NC F13 NC F14 GND F15 NC F16 IO37RSB1 F17 IO41RSB1 G1 IO110RSB3 G2 GND G3 IO113RSB3 G4 NC G5 NC G6 NC G7 GND G8 GND G9 VCC CS289 Pin Number AGLP030 Function

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-19 P2 NC P3 GND P4 NC P5 NC P6 IO87RSB2 P7 IO80RSB2 P8 GND P9 IO72RSB2 P10 IO67RSB2 P11 IO61RSB2 P12 NC P13 VCCIB2 P14 NC P15 IO60RSB2 P16 IO62RSB2 P17 VJTAG R1 GND R2 IO91RSB2 R3 NC R4 NC R5 NC R6 VCCIB2 R7 IO83RSB2 R8 IO78RSB2 R9 IO74RSB2 R10 IO70RSB2 R11 GND R12 NC R13 NC R14 NC R15 NC R16 TMS R17 TRST T1 IO92RSB3 T2 IO89RSB2 T3 NC T4 GND CS289 Pin Number AGLP030 Function T5 NC T6 IO84RSB2 T7 IO81RSB2 T8 IO76RSB2 T9 VCCIB2 T10 IO69RSB2 T11 IO65RSB2 T12 IO64RSB2 T13 NC T14 GND T15 NC T16 TDI T17 TDO U1 FF/IO90RSB2 U2 GND U3 NC U4 IO88RSB2 U5 IO86RSB2 U6 IO82RSB2 U7 GND U8 IO75RSB2 U9 IO73RSB2 U10 IO68RSB2 U11 IO66RSB2 U12 GND U13 NC U14 NC U15 NC U16 TCK U17 VPUMP CS289 Pin Number AGLP030 Function

Pin Number AGLP060 Function A1 GAB1/IO03RSB0 A2 NC A3 NC A4 GND A5 IO10RSB0 A6 IO14RSB0 A7 IO16RSB0 A8 IO18RSB0 A9 GND A10 IO23RSB0 A11 IO27RSB0 A12 NC A13 NC A14 GND A15 NC A16 NC A17 GBC0/IO30RSB0 B1 GAA1/IO01RSB0 B2 GND B3 NC B4 NC B5 IO07RSB0 B6 NC B7 VCCIB0 B8 IO17RSB0 B9 IO19RSB0 B10 IO24RSB0 B11 IO28RSB0 B12 VCCIB0 B13 NC B14 NC B15 NC B16 GBC1/IO31RSB0 B17 GND C1 IO155RSB3 C2 GAA0/IO00RSB0 C3 GAC0/IO04RSB0 C4 NC C5 VCCIB0 C6 IO09RSB0 C7 IO13RSB0 C8 IO15RSB0 C9 IO21RSB0 C10 GND C11 IO29RSB0 C12 NC C13 NC C14 NC C15 GND C16 GBA0/IO34RSB0 C17 IO39RSB1 D1 IO150RSB3 D2 IO151RSB3 D3 GND D4 GAB0/IO02RSB0 D5 NC D6 NC D7 NC D8 GND D9 IO20RSB0 D10 IO25RSB0 D11 NC D12 NC D13 GND D14 GBB0/IO32RSB0 D15 GBA1/IO35RSB0 D16 IO37RSB1 D17 IO42RSB1 E1 VCCIB3 E2 IO147RSB3 E3 GAC2/IO152RSB3 E4 GAA2/IO156RSB3 E5 GAC1/IO05RSB0 E6 NC E7 IO06RSB0 E8 IO11RSB0 CS289 Pin Number AGLP060 Function E9 IO22RSB0 E10 IO26RSB0 E11 VCCIB0 E12 NC E13 GBB1/IO33RSB0 E14 GBA2/IO36RSB1 E15 GBB2/IO38RSB1 E16 VCCIB1 E17 IO44RSB1 F1 GFC1/IO140RSB3 F2 IO142RSB3 F3 IO149RSB3 F4 VCCIB3 F5 GAB2/IO154RSB3 F6 IO153RSB3 F7 NC F8 IO08RSB0 F9 IO12RSB0 F10 NC F11 NC F12 NC F13 GBC2/IO40RSB1 F14 GND F15 IO43RSB1 F16 IO46RSB1 F17 IO45RSB1 G1 GFC0/IO139RSB3 G2 GND G3 IO144RSB3 G4 IO145RSB3 G5 IO146RSB3 G6 IO148RSB3 G7 GND G8 GND G9 VCC G10 GND G11 GND G12 IO48RSB1 CS289 Pin Number AGLP060 Function

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-21 G13 IO41RSB1 G14 IO47RSB1 G15 IO49RSB1 G16 IO50RSB1 G17 GND H1 VCOMPLF H2 GFB0/IO137RSB3 H3 NC H4 IO141RSB3 H5 IO143RSB3 H6 GFB1/IO138RSB3 H7 GND H8 GND H9 GND H10 GND H11 GND H12 GCC1/IO52RSB1 H13 IO51RSB1 H14 GCA0/IO57RSB1 H15 VCCIB1 H16 GCA2/IO58RSB1 H17 GCC0/IO53RSB1 J1 VCCPLF J2 GFA1/IO136RSB3 J3 VCCIB3 J4 IO131RSB3 J5 IO130RSB3 J6 IO129RSB3 J7 VCC J8 GND J9 GND J10 GND J11 VCC J12 GCB2/IO59RSB1 J13 GCB1/IO54RSB1 J14 IO62RSB1 J15 IO63RSB1 J16 GCB0/IO55RSB1 CS289 Pin Number AGLP060 Function J17 GCA1/IO56RSB1 K1 GND K2 GFA0/IO135RSB3 K3 GFB2/IO133RSB3 K4 IO128RSB3 K5 IO123RSB3 K6 IO125RSB3 K7 GND K8 GND K9 GND K10 GND K11 GND K12 IO64RSB1 K13 IO61RSB1 K14 IO66RSB1 K15 IO65RSB1 K16 GND K17 GCC2/IO60RSB1 L1 GFA2/IO134RSB3 L2 GFC2/IO132RSB3 L3 IO127RSB3 L4 GND L5 IO121RSB3 L6 GEC1/IO116RSB3 L7 GND L8 GND L9 VCC L10 GND L11 GND L12 GDC1/IO72RSB1 L13 GDB1/IO74RSB1 L14 VCCIB1 L15 IO70RSB1 L16 IO68RSB1 L17 IO67RSB1 M1 IO126RSB3 M2 VCCIB3 M3 IO124RSB3 CS289 Pin Number AGLP060 Function M4 IO122RSB3 M5 GEB0/IO113RSB3 M6 GEB1/IO114RSB3 M7 NC M8 NC M9 IO90RSB2 M10 NC M11 IO83RSB2 M12 NC M13 GDA1/IO76RSB1 M14 GDA0/IO77RSB1 M15 IO71RSB1 M16 IO69RSB1 M17 VCCIB1 N1 IO119RSB3 N2 IO120RSB3 N3 GEC0/IO115RSB3 N4 GEA0/IO111RSB3 N5 GND N6 NC N7 IO104RSB2 N8 IO98RSB2 N9 IO96RSB2 N10 VCCIB2 N11 NC N12 NC N13 GDB2/IO79RSB2 N14 NC N15 GND N16 GDB0/IO75RSB1 N17 GDC0/IO73RSB1 P1 IO118RSB3 P2 IO117RSB3 P3 GND P4 NC P5 NC P6 IO106RSB2 P7 IO99RSB2 CS289 Pin Number AGLP060 Function

Pin Number AGLP060 Function T12 IO82RSB2 T13 NC T14 GND T15 NC T16 TDI T17 TDO U1 FF/GEB2/IO109RS U2 GND U3 NC U4 IO107RSB2 U5 IO105RSB2 U6 IO101RSB2 U7 GND U8 IO94RSB2 U9 IO92RSB2 U10 IO87RSB2 U11 IO85RSB2 U12 GND U13 NC U14 NC U15 NC U16 TCK U17 VPUMP CS289 Pin Number AGLP060 Function

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-23 CS289 Pin Number AGLP125 Function A1 GAB1/IO03RSB0 A2 IO11RSB0 A3 IO08RSB0 A4 GND A5 IO19RSB0 A6 IO24RSB0 A7 IO26RSB0 A8 IO30RSB0 A9 GND A10 IO35RSB0 A11 IO38RSB0 A12 IO40RSB0 A13 IO42RSB0 A14 GND A15 IO48RSB0 A16 IO54RSB0 A17 GBC0/IO57RSB0 B1 GAA1/IO01RSB0 B2 GND B3 IO06RSB0 B4 IO13RSB0 B5 IO15RSB0 B6 IO21RSB0 B7 VCCIB0 B8 IO28RSB0 B9 IO31RSB0 B10 IO37RSB0 B11 IO39RSB0 B12 VCCIB0 B13 IO44RSB0 B14 IO46RSB0 B15 IO49RSB0 B16 GBC1/IO58RSB0 B17 GND C1 IO210RSB3 C2 GAA0/IO00RSB0 C3 GAC0/IO04RSB0 C4 IO09RSB0 C5 VCCIB0 C6 IO17RSB0 C7 IO23RSB0 C8 IO27RSB0 C9 IO33RSB0 C10 GND C11 IO43RSB0 C12 IO45RSB0 C13 IO50RSB0 C14 IO52RSB0 C15 GND C16 GBA0/IO61RSB0 C17 IO68RSB1 D1 IO204RSB3 D2 IO205RSB3 D3 GND D4 GAB0/IO02RSB0 D5 IO07RSB0 D6 IO10RSB0 D7 IO18RSB0 D8 GND D9 IO34RSB0 D10 IO41RSB0 D11 IO47RSB0 D12 IO55RSB0 D13 GND D14 GBB0/IO59RSB0 D15 GBA1/IO62RSB0 D16 IO66RSB1 D17 IO70RSB1 E1 VCCIB3 E2 IO200RSB3 E3 GAC2/IO207RSB3 E4 GAA2/IO211RSB3 E5 GAC1/IO05RSB0 E6 IO12RSB0 E7 IO16RSB0 E8 IO22RSB0 CS289 Pin Number AGLP125 Function E9 IO32RSB0 E10 IO36RSB0 E11 VCCIB0 E12 IO56RSB0 E13 GBB1/IO60RSB0 E14 GBA2/IO63RSB1 E15 GBB2/IO65RSB1 E16 VCCIB1 E17 IO73RSB1 F1 GFC1/IO194RSB3 F2 IO196RSB3 F3 IO202RSB3 F4 VCCIB3 F5 GAB2/IO209RSB3 F6 IO208RSB3 F7 IO14RSB0 F8 IO20RSB0 F9 IO25RSB0 F10 IO29RSB0 F11 IO51RSB0 F12 IO53RSB0 F13 GBC2/IO67RSB1 F14 GND F15 IO75RSB1 F16 IO71RSB1 F17 IO77RSB1 G1 GFC0/IO193RSB3 G2 GND G3 IO198RSB3 G4 IO203RSB3 G5 IO201RSB3 G6 IO206RSB3 G7 GND G8 GND G9 VCC G10 GND G11 GND G12 IO72RSB1 CS289 Pin Number AGLP125 Function

Pin Number AGLP125 Function J17 GCA1/IO83RSB1 K1 GND K2 GFA0/IO189RSB3 K3 GFB2/IO187RSB3 K4 IO179RSB3 K5 IO175RSB3 K6 IO177RSB3 K7 GND K8 GND K9 GND K10 GND K11 GND K12 IO88RSB1 K13 IO94RSB1 K14 IO95RSB1 K15 IO93RSB1 K16 GND K17 GCC2/IO87RSB1 L1 GFA2/IO188RSB3 L2 GFC2/IO186RSB3 L3 IO182RSB3 L4 GND L5 IO173RSB3 L6 GEC1/IO170RSB3 L7 GND L8 GND L9 VCC L10 GND L11 GND L12 GDC1/IO99RSB1 L13 GDB1/IO101RSB1 L14 VCCIB1 L15 IO98RSB1 L16 IO92RSB1 L17 IO91RSB1 M1 IO184RSB3 M2 VCCIB3 M3 IO176RSB3 CS289 Pin Number AGLP125 Function M4 IO172RSB3 M5 GEB0/IO167RSB3 M6 GEB1/IO168RSB3 M7 IO159RSB2 M8 IO161RSB2 M9 IO135RSB2 M10 IO128RSB2 M11 IO121RSB2 M12 IO113RSB2 M13 GDA1/IO103RSB1 M14 GDA0/IO104RSB1 M15 IO97RSB1 M16 IO96RSB1 M17 VCCIB1 N1 IO180RSB3 N2 IO178RSB3 N3 GEC0/IO169RSB3 N4 GEA0/IO165RSB3 N5 GND N6 IO156RSB2 N7 IO148RSB2 N8 IO144RSB2 N9 IO137RSB2 N10 VCCIB2 N11 IO119RSB2 N12 IO111RSB2 N13 GDB2/IO106RSB2 N14 IO109RSB2 N15 GND N16 GDB0/IO102RSB1 N17 GDC0/IO100RSB1 P1 IO174RSB3 P2 IO171RSB3 P3 GND P4 IO160RSB2 P5 IO157RSB2 P6 IO154RSB2 P7 IO152RSB2 CS289 Pin Number AGLP125 Function

IGLOO PLUS Low Power Flash FPGAs Revision 16 4-25 P8 GND P9 IO132RSB2 P10 IO125RSB2 P11 IO126RSB2 P12 IO112RSB2 P13 VCCIB2 P14 IO108RSB2 P15 GDA2/IO105RSB2 P16 GDC2/IO107RSB2 P17 VJTAG R1 GND R2 GEA2/IO164RSB2 R3 IO158RSB2 R4 IO155RSB2 R5 IO150RSB2 R6 VCCIB2 R7 IO145RSB2 R8 IO141RSB2 R9 IO134RSB2 R10 IO130RSB2 R11 GND R12 IO118RSB2 R13 IO116RSB2 R14 IO114RSB2 R15 IO110RSB2 R16 TMS R17 TRST T1 GEA1/IO166RSB3 T2 GEC2/IO162RSB2 T3 IO153RSB2 T4 GND T5 IO147RSB2 T6 IO143RSB2 T7 IO140RSB2 T8 IO139RSB2 T9 VCCIB2 T10 IO131RSB2 T11 IO127RSB2 CS289 Pin Number AGLP125 Function T12 IO124RSB2 T13 IO122RSB2 T14 GND T15 IO115RSB2 T16 TDI T17 TDO U1 FF/GEB2/IO163RS U2 GND U3 IO151RSB2 U4 IO149RSB2 U5 IO146RSB2 U6 IO142RSB2 U7 GND U8 IO138RSB2 U9 IO136RSB2 U10 IO133RSB2 U11 IO129RSB2 U12 GND U13 IO123RSB2 U14 IO120RSB2 U15 IO117RSB2 U16 TCK U17 VPUMP CS289 Pin Number AGLP125 Function

5 – Datasheet Information List of Changes The following table lists critical changes that were made in each revision of the IGLOO PLUS datasheet. Revision Changes Page Revision 16 (December 2012) The "IGLOO PLUS Ordering Information" section has been updated to mention "Y" as "Blank" mentioning "Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43175). III The note in Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to the online help associated with the core (SAR 42566). 2-61, 2-62 Live at Power-Up (LAPU) has been replaced with ’Instant On’. NA Revision 15 (October 2012) Values updated for IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage in Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices and for IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage in Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices (SAR 31988). Also added a new Note to the two tables. 2-10, 2-11 Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip (SoC) throughout the document (SAR 40277). N/A Revision 14 (September 2012) The "Security" section was modified to clarify that Microsemi does not support read- back of programmed data. 1-2 Revision 13 (June 2012) Figure 2-30 • FIFO Read and Figure 2-31 • FIFO Write have been added (SAR 34843). 2-73 Updated the terminology used in Timing Characteristics in the following tables: Table 2-96 • FIFO and Table 2-97 • FIFO (SAR 38236). 2-76 The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section in the "Pin Descriptions and Packaging" section : "Within the package, the VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI domain" and replaced with “Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks” (SAR 38320). The datasheet mentions that "VMV pins must be connected to the corresponding VCCI pins" for an ESD enhancement. 3-1 Revision 12 (March 2012) The "In-System Programming (ISP) and Security" section and "Security" section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implem ent the best security available in the industry (SAR 34664). I, 1-2 The Y security option and Licensed DPA Logo were added to the "IGLOO PLUS Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 34724). III The "Specifying I/O States During Programming" section is new (SAR 34695). 1-7 The following sentence was removed from the "Advanced Architecture" section: "In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IG LOO PLUS devices via an IEEE 1532 JTAG interface" (SAR 34684). 1-3

(continued) The reference to guidelines for global spines and VersaTile rows, given in the "Global Clock Contribution—PCLOCK" section , was corrected to t he "Spine Architecture" section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric User's Guide (SAR 34733). 2-12 tDOUT was corrected to t DIN in Figure 2-4 • Input Buffer Timing Model and Delays (example) (SAR 37107). 2-16 The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section (SAR 34887). 2-27 Minimum pulse width High and Low values were added to the tables in the "Global Tree Timing Characteristics" section . The maximum frequency for global clock parameter was removed from these tables because a frequency on the global is only an indication of what the global network can do. There are other limiters such as the SRAM, I/Os, and PLL. SmartTime software should be used to determine the design frequency (SAR 36963). 2-58 Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS CCC/PLL Specification were updated. A note was added to both tables indicating that when the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available (SAR 34820). The value for serial clock was missing from these tables and has been restored. The value and units for input cycle-to-cycle jitt er were incorrect and have been restored. The note to Table 2-90 • IGLOO PLUS CCC/PLL Specification giving specifications for which measurements done was corre cted from VCC/VCCPLL = 1.14 V to VCC/VCCPLL = 1.425 V. The Delay Range in Block: Programmable Delay 2 value in Table 2-91 • IGLOO PLUS CCC/PLL Specification was corrected from 0.025 to 0.863 (SAR 37058). 2-61, 2-62 Figure 2-28 • Write Access after Read onto Same Address was deleted. Reference was made to a new application note, Simultaneous Read-Write Operations in Dual- Port SRAM for Flash-Based cSoCs and FPGA s, which covers these cases in detail (SAR 34868). The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" tables, Figure 2-32 • FIFO Reset, and the FIFO "Timing Characteristics" tables were revised to ensure consistency with the software names (SAR 35748). 2-65, 2-68, 2-74, 2-76 The "Pin Descriptions and Packaging" chapter has been added (SAR 34769). 3-1 Package names used in the "Package Pin Assignments" section were revised to match standards given in Package Mechanical Drawings (SAR 34769). 4-1 Revision 11 (July 2010) The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "IGLOO PLUS Device Status" table indicates the status for each device in the family. N/A The "Reprogrammable Flash Technology" section was revised to add "250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance." I The "I/Os with Advanced I/O Standards" section was revised to add definitions for hot-swap and cold-sparing. 1-6 Conditional statements regarding hot insertion were removed from the description of VI in Table 2-1 • Absolute Maximum Ratings, since all IGLOO PLUS devices are hot insertion enabled. 2-1 Revision Changes Page

IGLOO PLUS Low Power Flash FPGAs Revision 16 5-3 Revision 11 (continued) Table 2-2 • Recommended Operating Conditions1,2 was revised. 1.2 V DC wide range supply voltage and 3.3 V wide range supply voltage (SAR 26270) were added for VCCI. VJTAG DC Voltage was revised (SAR 24052). The value range for VPUMP programming voltage for operation was changed from "0 to 3.45" to "0 to 3.6" (SAR 25220). 2-2 Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were revised. 2-6, 2-7 Table 2-8 • Power Supply State per Mode is new. 2-7 The tables in the "Quiescent Supply Current" section were updated (SARs 24882 and 24112). Some of the table notes were changed or deleted. 2-7 VIH maximum values in tables were updated as needed to 3.6 V (SARs 20990, 79370). N/A The values in the following tables were updated. 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added to the tables where applicable. Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Table 2-22 • Summary of Maximum and Minimum DC Input Levels Table 2-23 • Summary of AC Measuring Points Table 2-25 • Summary of I/O Timing Char acteristics—Software Default Settings, STD Speed Grade, Commercial-Case Cond itions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Table 2-26 • Summary of I/O Timing Char acteristics—Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Table 2-28 • I/O Output Buffer Maximum Resistances 1 2-9 2-9 2-19 2-20 2-21 2-22 2-23 2-24 A table note was added to Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices and Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices stating the value for PDC4 is the minimum contribution of the PLL when operating at lowest frequency. 2-11, 2-12 Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances was revised, including addition of 3.3 V and 1.2 V LVCMOS wide range. The notes defining R WEAK PULL-UP-MAX and R WEAK PULLDOWN-MAX were revised (SAR 21348). 2-25 Table 2-30 • I/O Short Currents IOSH/IOSL was revised to include data for 3.3 V and 1.2 V LVCMOS wide range (SAR 79353 and SAR 79366). 2-25 Table 2-31 • Duration of Short Circuit Event before Failure was revised to change the maximum temperature from 110°C to 100°C, with an example of six months instead of three months (SAR 26259). 2-26 Revision Changes Page

(continued) The tables in the "Single-Ended I/O Characteristics" section were updated. Notes clarifying IIL and IIH were added. Tables for 3.3 V LVCMOS and 1.2 V LVCMOS wide range were added (SAR 79370, SAR 79353, and SAR 79366). Notes in the wide range tables state th at the minimum drive strength for any LVCMOS 3.3 V (or LVCMOS 1.2 V) software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 25700). 2-27 The following sentence was deleted from the "2.5 V LVCMOS" section : It uses a 5 V–tolerant input buffer and push-pull output buffer (SAR 24916). 2-32 The tables in the "Input Register" section , "Output Register" section , and "Output Enable Register" section were updated. The tables in the "VersaTile Characteristics" section were updated. 2-45 through 2-56 The following tables were updated in the "Global Tree Timing Characteristics" section: Table 2-85 • AGLP060 Global Resource (1.5 V) Table 2-86 • AGLP125 Global Resource (1.5 V) Table 2-88 • AGLP060 Global Resource (1.2 V) 2-58 Table 2-90 • IGLOO PLUS CCC/PLL Specification and Table 2-91 • IGLOO PLUS CCC/PLL Specification were revised (SAR 79388). VCO output jitter and maximum peak-to-peak jitter data were changed. Three notes were added to the table in connection with these changes. 2-61 Figure 2-28 • Write Access after Write onto Same Address and Figure 2-29 • Write Access after Read onto Same Address were deleted. N/A The tables in the "SRAM", "FIFO" and "Embedded FlashROM Characteristics" sections were updated. 2-68, 2-78 Revision Changes Page

IGLOO PLUS Low Power Flash FPGAs Revision 16 5-5 Revision Changes Page Revision 10 (Apr 2009) Product Brief v1.5 DC and Switching Characteristics Advance v0.5 The –F speed grade is no longer offered for IGLOO PLUS devices. References to it have been removed from the document. The speed grade column and note regarding –F speed grade were removed from "IGLOO PLUS Ordering Information". The "Speed Grade and Temperature Grade Matrix" section was removed. III, IV Revision 9 (Feb 2009) Product Brief v1.4 The "Advanced I/O" section was revised to add two bullets regarding support of wide range power supply voltage. I The "I/Os with Advanced I/O Standards" section was revised to add 3.0 V wide range to the list of supported voltages. The "Wide Range I/O Support" section is new. 1-7 Revision 8 (Jan 2009) Packaging v1.5 The "CS201" pin table was revised to add a note regarding pins G1 and H1. 4-8 Revision 7 (Dec 2008) Product Brief v1.3 A note was added to IGLOO PLUS Devices : "AGLP060 in CS201 does not support the PLL." I Table 2 • IGLOO PLUS FPGAs Package Size Dimensions was updated to change the nominal size of VQ176 from 100 to 400 mm II Revision 6 (Oct 2008) DC and Switching Characteristics Advance v0.4 Data was revised significantly in the following tables: Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings, STD Speed Grade Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Table 2-50 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Table 2-51 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage 2-22, 2-33 Revision 5 (Aug 2008) Product Brief v1.2 The VQ128 and VQ176 packages were added to Table 1 • IGLOO PLUS Product Family, the "I/Os Per Package 1" table, Table 2 • IGLOO PLUS FPGAs Package Size Dimensions , "IGLOO PLUS Ordering Information" , and the "Temperature Grade Offerings" table. I to IV Packaging v1.4 The "VQ128" package drawing and pin table are new. 4-2 The "VQ176" package drawing and pin table are new. 4-5 Revision 4 (Jul 2008) Product Brief v1.1 DC and Switching Characteristics Advance v0.3 As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. N/A Revision 3 (Jun 2008) DC and Switching Characteristics Advance v0.2 Tables have been updated to reflect default values in the software. The default I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O set. N/A Table note 3 was updated in Table 2-2 • Recommended Operating Conditions1,2 to add the sentence, "VCCI should be at the same voltage within a given I/O bank." References to table notes 5, 6, 7, and 8 were added. Reference to table note 3 was removed from VPUMP Operation and placed next to VCC. 2-2 Table 2-4 • Overshoot and Undershoot Limits 1 was revised to remove "as measured on quiet I/Os" from the title. Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was deleted. 2-3

Revision 3 (continued) The table note for Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Flash*Freeze Mode* to remove the sentence stating that values do not include I/O static contribution. 2-7 The table note for Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Sleep Mode* was updated to remove VJTAG and VCCI and the statement that values do not include I/O static contribution. 2-7 The table note for Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO PLUS Shutdown Mode was updated to remove the statement that values do not include I/O static contribution. 2-8 Note 2 of Table 2-12 • Quiescent Supply Current (IDD), No IGLOO PLUS Flash*Freeze Mode 1 was updated to include VCCPLL. Table note 4 was deleted. 2-8 Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings and Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 were updated to remove static power. The table notes were updated to reflect that power was measured on VCC I. Table note 2 was added to Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings. 2-9, 2-9 Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices and Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices were updated to change the definition for P DC5 from bank static power to bank quiescent power. Table subtitles were added for Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices , Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices, and Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices. 2-11, 2-12 The "Total Static Power Consumption—PSTAT" section was revised. 2-12 Table 2-32 • Schmitt Trigger Input Hysteresis is new. 2-26 Packaging v1.3 The "CS281" package drawing is new. 4-13 The "CS281" table for the AGLP125 device is new. 4-13 CS281 mechanical drawing and not the CS289 mechanical drawing. This has now been corrected. 4-17 Revision 2 (Jun 2008) Packaging v1.2 The "CS289" table for the AGLP030 device is new. 4-17 Revision 1 (Jun 2008) Packaging v1.1 The "CS289" table for the AGLP060 device is new. 4-20 The "CS289" table for the AGLP125 device is new. 4-23 Revision Changes Page

IGLOO PLUS Low Power Flash FPGAs Revision 16 5-7 Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "IGLOO PLUS Device" table on page II , is designated as ei ther "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a data sheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, bu t not for production. This label only applies to the DC and Switching Characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Production This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subj ect to the Export Administ ration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The products described in this advance status document may not have completed the Microsemi qualification process. Products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult the Microsemi SoC Products Group Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the SoC Products Group’s products is available at http://www.microsemi.com/soc/documents/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local sales office for additional reliability information.

51700102-16/12.12 © 2012 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquarter ed in Aliso Viejo, Calif. Learn more at www.microsemi.com. Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA 92656 USA Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996

Product Information

AGLP125V2-CS281I specifications and overview.

Summary

IGLOO PLUS Low Power Flash FPGAs

Description

IGLOO PLUS Low Power Flash FPGAs

Source title AGLP125V2-CS281I Datasheet(PDF) - Microsemi Corporation

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