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XGS ONSEMI | Alldatasheet

Document overview

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Technical content

Features

• On−chip 12−bit Column ADCs
• 10−bit Mode with Increased Frame Rate of 100 fps (24−lane) at Full Resolution
• Companding and 10−Bit Mode at 60 fps (12−lane) and 30 fps (6−lane)
• Data Interface: 24−lane HiSPi (Scalable Low−V oltage Signaling)
• Configurable Number of HiSPi Lanes: 24, 18, 12 or 6 Lanes
• Two−Wire (I2C) and Four−Wire (SPI) Serial Interface
• Triggered Integration and Readout Control
• Programmable Control for up to 8 Regions of Interest (ROI)
• Context Switching
• These Devices are Pb−Free, Halogen Free/ BFR Free and are RoHS Compliant

Applications

• Machine Vision
• Security
• Intelligent Transportation Systems (ITS)
• Broadcasting
• Medical
• Scientific

www.onsemi.com

ORDERING INFORMATION

Table 2. ORDERABLE PART NUMBERS (Notes 1 and 2)

1. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for ima ge

sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.

1. All devices listed in Table 2 are equipped with microlenses.

Table 3. ORDERING INFORMATION EVALUATION KITS NOIX1SN012KBLFB−GEVB Sensor Headboard (12.6 Mp, Mono, 24−Lane) Demo Kit Headboard (incl. NOIX1SE012KBLFB−GEVB Sensor Headboard (12.6 Mp, Color, 24−Lane) Demo Kit Headboard (incl.

1. Sensors are soldered to the headboard.

www.onsemi.com The on−chip logic, programmable through the Two−Wire (I2C) or Four −Wire (SPI) Serial Interface, generates all internal timing for integration control and frame readout. Once a row has been read, the data from the columns is sequenced through an analog signal chain (providing coarse analog gain) and then through a 12 −bit column ADC. The data from the ADCs is first stored in the on −chip column memory bank prior to being processed by the digital data path (which provides additional data processing including digital gain and offset). The digital multiplexer can be configured to reduce the number of active data lanes. The maximum output pixel rate on a single lane is 64.8 Megapixel per second, corresponding to a clock rate of 32.4 MHz. Advanced trigger functions enable synchronization to external events (triggered master and slave mode) but also allow synchronizing image readout with the host (receiver) on a frame or line basis (triggered frame or line readout). The sensor supports configuration of up to eight independent ROIs and up to three register configurations (contexts) can be programmed and sequentially applied (frame by frame) with a single command over the control interface. Refer to Figure 1 for the functional blocks described hereafter.

• Two−Wire Serial Interface (I2C) I2C−compatible, two−wire serial interface enables user interaction with sensor.
• (Four−Wire) Serial Peripheral Interface (SPI) The Four−Wire serial interface can be used as an alternative to the two−wire interface. The SPI enables faster sensor (re−)configuration compared to the two−wire serial interface.
• EXTCLK The nominal input−clock frequency is 32.4 MHz. This clock serves as the base clock for the derived clock domains required by the internal sub−blocks and HiSPi output interface.
• Phase−locked Loop (PLL) The on−chip phase−locked loop generates all the internal system clocks, including the HiSPi clock.
• Bias Generator The bias generator generates the required reference currents used by the on−chip blocks.
• Sequencer The sequencer generates the sensor timing and controls the image core which contains all pixels, driving and readout circuits. It controls the ADC circuits and provides the necessary information to the digital data path. The sequencer operating and readout modes (ROI readout, subsampling...) can be configured through the SPI interface. The readout parameters are synchronized to frame boundaries to support dynamic reconfiguration without generating any corrupted images.
• Row Driver The row drivers generate the reset and select signals used to operate the pixel array.
• Monitor Pins The sequencer can communicate its internal states through the monitor output pins.
• Column Structure The column structure contains the analog circuits necessary to ensure a proper transfer of the signal to the column ADC. This structure includes the column amplifiers which can be used to apply analog gain to the signal before these are converted by the ADCs. The sensor supports analog gain of 1x, 2x and 4x. The analog gain is applied globally to all pixels.
• Column ADC For each column, a 12−bit ADC converts the analog signal into a digital value.
• Digital Gain A linear, digital gain ranging from 1/32x up to 2x can be configured separately for each color channel in steps of 1/32.
• Data Pedestal This block adds a user programmable, per color channel digital offset to the pixel values.
• Digital Mux This block handles the lane multiplexing which can be used to reduce the number of output lanes.
• HiSPi The 24 HiSPi lanes are laid out in six identical HiSPi blocks. Each block consists of four data lanes and one clock lane. The number of active data lanes (1, 2, 3 or 4) depends on the selected multiplex mode.

Table 1. As shown in Figures 2 through 4, the active array that the windows are configured in logical kernel addresses. overlapping part is read out only once. image pixels are preceded and followed by 4 dummy pixels. reference pixels followed by 4 dummy pixels.

Figure 2. XGS 12000 Pixel Array

Figure 3. XGS 9400 Pixel Array

Figure 4. XGS 8000 Pixel Array

www.onsemi.com CONFIGURATION AND PINOUT TYPICAL CONFIGURATIONS Two possible configuration examples are depicted in the figures below. The first example (Figure 8) uses the Four−Wire Serial Interface while the second example (Figure 9) depicts a typical Two −Wire Serial Interface implementation. Pin connections to (and from) the sensor and power supply configurations are shown in the figures below. The recommended decoupling capacitors are listed in Table 4. Configuration Example:

• VDD_SLVS = 1.2 V (or 0.4 V); VDD = 1.2 V; VDD_IO = 2.8 V (or 1.8 V); VDD_PLL = 2.8 V;
• VAA = 2.8 V; VAA_PIX = 3.0 V; VAA_RD = 3.0 V; VAA_PIX_BST = 3.0 V
• 24 data lanes + 2 clock lanes

Figure 8. Typical Configuration (Four−Wire Serial Interface)

32.4 MHz

1. All power supplies must be adequately decoupled (see Table 4) Decoupling.
2. In this example, only 2 (out of 6) HiSPi clock lanes are used; D_CLK_2 to sample data on the even data lanes (top readout) and

D_CLK_3 to sample data on the odd data lanes (bottom readout).

1. The active HiSPi lanes need to be terminated using 100 /C0087 resistors placed as close to the receiver as possible.
2. Unused HiSPi outputs (data and/or clock lanes) must be left floating.
3. It is highly recommended to route the monitor signals to the receiver (FPGA) for debugging purposes. If the MONITOR outputs

are not used, they must be left floating.

1. If the TRIGGER inputs are not used, tie them to GND.
2. No distinction is made between analog and digital ground (internally shorted).
3. FWSI_EN must be connected to V

DD_IO through a 10 k/C0087 resistor (enable Four−Wire Serial Interface).

1. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
2. Digital inputs RESET_N and CS_N are both active low.

Figure 9. Typical Configuration (Two−Wire Serial Interface)

1. All power supplies must be adequately decoupled (see Table 4) Decoupling.
2. In this example, only 2 (out of 6) HiSPi clock lanes are used; D_CLK_2 to sample data on the even data lanes (top readout) and

D_CLK_3 to sample data on the odd data lanes (bottom readout).

1. The active HiSPi lanes need to be terminated using 100 /C0087 resistors placed as close to the receiver as possible.
2. Unused HiSPi outputs (data and/or clock lanes) must be left floating.
3. It is highly recommended to route the monitor signals to the receiver (FPGA) for debugging purposes. If the MONITOR outputs

are not used, they must be left floating.

1. If the TRIGGER inputs are not used, tie them to GND.
2. No distinction is made between analog and digital ground (internally shorted).
3. FWSI_EN and CS_N must be tied to GND when using the Two−Wire Serial Interface. S

dataout can be left floating.

1. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
2. Digital input RESET_N is active low.
3. ON Semiconductor recommends using a 1.5 k/C0087 pull−up resistor to VDD_IO on both Sclk and Sdata.

Table 4. DECOUPLING RECOMMENDATIONS Figure 10. XGS CLGA Package Pinout (Top View; Pads Down)

Table 5. PIN DESCRIPTIONS (163−PIN LGA PACKAGE) MONITOR_2 D7 Output Monitor Output 2. If unused, do not connect. MONITOR_1 D8 Output Monitor Output 1. If unused, do not connect. MONITOR_0 E8 Output Monitor Output 0. If unused do not connect.

RESET_N signal is de−asserted. reset_register_reg (R0x3700) needs to be set to 0x001C. to receive image data, the sensor’s sequencer can be enabled. state machine will transition back to the SLEEP state. RESET state, regardless of the current state. The sensor state diagram is shown in Figure 11. Figure 11. Sensor State Diagram found in the developer guide. Table 6. TYPICAL TRANSITION TIMES POWER−DOWN 25 ms Time required to transition from POWER−DOWN to CAPTURE state. SLEEP 10 ms Time required to transition from SLEEP to CAPTURE state. STANDBY < 16 line times Time required to transition from STANDBY to CAPTURE state. trigger action). A minimum delay of one line time will be added.

1. Turn on VDD_IO power supply.
2. After 0−100 /C0109s, turn on VDD_PLL power supply.
3. After 0−100 /C0109s, turn on VDD power supply.
4. After 0−100 /C0109s, turn on VAA power supply.
5. Once VAA is stable, power up VAA_PIX,
6. Once VAA_PIX, VAA_PIX_BST and VAA_RD are
7. After VDD_SLVS is stable, enable EXTCLK.
8. After EXTCLK has settled, hold RESET_N low

de−asserting the reset signal.

1. The sensor then loads the default register values

default register values from it internal memory.

1. Enable PLL and initialize sensor’s internal analog

blocks (reset_register_reg = 0x001C).

1. Once the analog blocks are initialized
2. Enable the sequencer to transition to the

CAPTURE state (general_config0_reg[0] = 1). Figure 12. Power−Up Sequence

Table 7. POWER−UP SEQUENCE

1. The EXTCLK settling time is component −dependent.
2. The minimum time does not include the settling time of the power supply.

supplies must have the separation specified below.

1. Disable CAPTURE if output is active by disabling

the sequencer (general_config0_reg[0] = 0).

1. Issue a sensor STANDBY request
2. In STANDBY mode, activate reset by pulling
3. EXTCLK can be stopped 0.5 ms after RESET_N.
4. Turn off power supplies one by one. Wait at least

Figure 13. Power−Down Sequence Table 8. POWER−DOWN SEQUENCE

1. The minimum time does not include the settling time of the power supply.

Table 10. MINIMUM INTEGRATION TIME LIMITATIONS (Note 7)

1. The minimum integration time depends on the configured line time. The values in this table assume the minimum recommended line time
2. Refer to the XGS 12000 Developer Guide for more information on the minimum integration times.

autonomously. This is the default readout mode. that control the triggered readout operation. Table 11. TRIGGERED READOUT PARAMETERS frame_trigger_en Start the frame readout upon assertion of TRIG_RD when enabled. This configuration has priority over line_trigger_en. frame_trigger_mode Only valid for frame triggered readout modes. ‘1’: The sequencer continues frame grabbing as long as the trigger is asserted. desired, frames should be configured to 0. Figure 21. Frame Triggered Readout Mode first coming internal new line reference (internal time base).

• contexts_reg.frames > 0: The Sequencer continues running and reads out the given amount of frames, after which it returns to the WAIT_ON_TRIGGER state. After the readout, the sequencer is waiting for another trigger, after which a new sequence is initiated. Note that a new batch of frames shall be read out in case the trigger is asserted at the end of the previous batch.
• contexts_reg.frames = 0: The Sequencer continues running as long as the TRIG_RD is asserted. Once the trigger is deasserted, the Sequencer returns to the

FWSI_EN pin (‘LOW’ = two−wire, ‘HIGH’ = four−wire). Figure 38. Serial Interface Selection access to control and status registers within the sensor. is an input to the sensor and is used to synchronize transfers.

• a (repeated) start condition
• a slave address/data direction byte
• an (a no) acknowledge bit
• a message byte
• a stop condition The bus is idle when both S CLK and S DATA are HIGH. Control of the bus is initiated with a start condition, and the bus is released with a stop condition. Only the master can generate the start and stop conditions. Start Condition A start condition is defined as a HIGH −to−LOW transition on S DATA while S CLK is HIGH. At the end of a transfer, the master can generate a start condition without previously generating a stop condition; this is known as a ”repeated start” or ”restart” condition. Stop Condition A stop condition is defined as a LOW−to−HIGH transition on SDATA while SCLK is HIGH. Data Transfer Data is transferred serially, 8 bits at a time, with the MSB transmitted first. Each byte of data is followed by an acknowledge bit or a no−acknowledge bit. This data transfer mechanism is used for the slave address/data direction byte and for message bytes. One data bit is transferred during each S CLK clock period. SDATA can change when S CLK is LOW and must be stable while SCLK is HIGH. Slave Address/Data Direction Byte Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data transfer direction. A ’0’ in bit [0] indicates a WRITE, and a ’1’ indicates a READ. The default slave addresses used by the sensor are 0x20 (write address) and 0x21 (read address).

generating a stop conditions. Figure 44. Sequential WRITE, Start at Random Location

NOTE: Read sequence: For an 8 −bit READ, read waveforms start after WRITE command and register address are issued. Figure 49. Two−Wire Serial Bus Timing Parameters Table 13. TWO−WIRE SERIAL BUS CHARACTERISTICS

1. This table is based on I 2C standard (v2.1 January 2000). Philips Semiconductor.

10.Two−wire control is I2C−compatible.

1. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.

12.The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 13.A Fast−mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU;DAT 250 ns must then be met. mode I2C−bus specification) before the SCLK line is released. 14.Cb = total capacitance of one bus line in pF.

The DC electrical characteristics of the XGS 12000/8000 sensor are listed in Tables 17 through 28. Table 17. DC ELECTRICAL CHARACTERISTICS tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 18. ABSOLUTE MAXIMUM RATINGS should not be assumed, damage may occur and reliability may be affected. 16.Exposure to absolute maximum rating conditions for extended periods may affect reliability. 17.Operating ratings are conditions in which operation of the device is intended to be functional. to (AN52561/D). Long term exposure toward the maximum storage temperature will accelerate color filter degradation. absorb moisture if the sensor is placed in a high % RH environment.

Table 19. OPERATING CURRENT CONSUMPTION (XGS 12000−X1) Table 20. OPERATING CURRENT CONSUMPTION (XGS 12000−X3) Table 21. OPERATING CURRENT CONSUMPTION (XGS 9400−X1)

Table 22. OPERATING CURRENT CONSUMPTION (XGS 9400−X2) Table 23. OPERATING CURRENT CONSUMPTION (XGS 8000−X1) Table 24. OPERATING CURRENT CONSUMPTION (XGS 8000−X2)

Table 25. STANDBY CURRENT CONSUMPTION

VDD_TX in the HiSPi Physical Layer Specification. referenced in the specification. any even clock lane and any even data lane. clock lane and any odd data lane, can be maximum 4 pixels. the Packetized SP protocol only. Figure 55. HiSPi DC Parameters Table 26. HISPI DC SPECIFICATIONS (VDD_SLVS = 0.4 V) Table 27. DIFFERENTIAL DATA OUTPUT DC SPECIFICATIONS (VDD_SLVS = 1.2 V)

Figure 56. Differential Data Output AC Parameters Table 28. DIFFERENTIAL DATA OUTPUT AC SPECIFICATIONS (VDD_SLVS = 0.4 V, 1.2 V) 20.One UI is defined as the normalized mean time between one edge and the following edge of the clock.

configuration and default operation mode. monochrome and color devices are shown in Figure 57. Table 29. ELECTRO−OPTICAL SPECIFICATIONS 21.Measured on devices with cover glass (typical transmittance cover glass = 91%). Figure 57. Quantum Efficiency

Figure 58. Cover Glass Transmission Curve Table 30. COVER GLASS SPECIFICATIONS

Figure 59. XGS 12000 7.3/C0053CRA part Chief Ray Angle vs. Image Height Plot Table 31. XGS 12000 ARRAY DIMENSIONS

Figure 60. XGS 12000 Shipping Tray − Top View

Figure 61. XGS12M Protective Film Variations Thunderbolt is a trademark of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

CLGA163 20.88x19.9, 1P CASE 621AB ISSUE A DATE 11 SEP 2018 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON30089GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2CLGA163 20.88x19.9, 1P © Semiconductor Components Industries, LLC, 2018 www.onsemi.com

www.onsemi.com CLGA163 20.88x19.9, 1P CASE 621AB ISSUE A DATE 11 SEP 2018 XXXX = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week NN = Serial Number *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “/C0071”, may or may not be present. Some products may not follow the Generic Marking. GENERIC MARKING DIAGRAM* ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 98AON30089GDOCUMENT NUMBER: DESCRIPTION: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2CLGA163 20.88x19.9, 1P © Semiconductor Components Industries, LLC, 2018 www.onsemi.com

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