AGB1N0CS-GEVK ONSEMI | Alldatasheet
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that controls data from the on-board DDR3 SDRAM. Figure 5. FPGA Block Diagram the MIPI Alliance Specification for D−PHY v.1.00.00. the HiSPi protocol specification v.1.50.00. receiver conforms to the SMIA CCP2 1.0 specification. registers inside the HDMI transmitter block.
supports bus frequencies of 100 kHz, 400 kHz, and 1 MHz. 2C interface from the controller. configurable up to 0xAX using software. Streaming−SP, and Packetized SP. low-power state according to their nominal 0 V levels. be output. Only linear mode is supported on this interface. Standard mode, and 400 kHz for High-speed mode. Table 1. 52-PIN CONNECTOR TO HEADBOARD FUNCTION DESCRIPTION (P5)
1 MH_DATA1_P MIPI/HiSPi Data1+ Out MIPI/HiSPi Data1+ Signal
2 MH_DATA2_P MIPI/HiSPi Data2+ Out MIPI/HiSPi Data2+ Signal
3 MH_DATA1_N MIPI/HiSPi Data1− Out MIPI/HiSPi Data1− Signal
4 MH_DATA2_N MIPI/HiSPi Data2− Out MIPI/HiSPi Data2− Signal
6 MH_DATA3_P MIPI/HiSPi Data3+ Out MIPI/HiSPi Data3+ Signal
8 MH_DATA3_N MIPI/HiSPi Data3− Out MIPI/HiSPi Data3− Signal
9 S_DATA1 Parallel Data1 I/O Parallel Interface Data Bit
10 S_DATA0 Parallel Data0 I/O Parallel Interface Data Bit
11 S_DATA3 Parallel Data3 I/O Parallel Interface Data Bit
12 S_DATA2 Parallel Data2 I/O Parallel Interface Data Bit
13 S_DATA5 Parallel Data5 I/O Parallel Interface Data Bit
14 S_DATA4 Parallel Data4 I/O Parallel Interface Data Bit
15 VDDIO_SENSE Reference Input for I/O Voltage PWR Lets Demo3 Set Voltage Level
16 S_DATA6 Parallel Data6 I/O Parallel Interface Data Bit
17 S_DATA7 Parallel Data7 I/O Parallel Interface Data Bit
18 S_DATA8 Parallel Data8 I/O Parallel Interface Data Bit
19 S_DATA9 Parallel Data9 I/O Parallel Interface Data Bit
20 S_DATA10 Parallel Data10 I/O Parallel Interface Data Bit
21 S_DATA11 Parallel Data11 I/O Parallel Interface Data Bit
Table 1. 52-PIN CONNECTOR TO HEADBOARD FUNCTION DESCRIPTION (P5) (continued)
22 S_DATA12 Parallel Data12 I/O Parallel Interface Data Bit
23 S_DATA13 Parallel Data13 I/O Parallel Interface Data Bit
24 S_DATA14 Parallel Data14 I/O Parallel Interface Data Bit
25 S_DATA15 Parallel Data15 I/O Parallel Interface Data Bit
29 S_LINE_VALID Serial Line Valid Signal Out Checks if Data has Valid Line
31 HEAD_RESET_L Reset Signal to Headboard Out Resets the Headboard Sensor
34 HEAD_SSN Headboard Slave Signal In SPI Slave Signal to Headboard
35 S_FRAME_VALID Parallel Frame Valid Signal Out Checks if Data has Valid Frame
36 S_PIXCLK Pixel Clock Out Parallel Data Pixel Clock
49 MH_DATA0_P MIPI/HiSPi Data0+ Out MIPI/HiSPi Data0+ Signal
50 MH_CLK_N MIPI/HiSPi Clock− Out MIPI/HiSPi Clock− Signal
51 MH_DATA0_N MIPI/HiSPi Data0− Out MIPI/HiSPi Data0− Signal
52 MH_CLK_P MIPI/HiSPi Clock+ Out MIPI/HiSPi Clock+ Signal
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