AFEDRI8201 BURR-BROWN | Alldatasheet
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Technical content
FEATURES
/C0068Interfaces To Texas Instruments DRIx50 HD Radio Baseband Processors /C006812-Bit, 80MSPS ADC Reduces Noise and Improves Sensitivity /C0068Typical SNR of 102dB in 3kHz Bandwidth /C0068Programmable Input Range For Optimum Tuner Dynamic Range /C0068Integrated Digital Downconverter (DDC) − Quadrature Mixer, NCO, CIC Decimation Filter, And FIR Filters /C0068Mixer: 32-Bit Frequency and Phase /C0068Decimation Ratio: 32 to 4096 /C0068User-Programmable FIR Filters with 16-Bit Coefficients /C006812-Bit Auxiliary DAC /C0068Code Composer Module for Easy Software Generation /C0068SPI Control Interface
APPLICATIONS
/C0068AM/FM and HD Radio Receivers /C0068IF Receive Channels /C0068Software Radios /C0068Narrowband Receivers
DESCRIPTION
The AFEDRI8201 implements the receive channel analog functions required for intermediate-frequency (IF) sampled AM/FM and HD digital radio receivers. It is designed to be used with TI’s DRIx50 digital baseband processor. The AFEDRI8201 is programmed by the DRIx50 for use in AM/FM and HD radio. The AFEDRI8201 oversamples the radio tuner IF output at speeds of up to 80MHz to reduce noise and improve dynamic range. The radio tuner output IF is typically 10.7MHz for AM or FM as well as 450kHz or 455kHz for AM, as desired. The AFEDRI8201 then mixes, filters, and decimates the signal to provide baseband I and Q output signals to the digital baseband processor. The AFEDRI8201 also includes a general-purpose 12-bit control digital-to-analog converter (DAC) to provide a gain control signal or other analog feedback to the tuner. The DRIx50 digital baseband device writes control register data as well as decimation filter coefficients to the AFEDRI8201 through the industry-standard SPI control interface. The baseband output signals are transported to the DRIx50 through a general-purpose, high-speed serial interface (TI’s Buffered Serial Ports, McBSP). This unit uses 3.3V analog and 1.8V digital power supplies. Typical power dissipation is 490mW. The digital I/O lines can be powered by a 3.3V supply. 12−Bit Pipeline ADC Auxiliary DAC Voltage Reference AUX IFM IFP Quadrature Mixer NCO CIC Filter FIR Filter 1 FIR Filter 2A Data Interface DOUT0 DOUT1 DFSO DCLK DIN DFSI FIR Filter 2B N 2 2 REFM VCM REFP VGB SPI Control Interface SCK MOSI MISO CS Timing Generator PWD SYNC RESET Clock Interface MCLK MCLKB /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 AFEDRI8201 SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 IF ADC Front End for AM/FM and HD Radios www.ti.com Copyright 2003−2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners.
/C0065/C0070/C0069/C0068/C0082/C0073/C0056/C0050/C0048/C0049 SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 www.ti.com ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY AFEDRI8201 TQFP-48 PFB −40°C to +85°C DRI8201 AFEDRI8201PFBT Tape and Reel, 250 AFEDRI8201 TQFP-48 PFB −40°C to +85°C DRI8201 AFEDRI8201PFBR Tape and Reel, 2000 (1)For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) AFEDRI8201 UNIT AVDD −0.5 to 4.0 V Supply Voltage Range DVDD −0.5 to 2.3 VSupply Voltage Range IOVDD −0.5 to 3.6 V Voltage between AGND and DGND −0.3 to 0.5 V Voltage between AVDD and DVDD −3.3 to 3.3 V Digital inputs(2) −0.3 to DVDD + 0.3 V Digital data output −0.3 to DVDD + 0.3 V Operating free-air temperature range, TA −40 to +85 °C Storage temperature range −55 to +125 °C (1)Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2)Measured with respect to DGND. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT Operating free-air temperature range, TA −40 +85 °C Analog supply voltage range, AVDD 3.15 3.3 3.45 V Supplies and Digital supply voltage range, DVDD 1.71 1.8 1.89 VSupplies and References Output driver supply voltage range, IOVDD 3.15 3.3 3.45 VReferences Input common-mode voltage VCM V Differential input voltage 2 VPP Sample rate, fS 5 80 MHz Differential input mode voltage input swing 0.4 3.3 V Clock Inputs: Single-ended mode high-level input voltage, VIHC 2 VClock Inputs: MCLK and MCLKB Single-ended mode low-level input voltage, VILC 0.8 VMCLK and MCLKB Clock pulse width high, tW(H) 5.625 6.25 ns Clock pulse width low, tW(L) 5.625 6.25 ns
/C0065/C0070/C0069/C0068/C0082/C0073/C0056/C0050/C0048/C0049 SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 www.ti.com AUXILIARY DAC CHARACTERISTICS All specifications at +25°C, AVDD = +3.3V, and DVDD = +1.8V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT Resolution 12 bits Output voltage range Input code 0x000 0.0 V Output voltage range Input code 0xFFF 2.75 V Output impedance 1 kΩ Settling time to 0.1% FSR 10 µs Offset ±1 % of FSR DC Gain error ±5 % of FSR DC performance Differential nonlinearity, DNL Ensured monotonic ±0.5 LSBperformance Integral nonlinearity, INL After correcting for gain and offset errors ±2 LSB Power-supply rejection ratio, PSRRInput code 0x400, AVDD = 3.15VDC to 3.45VDC 60 dB RECEIVE CHANNEL CHARACTERISTICS All specifications at +25°C, fS = 80MSPS, AVDD = +3.3V, DVDD = +1.8V, IOVDD = +3.3V, Gain = 1, Decimation Ratio = 80, Internal Digital Filter Bandwidth = 284kHz, and Input Signal = 10.7MHz, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT DC Accuracy Input impedance 6.25 kΩ Differential nonlinearity, DNL −0.0244 ±0.0122 +0.0244 %FSR Integral nonlinearity, INL −0.0244 ±0.012 +0.0244 %FSR Offset error 3 mV Gain error 1 %FS Gain = 1 1.0 V Gain = 1.14 0.875 V Gain = 1.33 0.75 V Full-scale input level (peak differential)Gain = 1.6 0.625 VFull-scale input level (peak differential) Gain = 2.0 0.5 V Gain = 2.67 0.375 V Gain = 4.0 0.25 V Gain change settling time Number of samples to achieve rated accuracy 2 Samples Power-supply rejection ratio, PSRR AVDD = 3.15VDC to 3.45VDC 70 dB References Negative reference, VREFN 1.1 1.25 1.4 V Positive reference, VREFP 2.1 2.25 2.4 V Common-mode voltage, VCM 1.8 V AC Performance Spurious-free dynamic range, SFDR Input 455kHz, −1dBFS 76 dBc Spurious-free dynamic range, SFDR Input 10.7MHz, −1dBFS 76 86 dBc Input 455kHz, −1dBFS 75 dB Signal-to-noise ratio, SNR Input 10.7MHz, −1dBFS 70 74 dBSignal-to-noise ratio, SNR In 3kHz bandwidth, −1dBFS, 10.7MHz, 20kHz from fundamental 102 dB Aperture delay 2 ns Aperture uncertainty 0.2 ps Power Supply Analog supply voltage, AVDD 3.15 3.3 3.45 V Digital supply voltage, DVDD 1.71 1.8 1.89 V Output driver supply voltage, IOVDD 3.15 3.3 3.45 V Power dissipation Normal operation 490 570 mW Power dissipation Power-down 20 mW Digital I/O supply current 7 mA Digital supply current 72 mA Analog supply current 103 mA
/C0065/C0070/C0069/C0068/C0082/C0073/C0056/C0050/C0048/C0049 SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 www.ti.com PIN ASSIGNMENTS SYNC RESET DOUT1 DOUT0 DCLK DFSO DIN DFSI SCK MISO MOSI CS AVDD AGND AVDD AVDD AGND AGND DGND DVDD IOGND IOVDD IOGND PWD AVDD AUX AGND NC AGND MCLK MCLKB AVDD DGND DVDD IOGND IOVDD AVDD AGND IFP IFM AGND VCM AVDD VREFN VREFP AVDD AGND VBG 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 AFEDRI8201 PIN DESCRIPTIONS NAME PIN TYPE FUNCTION IFP 3 Input Positive IF input IFM 4 Input Negative IF input VCM 6 Output Common-mode voltage output VREFN 8 Output Negative reference voltage output VREFP 9 Output Positive reference Voltage output VBG 12 Output Bandgap voltage output AUX 14 Output Auxiliary DAC output MCLK 18 Input Master clock input MCLKB 19 Input Complementary master clock input CS 25 Input SPI chip select (active low) MOSI 26 Input SPI serial Input MISO 27 Output SPI serial output SCK 28 Input SPI serial clock DFSI 29 Input Data interface input frame sync DIN 30 Input Data interface input data DFSO 31 Output Data interface output frame sync DCLK 32 Output Data interface clock output DOUT0 33 Output Data interface filter 0 output data DOUT1 34 Output Data interface filter 1 output data RESET 35 Input Global reset (active low). Resets all registers to zero, except for FIR filters. SYNC 36 Input External sync PWD 37 Input Power-down: PWD = 1; normal operation: PWD = 0 AVDD 1, 7, 10, 13, 20, 45, 46, 48 Supply Analog supply (3.3V) AGND 2, 5, 11, 15, 17, 43, 44, 47 Ground Analog ground DVDD 22, 41 Supply Digital supply (1.5V to 1.8V) DGND 21, 42 Ground Digital ground IOVDD 24, 39 Supply Digital I/O supply (3.3V) IOGND 23, 38, 40 Ground Digital I/O ground NC 16 — Not connected
Figure 3. Control Interface Timing
/C0065/C0070/C0069/C0068/C0082/C0073/C0056/C0050/C0048/C0049 SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 www.ti.com DETAILED DESCRIPTION The AFEDRI8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC) with programmable input range, digital downconverter (DDC), and user programmable digital filters with 16-bit coefficients. It is designed to sample narrowband (up to 2.5MHz) IF signals and digitally mix, filter, and decimate the signals to baseband. The ADC integrates a programmable gain sample-and-hold amplifier that is variable over gains of 1x to 4x to change the full-scale input voltage range of the device from 1.0V peak to 0.25V peak. When the gain is changed, two sample periods may be needed for the output of the ADC to settle to the correct value. The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters (FIR1 and FIR2). The mixer frequency and initial phase are independently programmed by 32-bit control words. The quadrature mixer generates I and Q signals, each of which are decimated by the CIC filter. The CIC is a 5th-order Comb filter with a decimation factor that is programmable over a range of 8 to 1024. Each of the FIR filters adds an additional decimation factor of 2, for a total range of 32 to 4096. The I and Q signals generated by the quadrature mixer are then passed on to the first FIR filter (FIR1). This decimate-by-two FIR filter can implement even, odd, halfband, and arbitrary impulse responses. The length of the filter response is dependent on the decimation factor of the CIC filter and the FIR filter response type, up to a maximum of 62 taps. Coefficients for multiple filter responses may be stored in the coefficient memory (up to 64 unique coefficients may be stored); responses can be changed by changing a control register to point the filter to a different section of coefficient memory. Following FIR1 are two parallel decimate-by-two FIR filters (FIR2A and FIR2B). These filters are similar to FIR1, but have twice the data and coefficient memory and can therefore realize longer filter responses. The responses of the FIR2A and FIR2B can be different from each other (with some limitations). In addition, FIR2A and FIR2B can be optionally interleaved to form a single extra-long FIR filter that can realize up to 251 taps. Control register information, as well as decimation filter coefficients, are written to the AFEDRI8201 through the industry-standard SPI control interface. The baseband output signals are transported through a high-speed serial interface that is compatible with the TI C5x/C6x DSP buffered serial ports (McBSP). The AFEDRI8201 also contains a 12-bit auxiliary digital-to-analog converter (DAC) which can be used for a number of purposes, including tuner automatic gain control or frequency control. Input data for the DAC may be sent either from the DSP through the serial data port or from a microcontroller through the SPI control interface.
parameters. The memory banks store 16-bit FIR filter coefficient data. To read and write to control registers and memory banks, data is transferred by a 16-bit instruction followed by 16 bits of data. followed by multiple 16-bit data words. Table 1. Control Registers
0 Data interface parameters DIV, MODE
1 NCO frequency (bits 0−15)
2 NCO frequency (bits 16−31)
3 NCO Initial Phase (bits 0−15)
4 NCO Initial Phase (bits 16−31)
5 CIC Filter Decimation Rate: DEC_RATE
6 CIC Filter Parameters: SCALE, SHIFT
7 First FIR Filter Parameters: BASE_ADDR, NCOEFF, MODE
8 Second FIR A Filter Parameters: BASE_ADDR, NCOEFF, MODE
9 Second FIR B Filter Parameters: BASE_ADDR, NCOEFF, MODE
10 Setup for the Second FIR
11 Auxiliary DAC: DAC_DATA
12 ADC Parameters: GAIN, PWD
Table 2. Memory Banks
00 FIR Filter 1 Coefficients 64 Coefficients 62 Samples
01 FIR Filter 2A Coefficients 128 Coefficients 126 Samples
10 FIR Filter 2B Coefficients 128 Coefficients 126 Samples
(3) the address of the data target. The second 16 bits are the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle.
instructions: register write and memory write. The formats for these instructions are shown in Figure 5 and Figure 6. Figure 4. Single Data Word Control Interface Write Cycle for Registers or Memory Figure 5. Register Write Instruction Format
101 MEM_ADDRMEMDon’t Care
Figure 6. Memory Write Instruction Format address (MEM_ADDR) are required (see Table 2). word is written to the appropriate register or memory location in the AFE.
similar to the corresponding data write instructions and are shown in Figure 8 and Figure 9. Figure 7. Single Data Word Control Interface Read Cycle for Registers or Memory Figure 8. Register Read Instruction Format
011 MEM_ADDRMEMDon’t Care
Figure 9. Memory Read Instruction Format starting at the address contained in the instruction. The sequential RAM access terminates when the CS line goes high. address N. The memory block write cycle is similar, except of course data is clocked into MOSI. Figure 10. Block Memory Read Cycle Control Interface
- input frame sync DFSI; and
The decimation filter outputs from the DDC (either IA and QA, or IA, QA, IB, and QB) are multiplexed onto the data outputs.
0000 DIV MODEDon’t Care0
Figure 11. Data Interface Control Register where DIV ranges from 0 to 3. fast enough to clock out the I and Q data words generated by the on-chip DDC and filters. Figure 12. When MODE is 1, IA and QA outputs are multiplexed onto DOUT0 while IB and QB outputs are multiplexed onto Figure 12. Data Interface Timing for MODE = 0
Figure 13. Data Interface Timing for MODE = 1 out before the next I and Q data words must be clocked out. that DIV may be increased to 1, cutting the frequency of DCLKO in half). the DAC as the unsigned DAC input.
Figure 14. Mixer Control Registers low, the phase accumulator is incremented by the value FREQ once per MCLK cycle. Note that the mixer can be bypassed by setting FREQ and PHASE to 0 and using only the Q (real) output. the unsigned variable DEC_RATE, SCALE, and SHIFT which are mapped into control registers as illustrated in Figure 15. The valid range for DEC_RATE is from 8 to 1024.
0010 DEC_RATE1
0011 S C A L E
Figure 15. CIC Filter Control Registers 20, setting SHIFT to 22 and scale to 41 will result in a GAIN of 0.9775.
Figure 17. Application of Filter Coefficients in Different Filter Modes
Table 3. ODD Mode Calculation Example with Six Filter Coefficients
1 BASE_ADDR N and N+10
2 BASE_ADDR+1 N+1 and N+9
3 BASE_ADDR+2 N+2 and N+8
4 BASE_ADDR+3 N+3 and N+7
5 BASE_ADDR+4 N+4 and N+6
6 BASE_ADDR+5 N+5
Figure 17 clearly illustrates that the overall filter length is different in different filter modes even if NCOEFF is unchanged. For NCOEFF = 6, filter length ranges from 6 taps for ARBITRARY mode to 19 taps for HALFBAND mode. The dc gain of the FIR filter depends on the coefficient values and the filter mode. where hn is the nth of NCOEFF filter coefficients stored in memory.
The second FIR filter, shown in Figure 18, is similar to the first FIR filter with four notable exceptions.
- The depth of the coefficient and data memories are doubled to 128. This allows for filters up to 126 taps to be
coefficient memory. Note that BASE_ADDR and NCOEFF are each one bit wider in the control register.
- Because of the additional decimation by two from the first FIR filter, twice as many MCLK cycles are available
- In the first FIR filter, the total of all the filter tap weights must add up to 215 − 1 in order to achieve unity gain through
FIR2B. Note that shift values for FIR2A and FIR2B can be set separately.
- A second coefficient memory and computational unit is added to allow the simultaneous implementation of two
bank 1 (MEM = 1) and coefficients for filter B are stored in memory bank 2 (MEM = 2).
0100 NCOEFF_ABASE_ADDR_A MODE_A0
0100 NCOEFF_BBASE_ADDR_B MODE_B1
0101 SHIFT_BM2XDon’t Care SHIFT_A0
Figure 18. Second FIR Filter Control Register
- only odd symmetrical filters may be realized;
- the filter length M must be such that (M + 1)/4 is an integer; and
- only one filter can be realized (in M2X mode the A and B outputs are identical: IB = IA and QB = QA).
end up as the last coefficient loaded into FIR2B.
In normal operation the auxiliary DAC values are sent over the data interface through input pin DIN and framed by DFSI.
0101 DAC_DATADon’t Care1
Figure 19. Auxiliary DAC Control Register The gain of PGA and the power-down mode can be set in register 12. The gain setting of the PGA is shown in Table 4. Table 4. PGA Gain Setting PWD = 0 for normal operation.
0110 GAINDon’t Care Don’t
Figure 20. PGA and PWD Register
SBWS017F − SEPTEMBER 2003 − REVISED AUGUST 2005 www.ti.com DATE REV PAGE SECTION DESCRIPTION 6 Control Interface Timing Changed Maximum SCK Frequency from 10MHz to 1MHz. Changed “16 bit” to “16-bit” (added hyphen) in last sentence of 2nd paragraph. Control Interface Changed “16 bits is” to “16 bits are” in last paragraph. 8/25/05 F Control Interface Changed 1st sentence of 4th paragraph to include additional info on initializing the SPI interface correctly. 13 Quadrature Mixer/NCO Changed “mixer” to “the mixer” in 1st sentence of 1st paragraph. 16 Control Interface Changed “mode” to “modes” in 1st sentence of 2nd paragraph. NOTE : Page numbers for previous revisions may differ from page numbers in the current version.
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) AFEDRI8201PFBR ACTIVE TQFP PFB 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR AFEDRI8201PFBT ACTIVE TQFP PFB 48 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 23-Aug-2005 Addendum-Page 1
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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