AFE8221IRFPQ1

AFE8221-Q1 TI | Alldatasheet

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www.ti.com SBAS434 DECEMBER 2008 DUAL INTERMEDIATE FREQUENCY (IF) ANALOG FRONT-END FOR DIGITAL RADIO Flexible Data Interface Optimized for TMS Family of Digital Baseband Processors Qualified for Automotive I C Control Two Intermediate Frequency (IF) Interfaces Analog-to-Digital Converters (ADCs) 3.3-V/1.8-V Supply (Integrated Regulator Two 12-Bit Auxiliary Digital-to-Analog Available to Optionally Generate 1.8-V Supply) Converters (DACs) TQFP-144 (RFP) PowerPAD Package 8-Bit Auxiliary ADCs with Four-Channel Input Multiplexer (MUX) Integrated IF Digital Processing Core IF-Sampled AM/FM Radio Integrated Circuitry for Third-Overtone Master Hybrid Digital (HD) Digital Audio Broadcasting Clock Oscillator (DAB) Digital Radio Wakeup Circuit/Real-Time Clock With Separate Crystal Oscillator The AFE8221 implements the intermediate frequency (IF) sampling and processing functions of a digital radio receiver system. It is designed to be used with TI s digital radio baseband processors and AM/FM tuners. The AFE8221 can also be programmed by the baseband processor for use in conventional AM/FM and digital radio. This unit includes two IF inputs with associated filtering and digital processing circuitry. The receive circuit oversamples the radio tuner IF output to reduce noise and improve dynamic range. The IF analog-to-digital converter (ADC) oversamples the IF input at rates up to MHz. The AFE8221 then digitally mixes, filters, and decimates the signal to provide I and Q output signals to the baseband processor. A clock oscillator circuit is provided that can be used with an appropriate third-overtone crystal and external tank circuit to generate the sampling clock for the IF ADCs. The AFE8221 also includes a real-time clock and associated low-power oscillator circuit. Two auxiliary digital-to-analog converters (DACs) are included for system control functions. An 8-bit auxiliary ADC and input multiplexer (MUX) can be used for system diagnostic functions. Other (GPIO) lines, programmable interrupt generators, and an I C master for communication between the AFE and the tuner(s). The AFE8221 is available in a TQFP-144 (20 mm mm) package and uses a 3.3-V and a 1.8-V power supply. An onboard voltage regulator is included to optionally generate the 1.8-V digital supply for the AFE8221. ORDERING INFORMATION (1) T A PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING C to C HTQFP RFP Tray of AFE8221IRFPQ1 AFE8221Q (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PowerPAD is a trademark of Texas Instruments. SPI is a trademark of Motorola, Inc. I2C is a trademark of NXP Semiconductors. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1) RECOMMENDED OPERATING CONDITIONS AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. over operating free-air temperature range (unless otherwise noted) AVDD 0.5 V to 3.6 V Supply voltage range DVDD 0.5 V to 3.6 V IOVDD 0.5 V to 3.6 V AGND to DGND 0.3 V to 0.5 V Voltage between AVDD to DVDD 3.3 V to 3.3 V V IN Digital input voltages (2) 0.3 V to (DVDD 0.3 V OUT Digital data output voltage 0.3 V to (DVDD 0.3 T A Operating free-air temperature range C to C T stg Storage temperature range C to 125 C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Measured with respect to DGND. over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT AVDD Analog supply voltage 3.14 3.3 3.6 V DVDD Digital supply voltage 1.6 1.8 2.0 V IOVDD Output driver supply voltage 1.6 3.6 V Input common-mode voltage VCM V Differential input voltage V PP V IH High-level input voltage, digital inputs 0.7 IOVDD V V IL Low-level input voltage, digital inputs 0.25 IOVDD V T A Operating free-air temperature +85 C Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 T A AVDD IOVDD 3.3 DVDD 1.8 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Consumption Analog supply current 130 155 mA Digital supply current REG_ENB disabled mA REG_ENB disabled mA Digital I/O supply current REG_ENB enabled 105 125 mA REG_ENB disabled 660 mW Power dissipation REG_ENB enabled 725 mW Reduced-Power Modes Software power-down Control register address set to 0x0000 100 mW Hardware power-down PWD enabled µ W T A AVDD IOVDD 3.3 DVDD 1.8 f S MHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DC Accuracy Input impedance k Ω Offset error 3.0 mV Gain error 1.0 %FS Peak differential, gain 2.0 V PP Full-scale input level Peak differential, gain 1.0 V PP Power Supply PSRR Power-supply rejection ratio AVDD 3.15 VDC to 3.6 VDC dB References REFP Positive reference 1.9 2.0 2.1 V REFN Negative reference 0.9 1.0 1.1 V VCM Common-mode voltage 1.4 1.5 1.6 V AC Performance Input sample rate MHz Input 10.7 MHz, dBFS, in 3-kHz passband 105 Signal-to-noise ratio within a limited SNR dBc passband Input 10.7 MHz, dBFS, in 100-kHz passband 7-dB signals at 10.656 MHz and 10.729 MHz Third-order intermodulation dB distortion 10-dB signals at 10.656 MHz and 10.729 MHz SFDR Spurious-free dynamic range 1-dB input at 10.7 MHz, 100-kHz passband dBc Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com T A AVDD IOVDD 3.3 DVDD 1.8 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution Resolution Bits Output Voltage Range Output voltage range Input code 0x000 V Input code 0x3FF 2.7 V Settling Time Settling time 0.1% of FSR µ s DC Performance Offset of FSR Gain error of FSR DNL Monotonic 0.5 LSB INL Offset and gain errors removed 3.0 LSB PSRR Input code 0x200, AVDD 3.15 VDC to 3.6 VDC dB T A AVDD IOVDD 3.3 DVDD 1.8 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution Resolution Bits Input Voltage Range Input voltage range Input code 0x00 V Input code 0xFF 3.0 V Input Impedance Input impedance k Ω Conversion Time MCLK Conversion Time 8704 cycles DC Performance Offset 1.0 of FSR Gain error 1.5 of FSR DNL Monotonic 1.0 1.5 LSB INL Offset and gain errors removed 1.5 0.5 1.5 LSB PSRR Midscale input, AVDD 3.15 VDC to 3.6 VDC dB Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 T A IOVDD 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I IH High-level input current V IH 1.6 V to 3.6 V µ A I IL Low-level input current V IL V to 0.4 V µ A V OH High-level output voltage I OH µ A 0.8 IOVDD V V OL Low-level output voltage I OL µ A 0.2 IOVDD V T A DVDD 1.8 IOVDD 3.3 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f XTAL Crystal frequency See the Master Clock Oscillator section MHz Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

C ton□rol DAC Quadrature Mixer IF Dat a Interface Timing Ge eran tor V tol□age Re□eref nce IF_VCM IF REF_ P IF REF_ M IF_INP1 IF_INM1 CDAC0 IF B_ IAS Master Oscilla rto CIC Fil rte N FIR□Filter□1 FIR□Filter□2A NCO PGA S/H PGA S/H 12-Bit Pipeline ADC 12-Bit Pipeline ADC IF_INP0 IF_INM0 Attenuator and Overflow Sensor Attenuator and Overflow Sensor Control Interface Control DACCDAC1 GPIO RT□Clock Oscillator Real-Time Clock Interrupt Generator FIR□Filter□2B MCLKIMCLKO REFCLK PWD RSTGRST Quadrature Mixer C□C□FiI lter N FIR□Filt r□1e FIR□Filter□2A NCO FIR i F lter□2B WAKEUPIRQ1IRQ0IRQ2RTCIRTCORTC_REFRTC_REFMISO/SDA MOSI/A0 SCK/SCLCS/A1CTRL_MODE Aux□ADC MUX AUX_ADC3 AUX_ADC2 AUX_ADC1 AUX_ADC0 GPIO0GPIO1GPIO2GPIO3GPIO4GPIO5GPIO6GPIO7GPIO8GPIO9GPIO10GPIO11 IF_D UO T0 IF_DFSO IF_DCLK IF_D UO T1 IF_DOUT2 IF_DOUT3 BB_QDAT0 BB_IDAT1 BB_QDAT1 BB_IDAT0 BB_BCK BB_WS Dual I C□Master SDA0SCL0 SCL1SDA1 AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

REG_ENB CTRL_MODE SCK/SCL MISO/SDA MOSI/A0 CS/A1 IOVDD IOVSS IF_DOUT0 IF_DOUT1 IF_DOUT2 DVDD DVSS IF_DOUT3 IF_DCLK IF_DFSO IOVDD IOVSS DVDD DVSS NC NC NC NC NC NC NC NC NC NC AVDD AVDD AVDD AVDDNC NC NC SDA0 SCL0 VSSAVDDRTC_REFRTC_REFAVSSDVSSRTCI RTCO DVDD1 VSSAVDD AVDD AVDDAVDD AVDD NC SDA1SCL1VSSAVDD REFCLKREFCLK AVSSDVSS MCLKIMCLK O DVDD2 VSSAVDDAVSSDVDD NC NC NC AUX_ADC0 AUX_ADC1 AUX_ADC2 AUX_ADC3 AVDD1 CDAC0 AVSS CDAC1 AVDD1 AVDD1 AVSS AVSS AVSS IF_INP0 IF_INM0 IF_VCM IF_REFP IF_REFM AVSS AVDD1 AVDD1 AVSS AVSS IF_BIAS AVSS IF_INM1 IF_INP1 AVSS AVSS AVSS AVDD1 NC NC 144 143 142 141 140 139 138 137 136 135 134 37 38 39 40 41 42 43 44 45 46 47 133 48 49 50 51 52 53 54 55 56 IOVDDDVSSIOVSSBB_WSBB_BCKBB_ID AT0 BB_QD AT0 BB_IDAT1BB_QDAT1 GRST WAKEUP IRQ0IRQ1IRQ2 PWDRST 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 132 131 130 129 128 127 126 125 AVSSDVDD IOVDD DVSS IOVSS DVSS DVSSGPIO8 GPIO9 GPIO10 GPIO11 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 AFE8221 NC – No connection AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 TQFP-144 Top View Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com TERMINAL FUNCTIONS TERMINAL FUNCTION NO. NC Open No connect NC Open No connect NC Open No connect AUX_ADC0 Analog input Auxiliary ADC channel AUX_ADC1 Analog input Auxiliary ADC channel AUX_ADC2 Analog input Auxiliary ADC channel AUX_ADC3 Analog input Auxiliary ADC channel AVDD1 Supply 3.3-V analog supply (internally switched) CDAC0 Output Control DAC output AVSS Ground Analog ground CDAC1 Output Control DAC output AVDD1 Supply 3.3-V analog supply (internally switched) AVDD1 Supply 3.3-V analog supply (internally switched) AVSS Ground Analog ground AVSS Ground Analog ground AVSS Ground Analog ground IF_INP0 Input IF ADC channel positive input IF_INM0 Input IF ADC channel negative input IF_VCM Output IF ADC common-mode voltage IF_REFP Output IF ADC positive reference IF_REFM Output IF ADC negative reference AVSS Ground Analog ground AVDD1 Supply 3.3-V analog supply (internally switched) AVDD1 Supply 3.3-V analog supply (internally switched) AVSS Ground Analog ground AVSS Ground Analog ground IF_BIAS Input IF ADC bias input AVSS Ground Analog ground IF_INM1 Input IF ADC channel negative input IF_INP1 Input IF ADC channel positive input AVSS Ground Analog ground AVSS Ground Analog ground AVSS Ground Analog ground AVDD1 Supply 3.3-V analog supply (internally switched) NC Open No connect NC Open No connect AVDD Supply 3.3-V analog supply AVDD Supply 3.3-V analog supply AVDD Supply 3.3-V analog supply AVDD Supply 3.3-V analog supply NC Open No connect SDA1 Bidirectional Channel tuner I C data SCL1 Output Channel tuner I C clock AVSS Ground Analog ground AVDD Supply 3.3-V analog supply REFCLK Output Inverted reference clock output Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL FUNCTION NO. REFCLK Output Reference clock output AVSS Ground Analog ground DVSS Ground Digital ground (for MCLK oscillator) MCLKI Input MCLK oscillator input MCLKO Output MCLK oscillator output DVDD2 Supply 1.8-V digital supply (for MCLK oscillator) AVSS Ground Analog ground AVDD Supply 3.3-V analog supply AVSS Ground Analog ground DVDD Supply 1.8-V digital supply IOVDD Supply 3.3-V digital I/O supply DVSS Ground Digital ground IOVSS Ground Digital I/O ground BB_WS Output Secondary baseband word select BB_BCK Output Secondary baseband word bit clock BB_IDAT0 Output Secondary baseband channel output (I) BB_QDAT0 Output Secondary baseband channel output (Q) BB_IDAT1 Output Secondary baseband channel output (I) BB_QDAT1 Output Secondary baseband channel output (Q) GRST Input Global reset (active low) WAKEUP Output WAKEUP interrupt output IRQ0 Output Interrupt output IRQ1 Output Interrupt output IRQ2 Output Interrupt output PWD Input Power-down pin (active high) RST Input Reset pin (active low) NC Open No connect NC Open No connect NC Open No connect NC Open No connect NC Open No connect NC Open No connect NC Open No connect NC Open No connect NC Open No connect NC Open No connect DVSS Ground Digital ground DVDD Supply 1.8-V digital supply IOVSS Ground Digital I/O ground IOVDD Supply 3.3-V digital I/O supply IF_DFSO Output IF interface frame sync IF_DCLK Output IF interface bit clock IF_DOUT3 Output IF interface data out DVSS Ground Digital ground DVDD Supply 1.8-V digital supply IF_DOUT2 Output IF interface data out Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL FUNCTION NO. IF_DOUT1 Output IF interface data out IF_DOUT0 Output IF interface data out IOVSS Ground Digital I/O ground IOVDD Supply 3.3-V digital I/O supply CS /A1 Input SPI chip select (active low) I C address bit MOSI/A0 Input SPI data in I C address bit MISO/SDA Bidirectional SPI data out I C SDA SCK/SCL 100 Input SPI clock I C SCL CTRL_MODE 101 Input Control interface mode select (SPI I C REG_ENB 102 Input Enable onboard DVDD regulator (active low) DVSS 103 Ground Digital ground DVDD 104 Supply 1.8-V digital supply GPIO7 105 Bidirectional GPIO GPIO6 106 Bidirectional GPIO GPIO5 107 Bidirectional GPIO NC 108 Open No connect GPIO4 109 Bidirectional GPIO GPIO3 110 Bidirectional GPIO GPIO2 111 Bidirectional GPIO GPIO1 112 Bidirectional GPIO GPIO0 113 Bidirectional GPIO GPIO11 114 Bidirectional GPIO GPIO10 115 Bidirectional GPIO GPIO9 116 Bidirectional GPIO GPIO8 117 Bidirectional GPIO DVSS 118 Ground/input Digital ground/Test1 DVSS 119 Ground/input Digital ground/Test0 IOVSS 120 Ground Digital I/O ground DVSS 121 Ground Digital ground IOVDD 122 Supply 3.3-V digital I/O supply DVDD 123 Supply 1.8-V digital supply AVSS 124 Ground Analog ground AVDD 125 Supply 3.3-V analog supply AVSS 126 Ground Analog ground DVDD1 127 Supply 1.8-V digital supply (for RTC oscillator) RTCO 128 Output RTC oscillator output RTCI 129 Input RTC oscillator input DVSS 130 Ground Digital ground (for RTC oscillator) AVSS 131 Ground Analog ground RTC_REF 132 Output RTC output RTC_REF 133 Output Inverted RTC output AVDD 134 Supply 3.3-V analog supply AVSS 135 Ground Analog ground SCL0 136 Output Channel tuner I C clock SDA0 137 Bidirectional Channel tuner I C data NC 138 Open No connect Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL FUNCTION NO. NC 139 Open No connect NC 140 Open No connect AVDD 141 Supply 3.3-V analog supply AVDD 142 Supply 3.3-V analog supply AVDD 143 Supply 3.3-V analog supply AVDD 144 Supply 3.3-V analog supply AVSS Analog ground Center pad Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

DOUTx IA[15] IA[14] IA[13] IA[12] tD1 tD2 Primary Data Interface Timing BCLK WS DOUTx IA[15] IA[14] IA[13] IA[12] tD1 tD2 AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t DCLK to DFSO delay 2.9 3.7 ns t DCLK to DOUTx delay 3.1 3.8 ns Figure Output Data Interface Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t BCLK to WS delay 2.9 3.7 ns t BCLK to DOUTx delay 3.1 3.8 ns Figure Primary Data Interface Timing Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

I C Bus Interface Timing tHIGH tLOW tSU_DA T tHD_DA T tSTOP tST ART SCK SDA VIL VIH tBUF AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT f SCK Maximum SCK frequency MHz t L CS lead time Trailing CS to leading SCK 5.0 ns t T CS trail time Trailing SCK to leading CS 5.0 ns t I CS idle time Leading CS to trailing CS 5.0 ns t SU3 MOSI to SCK setup time 5.0 ns t MOSI to SCK hold time 1.0 ns t SCK to MISO delay 1.0 10.4 ns Figure SPI Control Interface Timing PARAMETER MIN TYP MAX UNIT f SCK SCK clock frequency 400 kHz V IL Input voltage, low 0.3 V DD V V IH Input voltage, high 0.7 V DD V t START Setup time for START or repeated START condition 0.6 µ s t STOP Setup time for STOP condition 0.6 µ s t LOW LOW period of SCK clock 1.3 µ s t HIGH HIGH period of SCK clock 0.6 µ s 100 (1) t HD_DAT Data hold time from SCK falling ns 250 100 (1) t SU_DAT Data setup time to SCK rising ns 250 t BUF Bus free time between a STOP and START condition 4.7 µ s (1) Valid when MCLK MHz; otherwise, is 250 ns. Figure I C Bus Interface Timing Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

1.8-V Core Supply Internal 1.8-V Regulator AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com The AFE8221 has two active-low reset pins, GRST and RST When GRST is brought low, all registers on the chip are brought to default values (0, unless otherwise specified). When RST is brought low, all registers are brought to default values except for: Real-time clock registers (counters and alarms) Registers to configure the WAKEUP interrupt Registers controlling the GPIO pins These registers are left in the previously programmed states. A clean 3.3-V analog supply should be connected to all AVDD pins (37 40, 45, 54, 125, 134, and 141 144). Limited decoupling is required on the AVDD pins; a 0.1- µ F capacitor near pins and and another capacitor near pins 125 and 134 should suffice. The AFE8221 contains an internal analog switch that is used to disconnect power from the major analog blocks when the PWD pin is high. When the PWD pin is low, the AVDD1 pins (8, 12, 13, 23, 24, and 34) are internally connected to the AVDD pins (37 and 141 144). Since the AVDD1 pins are actually the active supply pins for the IF ADC and other analog components, the AVDD1 pins should be heavily bypassed with a minimum of parallel 0.1- µ F and 0.01- µ F ceramic capacitors at each pin (or pin pair). The digital supply connections depend on whether the onboard regulators are used to generate the 1.8-V digital core voltage REG_ENB low); or if the digital core voltage comes from a system-level supply REG_ENB high). In either case, all IOVDD pins should be connected to the 3.3-V I/O supply and appropriately bypassed. If the internal regulators are used, this supply also sources the current drawn by the digital core. If an external 1.8-V supply is used, all DVDD pins should be connected to the 1.8-V supply and appropriately bypassed with 0.1- µ F and 0.01- µ F capacitors. DVDD1 and DVDD2 pins may also be connected directly to the 1.8-V supply or may be optionally connected through a small Ω to Ω series resistor to reduce supply noise coupling into the MCLK oscillator (powered through DVDD1) or the RTC oscillator (powered through DVDD2). When using an external supply, the PWD pin disables the MCLK oscillator when high, shutting off the clock to most of the digital core. As long as the external 1.8-V supply is maintained, all register settings in the digital core are maintained when PWD is high. If the internal 1.8-V regulator is used, then 0.1- µ F and 0.01- µ F decoupling capacitors should still be put at the DVDD, DVDD1, and DVDD2 pins. DVDD2 should still be connected to the DVDD pins either directly or through a small series resistor. DVDD1 must be isolated from DVDD and DVDD2. While using the internal regulators, the MCLK oscillator and the internal regulators are disabled when the PWD pin is high. This condition causes most of the register settings to be lost, except for the registers associated with the real-time clock, GPIO, and WAKEUP interrupt. For this reason, the RST pin should be brought low prior to bringing the PWD pin low (to come out of power-down). The RST pin should be held low for at least ms after PWD goes low to allow the internal regulators to stabilize. Note that the internal regulators are linear regulators, and therefore are relatively inefficient. Power dissipation as a result of the digital core almost doubles when the internal regulators are used (same core current, but drawn from a 3.3-V supply instead of a 1.8-V supply). Whenever possible, the use of a more efficient external switching regulator is encouraged in order to minimize overall system power as well as to reduce the thermal stress on the AFE8221. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

1 0 0 REG_ADDR 07815 14 13 12 11 10 9 6 5 4 3 2 1 1 0 1 MEM MEM_ADDR 07815 14 13 12 11 10 9 6 5 4 3 2 1 AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 Configuration and control data are written to the AFE8221 via the control interface. The control interface supports two protocols, SPI and I If the CTRL_MODE pin is tied low, then an SPI interface is implemented. If CTRL_MODE is tied high, then an I C protocol-compatible interface is implemented. The SPI interface consists of four signals: a serial clock (SCK), an active-low chip select CS a serial data input (MOSI master out, slave in), and a serial data output (MISO master in, slave out). Data are transferred in groups of bits. The first bits are the instruction, which indicates: If data are to be written or to be read; If the data target is a register or RAM; and The address of the data target. The second bits are the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle. Figure shows an SPI write cycle. The cycle is initiated by the high-to-low transition of the CS line. SCK pulses clock the instruction and the data into the MOSI line. Data are clocked in MSB first. The first bits are the instruction. There are two possible write cycle instructions: register write and memory write. The formats for these instructions are shown in Figure and Figure respectively. The only information required for a register write is the seven-bit register address (REG_ADDR). For a memory write, both the five-bit memory select (MEM) plus the six-bit memory address (MEM_ADDR) are required. Following the 16-bit instruction, the 16-bit data word is clocked in, again MSB first. At the end of the write cycle, this data word is written to the appropriate register or memory location in the AFE8221. NOTE: To terminate a Write/Read cycle, CS must be brought high. Figure SPI Control Interface Write Cycle Figure Register Write Instruction Format Figure Memory Write Instruction Format Figure shows the SPI interface read cycle. It is similar to the write cycle, except that instead of the data word being clocked into MOSI during the second half of the cycle, the data word is clocked out of MISO. Note that only register reads are permitted; RAM reads cannot be read back. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

I C Slave Interface CS SCK MOSI MISO I STRN UCTION DA T A CS SCK MOSI MISO INSTRUCTION DA T A[N] DA T A[N+1] DA T A[N+2] AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com For reading and writing, data block transfers are supported. For a block transfer, multiple data words are transmitted following the memory read or write instruction. The data words are read from or written sequentially starting at the address contained in the instruction. The sequential access terminates when the CS line goes high. Figure shows a register block read cycle. In the illustration, three succeeding register locations are read starting at address The block write cycle is similar except, of course, data are clocked into MOSI. In all cases, the control interface is reset when CS goes high. If the final SCK is not received before CS goes high, then the cycle ends prematurely. For a read cycle, data transfer terminates; for a write cycle, no data are written to either a register or to memory. The AFE8221 control interface can be configured to provide I C slave operation. It has a 10-bit slave address of 00010010AB and complies with the Philips I C specification Note that address bits A and B are determined by the state of the I C address pins and A0. The mapping of SPI pins to I C pins is shown in Table Table SPI/I C Pin Mapping CTRL_MODE (SPI) CTRL_MODE Chip select CS I C address bit (A1) Master out slave in (MOSI) I C address bit (A0) Master in slave out (MISO) Serial data line (SDA) SPI clock (SCK) Serial clock line (SCL) The AFE8221 I C interface supports both fast mode (400K bits/sec) and standard mode (100K bits/sec) operation. However, if the master crystal frequency is less than MHz, then only standard mode is supported. Figure SPI Control Interface Read Cycle Figure SPI Control Interface Block Read Cycle As a reference, a typical data transfer on the I C bus is described in Figure Each data byte is eight bits long and must be followed by an Acknowledge bit. Start and stop conditions are defined as a transition of the SDA signal with SCL high. A pulse of the SCL clock signal indicates the transfer of data or an Acknowledge bit on the SDA pin. The transmitting device drives SDA data during clock periods The receiving device acknowledges by driving SDA low during clock Master devices always generate the SCL clock and initiate transactions. Refer to the Philips I C Bus Specification for further details. The AFE8221 has 16-bit internal registers and operates on 16-bit instructions. Because the I C interface is inherently an 8-bit interface, special formats are required to send instructions and data between an I C Master and the AFE8221. The I C Write Operation and I C Read Operation sections describe these formats in detail. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

S ST ART CONDITION P STOP CONDITION SDA SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 R/W 0 1 0 REG_ADDR 07815 14 13 12 11 10 9 6 5 4 3 2 1 AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 I C Write Operation Write operations require a start condition followed by two bytes describing both a 10-bit address format and the AFE8221 10-bit slave address. The next two bytes must contain the 16-bit instruction word format described previously in Figure or Figure depending on the internal resource being addressed. Finally, a pair of bytes containing the 16-bit write data must be provided. If additional 16-bit writes are required, further pairs of bytes may be used as part of a block transfer. After the final pair of write data bytes, an I C stop condition must be provided to terminate the transaction. Figure illustrates a block write transfer of N 16-bit data words. Gray areas denote slave-driven SDA cycles; white areas are master-driven. I C Read Operation Read operations require a start condition followed by two bytes describing both a 10-bit address format and the AFE8221 10-bit slave address. The next two bytes must contain the 16-bit instruction word format, as illustrated in Figure A repeated start followed by the first byte of the slave address is then required to create a combined transaction. Note that the W bit is set to (read), indicating that subsequent bytes are to be read from the slave. The AFE8221 presents addressed 16-bit data words in 8-bit pairs until a NACK (N) is provided by the master. After the final pair of read data bytes, an I C stop condition must be provided to terminate the transaction. Figure illustrates a block read transfer of N 16-bit data words. Gray areas denote slave-driven SDA cycles; white areas are master-driven. Figure 10. Example Data Transfer on the I C Bus Figure 11. Register Read Instruction Format Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

S Slave□Address□1st□7□Bits R/W A Slave□Address□2nd□Byte A 1 1 1 1 0 I C□Reserved□Combination Indicating□10-B t□Ai ddressing□is in Use 00 0 0 1 0 0 1 0 A B Write Slave ACK Slave ACK Slave ACK Slave ACK Slave ACK Slave ACK Slave ACK Slave ACK Slave ACK Slave ACK 10-Bit Slave□Address Bits□15/c45 8□of□Instruction A Bits□7/c45 0 o□□Instructiof n A Bits□15/c45 8□of□First□16-Bit Data□Word A Bits□7 0/c45 of□First□16-Bit Data□Word A Bits□15/c45 8 f□Secondo 16-B Data□Wordit A Bits□7 0/c45 of□Second□16-Bit□Data□Word A Bits□15/c45 8□of□Nth□16-Bit Data□Word A Bits□7 0/c45 f□Nth□16-Bito Data□Word A /c188 P Start Stop ‘0’ Indicates□Following□Bytes a e r Written□to□Slave AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com Figure 12. Example I C Write Operation Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

S Slave Address 1st 7 Bits R/W A Slave Address t2nd□By e A 1 1 1 1 0 I C□Reserved□Combination Indicating□10-Bit□Addressing□is in Use 00 0 0 1 0 0 1 0 A B Write 10-Bit Slave□Address Slave ACK Slave ACK Slave ACK Slave ACK Slave ACK Bits□15/c45 8□of□Instruction A Bits□7 0/c45 o□□Instructf ion A Bits□15/c45 8□of□Firs□□16-Bt it Data□W rd o A Bits□7 0/c45 f□First□16-Bito Data□Word Bits□15/c45 8□of□Second□16-Bit□Data□Word Bits□7 0/c45 of□Secon 6d 1 -Bit□Data□W rdo Bits□15/c45 8□of□Nth□16-Bit Data□Word Bits□7 0/c45 of□Nth□16-Bit Data□Word P Start Stop Sr Repeated Start Slave□Addres 1st Bitss 7 R/W A 1 1 1 1 0 I C□Reserved□Combination Indicating□10-B t□Ai ddressi g□isn in Use 10 0 Read Bits□9 and□8□of□the 10-Bit Slave Address A A Master ACK Master ACK Master ACK Master ACK Master ACK Master NACK A A N /c188 ‘0’ Indicates□Following□Bytes are□Written□to□Slave ‘1’ Indi tes□Followca ing□Bytes ar Re ea f d Sl vrom a e IF Analog-to-Digital Converters (IF_ADC0 and IF_ADC1) AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 Figure 13. Example I C Read Operation IF_ADC0 and IF_ADC1 are 12-bit pipeline ADCs that are used to sample the output of the tuner(s). Figure shows recommended connections for the IF ADCs. The IF ADCs have three power modes controlled by ifadc_en[0] and ifadc_en[1] Full-power mode occurs when both ifadc_en[0] and ifadc_en[1] are high. In this case, both ADCs are biased to the highest levels and are ready to operate. If only ifadc_en[0] or ifadc_en[1] is high, then the converters are operating in reduced-power mode, where the enabled ADC is fully biased and ready to operate while the second ADC is in a low (but not zero) bias state minimum bias current is necessary to maintain safe voltages within the ADC core). In low-power mode, both ifadc_en[0] and ifadc_en[1] are low. In this case, all IF ADC circuits are in the minimum bias mode. Note that to reach a true sleep mode, the analog supply to the IF ADC block must be turned off. When ifadc_gain0 is low, IF_ADC0 is in its normal gain operating state. If ifadc_gain0 is high, then the gain of IF_ADC0 is changed to 2x. In a similar fashion, ifadc_gain1 controls the gain of IF_ADC1. Table shows the ifadc_en and ifadc_gain control variable parameters. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

TUN RE _0 13/c87 13/c87 12pF IFP IFM VCM TU EN R_1 13/c87 13/c87 0.1/c109F 0.1/c109F 0.01 F/c109 0.01 F/c109

0.1 F/c109

1 F/c109 0.1 F/c10956k/c87 AFE8221 IF_INP0 IF_INM0 IF_INP1 IF_INM1 IF_VCM IF_REFP IF_REFM IF_BIAS 20 21 27 12pF

1 F/c109

www.ti.com Table IF_ADC Control Register Settings PARAMETER ADDRESS BITS ifadc_en[0] ifadc_en[1] ifadc_gain0 ifadc_gain1 Figure 14. IF ADC Connections The output of each IF ADC is monitored to ensure that the full-scale input range is not exceeded. If an ADC over-range condition occurs, an overflow signal is generated that may be used to generate an interrupt on the IRQ line, depending on the settings in the IRQ interrupt generator. In addition, programmable limits may be set for each IF ADC. If the absolute value of IF_ADC0 exceeds if_adc_limit0 or the absolute value of IF_ADC1 exceeds ifadc_limit1 then an interrupt may be generated on IRQ again depending on the settings in the IRQ interrupt generator. In the case of an IF ADC event, the IRQ status register can be read back to determine the type of event and on which ADC channel it occurred. The IRQ status register can be polled to determine if an IF ADC event has occurred in the case where IF ADC events are masked from generating an interrupt. The control variable ddc0_atten causes an attenuation of the IF_ADC0 output prior to the DDC. The attenuation ranges in 3-dB steps from dB (for ddc0_atten to dB (for ddc0_atten 6). ddc1_atten has the same effect on the output of IF_ADC1. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

(DDC0) AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 To better synchronize the IF ADC attenuator with the tuner automatic gain control (AGC), a delay may be programmed between when a new value of ddc_atten is written and when it takes effect. When a new value of ddc0_atten is written, a counter (driven by MCLK) is initialized to ddc0_delay When the counter reaches zero, the actual attenuation change occurs. Likewise, ddc1_delay affects ddc1_atten Note that if a new ddc0_atten is written before the delay counter has reached zero from the previous write, the previous write is discarded. Table shows the attenuator, delay, and limit control variables. Table IF ADC Control Register Settings PARAMETER ADDRESS BITS ddc0_atten 2:0 ddc1_atten 2:0 ddc0_delay 15:0 ddc1_delay 15:0 ifadc_limit0 11:0 ifadc_limit1 11:0 DDC0 operation is controlled by ddc_en[0] When ddc_en[0] is operation of DDC0 is enabled. If ddc_en[0] is operation of DDC0 is disabled. Table shows the DDC0 operation control settings. Table DDC Control Register Settings PARAMETER ADDRESS BITS ddc0_cic_dec_rate 8:0 ddc0_cic_scale 11:6 ddc0_cic_shift 5:0 ddc0_demod_freq[31:16] 15:0 ddc0_demod_freq[15:0] 15:0 ddc0_demod_phase[31:16] 15:0 ddc0_demod_phase[15:0] 15:0 ddc0_fir1_base_address 13:8 ddc0_fir1_mode 1:0 ddc0_fir1_ncoeffs 7:2 ddc0_fir1_nodec ddc0_fir2_nodec ddc0_fir2a_base_address 15:9 ddc0_fir2a_mode 1:0 ddc0_fir2a_ncoeffs 8:2 ddc0_fir2a_shift 3:0 ddc0_fir2b_base_address 15:9 ddc0_fir2b_mode 1:0 ddc0_fir2b_ncoeffs 8:2 ddc0_fir2b_shift 7:4 ddc0_interleave ddc_en[0] ddc_sync Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

I□=□ADC cos(2 ft□+/c180 /c112 /c102 ) (1) Q□=□ADC sin(2 ft□+/c180 /c112 /c102 ) (2) f□=□fMCLK ddc0_demod_freq (3) /c102 /c112=□2 ddc0_demod_phase (4) CIC Filter 5 ddc0_cic_scale/32 2ddc0_cic_shift (5) First FIR Filter AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com The NCO frequency and initial phase are set by the 32-bit unsigned variables ddc0_demod_freq and ddc0_demod_phase The I and Q outputs of the mixer can be calculated by Equation and Equation where ADC is the output of the IF analog-to-digital converter, f is the NCO phase offset (in radians) given by Equation and φ is the NCO phase offset (in radians) given by Equation The ddc_sync signal can be used to control the phase of the mixer. While the ddc_sync signal is high, the phase accumulator is held to a constant value ddc0_demod_phase essentially holding it to in Equation and Equation When the ddc_sync signal is brought low, the phase accumulator is incremented by the value ddc0_demod_freq once per MCLK cycle. The first stage of decimation filtering is provided by a fifth-order CIC filter. The operation of the CIC filter is controlled by the unsigned variables ddc0_cic_dec_rate ddc0_cic_scale and ddc0_cic_shift The valid range for ddc0_cic_dec_rate is from to 256. The inherent dc gain of the CIC filter is ddc0_cic_dec_rate. The control variables ddc0_cic_shift and ddc0_cic_scale are used to reduce this very high gain before the signal is output to the next stage of the decimation filter. The combined effect of ddc0_cic_dec_rate ddc0_cic_shift and ddc0_cic_scale produces an overall dc gain for the CIC filter of Equation In general, ddc0_cic_shift and ddc0_cic_scale should be chosen to make GAIN as close to as possible. For example, if ddc0_cic_dec_rate is 20, setting ddc0_cic_shift to and ddc0_cic_scale to results in a GAIN of 0.9775. The block following the CIC filter is a decimate-by-two finite impulse response (FIR) filter with programmable coefficients. ddc0_fir1_mode sets the type of filter response ODD (MODE 00: symmetric impulse response, odd number of taps), EVEN (MODE 01: symmetric impulse response, even number of taps), HALFBAND (MODE 10), and ARBITRARY (MODE 11: non-symmetric impulse response). The 16-bit wide filter coefficients are stored in memory bank Up to coefficients can be stored in this memory. Depending on the types of filters desired and the number of taps, coefficients for multiple filter responses may be stored in the memory bank. The filter response may be changed simply by updating the control register with new values for ddc0_fir1_mode ddc0_fir1_ncoeff and ddc0_fir1_base_addr ddc0_fir1_ncoeff defines the number of unique filter coefficients that make up the filter response. ddc0_fir1_base_addr defines the memory location where the first filter coefficient is stored. The actual filter length is a function of the ddc0_fir1_mode and ddc0_fir1_ncoeff as shown in Equation Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

Filter□Length□=□2 (ddc0_fir1_ncoeff 1)□+□1□for□ODD/c180 /c45 Filter□Length□=□2 ddc0_fir1_ncoeff□for□EVEN/c180 Filter□Length□=□4 (ddc0_fir1_ncoeff 1)□+□1□for□HALFBAND/c180 /c45 Filter□Length□=□ddc0_fir1_ncoeff□for□ARBITRARY (6) ddc0_fir1_ncoeff 2 ddc0_cic_dec_rate/c163 /c180 (7) GAIN□= h +NCOEFF /c229 NCOEFF 1/c45 n□=□1 2hn 2 1/c45 (8) GAIN□= /c229 NCOEFF n□=□1 2hn 2 1/c45 (9) GAIN□= /c229 NCOEFF n□=□1 hn 2 1/c45 (10) Second FIR Filters ddc0_fir2a_ncoeff 4 ddc0_cic_dec_rate/c163 /c180 (11) ddc0_fir2b_ncoeff 4 ddc0_cic_dec_rate/c163 /c180 (12) AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 The maximum filter length that can be realized is limited by two factors. First, the number of clock cycles between successive filter outputs limits the number of coefficients that can be processed, as shown in Equation where ddc0_cic_dec_rate is the decimation ration of the CIC filter. Second, the size of the data memory (which stores incoming data samples) limits filter length to taps. Note that two data memory locations are required to filter processing. The dc gain of the FIR filter depends on the coefficient values and the filter mode. For ODD mode and HALFBAND mode, the dc gain is given by Equation where h n is the n th of NCOEFF filter coefficients stored in memory. For EVEN mode the, dc gain is shown by Equation while for ARBITRARY mode the gain is shown by Equation The first FIR filter is followed by two parallel second FIR filters, FIR2A and FIR2B. Duplicate filters allow the output of two I and Q output streams with different bandwidths. For example, the bandwidth of FIR2A may be set wide to accommodate reception of digital broadcasts, while FIR2B may be set narrower to receive an analog broadcast sharing the same band. Coefficients for FIR2A are stored in memory bank (MEM and coefficients for FIR2B are stored in memory bank (MEM 2). The operation of the second FIR filter is similar to the first FIR filter with several notable exceptions. First, the depths of the coefficient and data memories are doubled to 128. This size increase allows for filters up to 126 taps to be realized without running out of data memory. It also allows longer sets of filter coefficients to be stored in coefficient memory. Second, because of the additional decimation by two from the first FIR filter, twice as many MCLK cycles are available to process coefficients, increasing the maximum allowable value of NCOEFF, as shown in Equation and Equation Third, in the first FIR filter the total of all the filter tap weights must add up to to achieve unity gain through the filter. With longer filters (and therefore, smaller coefficients), frequency response errors may be introduced as a result of coefficient truncation. A Shift parameter has been added to the second FIR filter to alleviate this problem. The total of all filter tap weights must add up to 15+ddc0_fir2a_shift to achieve unity gain through FIR2A (similarly for ddc0_fir2b_shift and FIR2B). Note that shift values for FIR2A and FIR2B can be set separately. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

H (z)□=EVEN /c229 NCOEFF 1/c45 n□=□0 COEFF (z /c180BASE_ADDR□+ n +□z ) /c45 /c45 /c180 /c45 /c45n (2 NCOEFF 1 n) (13) H (z)□=ODD /c229 NCOEFF 2/c45 n□=□0 COEFF (z /c180BASE_ADDR□+ n BASE_ADDR□+ NCOEFF 1/c45+□z )□+□COEFF /c45 /c45 /c180 /c45 /c45 /c45n (2 NCOEFF 2 n) NCOEFF 1 z/c180 (14) H (z)□=HALFBAND /c229 NCOEFF 2/c45 n□=□0 COEFF (z /c180BASE_ADDR□+ n BASE_ADDR□+ NCOEFF 1/c45+□z )□+□COEFF z /c180 /c45 /c45 /c180 /c45 /c45 /c180 /c452n (4 NCOEFF 6 2n) 2 NCOEFF 3 (15) H (z)□=ARBITRARY /c229 NCOEFF 1/c45 n□=□0 COEFF z /c180BASE_ADDR□+ n /c45 n (16) GAIN (z)□=□2EVEN /c180 /c45 SHIFT 2 /c180 /c229 NCOEFF 1/c45 n□=□0 COEFFBASE_ADDR□+ n 2 1/c45 (17) GAINODD HALFBAND=□GAIN =□2 /c180 /c45 SHIFT 2 /c180 /c229 NCOEFF 2/c45 n□=□0 COEFF +□COEFFBASE_ADDR□+ n BASE_ADDR□+ NCOEFF 1 /c45 2 1/c45 (18) GAIN (z)□=□2ARBITRARY /c180 /c45 SHIFT /c229 NCOEFF 1/c45 n□=□0 COEFFBASE_ADDR□+ n 2 1/c45 (19) AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com Extended-Length Filter Mode If FIR2A or FIR2B cannot provide enough filter taps to achieve the desired frequency response, setting control bit ddc0_interleave puts the two filters into an interleaved mode that doubles the length of the filter that can be realized. However, there are several limitations: Only odd symmetrical filters may be realized; The filter length M must be such that 1)/4 is an integer; and Only one filter can be realized (in ddc_interleave mode the A and B outputs are identical: IB IA and QB QA). In addition to setting the ddc0_interleave bit, FIR2A must be set to EVEN mode and FIR2A must be set to ODD mode. ddc0_fir2a_ncoeff and ddc0_fir2b_ncoeff are both set to 1)/4. ddc0_fir2a_shift and ddc0_fir2b_shift should be identical. There are no restrictions on ddc0_fir2a_base_addr or ddc0_fir2b_base_addr The M-tap filter has 1)/2 unique coefficients. The first, third, fifth, etc. coefficients are loaded into the FIR2A coefficient memory; the second, fourth, sixth, etc. coefficients are loaded into the FIR2B memory. The center coefficients of the filter end up as the last coefficient loaded into FIR2B. FIR Filter Transfer Functions Equation to Equation show transfer functions and dc gain for the various filter modes. Generic names for the control variables are used; just substitute the appropriate variable (that is, ddc0_fir2a_ncoeff for NCOEFF) as necessary. Also, note that SHIFT has a value of for FIR1. Basic Filter Modes Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

H (z)□=□2EXTENDED /c180 /c45 SHIFT /c229 NCOEFF 1/c45 n□=□0 COEFF_A (z /c180BASE_ADDR_A + n +□z ) /c45 /c180 /c180 /c45 /c452 n 2 (2 NCOEFF 1 n)/c180 /c45 /c229 NCOEFF 2/c45 n□=□0 COEFF_B (z /c180BASE_ADDR_B + n +□z ) /c45 /c180 2 n + 1 /c45 /c180 /c180 /c45 /c452 (2 NCOEFF 2 n) + 1 +□COEFF_B /c180BASE_ADDR_B + NCOEFF 1/c45 z

2 NCOEFF/c180 (20)

/c1802 /c45 SHIFT 2 1/c45 GAIN =EXTENDED /c229 NCOEFF 1/c45 n□=□0 COEFF_ABASE_ADDR_A + n2 /c180 /c229 NCOEFF 2/c45 n□=□0 COEFF_BBASE_ADDR_B + n+□2 /c180 +□COEFF_BBASE_ADDR_B + NCOEFF 1/c45 (21) Digital Downconverter (DDC1) Primary IF Data Interface AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 Extended-Length Filter Mode The DDC0, with the following exceptions: DDC1 is enabled by ddc_en[1] Control variables are prefixed with ddc1 instead of ddc0 FIR coefficients are stored in memory banks and instead of and Table shows the DDC1 operation control settings. The two DDCs produce a total of eight 16-bit output values and Q from each of four final-stage FIR filters). The IF data interface time-multiplexes these eight values onto four serial lines. The IF data interface also generates the necessary clock and frame sync signals to complete the interface to the DSP. The general timing of the IF data interface is shown in Figure Note that each serial line (IF_DOUT0 through IF_DOUT3) can carry up to four time-multiplexed 16-bit signals. The actual number of signals per line is limited by: the frequency of IF_DCLK, which can be programmed to be the same as the IF sampling clock (MCLK), one-half the IF sampling frequency, or one-fourth the IF sampling frequency; and the overall decimation ratio of the DDC that determines the frequency of IF_DFSO pulses and therefore the number of IF_DCLK cycles available to clock out data. Table IF Control Register Settings PARAMETER ADDRESS BITS ddc1_cic_dec_rate 8:0 ddc1_cic_scale 11:6 ddc1_cic_shift 5:0 ddc1_demod_freq[31:16] 15:0 ddc1_demod_freq[15:0] 15:0 ddc1_demod_phase[31:16] 15:0 ddc1_demod_phase[15:0] 15:0 ddc1_fir1_base_address 13:8 ddc1_fir1_mode 1:0 ddc1_fir1_ncoeffs 7:2 ddc1_fir1_nodec ddc1_fir2_nodec ddc1_fir2a_base_address 15:9 ddc1_fir2a_mode 1:0 ddc1_fir2a_ncoeffs 8:2 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

IF_DOUT1 IF_DFSO IF_DOUT2 IF_DOUT3 IF_DCLK AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com Table IF Control Register Settings (continued) PARAMETER ADDRESS BITS ddc1_fir2a_shift 3:0 ddc1_fir2b_base_address 15:9 ddc1_fir2b_mode 1:0 ddc1_fir2b_ncoeffs 8:2 ddc1_fir2b_shift 7:4 ddc1_interleave ddc_en[1] ddc_sync Figure 15. IF Data General Timing Control register variables dout0_config dout1_config dout2_config and dout3_config are used to assign specific output data streams to particular time slots in the IF interface output frame. Each register is broken into four 4-bit values, each of which is used to assign the source for a given time slot according to Table Table Time Slot Sources VALUE SOURCE No source assigned DDC0, FIR2A, I DDC0, FIR2A, Q DDC0, FIR2B, I DDC0, FIR2B, Q DDC1, FIR2A, I DDC1, FIR2A, Q DDC1, FIR2B, I DDC1, FIR2B, Q dout0_config controls the four time slots of IF_DOUT0, register controls the four time slots of IF_DOUT1, and so on. The mapping of register bits to time slots is summarized in Table Table Register Bit Mapping PARAMETER [15:12] [11:8] [7:4] [3:0] dout0_config dout1_config dout2_config dout3_config Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

f =IF_DCLK fMCLK f =□fIF_DCLK MCLK if_dclk_div 1/c163 (23) IF_DFSO Mode□0 IF_DCLK IF_DFSO Mode□1 IF_DFSO Mode□2 AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 For example, bits [11:8] of dout2_config set the source assignment for time slot of IF_DOUT2. The control variable if_dclk_div sets the frequency of IF_DCLK, as shown in Equation and Equation Normally the data and the frame sync change on the rising edge of IF_DCLK. If if_dclk_edge is set to then IF_DCLK is inverted so that data and frame sync change on the falling edge of IF_DCLK. The control value if_dfso_select determines which DDC is responsible for generating IF_DFSO. If if_dfso_select is then an IF_DFSO pulse is generated each time a new output is ready from DDC0. Similarly, if if_dfso_select is then an IF_DFSO pulse is generated each time a new output is ready from DDC1. If the decimation rates of DDC0 and DDC1 are identical, then it does not matter which DDC initiates the IF_DFSO pulse. If the decimation rates are different, then the DDC with the smaller decimation ratio (higher output rate) should be chosen to generate the IF_DFSO pulse. Note that in this case, outputs from the slower DDC are repeated for multiple frames and it is the responsibility of the DSP software to compensate. This compensation is easiest to do if the higher decimation rate is an integer multiple of the lower decimation rate. Finally, if_dfso_mode is used to select alternate forms of frame sync. In the default case if_dfso_mode 0), the frame sync is a high pulse one clock period wide that occurs the clock cycle before the first data bit of the serial output. If if_dfso_mode is set to then the frame sync changes polarity once per frame; again, one clock cycle before the first data bit of the frame. If if_dfso_mode is set to then the frame sync behaves like the default frame sync except that the sync pulse is clock periods wide. The three frame sync modes are illustrated in Figure and Figure Table shows the detailed timing conditions for Figure It is recommended that the DSP interface be configured to sample IF_DFSO and the four IF_DOUT lines on the trailing edge of IF_DCLK. Table shows the dout if_dclk if_dfso and if_dout operation control settings. Table Detailed Timing Conditions PARAMETER t IF_DCLK0 to IF_DFS0 delay 2.9 3.7 ns t IF_DCLK0 to IF_DOUTx delay 3.1 3.8 ns Table Primary IF Control Register Settings PARAMETER ADDRESS BITS dout_en if_dclk_div 4:0 if_dclk_edge if_dfso_mode 8:7 if_dfso_select if_dout0_config 15:0 if_dout1_config 15:0 if_dout2_config 15:0 if_dout3_config 15:0 Figure 16. Frame Sync Modes Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

I UF_DO T0 I UF_DO T1 IF_DFSO IF_DCLK td1 td2 A0[14] A1[14] A0[15] A1[15] IF D U_ O T2 IF D U_ O T3 A2[14] A3[14] A2[15] A3[15] Alternate IF Data Interface Auxiliary DACs AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com Figure 17. Detailed Timing The operation and timing of the alternate IF data interface are identical to the primary IF data interface. Pin names are changed such that BB_BCK is equivalent to IF_DCLK; BB_WS is equivalent to IF_DFSO;\` and BB_IOUT0, BB_IOUT1, BB_QOUT0, and BB_QOUT1 are each equivalent to any IF_DOUTx pins. The parameter names are also changed to reflect the different interface pin names. Table shows the BB operation control settings. Table 10. Alternate IF Control Register Settings PARAMETER ADDRESS BITS bb_dclk_edge bb_dclk_div 4:0 bb_dout0_config 15:0 bb_dout1_config 15:0 bb_dout2_config 15:0 bb_dout3_config 15:0 bb_en bb_ws_mode 10:7 bb_ws_select CDAC0 is enabled by a high value set for cdac_en[0] Similarly, CDAC1 is enabled by a high value set for cdac_en[1] A control DAC that is disabled is put into a low-power state. The control DAC outputs are set by the control variable cdac0_out for CDAC0 and CDAC1_OUT for CDAC1. A value of zero generates a output from the control DAC while a value of 4095 generates a full-scale output from the control DAC. Table shows the CDAC operation control settings. Table 11. CDAC Control Register Settings PARAMETER ADDRESS BITS cdac_en[0] cdac_en[1] cdac0_out 11:0 cdac1_out 11:0 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 The auxiliary ADC is an 8-bit successive approximation converter that is intended for low-speed, low-accuracy tasks such as system diagnostics. Any one of four input pins can be connected to the auxiliary ADC. The parameter aux_adc_sel is used to connect a particular input pin to the converter. This input multiplexer operates according to the following sequence: aux_adc_sel No aux ADC inputs are connected, all inputs high impedance aux_adc_sel AUX_ADC0 pin connected to aux ADC aux_adc_sel AUX_ADC1 pin connected to aux ADC aux_adc_sel AUX_ADC2 pin connected to aux ADC aux_adc_sel AUX_ADC3 pin connected to aux ADC A conversion in initiated by writing to register with bit aux_adc_trig high. The conversion time is 8704 MCLK cycles. At the end of the conversion auc_adc_done goes high and the result is returned in aux_adc_out As an alternative to polling aux_adc_done the AFE8221 can be configured to generate an interrupt when an auxiliary ADC conversion is completed. Table shows the aux_adc operation control settings. Table 12. AUX_ADC Control Register Settings PARAMETER ADDRESS BITS aux_adc_done aux_adc_out 7:0 aux_adc_sel 11:8 aux_adc_trig The master clock oscillator supports third-overtone designs from MHz to MHz. It can also support fundamental operations in the 20-MHz to 30-MHz range. The recommended third-overtone circuit for third-overtone operation is shown in Figure and Table Figure 18. Third-Overtone Operation Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

I C Master f =SCL fMCLK 4 i2cm_clk_cycles/c180 (24) AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com Table 13. Third-Overtone Operation Recommendations C C R FREQUENCY (MHz) (pF) (pF) µ µ Ω 0.1 4.7 6.8 0.82 3.3 4.7 0.68 2.7 3.3 0.56 2.7 3.3 0.56 2.2 3.3 The master clock oscillator may be optionally divided down to provide a reference clock on the REFCLK pin. Control variable refclk_en enables the generation of the reference clock when high. Two variables, refclk_hi and refclk_lo define the high and low periods of REFCLK in terms of MCLK cycles. REFCLK is high for refclk_hi cycles of MCLK, then low for refclk_lo periods of MCLK. REFCLK frequency is limited to integer submultiples of MCLK. Table shows the refclk operation control settings. Table 14. REFCLK Control Register Settings PARAMETER ADDRESS BITS refclk_en refclk_hi 15:0 refclk_lo 15:0 The real-time clock oscillator supports crystals in the frequency range of 32.768 kHz through 150 kHz. The real-time clock module can be programmed to operate accurately with crystals in this frequency range. The real-time clock oscillator output may be optionally output on the RTC_OUT pin when rtc_oe is set high. This option allows the real-time clock oscillator to be used as an alternate reference clock in the event that an acceptable frequency cannot be derived from MCLK. Table shows the rtc_oe control setting. Table 15. RTC Control Register Setting PARAMETER ADDRESS BITS rtc_oe The I C Master interface uses control variables (as shown in Table and two 16-byte buffers to create I C bus transactions compliant with the Philips I Bus Specification Version 2.1 Both and 10-bit addressing schemes are supported. Control variables supply address, data transfer direction, data burst length, and transaction control information to an I C master engine. This engine handles the details of the I C signaling and uses two 16-byte buffers to store data transferred during the transaction. A block diagram for this interface is illustrated in Figure SCL clock rates are controlled using the i2cm_clk_cycles control variable given by Equation The interface supports both standard and fast-mode clock rates of 100 kHz and 400 kHz, respectively. Although two pairs of SCL and SDA pins are provided, the pins share a common master function. Reprogramming of the i2cm_if_select variable should only be performed when the i2cm_done status is indicating that all pending I C transactions have completed and that it is safe to change the selected pair. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Table 16. I C Control Register Settings PARAMETER ADDRESS BITS i2cm_10b_addressing 124 i2cm_allow_slave_nack 124 i2cm_clear_slave_nack 124 i2cm_clk_cycles 124 7:0 i2cm_done 124 i2cm_holding 124 i2cm_if_sel 121 i2cm_multimaster 124 i2cm_read_auto_inc 123 i2cm_read_byte 123 7:0 i2cm_read_byte_ptr 123 11:8 i2cm_restart_data_length 121 12:8 i2cm_restart_rw 121 i2cm_scl_sync_en 124 i2cm_slave_addr 120 14:0 i2cm_start_data_length 121 4:0 i2cm_start_rw 121 i2cm_use_sr 121 i2cm_use_stop 124 i2cm_write_auto_inc 122 i2cm_write_byte 122 7:0 i2cm_write_byte_ptr 122 11:8 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

START_DATA_LE TH[NG 4:0] SLAVE_ADDR[14 ]:0 I C□Master□Engine RESTART_DATA_LENGTH[4:0] TEN_BIT_ADDR U E_SRS WRITE_DATA[7:0] READ_DATA[7:0]I CM_READ_BYTE[7:0] I CM_SLAVE_ADDR[14:0] I CM_START_DATA_LENGTH[4:0] I CM_RESTART_DATA_LENGTH[4:0] I CM_10B_ADDR I CM_USE_SR SCL0 SDA0 DONE I M_DC ONE ST RT_A RW RESTART_RW I CM_START_RW I CM_RESTAR _ WT R I CM_READ_BYTE PTR_ [3:0] I CM_IF_SEL SCL1 SDA1 I CM_READ_BYTE AUT_ O_□NCI SCL SDA CLK_CYCLE [7:0]SI CM_CLK_CYCLES[7:0] MULTIMASTERI CM_MULTIMASTER SCL_SYNC_ENI CM_SCL_SYNC_EN I CM_HOLDING HOLDING I CM_USE_STOP

2 USE_STOP

I CM_ALLOW_SLAVE_NACK I CM_CLEAR_SLAVE_NACK ALLOW_SLAVE_NACK CLEAR_SLAVE_NACK Transaction Control Read□Buffer Control Write□Buffer Control Slave□Burst Length Slave Address I CM_WRITE_BYTE_PTR[3:0] I CM_WRITE_BYT [7:E 0] I CM_WRITE_AUTO_INC I C Write Transactions I C Read Transactions AFE8221-Q1 SBAS434 DECEMBER 2008 www.ti.com Figure 19. I C Master Block Diagram Write data must be stored in sequential locations in the write buffer starting at location zero. i2cm_write_byte_ptr[3:0] specifies one of the memory locations where i2cm_write_byte[7:0] data will be written. An auto-increment feature permits the internal update of this pointer without specifying an offset for each byte after the first byte. Once the desired write data are loaded into this memory, i2cm_start_data_length[4:0] must specify the number of bytes to write and i2cm_start_rw should be set to indicating that write data will follow the address. i2cm_10b_addr should be set to select the desired or 10-bit addressing scheme as described in the Control Register Assignments section of this document. The write transaction is initiated by writing the slave address to i2cm_slave_addr The host controller should poll the i2cm_done bit for a indicating that the transaction has completed. The sequence of actions generated on the I C bus are: Start Slave Addr Write Data Burst Stop i2cm_start_data_length[4:0] must specify the number of bytes to read and i2cm_start_rw should be indicating that read data will follow the address. i2cm_10b_addr specifies the addressing scheme. The read transaction is initiated by writing the slave address to i2cm_slave_addr The host controller should poll the i2cm_done bit for a indicating the transaction has completed. Once completed, the read data can be extracted from the read buffer using the control variables i2cm_read_ptr[3:0] and i2cm_read_byte[7:0] The sequence of actions generated on the bus are: Start Slave Addr Read Data Burst Stop Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

I C Combined Format Transactions I C Data Bursts Greater than Bytes Interrupt Operation Real-Time Clock Setting and Reading the RTC AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 The I C specification describes combined write/read formats where a master initially transmits data to a slave and then reads data from the same slave. The i2cm_use_sr parameter is used to create a repeated START condition to support this format. By setting the i2cm_use_sr parameter to the master interface can create the following sequence of actions: Start Slave Addr Data Burst Start Slave Addr Data Burst Stop i2cm_start_data_length[4:0] and i2cm_start_rw control the data burst length and direction for DATA BURST i2cm_restart_data_length[4:0] and i2cm_restart_rw control the data burst length and direction for DATA BURST If the data direction is the same for both halves of the combined transaction, data are stored sequentially in the 16-byte buffer. Writing i2cm_slave_addr initiates the transaction. To create an I C read or write burst greater than bytes, the i2cm_use_stop parameter should be set to causing the interface to pause between each burst of bytes transferred. This pause allows the host to either reload or empty the buffers, depending on the direction of data transfer. After starting the transaction by writing i2cm_slave_addr the i2cm_holding status bit should be monitored for a logic indicating that the interface has completed the current set of byte transfers and is waiting for the host to continue. After reloading or emptying the buffers as needed, the host should rewrite i2cm_slave_address to continue the transfer for the next block of up to bytes. For the final transfer of the long data burst, i2cm_use_stop must be set to prior to re-writing the i2cm_slave_address This configuration creates a normal STOP condition to properly terminate the transfer. As an alternative to polling the values of i2cm_done or i2cm_use_stop the AFE8221 can be programmed to generate an interrupt when either of these values goes high. The real-time clock (RTC) is enabled by setting rtc_en to While rtc_en is the RTC oscillator continues to run but the RTC registers do not advance. The RTC can operate with a range of oscillator frequencies up to 100 kHz. At the beginning of each second, the value of rtc_max_count is loaded into the RTC crystal counter. This counter is decremented at the rate of the RTC oscillator until it hits zero, which generates a strobe that increments the seconds counter as well as re-initializes the RTC crystal counter. For a nominal 32.768-kHz clock crystal, rtc_max_count should be set to 16,384 (the default value); for a nominal 100-kHz crystal, rtc_max_count should be set to 50,000. Table illustrates the RTC control variable settings. The RTC can be coarsely calibrated by adjusting the rtc_max_count to an appropriate value other than half the nominal crystal frequency. If finer calibration is required, compensation mode can be enabled by setting rtc_comp_en to In compensation mode, the two's-complement value stored in rtc_comp_val is added to the one-second counter when it is re-initialized at the beginning of each hour; thus, the first second of each hour is lengthened or shortened depending on the sign of rtc_comp_val The compensation can be applied to several seconds at the beginning of each hour; rtc_comp_cnt holds the number of seconds per hour to which the compensation is applied. By spreading the compensation out over a number of seconds, the impact on the length of any given second is minimized. Because of the need to carefully synchronize any update of the RTC time registers rtc_seconds rtc_minutes etc.), they must be written in a slightly different manner than the other control registers. Time registers must be written individually; after a particular register address is written, at least two clock cycles of the RTC oscillator must pass before another register write occurs. The MSB of each time register address can be polled to determine if it is safe to make another write: if the MSB is the interface is still busy and a new write should not be initiated. If the MSB is then the interface is ready to accept another write. There is no limitation on reading the time registers. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Note that all time register values are BCD-encoded. Also note that the rtc_day_of_week is a read-only value that is internally calculated from the rtc_day rtc_month and rtc_year registers. Ranges on the various time registers are shown in Table When the rtc_mode changes, the real-time clock alarm settings should also be changed to reflect the new time format. For instance, an alarm setting of 1300 hours never generates an interrupt in 12-hour mode. This setting should be reset to 1:00 PM when the mode is changed to 12-hour mode. Table 17. Time Register Ranges PARAMETER RANGE rtc_seconds to rtc_minutes to to (12-hour mode); rtc_hours to (24-hour mode) (AM) or (PM) rtc_ampm 12-hour mode only rtc_day to 31, depending on month rtc_month to to rtc_year (for years 2000 to 2099) rtc_day_of_week (Sunday) to (Saturday) Invalid combinations of rtc_day and rtc_month (trying to set February 30, for example) cause unpredictable behavior and should be avoided. The February rollover variation based on leap year is automatically corrected for. The RTC defaults to operate in 12-hour plus AM/PM mode. To operate in 24-hour mode (where the AM/PM bits are disabled) set rtc_mode to Care must be taken when switching between AM/PM mode and 24-hour mode to avoid setting the time to a invalid value. See Figure and Figure for the proper procedures. The real-time clock alarm function can be used to generate an interrupt (or a wakeup interrupt) at a pre-programmed time. If the appropriate bit in an interrupt enable register is set, an interrupt will be generated when the values in the RTC time registers become equal to the values in the RTC alarm registers. The register settings are shown in Table Table 18. RTC Alarm Control Register Settings PARAMETER ADDRESS BITS rtc_seconds_alarm[6:0] 6:0 rtc_minutes_alarm[6:0] 6:0 rtc_hours_alarm[5:0] 5:0 rtc_ampm_alarm rtc_day_alarm[5:0] 5:0 rtc_month_arlarm[4:0] 4:0 rtc_year_alarm[7:0] 7:0 general-purpose I/O pins are provided, labeled GPIO0 through GPIO11. The direction of the GPIO pins can be independently set through control variable gpio_oe(11:0) A pin is an input if the corresponding bit of gpio_oe is a pin is an output if the corresponding bit of gpio_oe is The control variable gpio(11:0) serves different functions, depending on whether it is read from or written to. A read operation from gpio returns the logic state of the eight GPIO pins regardless of their direction. A write to gpio sets the output state of the GPIO pins if they are configured as outputs; there is no effect if the pin is configured as an input. Note that the write value of gpio is stored in a register, so that if a GPIO pin is changed from an input to an output its logic state is set by the stored value of gpio Table shows the gpio control variable settings. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

Read□rtc_hours□and rtc_ampm□Registers No YesDoes rtc_hours□=□12□and rtc_ampm□=□0? Set□rtc_hours□= rtc_hours□+□12 Set□rtc_hours□=□0 No YesIs rtc_ampm□=□0? (AM) No YesDoes rtc_hours□=□12□and rtc_ampm□=□1? 12:00AM□=□0000□Hours (Midnight) 12:00□PM□=□1200□Hours (Noon) Recalculate Alarm□Registers Set□rtc_mode□=□1 AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 The GPIO inputs can be optionally debounced if an RTC oscillator is running. Debouncing is controlled by gpio_delay which is divided into 2-bit fields, each controlling a particular GPIO input according to Table Table 19. gpio_delay [23:22] [21:20] [19:18] [17:16] [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Figure 20. Procedure for Updating RTC Hour When Going from 12-Hour Mode to 24-Hour Mode Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

Set□rtc_mode□=□0 No YesDoes rtc_hours□=□0? Read□rtc_hours□Register Set□rtc_hours□= rtc_hours 12 and□rtc_ampm□=□1 /c45 Set□rtc_hours□=□12 and□rtc_ampm□=□0 No YesIs No YesDoes (Midnight) (AM) (Noon) Recalculate Alarm□Registers f =DEBOUNCE fRTC

2 GPIO_DEBOUNCE_FREQ + 1/c180 (25)

www.ti.com Figure 21. Procedure for Updating RTC Hour When Going from 24-Hour Mode to 12-Hour Mode The debounce circuitry uses a clock divided from the RTC oscillator, with a debounce clock frequency given by Equation If debounce is enabled, then in order for a GPIO input to change value (and possibly generate an interrupt if so programmed) it must remain stable for the number of debounce clock cycles (zero to three) given in the appropriate field of gpio_delay. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

(GPIO and Input Attenuator) Interrupt Generators AFE8221-Q1 www.ti.com SBAS434 DECEMBER 2008 Table 20. General RTC Control Register Settings PARAMETER ADDRESS BITS rtc_ampm rtc_comp_cnt[5:0] 12:7 rtc_comp_en rtc_comp_val 15:0 rtc_day[5:0] 5:0 rtc_day_of_week[2:0] 2:0 rtc_en rtc_hours[5:0] 5:0 rtc_max_count[15:0] 15:0 rtc_minutes[6:0] 6:0 rtc_mode rtc_month[4:0] 4:0 rtc_seconds[6:0] 6:0 rtc_year[7:0] 7:0 Table 21. GPIO Control Register Settings PARAMETER ADDRESS BITS gpio 11:0 gpio_delay[15:0] 15:0 gpio_oe 11:0 If some of the GPIO pins on the AFE8221 are to be used to control the gain of a tuner, it may be desirable to change the GPIO values at the same time as the input attenuation to the DDC. To make this process more deterministic, the control parameters gpio ddc0_atten and ddc1_atten can be accessed through the alternate control register addresses of and 97. By writing to register 96, gpio and ddc0_atten can be changed in a single register write; by writing to register 97, gpio and ddc1_atten can be changed in a single register write. Table shows the operation control settings for these parameters. Table 22. Alternate GPIO and DDC Control Register Settings PARAMETER ADDRESS BITS gpio 11:0 ddc0_atten 14:12 ddc1_atten There are three programmable interrupt pins; IRQ0, IRQ1, and IRQ2. Only the operation of IRQ0 is described here; IRQ1 and IRQ2 are programmed in the same way, using different control variables. Interrupts can be generated from various sources. Interrupt generation is enabled through irq0_en as Table shows. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 23. Interrupt Generation BIT POSITION SOURCE BIT POSITION SOURCE GPIO RTC alarm None RTC seconds rollover I C Master done RTC minutes rollover Aux ADC done RTC hours rollover IFADC0 over-range RTC months rollover IFADC1 over-range RTC day rollover IFADC0 limit RTC year rollover IFADC1 limit Setting a bit of irq0_en allows the generation of an interrupt for the corresponding event. All three IRQ generators run on the master clock (MCLK). When an interrupt event occurs on a given source signal, a value of is written to the corresponding bit of irq0_status This value is held in irq0_status until it is explicitly cleared by writing a to the appropriate bit of irq0_status A typical sequence upon receipt of an interrupt would be to poll irq0_status to determine the source of the interrupt, take whatever system action is appropriate, and then clear irq0_status Changes to any of the GPIO pins can also be programmed as interrupts. GPIO pin events are defined as changes from low to high or from high to low, depending on whether the corresponding bit in irq0_gpio_edge is high or low. GPIO interrupts are enabled by setting the corresponding bit in irq0_gpio_en they are identified and cleared by reading and writing the corresponding bit in irq0_gpio_status The behavior of the IRQ0 pin is determined by irq0_sense When irq0_sense is IRQ0 is normally low and goes high on an unmasked interrupt event. When irq0_sense is IRQ0 is normally high and goes low on an unmasked interrupt event. Table shows the irq0 irq1 and irq2 operations control settings. Table 24. IRQ Control Register Settings PARAMETER ADDRESS BITS irq0_en 15:0 irq1_en 15:0 irq2_en 15:0 irq0_gpio_edge 11:0 irq1_gpio_edge 11:0 irq2_gpio_edge 11:0 irq0_gpio_en 11:0 irq1_gpio_en 11:0 irq2_gpio_en 11:0 irq0_gpio_status 11:0 irq1_gpio_status 11:0 irq2_gpio_status 11:0 irq0_sense irq1_sense irq2_sense irq0_status 15:0 irq1_status 15:0 irq2_status 15:0 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 The WAKEUP interrupt generator functions in the same way as the IRQ generators with the following exceptions: The WAKEUP generator runs on the RTC clock instead of MCLK; The WAKEUP generator operates when the AFE is in low-power mode, whereas the IRQ generators do not; and The interrupt sources for the WAKEUP interrupt generator are slightly different. Table shows the wakeup control settings. Table shows the generator functions. Table 25. Wakeup Control Register Settings PARAMETER ADDRESS BITS wakeup_sense wakeup_gpio_edge 11:0 wakeup_gpio_en 11:0 wakeup_en 15:0 wakeup_status 15:0 wakeup_gpio_status 11:0 Table 26. WAKEUP Interrupt Generator BIT POSITION SOURCE GPIO None None None None None None None RTC alarm RTC seconds rollover RTC minutes rollover RTC hours rollover RTC months rollover RTC day rollover RTC year rollover Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 27. Control Registers Address: Description: Functional Block Enables Bits Range Action Parameter Name 1:0 0..3 Enable IFADC converters ifadc_en(1:0) Gain control for IF_ADC0 ifadc_gain0 Gain control for IF_ADC1 ifadc_gain1 5:4 0..3 Enable DDCs ddc_en(1:0) Synchronize DDC0 and DDC1 ddc_sync Enable primary IF data interface dout_en Enable secondary IF data interface bb_en 10:9 0..3 Enable auxiliary DACs cdac_en(1:0) Enable auxiliary ADC aux_adc_en Enable RTC output pins rtc_oe Enable reference clock output pins refclk_en Address: Description: Interrupt Output Level Configuration Bits Range Action Parameter Name Active high WAKEUP interrupt wakeup_sense Active low WAKEUP interrupt Active high IRQ0 interrupt irq0_sense Active low IRQ0 interrupt Active high IRQ1 interrupt irq1_sense Active low IRQ1 interrupt Active high IRQ2 interrupt irq2_sense Active low IRQ2 interrupt Address: Description: DDC0 Input Attenuator Bits Range Action Parameter Name 2:0 0..6 Attenuation setting for DDC0 ddc_atten(2:0) Address: Description: DDC0 Input Attenuator Bits Range Action Parameter Name 15:0 0..65535 Delay setting for DDC0 attenuator ddc0_delay(15:0) Address: Description: DDC0 NCO Frequency Bits Range Action Parameter Name 15:0 0..65535 Upper bytes of DDC0 NCO frequency ddc0_demod_freq(31:16) Address: Description: DDC0 NCO Frequency Bits Range Action Parameter Name 15:0 0..65535 Lower bytes of DDC0 NCO frequency ddc0_demod_freq(15:0) Address: Description: DDC0 NCO Phase Bits Range Action Parameter Name 15:0 0..65535 Upper bytes of DDC0 NCO phase ddc0_demod_phase(31:16) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Table 27. Control Registers (continued) Address: Description: DDC0 NCO Phase (continued) Bits Range Action Parameter name 15:0 0..65535 Lower bytes of DDC0 NCO phase ddc0_demod_phase(15:0) Address: Description: DDC0 CIC Filter Bits Range Action Parameter Name 8:0 4..256 CIC filter decimation rate ddc0_cic_dec_rate(8:0) Address: Description: DDC0 CIC Filter Bits Range Action Parameter Name 5:0 0..63 CIC filter post-filter shift ddc0_cic_shift(5:0) 11:6 0..32 CIC filter post-filter scale ddc0_cic_scale(5:0) Address: Description: DDC0 FIR Filter Bits Range Action Parameter Name 1:0 0..3 FIR filter mode ddc0_fir1_mode(1:0) 7:2 0..63 Number of coefficients to process ddc0_fir1_ncoeffs(5:0) 13:8 0..63 Coefficient base address ddc0_fir1_base_addr(5:0) Address: Description: DDC0 FIR Filter Bits Range Action Parameter Name 1:0 0..3 FIR filter mode ddc0_fir2a_mode(1:0) 8:2 0..127 Number of coefficients to process ddc0_fir2a_ncoeffs(6:0) 15:9 0..127 Coefficient base address ddc0_fir2a_base_addr(6:0) Address: Description: DDC0 FIR Filter Bits Range Action Parameter Name 1:0 0..3 FIR filter mode ddc0_fir2b_mode(1:0) 8:2 0..127 Number of coefficients to process ddc0_fir2b_ncoeffs(6:0) 15:9 0..127 Coefficient base address ddc0_fir2b_base_addr(6:0) Address: Description: DDC0 FIR Filter Extended 3:0 0..15 Post-filter shift for FIR filter ddc0_fir2a_shift(3:0) 7:4 0..15 Post-filter shift for FIR filter ddc0_fir2b_shift(3:0) Enable interleave mode for FIR filter and FIR filter ddc0_interleave Disable decimation for FIR filter ddc0_fir1_nodec Disable decimation for FIR filter and FIR filter ddc0_fir2_nodec Address: Description: DDC1 Input Attenuator Bits Range Action Parameter Name 2:0 0..6 Attenuation setting for DDC1 ddc1_atten(2:0) Address: Description: DDC1 Input Attenuator Bits Range Action Parameter Name 15:0 0..65535 Delay setting for DDC1 attenuator ddc1_delay(15:0) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 27. Control Registers (continued) Address: Description: DDC1 NCO Frequency Bits Range Action Parameter Name 15:0 0..65535 Upper bytes of DDC1 NCO frequency ddc1_demod_freq(31:16) Address: Description: DDC1 NCO Frequency Bits Range Action Parameter Name 15:0 0..65535 Lower bytes of DDC1 NCO frequency ddc1_demod_freq(15:0) Address: Description: DDC1 NCO Phase Bits Range Action Parameter Name 15:0 0..65535 Upper bytes of DDC1 NCO phase ddc1_demod_phase(31:16) Address: Description: DDC1 NCO Phase Bits Range Action Parameter Name 15:0 0..65536 Lower bytes of DDC1 NCO phase ddc1_demod_phase(15:0) Address: Description: DDC1 CIC Filter Decimation Bits Range Action Parameter Name 8:0 4..256 CIC filter decimation rate ddc1_cic_dec_rate(8:0) Address: Description: DDC1 CIC Filter Bits Range Action Parameter Name 5:0 0..63 CIC filter post-filter shift ddc1_cic_shift(5:0) 11:6 0..32 CIC filter post-filter scale ddc1_cic_scale(5:0) Address: Description: DDC1 FIR Filter Bits Range Action Parameter Name 1:0 0..3 FIR filter mode ddc1_fir1_mode(1:0) 7:2 0..63 Number of coefficients to process ddc1_fir1_ncoeffs(5:0) 13:8 0..63 Coefficient base address ddc1_fir1_base_addr(5:0) Address: Description: DDC1 FIR Filter Bits Range Action Parameter Name 1:0 0..3 FIR filter mode ddc1_fir2a_mode(1:0) 8:2 0..127 Number of coefficients to process ddc1_fir2a_ncoeffs(6:0) 15:9 0..127 Coefficient base address ddc1_fir2a_base_addr(6:0) Address: Description: DDC1 FIR Filter Bits Range Action Parameter Name 1:0 0..3 FIR filter mode ddc1_fir2b_mode(1:0) 8:2 0..127 Number of coefficients to process ddc1_fir2b_ncoeffs(6:0) 15:9 0..127 Coefficient base address ddc1_fir2b_base_addr(6:0) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Table 27. Control Registers (continued) Address: Description: DDC1 FIR Filter Extended 3:0 0..15 Post-filter shift for FIR filter ddc1_fir2a_shift(3:0) 7:4 0..15 Post-filter shift for FIR filter ddc1_fir2b_shift(3:0) Enable interleave mode for FIR filter and FIR filter ddc1_interleave Disable decimation for FIR filter ddc1_fir1_nodec Disable decimation for FIR filter and FIR filter ddc1_fir2_nodec Address: Description: Data Interface Configuration Bits Range Action Parameter Name 15:0 0..65535 Configuration for IF_DOUT0 if_dout0_config Address: Description: Data Interface Configuration Bits Range Action Parameter Name 15:0 0..65535 Configuration for IF_DOUT1 if_dout1_config Address: 15:0 0..65535 Configuration for IF_DOUT2 if_dout2_config Address: Description: Data Interface Configuration Bits Range Action Parameter Name 15:0 0..65535 Configuration for IF_DOUT3 if_dout3_config Address: Description: Data Interface Configuration Bits Range Action Parameter Name 4:0 0..16 Divide factor to derive IF_DCLK from MCLK if_dclk_div(4:0) IF_DFSO and IF_DOUTx change on rising edge of IF_DCLK if_dclk_edge IF_DFSO and IF_DOUTx change on falling edge of IF_DCLK IF_DFSO generated by DDC0 if_dfso_select IF_DFSO generated by DDC1 IF_DFSO one IF_DCLK cycle wide 8:7 0..2 IF_DFSO toggles once per frame if_dfso_mode(1:0) IF_DFSO IF_DCLK cycles wide Address: Description: Data Interface Configuration Bits Range Action Parameter Name 15:0 0..65535 Configuration for BB_DOUT0 bb_dout0_config Address: Description: Data Interface Configuration Bits Range Action Parameter Name 15:0 0..65535 Configuration for BB_DOUT1 bb_dout1_config Address: Description: Data Interface Configuration Bits Range Action Parameter Name 15:0 0..65535 Configuration for BB_DOUT2 bb_dout2_config Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 27. Control Registers (continued) Address: Description: Data Interface Configuration (continued) Bits Range Action Parameter Name 15:0 0..65535 Configuration for BB_DOUT3 bb_dout3_config Address: Description: Data Interface Configuration Bits Range Action Parameter Name 4:0 0..16 Divide factor to derive BB_BCK from MCLK bb_bck_div(4:0) BB_WS and BB_DOUTx change on rising edge of BB_BCK bb_bck_edge BB_WS and BB_DOUTx change on falling edge of BB_BCK BB_WS generated by DDC0 bb_ws_select BB_WS generated by DDC1 BB_WS one BB_BCK cycle wide 8:7 0..2 BB_WS toggles once per frame bb_ws_mode(1:0) BB_WS BB_BCK cycles wide Address: Description: CDAC0 Output Bits Range Action Parameter Name 11:0 0..4095 Output value for CDAC0 cdac0_out(11:0) Address: Description: CDAC1 Output Bits Range Action Parameter Name 11:0 0..4095 Output value for CDAC1 cdac1_out(11:0) Address: Description: Aux ADC Bits Range Action Parameter Name 7:0 0..255 Register read: Conversion result for auxiliary ADC (read only) aux_adc_out(7:0) No aux ADC inputs connected AUX_ADC0 pin connected to aux ADC 11:8 or AUX_ADC1 pin connected to aux ADC aux_adc_sel(3:0) AUX_ADC2 pin connected to aux ADC AUX_ADC3 pin connected to aux ADC 14:12 Not used Register write: Starts a conversion when is written aux_adc_done Register read: Returns while conversion is in progress, when conversion is finished Address: Description: Reference Clock Configuration Bits Range Action Parameter Name 15:0 0..4095 Low period in units of MCLK cycles) for reference clock output refclk_lo(15:0) Address: Description: Reference Clock Configuration Bits Range Action Parameter Name 15:0 0..4095 High period (in units of MCLK cycles) for reference clock output refclk_hi(15:0) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Table 27. Control Registers (continued) Address: Description: GPIO Configuration Bits Range Action Parameter Name GPIO0 set as input gpio_oe(0) GPIO0 set as output GPIO1 set as input gpio_oe(1) GPIO1 set as output GPIO2 set as input gpio_oe(2) GPIO2 set as output GPIO3 set as input gpio_oe(3) GPIO3 set as output GPIO4 set as input gpio_oe(4) GPIO4 set as output GPIO5 set as input gpio_oe(5) GPIO5 set as output GPIO6 set as input gpio_oe(6) GPIO6 set as output GPIO7 set as input gpio_oe(7) GPIO7 set as output GPIO8 set as input gpio_oe(8) GPIO8 set as output GPIO9 set as input gpio_oe(9) GPIO9 set as output GPIO10 set as input gpio_oe(10) GPIO10 set as output GPIO11 set as input gpio_oe(11) GPIO11 set as output Address: Description: GPIO Configuration (continued) Bits Range Action Parameter Name Register write: drives value on GPIO0 pin if enabled as output gpio(0) Register read: returns value on GPIO0 pin Register write: drives value on GPIO1 pin if enabled as output gpio(1) Register read: returns value on GPIO1 pin Register write: drives value on GPIO2 pin if enabled as output gpio(2) Register read: returns value on GPIO2 pin Register write: drives value on GPIO3 pin if enabled as output gpio(3) Register read: returns value on GPIO3 pin Register write: drives value on GPIO4 pin if enabled as output gpio(4) Register read: returns value on GPIO4 pin Register write: drives value on GPIO5 pin if enabled as output gpio(5) Register read: returns value on GPIO5 pin Register write: drives value on GPIO6 pin if enabled as output gpio(6) Register read: returns value on GPIO6 pin Register write: drives value on GPIO7 pin if enabled as output gpio(7) Register read: returns value on GPIO7 pin Register write: drives value on GPIO8 pin if enabled as output gpio(8) Register read: returns value on GPIO8 pin Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 27. Control Registers (continued) Register write: drives value on GPIO9 pin if enabled as output gpio(9) Register read: returns value on GPIO9 pin Register write: drives value on GPIO10 pin if enabled as output gpio(10) Register read: returns value on GPIO10 pin Register write: drives value on GPIO11 pin if enabled as output gpio(11) Register read: returns value on GPIO11 pin Address: Description: GPIO Configuration Bits Range Action Parameter Name 1:0 0..3 GPIO0 debounce setting gpio_delay(1:0) 3:2 0..3 GPIO1 debounce setting gpio_delay(3:2) 5:4 0..3 GPIO2 debounce setting gpio_delay(5:4) 7:6 0..3 GPIO3 debounce setting gpio_delay(7:6) 9:8 0..3 GPIO4 debounce setting gpio_delay(9:8) 11:10 0..3 GPIO5 debounce setting gpio_delay(11:10) 13:12 0..3 GPIO6 debounce setting gpio_delay(13:12) 15:14 0..3 GPIO7 debounce setting gpio_delay(15:14) Address: Description: GPIO Configuration Bits Range Action Parameter Name 1:0 0..3 GPIO8 debounce setting gpio_delay(17:16) 3:2 0..3 GPIO9 debounce setting gpio_delay(19:18) 5:4 0..3 GPIO10 debounce setting gpio_delay(21:20) 7:6 0..3 GPIO11 debounce setting gpio_delay(23:22) Address: Description: IF ADC Alarm Bits Range Action Parameter Name 11:0 0..2047 Alarm limit for IF_ADC0 ifadc0_limit(11:0) Address: Description: IF ADC Alarm Bits Range Action Parameter Name 11:0 0..2047 Alarm limit for IF_ADC1 ifadc1_limit(11:0) Address: Description: IRQ0 Configuration Bits Range Action Parameter Name 11:0 0..4095 GPIO input edge select for IRQ0 irq0_gpio_edge(11:0) Address: Description: IRQ0 Configuration Bits Range Action Parameter Name 11:0 0..4095 IRQ0 GPIO enable irq0_gpio_en(11:0) Address: Description: IRQ0 Configuration Bits Range Action Parameter Name 15:0 0..65535 IRQ0 enable irq0_en(15:0) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Table 27. Control Registers (continued) Address: Description: IRQ0 Status Bits Range Action Parameter Name Register read: returns IRQ0 status 15:0 0..65535 irq0_status(15:0) Register write: clears interrupt bit if is written Address: Description: IRQ0 GPIO Status Bits Range Action Parameter Name Register read: returns IRQ0 status 11:0 0..4095 irq0_gpio_status(11:0) Register write: clears interrupt bit if is written Address: Description: IRQ1 Configuration Bits Range Action Parameter Name 11:0 0..4095 GPIO input edge select for IRQ1 irq1_gpio_edge(11:0) Address: Description: IRQ1 Configuration Bits Range Action Parameter Name 11:0 0..4095 IRQ1 GPIO enable irq1_gpio_en(11:0) Address: Description: IRQ1 Configuration Bits Range Action Parameter Name 15:0 0..65535 IRQ1 enable irq1_en(15:0) Address: Description: IRQ1 Status Bits Range Action Parameter Name Register read: returns IRQ1 status 15:0 0..65535 irq1_status(15:0) Register write: clears interrupt bit if is written Address: Description: IRQ1 GPIO Status (continued) Bits Range Action Parameter Name Register read: returns IRQ1 status 11:0 0..4095 irq1_gpio_status(11:0) Register write: clears interrupt bit if is written Address: Description: IRQ2 Configuration Bits Range Action Parameter Name 11:0 0..4095 GPIO input edge select for IRQ2 irq2_gpio_edge(11:0) Address: Description: IRQ2 Configuration Bits Range Action Parameter Name 11:0 0..4095 IRQ2 GPIO enable irq2_gpio_en(11:0) Address: Description: IRQ2 Configuration Bits Range Action Parameter Name 15:0 0..65535 IRQ2 enable irq2_en(15:0) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 27. Control Registers (continued) Address: Description: IRQ2 Status Bits Range Action Parameter Name Register read: returns IRQ2 status 15:0 0..65535 irq2_status(15:0) Register write: clears interrupt bit if is written Address: Description: IRQ2 GPIO Status Bits Range Action Parameter Name Register read: returns IRQ2 status 11:0 0..4095 irq2_gpio_status(11:0) Register write: clears interrupt bit if is written Address: Description: Not Used Bits Range Action Parameter Name Address: Description: Real-Time Clock Configuration Bits Range Action Parameter Name Freeze real-time clock rtc_en Enable real-time clock operation 0:12 hour mode rtc_mode 1:24 hour mode Enable clock compensation rtc_comp_en Enable clock test mode rtc_test_en 6:4 0..4 Clock test mode selection rtc_test_mode(2:0) 12:7 0..31 Compensation count rtc_comp_cnt(5:0) 15:13 0..7 Frequency select for GPIO debounce gpio_debounce_freq(2:0) Address: Description: Real-Time Clock Configuration Bits Range Action Parameter Name 15:0 0..32767 Real-time one second terminal count. Default 16384 (for 32.768-kHz rtc_max_count(15:0) crystal) Address: Description: Real-Time Clock Configuration (continued) Bits Range Action Parameter Name 15:0 32768..32767 Real-time clock compensation value. Default 16384 rtc_comp_val(15:0) Address: Description: Real-Time Clock Alarm Bits Range Action Parameter Name 6:0 0..59 Seconds alarm setting rtc_seconds_alarm(6:0) Address: Description: Real-Time Clock Alarm Bits Range Action Parameter Name 6:0 0..59 Minutes alarm setting rtc_minutes_alarm(6:0) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Table 27. Control Registers (continued) Address: Description: Realtime Clock Alarm Bits Range Action Parameter Name 1..12 Hour alarm setting, 12-hour mode 5:0 rtc_hours_alarm(5:0) 0..23 Hour alarm setting, 24-hour mode Not used 12-hour mode: AM, PM rtc_ampm_alarm 24-hour mode: not used Address: Description: Real-Time Clock Alarm Bits Range Action Parameter Name 5:0 1..31 Day of the month alarm setting rtc_day_alarm(5:0) Address: Description: Real-Time Clock Alarm Bits Range Action Parameter Name 4:0 1..12 Month alarm setting rtc_months_alarm(4:0) Address: Description: Real-Time Clock Alarm Bits Range Action Parameter Name 7:0 0..99 Year alarm setting rtc_year_alarm(7:0) Address: Description: Real-Time Clock Current Time Bits Range Action Parameter Name 6:0 0..59 Seconds register rtc_seconds(6:0) 14:7 Not used Real-time clock busy (read only) rtc_busy Address: Description: Real-Time Clock Current Time Bits Range Action Parameter Name 6:0 0..59 Minutes register rtc_minutes(6:0) 14:7 Not used Real-time clock busy (read only) rtc_busy Address: Description: Real-Time Clock Current Time (continued) Bits Range Action Parameter Name 1..12 Hour register, 12-hour mode 5:0 rtc_hours(5:0) 0..23 Hour register, 24-hour mode Not used 12-hour mode: AM, PM rtc_ampm 24-hour mode: not used 14:8 Not used Real-time clock busy (read only) rtc_busy Address: Description: Real-Time Clock Current Time Bits Range Action Parameter Name 5:0 1..31 Day of month register rtc_day(5:0) 14:6 Not used Real-time clock busy (read only) rtc_busy Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 27. Control Registers (continued) Address: Description: Real-Time Clock Current Time Bits Range Action Parameter Name 4:0 1..12 Month register rtc_month(4:0) 14:5 Not used Real-time clock busy (read only) rtc_busy Address: Description: Real-Time Clock Current Time Bits Range Action Parameter Name 7:0 0..99 Year register rtc_year(7:0) 14:8 Not used Real-time clock busy (read only) rtc_busy Address: Description: Real-Time Clock Current Time Bits Range Action Parameter Name 2:0 0..6 Day of week rtc_day_of_week(2:0) 14:3 Not used Real-time clock busy (read only) rtc_busy Address: Description: WAKEUP Configuration Bits Range Action Parameter Name 11:0 0..4095 GPIO input edge select for WAKEUP wakeup_gpio_edge(11:0) Address: Description: WAKEUP Configuration Bits Range Action Parameter Name 11:0 0..4095 WAKEUP GPIO enable wakeup_gpio_en(11:0) Address: Description: WAKEUP Configuration Bits Range Action Parameter Name 15:0 0..65535 WAKEUP enable wakeup_en(15:0) Address: Description: WAKEUP Status Bits Range Action Parameter Name Register read: returns WAKEUP status 15:0 0..65535 wakeup_status(15:0) Register write: clears interrupt bit if is written Address: Description: WAKEUP GPIO Status Bits Range Action Parameter Name Register read: returns WAKEUP status 11:0 0..4095 wakeup_gpio_status(11:0) Register write: clears interrupt bit if is written Address: 119 Description: Not Used Bits Range Action Parameter Name Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Table 27. Control Registers (continued) Address: 120 Description: I C Master Slave Address Bits Range Action Parameter Name Slave address used for master transactions. Also starts transaction. 7-bit addressing: bits 6:0 are the slave address. Bits 14:7 are ignored. 14:0 0..32767 i2cm_slave_addr(14:0) 10-bit addressing: bits 9:0 are the slave address. Bits 14:10 are the upper five bits for the slave address first byte Not used Address: 121 Description: I C Master Slave Burst length Bits Range Action Parameter Name 4:0 1..16 Number of bytes to transfer for the first data burst i2cm_start_data_length(4:0) Selects the Read/Write bit value used with the slave address following START. i2cm_start_rw selects Write selects Read 7:6 Not used Number of bytes to transfer for the second data burst in a combined 12:8 1..16 i2cm_restart_data_length(4:0) format transfer. This parameter is used only if i2cm_use_sr Selects the Read/Write bit value used with the slave address following RESTART. i2cm_restart_rw selects Write selects Read SDA0/SCL0 interface i2xm_if_sel SDA1/SCL1 interface selects I C transactions without a repeated start. i2cm_use_sr selects combined transactions with a repeated start. Address: 122 Description: I C Master Write Buffer Control Bits Range Action Parameter Name Stores data in the write buffer at the location specified by 7:0 0..255 i2cm_write_byte(7:0) i2cm_write_byte_ptr(3:0) 11:8 0..15 Buffer location where the i2cm_write_byte should be placed i2cm_write_byte_ptr(3:0) 14:12 Not used Auto increment i2cm_write_byte_ptr is used for storing the i2cm_write_byte value in the write buffer memory i2cm_write_auto_inc i2cm_write_byte_ptr is ignored from the host and it is auto-incremented for writing the i2cm_write_byte to the buffer Address: 123 Description: I C Master Read Buffer Control Bits Range Action Parameter Name 7:0 0..255 Read only retrieves data read by the I C master from the read buffer i2cm_read_byte(7:0) 11:8 0..15 Buffer location where the i2cm_read_byte should be retrieved i2cm_read_byte_ptr(3:0) 14:12 Not used Auto increment i2cm_read_byte_ptr is used for retrieving the i2cm_write_byte value in the read buffer memory i2cm_read_auto_inc i2cm_read_byte_ptr is ignored from the host and it is auto-incremented for retrieving the i2cm_read_byte from the buffer Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Table 27. Control Registers (continued) Address: 124 Description: I C Master Read Buffer Control Bits Range Action Parameter Name 7:0 to 200 Controls the I C SCL clock rate i2cm_clk_cycles(7:0) Multi-master single I C master on SDA and SCL signals i2cm_multimaster multiple I C masters present on SDA and SCL signals SCL sync enable prohibit SCL stretching by slave i2cm_scl_sync_en permit SCL stretching by slave Allow slave NACK require slave to ACK transfers i2cm_allow_slave_nack permit slave to not-acknowledge (NACK) Clear slave NACK. if i2cm_allow_slave_nack is zero and the slave fails to acknowledge, this bit when read will be set. No further I C i2cm_clear_slave_nack transactions are allowed until this bit is written as a to clear the slave NACK condition. Use bit addressing i2cm_10b_addressing Use bit addressing End transfer with stop do not issue a stop after last byte transferred and pause i2cm_use_stop transaction issue a stop after the last byte transferred Holding. Read-only. Used when i2cm_use_stop is set to zero. i2cm_holding Done. Read-only. When set, the I C master has completed any i2cm_done pending transactions. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com SBAS434 DECEMBER 2008 Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AFE8221-Q1

www.ti.com Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): AFE8221-Q1

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AFE8221IRFPQ1 Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 AFE8221Q AFE8221IRFPQ1.A Active Production HTQFP (RFP) | 144 60 | JEDEC TRAY (10+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 AFE8221Q (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) AFE8221IRFPQ1 RFP HTQFP 144 60 5 x 12 150 315 135.9 7620 25.4 17.8 17.55 Pack Materials-Page 1

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