AFE8201 BURR-BROWN | Alldatasheet
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Technical content
FEATURES
/C006812-BIT, 80MSPS ADC /C0068INTEGRATED DIGITAL DOWNCONVERTER (DDC): Quadrature Mixer/NCO CIC Decimation Filter FIR Filters /C0068MIXER: 32-BIT FREQUENCY AND PHASE /C0068DECIMATION RATIO: 32 to 4096 /C0068USER PROGRAMMABLE FIR FILTERS WITH 16-BIT COEFFICIENTS /C006812-BIT AUXILIARY DAC /C0068DATA INTERFACE COMPATIBLE WITH TI C5x/C6x DSP BUFFERED SERIAL PORT (McBSP): Code Composer Module for Easy Software Generation /C0068SPI CONTROL INTERFACE /C00683.3V ANALOG, 1.8V DIGITAL SUPPLY /C00681.8V to 3.3V I/O SUPPLY /C0068TQFP-48
APPLICATIONS
/C0068SOFTWARE RADIOS /C0068IF RECEIVE CHANNEL /C0068DIGITAL RADIO RECEIVERS /C0068NARROWBAND RECEIVERS
DESCRIPTION
The AFE8201 consists of a general-purpose, 80MSPS, 12-bit analog-to-digital converter (ADC), a digital downconverter (DDC), and user-programmable digital filters. It is designed to sample narrowband (2.5MHz or less) IF signals and digitally mix, filter, and decimate the signals to baseband. The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters. The mixer frequency and initial phase are independently programmed by 32-bit control words. After the CIC filter, the internal I and Q signals are passed on to the first FIR filter, which can implement even, odd, halfband, and arbitrary impulse responses with up to 62 taps using 16-bit coefficients. Following the first FIR filter are two parallel FIR filters that can be used to provide two output streams or interleaved to form one extended filter with up to 262 taps. The AFE8201 also contains a 12-bit general-purpose auxiliary digital-to-analog converter (DAC) for applications such as AGC amplifier control. Control register data as well as decimation filter coefficients are written to the AFE8201 through the industry-standard SPI control interface. The baseband output signals are transported through a general- purpose, high-speed serial interface that is compatible with TI C5x/C6x DSP family buffered serial ports (McBSP). 12− Bit Pipeline ADC Auxiliary DAC Voltage Reference AUX IFM IFP Quadrature Mixer NCO CIC Filter FIR Filter 1 FIR Filter 2A Data Interface DOUT0 DOUT1 DFSO DCLK DIN DFSI FIR Filter 2B N 2 2 REFM VCM REFP VGB SPI Control Interface SCK MOSI MISO CS_N Timing Generator PWD SYNC RST_N Clock Interface MCLK MCLKB PRODUCT PREVIEW AFE8201 SBWS016A − OCT OBER 2003 − REVISED JANUARY 2005 IF Analog-to-Digital Converter with Digital Downconverter www.ti.com Copyright 2003−2005, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. /C0080/C0082/C0079/C0068/C0085/C0067/C0084 /C0080/C0082/C0069/C0086/C0073/C0069/C0087 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0099/C0111/C0110/C0099/C0101/C0114/C0110/C0115 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0105/C0110 /C0116/C0104/C0101 /C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0118/C0101 /C0111/C0114 /C0100/C0101/C0115/C0105/C0103/C0110 /C0112/C0104/C0097/C0115/C0101 /C0111/C0102 /C0100/C0101/C0118/C0101/C0108/C0111/C0112/C0109/C0101/C0110/C0116/C0046 /C0067/C0104/C0097/C0114/C0097/C0099/C0116/C0101/C0114/C0105/C0115/C0116/C0105/C0099 /C0100/C0097/C0116/C0097 /C0097/C0110/C0100 /C0111/C0116/C0104/C0101/C0114 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0097/C0114/C0101 /C0100/C0101/C0115/C0105/C0103/C0110 /C0103/C0111/C0097/C0108/C0115/C0046 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0114/C0101/C0115/C0101/C0114/C0118/C0101/C0115 /C0116/C0104/C0101 /C0114/C0105/C0103/C0104/C0116 /C0116/C0111 /C0099/C0104/C0097/C0110/C0103/C0101 /C0111/C0114 /C0100/C0105/C0115/C0099/C0111/C0110/C0116/C0105/C0110/C0117/C0101 /C0116/C0104/C0101/C0115/C0101 /C0112/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0119/C0105/C0116/C0104/C0111/C0117/C0116 /C0110/C0111/C0116/C0105/C0099/C0101/C0046
/C0065/C0070/C0069/C0056/C0050/C0048/C0049 SBWS016A − OCT OBER 2003 − REVISED JANUARY 2005 www.ti.com ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY AFE8201 TQFP-48 PFB −40°C to +85°C AFE8201 AFE8201PFBT Tape and Reel, 250 AFE8201 TQFP-48 PFB −40°C to +85°C AFE8201 AFE8201PFBR Tape and Reel, 2000 (1)For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) Supply Voltage Range: (1)Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated under the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2)Measured with respect to DGND. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNITS Supplies and References Operating Free-Air Temperature, TA −40 85 °C Analog Supply Voltage, AVDD 3.15 3.3 3.45 V Digital Supply Voltage, DVDD 1.6 1.8 2.0 V Output Driver Supply Voltage, IOVDD 1.6 3.6 V Input Common-Mode Voltage VCM V Differential Input Voltage Range 2 VPP Clock Inputs: MCLK and MCLKB Sample Rate, fS 5 80 MHz Differential Input Mode Voltage Input Swing 0.4 3.3 V Differential Input Common-Mode Voltage 1.65 V Single-Ended Mode High-Level Input Voltage, VIHC 2 V Single-Ended Mode Low-Level Input Voltage, VILC 0.8 V Clock Pulse Width High, tW(H) 5.625 6.25 ns Clock Pulse Width Low, tW(L) 5.625 6.25 ns Digital Inputs High-Level Input Voltage, VIH 0.7 × IOVDD V Low-Level Input Voltage, VIL 0.25 × IOVDD V PRODUCT PREVIEW
/C0065/C0070/C0069/C0056/C0050/C0048/C0049 SBWS016A − OCT OBER 2003 − REVISED JANUARY 2005 www.ti.com AUXILIARY DAC CHARACTERISTICS All specifications at +25°C, AVDD = +3.3V, and DVDD = +1.8V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT Resolution 12 bits Output voltage range Input code 0x000 0.0 V Output voltage range Input code 0xFFF 2.75 V Output impedance 1 kΩ Settling time to 0.1% FSR 10 µs Offset ±1 % of FSR DC Gain error ±5 % of FSR DC performance Differential nonlinearity, DNL Ensured monotonic ±0.5 LSBperformance Integral nonlinearity, INL After correcting for gain and offset errors ±2 LSB Power-supply rejection ratio, PSRRInput code 0x400, AVDD = 3.15VDC to 3.45VDC 60 dB RECEIVE CHANNEL CHARACTERISTICS All specifications at +25°C, fS = 80MSPS, AVDD = +3.3V, DVDD = +1.8V, IOVDD = +3.3V, Gain = 1, Decimation Ratio = 80, Internal Digital Filter Bandwidth = 264kHz, and Input Signal = 10.7MHz, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNIT DC Accuracy Input impedance 6.25 kΩ Differential nonlinearity, DNL −0.0244 ±0.0122 +0.0244 %FSR Integral nonlinearity, INL −0.0244 ±0.012 +0.0244 %FSR Offset error 3 mV Gain error 1 %FS Gain = 1 1.0 V Gain = 1.14 0.875 V Gain = 1.33 0.75 V Full-scale input level (peak differential)Gain = 1.6 0.625 VFull-scale input level (peak differential) Gain = 2.0 0.5 V Gain = 2.67 0.375 V Gain = 4.0 0.25 V Gain change settling time Number of samples to achieve rated accuracy 2 Samples Power-supply rejection ratio, PSRR AVDD = 3.15VDC to 3.45VDC 70 dB References Negative reference, VREFN 1.1 1.25 1.4 V Positive reference, VREFP 2.1 2.25 2.4 V Common-mode voltage, VCM 1.8 V AC Performance Spurious-free dynamic range, SFDR Input 455kHz, −1dBFS 76 dBc Spurious-free dynamic range, SFDR Input 10.7MHz, −1dBFS 76 86 dBc 2nd-order harmonic, HD2 Input 10.7MHz, −1dBFS 80 dBc Input 455kHz, −1dBFS 75 dB Signal-to-noise ratio, SNR Input 10.7MHz, −1dBFS 70 74 dBSignal-to-noise ratio, SNR In 3kHz bandwidth, −1dBFS, 10.7MHz, 20kHz from fundamental 102 dB Aperture delay 2 ns Aperture uncertainty 0.2 ps Power Supply Analog supply voltage, AVDD 3.15 3.3 3.45 V Digital supply voltage, DVDD 1.71 1.8 1.89 V Output driver supply voltage, IOVDD 3.15 3.3 3.45 V Power dissipation Normal operation 490 570 mW Power dissipation Power-down 20 mW Digital I/O supply current 7 mA Digital supply current 72 mA Analog supply current 103 mA PRODUCT PREVIEW
Figure 3. Control Interface Timing
/C0065/C0070/C0069/C0056/C0050/C0048/C0049 SBWS016A − OCTOBER 2003 − REVISED JANUARY 2005 www.ti.com PIN ASSIGNMENTS SYNC RST_N DOUT1 DOUT0 DCLK DFSO DIN DFSI SCK MISO MOSI CS_N AVDD AGND AVDD AVDD AGND AGND DGND DVDD IOGND IOVDD IOGND PWD AVDD AUX AGND NC AGND MCLK MCLKB AVDD DGND DVDD IOGND IOVDD AVDD AGND IFP IFM AGND VCM AVDD VREFM VREFP AVDD AGND VBG 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 AFE8201 NAME PIN TYPE FUNCTION IFP 3 Input Positive IF Input IFM 4 Input Negative IF Input VCM 6 Output Common-Mode Voltage Output REFM 8 Output Negative Reference Voltage Output REFP 9 Output Positive Reference Voltage Output VGB 12 Output Bandgap Voltage Output AUX 14 Output Auxiliary DAC Output MCLK 18 Input Master Clock Input MCLKB 19 Input Complementary Master Clock Input CS_N 25 Input SPI Chip Select (active low) MOSI 26 Input SPI Serial Input MISO 27 Output SPI Serial Output SCK 28 Input SPI Serial Clock DFSI 29 Input Data Interface Input Frame Sync DIN 30 Input Data Interface Input Data DFSO 31 Output Data Interface Output Frame Sync DCLK 32 Output Data Interface Clock Output DOUT0 33 Output Data Interface Filter 0 Output Data DOUT1 34 Output Data Interface Filter 1 Output Data RESET 35 Input Global Reset SYNC 36 Input External Sync PWD 37 Input ‘1’ = power down; ‘0’ = normal operation AVDD 1, 7, 10, 13, 20, 45, 46, 48 Supply Analog Supply (3.3V) AGND 2, 5, 11, 15, 17, 43, 44, 47 Ground Analog Ground DVDD 22, 41 Supply Digital Supply (1.5V to 1.8V) DGND 21, 42 Ground Digital Ground IOVDD 24, 39 Supply Digital I/O Supply (1.5V to 3.3V) IOGND 23, 38, 40 Ground Digital I/O Ground PRODUCT PREVIEW
periods may be needed for the output of the ADC to settle to the correct value. The DDC consists of a digital quadrature mixer followed by a CIC decimation filter and FIR filters (FIR1 and FIR2). factor of 2, for a total range of 32 to 4096. different section of coefficient memory. to the first FIR filter, but have twice the data and coefficient memory and can therefore realize longer filter responses. can be optionally interleaved to form a single extra-long FIR filter which can realize up to 250 taps. that is compatible with the TI C5x/C6x DSP buffered serial ports (McBSP). the DSP through the serial data port or from a microcontroller through the SPI control interface. all chip parameters. The memory banks store 16-bit FIR filter coefficient data. of a 16-bit instruction followed by multiple 16 bit data words. Table 1. Control Registers
0 Data interface parameters DIV, MODE
1 NCO frequency (bits 0−15)
2 NCO frequency (bits 16−31)
3 NCO Initial Phase (bits 0−15)
4 NCO Initial Phase (bits 16−31)
5 CIC Filter Decimation Rate: DEC_RATE
6 CIC Filter Parameters: SCALE, SHIFT
7 First FIR Filter Parameters: BASE_ADDR, NCOEFF, MODE
8 Second FIR A Filter Parameters: BASE_ADDR, NCOEFF, MODE
9 Second FIR B Filter Parameters: BASE_ADDR, NCOEFF, MODE
10 Setup for the Second FIR
11 Auxiliary DAC: DAC_DATA
12 ADC Parameters: GAIN, PWD
Table 2. Memory Banks
0 FIR Filter 1 Coefficients 64 Coefficients 62 Samples
1 FIR Filter 2A Coefficients 128 Coefficients 126 Samples
2 FIR Filter 2B Coefficients 128 Coefficients 126 Samples
(3) the address of the data target. The second 16 bits is the data transfer, which is input on MOSI for a write cycle or output on MISO for a read cycle. Figure 4. Single Data Word Control Interface Write Cycle for Registers or Memory Figure 5. Register Write Instruction Format
101 MEM_ADDRMEMDon’t Care
Figure 6. Memory Write Instruction Format 2-bit memory select (MEM) and the 8-bit memory address (MEM_ADDR) are required. data word is written to the appropriate register or memory location in the AFE.
instructions are similar to the corresponding data write instructions and are shown in Figure 8 and Figure 9. Figure 7. Single Data Word Control Interface Read Cycle for Registers or Memory Figure 8. Register Read Instruction Format
011 MEM_ADDRMEMDon’t Care
Figure 9. Memory Read Instruction Format Figure 10. Block Memory Read Cycle Control Interface will be written to register or memory.
- input frame sync DFSI; and
interface, as seen in Figure 11.
0000 DIV MODEDon’t Care0
Figure 11. Data Interface Control Register where DIV ranges from 0 to 3. be fast enough to clock out the I and Q data words generated by the on-chip DDC and filters. Figure 12. Data Interface Timing for MODE = 0
Figure 13. Data Interface Timing for MODE = 1 be clocked out before the next I and Q data words must be clocked out. means that DIV may be increased to 1, cutting the frequency of DCLKO in half). sent to the DAC as the unsigned DAC input.
Figure 14. Mixer Control Registers pin is brought low, the phase accumulator is incremented by the value FREQ once per MCLK cycle. Note that the mixer can be bypassed by setting FREQ and PHASE to 0 and using only the Q (real) output. Figure 15. The valid range for DEC_RATE is from 8 to 1024.
0010 DEC_RATE1
0011 S C A L E
Figure 15. CIC Filter Control Registers is 20, setting SHIFT to 22 and scale to 41 will result in a GAIN of 0.9775.
Figure 17. Application of Filter Coefficients in Different Filter Modes
address N+5. The full cycle is shown in Table 3. Table 3. ODD Mode Calculation Example with Six Filter Coefficients
1 BASE_ADDR N and N+10
2 BASE_ADDR+1 N+1 and N+9
3 BASE_ADDR+2 N+2 and N+8
4 BASE_ADDR+3 N+3 and N+7
5 BASE_ADDR+4 N+4 and N+6
6 BASE_ADDR+5 N+5
unchanged. For NCOEFF = 6, filter length ranges from 6 taps for ARBITRARY mode to 19 taps for HALFBAND mode. The dc gain of the FIR filter depends on the coefficient values and the filter mode. where hn is the nth of NCOEFF filter coefficients stored in memory.
that BASE_ADDR and NCOEFF are each one bit wider in the control register.
0100 NCOEFF_ABASE_ADDR_A MODE_A0
0100 NCOEFF_BBASE_ADDR_B MODE_B1
0101 SHIFT_BM2XDon’t Care SHIFT_A0
Figure 18. Second FIR Filter Control Register bank 1 (MEM = 1) and coefficients for filter B are stored in memory bank 2 (MEM = 2). for MODE, NCOEFF, and BASE_ADDR.
- only odd symmetrical filters may be realized;
- the filter length M must be such that (M + 1)/4 is an integer; and
- only one filter can be realized (in M2X mode the A and B outputs are identical: IB = IA and QB = QA).
end up as the last coefficient loaded into FIR2B.
interfaces write to the DAC at the same time.
0101 DAC_DATADon’t Care1
Figure 19. Auxiliary DAC Control Register The gain of PGA and the power-down mode can be set in register 12. The gain setting of the PGA is shown in Table 4. Table 4. PGA Gain Setting PWD = 0 for normal operation.
0110 GAINDon’t Care Don’t
Figure 20. PGA and PWD Register
Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) AFE8201PFBR PREVIEW TQFP PFB 48 2000 None Call TI Call TI AFE8201PFBT PREVIEW TQFP PFB 48 250 None Call TI Call TI (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 31-Jan-2005 Addendum-Page 1
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 4073176/B 10/96 Gage Plane 0,13 NOM 0,25 0,45 0,75 Seating Plane 0,05 MIN 0,17 0,27 SQ 7,20 6,80 5,50 TYP SQ8,80 9,20 1,05 0,95 1,20 MAX 0,08 0,50 M0,08 0°–7° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026
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