Power Management

AFE78201RRUT

Texas Instruments

AFEx8201 16-Bit and 14-Bit Digital-to-Analog Converters (DACs) With Voltage Reference and Diagnostic ADC for Low-Power Applications MAY 2023

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AFEx8201 16-Bit and 14-Bit Digital-to-Analog Converters (DACs) With Voltage Reference and Diagnostic ADC for Low-Power Applications

1 Features

Functional Safety-Capable – Documentation available to aid functional safety system design
Low quiescent current: 170 µA (typical), 210 µA (maximum)
16-bit or 14-bit monotonic high-performance DAC – DAC output range: 0 V to 2.5 V – Digital DAC slew-rate control – 4-LSB INL at 16 bits – 0.07% FSR (max) TUE from –40°C to +125°C
12-bit 3.84-kSPS ADC for advanced diagnostics
Integrated 1.25-V reference at 10 ppm/°C (max)
Internal 1.2288-MHz oscillator with clock output
Digital interfaces: – Serial peripheral interface (SPI) – Universal asynchronous receiver-transmitter (UART)
Fault detection: CRC bit error checking, windowed watchdog timer, diagnostic ADC
Wide operating temperature: –55°C to +125°C

2 Applications

Process control and industrial automation
PLC or DCS I/O modules
3-wire and 4-wire transmitters
4-mA to 20-mA loop-powered applications

3 Description

The 16-bit AFE88201 and 14-bit AFE78201 (AFEx8201) are highly-integrated, high-accuracy, extremely low-power digital-to-analog converters (DACs) with voltage outputs designed for process- control and industrial-automation applications. The AFEx8201 devices include most of the components required to design a 4 ‑mA to 20 ‑mA, 3‑wire or 4-wire sensor transmitter or analog output module. In addition to the highly accurate DAC, the AFEx8201 incorporate a 10-ppm/°C voltage reference and diagnostic analog-to-digital converter (ADC). To accommodate intrinsic and functional-safety concerns, external voltage-to-current conversion and power-regulation are required. The internal diagnostic ADC is multiplexed to several internal nodes that enable an automatic self- health check. This check is capable of detecting errors or malfunctions of the internal bias sources, power regulator, voltage reference, DAC output, die temperature, and optional external voltage source. If any fault is detected from the diagnostic ADC, CRC frame-error checking, or windowed watchdog timer, the devices can optionally issue an interrupt, enter a user-specified fail-safe state, or both. Device Information PART NUMBER RESOLUTION PACKAGE(1) AFE78201 14-bit RRU (UQFN, 24) 4.00 mm × 4.00 mmAFE88201 16-bit (1) For all available packages, see the package option addendum at the end of the data sheet. GPIO0/CLK_OUT MUX12-Bit ADC MUX Internal Diagnostics Temperature Sensor AIN0 POL_SEL/AIN1 16-/14-Bit DAC VOUT Alarm Diagnostics Alarm Responses User Calibration Slew-Rate Control DAC Data Register ALARM SPI Interface UART Interface Control Logic SCLK SCLR PVDD VDD GPIO1 Internal Reference VREFIO REF_EN GND IOVDD RESET Internal Oscillator IRQ (UARTOUT or SDO) REF_GND NC GPIO5/SDI GPIO4/SDO GPIO3/UARTIN GPIO2/UARTOUT GPIO6/CS Watchdog Timer CRC Frame Error Check Simplified Block Diagram AFE78201, AFE88201 SLASF44 – MAY 2023 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES May 2023 * Initial release. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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5 Pin Configuration and Functions

24 ALARM24 ALARM7SCLK 7SCLK

1GPIO3/ UARTIN 1GPIO3/ UARTIN 18 VOUT18 VOUT

23 NC23 NC8GPIO5/ SDI 8GPIO5/ SDI

2GPIO2/ UARTOUT 2GPIO2/ UARTOUT 17 PVDD17 PVDD

22 GND22 GND9GPIO4/ SDO 9GPIO4/ SDO

3GPIO1 3GPIO1 16 POL_SEL/ AIN116 POL_SEL/ AIN1

21 GND21 GND10GPIO6/ CS 10GPIO6/ CS

4SCLR 4SCLR 15 AIN015 AIN0

20 REF_GND20 REF_GND11GPIO0/ CLK_OUT 11GPIO0/ CLK_OUT

5REF_EN 5REF_EN 14 GND14 GND

19 VREFIO19 VREFIO12IOVDD 12IOVDD

6RESET 6RESET 13 VDD13 VDD Not to scaleNot to scale

24 ALARM7SCLK

23 NC8GPIO5/ SDI

22 GND9GPIO4/ SDO

3GPIO1 16 POL_SEL/ AIN1

21 GND10GPIO6/ CS

20 REF_GND11GPIO0/ CLK_OUT

5REF_EN 14 GND

19 VREFIO12IOVDD

Figure 5-1. RRU Package, 24-pin UQFN (Top View) Table 5-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. AIN0 15 AI ADC input voltage. The input range is 0 V to 2 × VREF. ALARM 24 DO Alarm notification pin, open drain, active low. When alarm condition is asserted, this pin is held to logic low; otherwise, this pin is in a high-impedance state (Hi-Z). GND 14 P Digital and analog ground. Ground reference point for all circuitry on the device. GND 21 P Digital and analog ground. GND 22 P Digital and analog ground. GPIO0/ CLK_OUT 11 DO/DI General-purpose input/output (GPIO) pin. Can be configured as a clock output for the 1.2288-MHz internal clock or as a timer. In Hi-Z if not driven. If a GPIO pin is not driven, an external pullup or pulldown resistor is required. GPIO1 3 DO/DI General-purpose input/output (GPIO) pin. In Hi-Z if not driven. If a GPIO pin is not driven, an external pullup or pulldown resistor is required. GPIO2/ UARTOUT 2 DO/DI General-purpose input/output (GPIO) pin. Configured as UART data output at power up. This pin can be configured to function as IRQ pin in SPI only mode. In Hi-Z if not driven. If a GPIO pin is not driven, an external pullup or pulldown resistor is required. GPIO3/ UARTIN 1 DI/DO General-purpose input/output (GPIO) pin. Configured as UART data input at power up. Connect to IOVDD or logic high if not used. If a GPIO pin is not driven, an external pullup or pulldown resistor is required. GPIO4/ SDO 9 DO/DI General-purpose input/output (GPIO) pin. Can be configured as an SPI data output in SPI mode. Data are output on the rising edge of SCLK when CS is low. Interrupt request (IRQ) pin in the UART break mode (UBM). The output is in Hi-Z at power up and must be enabled in the CONFIG register. If a GPIO pin is not driven, an external pullup or pulldown resistor is required. GPIO5/ SDI 8 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI data input at power up. Data are clocked into the 24-bit input shift register on the falling edge of the serial clock input. SDI is a Schmitt-Trigger logic input. If a GPIO pin is not driven, an external pullup or pulldown resistor is required. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: AFE78201 AFE88201

Table 5-1. Pin Functions (continued) PIN TYPE(1) DESCRIPTION NAME NO. GPIO6/ CS 10 DI/DO General-purpose input/output (GPIO) pin. Configured as an SPI chip-select input at power up. Data bits are clocked into the serial shift register when CS is low. When CS is high, SDO is in Hi-Z and data on SDI are ignored. If a GPIO pin is not driven, an external pullup or pulldown resistor is required. IOVDD 12 P Interface supply. Supply voltage for digital input and output circuitry. This voltage sets the logical thresholds for the digital interfaces. NC 23 — Must be left unconnected. POL_SEL/ AIN1 16 DI/AI ADC input voltage if SPECIAL_CFG.AIN1_ENB bit is set to 1. The input range is 0 V to 2 × VREF. Otherwise, this pin acts as ALMV_POL, which sets the polarity of the VOUT alarm voltage. PVDD 17 P Power supply for the internal low-dropout regulator (LDO), ADC input and VOUT DAC output. REF_EN 5 DI Internal VREF enable input. A logic high on this pin enables the internal VREF and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal VREF and the external 1.25-V reference is required at the VREFIO pin. REF_GND 20 P GND reference for VREFIO pin. RESET 6 DI Reset pin, active low. Logic low on this pin places the device into power-down mode and resets the device. Logic high returns the device to normal operation. Do not leave any digital pins floating. SCLK 7 DI SPI clock. Data are transferred at rates up to 12.5 MHz. SCLK is a Schmitt-Trigger logic input. Connect to GND or logic low if not used. Do not leave any digital pins floating. SCLR 4 DI DAC clear input pin in SPI mode. A logic high on this pin forces the DAC output into a CLEAR state. Connect to GND in UBM. Do not leave any digital input pins floating. VDD 13 P/AO Internal low voltage LDO output. When 2.7 V to 5.5 V on PVDD pin is provided, the internal LDO is enabled. Connect a 1-μF to 10-μF capacitor on this pin. VOUT 18 AO DAC output voltage. VREFIO 19 AI/AO When the internal VREF is enabled by REF_EN pin, this pin outputs the internal VREF voltage. In this case, a load capacitance of 70 nF to 130 nF is required for stability. When disabled, this pin is the external 1.25‑V reference input. (1) AI = Analog input, AO = Analog output, DI = Digital input, DO = Digital output, P = Power. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage PVDD, IOVDD to GND –0.3 5.5 V VDD to GND –0.3 1.98 V AIN0, POL_SEL/AIN1, VOUT to GND –0.3 PVDD + 0.3 V Digital Input/Output to GND –0.3 IOVDD + 0.3 V VREFIO to GND –0.3 VDD + 0.3 V REF_GND to GND –0.3 0.3 V Input current into any pin –10 10 mA TJ Junction temperature –55 150 Tstg Storage temperature –65 150 (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±500 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT PVDD to GND 2.7 5.5 V VDD to GND 1.71 1.89 V IOVDD to GND 1.71 5.5 V VREFIO to GND, external VREF 1.2 1.25 1.3 V TA Ambient temperature Specified –40 125 °C Operating –55 125 °C

6.4 Thermal Information

THERMAL METRIC(1) AFEx8201 UNITRRU (UQFN)

24 PINS

RθJA Junction-to-ambient thermal resistance 103.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 84.4 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance N/A °C/W RθJB Junction-to-board thermal resistance 69.5 °C/W ΨJT Junction-to-top characterization parameter 0.4 °C/W ΨJB Junction-to-board characterization parameter 68.4 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: AFE78201 AFE88201

6.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT DAC STATIC PERFORMANCE Resolution AFE88201 16 Bits AFE78201 14 INL Integral nonlinearity(1) AFE88201, TA = –40°C to +125°C –12 12 LSBAFE88201, TA = –40°C to +85°C –4 4 AFE78201 –3 3 DNL Differential nonlinearity(1) –1 1 LSB TUE Total unadjusted error(1) %FSRTA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Zero code error, no load TA = –40°C to +125°C 1 mVTA = –40°C to +85°C 1 TA = 25°C 0.5 Zero code error temperature coefficient ±3 ppm/°C Offset error(1) %FSRTA = –40°C to +85°C –0.05 0.05 TA = 25°C –0.03 0.03 Offset error temperature coefficient (1) ±3 ppm/°C Gain error(1) %FSRTA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Gain error temperature coefficient(1) ±3 ppm FSR/°C Full-scale error %FSRTA = –40°C to +85°C –0.08 0.08 TA = 25°C –0.05 0.05 Full-scale error temperature coefficient ±3 ppm FSR/°C VOUT DAC DYNAMIC PERFORMANCE ts Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB 65 µs 10-mV step settling to ±2 LSB 30 Slew rate Fullscale transition measured from 10% to 90% 30 mV/µs Vn Output noise 0.1 Hz to 10 Hz, DAC at midscale 0.25 LSBpp 100-kHz bandwidth, DAC at midscale 32 µVrms Vn Output noise density Measured at 1 kHz, DAC at midscale, PVDD = 3 V 180 nV/√Hz Measured at 1 kHz, DAC at midscale, PVDD = 5 V 260 Power supply rejection ratio (ac) 200-mV 50-Hz to 60-Hz sine wave superimposed on power supply voltage, DAC at midscale. 85 dB Code change glitch impulse Midcode ±1 LSB (including feedthrough) 4.5 nV-s Code change glitch magnitude Midcode ±1 LSB (including feedthrough), PVDD = 5 V 1.5 mV Digital feedthrough At SCLK = 1 MHz, DAC output at midscale 1 nV-s AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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6.5 Electrical Characteristics (continued)

all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT DAC OUTPUT CHARACTERISTICS Output voltage 0 2.5 V VOUT alarm output high 2.35 2.5 2.65 V VOUT alarm output low 0.285 0.3 0.315 V RLOAD Resistive load(2) 10 kΩ CLOAD Capacitive load(2) 100 pF Load regulation DAC at midscale, –1 mA ≤ IOUT ≤ +1 mA 10 µV/mA Short-circuit current Full scale output shorted to GND 5 mA Zero output shorted to VDD 5 Output voltage headroom to PVDD DAC at full code, IOUT = 1 mA (sourcing) 200 mV ZO Large signal dc output impedance To GND, DAC at code 0 60 Ω DAC at midscale 10 mΩ DAC at code 65535 10 Output Hi-Z 500 kΩ Power supply rejection ratio (dc) DAC at midscale 0.1 mV/V Output voltage drift vs time, ideal VREF TA = 35°C, VOUT = midscale, 1000 hours ±5 ppmFSR DIAGNOSTIC ADC Input voltage 0 2.5 V Resolution 12 Bits DNL Differential nonlinearity Specified 12-bit monotonic –1 ±0.2 1 LSB INL Integral nonlinearity –4 ±1 4 LSB Offset error After calibration –10 ±1.6 10 LSB Gain error –0.8 ±0.13 0.8 %FSR Noise ±4 LSB Input capacitance 6 pF Input bias current ADC not converting –50 50 nA Acquisition time 52 µs Conversion time 210 µs Conversion rate 3.84 kSPS Temperature sensor accuracy 5 °C INTERNAL OSCILLATOR Frequency TA = –40°C to +125°C 1.2165 1.2288 1.2411 MHz www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: AFE78201 AFE88201

all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOLTAGE REFERENCE INPUT ZVREFIO Reference input impedance (VREFIO) 125 kΩ CVREFIO Reference input capacitance (VREFIO) 100 pF VOLTAGE REFERENCE OUTPUT Output (initial accuracy)(3) TA = 25°C 1.248 1.25 1.252 V Output drift(3) TA = –40°C to +125°C 10 ppm/℃ Output impedance(3) 0.1 Ω Output noise(3) 0.1 Hz to 10 Hz 7.5 µVPP Output noise density(3) Measured at 10 kHz, reference load = 100 nF 200 nV/√Hz Load current(3) Sourcing, 0.1% VREF change from nominal 2.5 mA Sinking, 0.1% VREF change from nominal 0.3 Load regulation(3) Sourcing, 0 mA to 2.5 mA 4 µV/mA COUT Stable output capacitance TA = –40°C to +125°C, ESR from 10 mΩ to 400 mΩ 70 100 130 nF Line regulation(3) 100 µV/V Output voltage drift vs time(3) TA = 35°C, 1000 hours ±100 ppm Thermal hysteresis(3) 1st cycle 500 µV Additional cycles 25 µV VDD VOLTAGE REGULATOR OUTPUT Output voltage 1.71 1.8 1.89 V Output impedance(3) Sourcing, 0.5 mA to 2.5 mA 3 Ω Load current(3) Sourcing, 1% VDD change from nominal 4 mA THERMAL ALARM Alarm trip point 130 °C Warning trip point 85 °C Hysteresis 12 °C Trip point absolute accuracy 5 °C Trip point relative accuracy 2 °C DIGITAL INPUT CHARACTERISTICS VIH High-level input voltage 0.7 V/IOVDD VIL Low-level input voltage 0.3 V/IOVDD Hysteresis voltage 0.05 V/IOVDD Input current –1.56 1.56 µA Pin capacitance Per pin 10 pF DIGITAL OUTPUT CHARACTERISTICS VOH High-level output voltage ISOURCE = 1 mA 0.8 V/IOVDD VOL Low-level output voltage ISINK = 1 mA 0.2 V/IOVDD VOL Open-drain low-level output voltage ISINK = 2 mA 0.3 V Output pin capacitance 10 pF AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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6.6 Timing Requirements

all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2, 2.7 V ≤ PVDD ≤ 5.5 V, VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V and TA = –40°C to +125°C (unless otherwise noted) PARAMETER MIN NOM MAX UNIT SERIAL INTERFACE - WRITE AND READ OPERATION fSCLK Serial clock frequency 12.5 MHz tSCLKHIGH SCLK high time 36 ns tSCLKLOW SCLK low time 36 ns tCSHIGH CS high time 80 ns tCSS CS to SCLK falling edge setup time 30 ns tCSH SCLK falling edge to CS rising edge 30 ns tCSRI CS rising edge to SCLK falling edge ignore 30 ns tCSFI SCLK falling edge ignore to CS falling edge 5 ns tSDIS SDI setup time 5 ns tSDIH SDI hold time 5 ns tSDOZD CS falling edge to SDO tri-state condition to driven 40 ns tSDODZ CS rising edge to SDO driven to tri-state condition 40 ns tSDODLY SCLK to SDO output delay 40 ns UART tBAUDUART Baud rate = 9600 ±1% 104 µs DIGITAL LOGIC tDACWAIT Sequential DAC update wait time 2.1 µs tPOR POR reset delay 100 µs tRESET RESET pulse duration 100 ns tRESETWAIT Wait time after RESET pulse 10 µs tPULSE_GPIO GPIO input pulse duration 10 ns AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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6.7 Timing Diagrams

Don’t Care Valid DataHi-Z SDO FSDO = 0 SDI SCLK SPI Mode 1 SDO FSDO = 1 CS Discontinuous Clock Mode Continuous Clock Mode Bit N Bit 0 Bit N Bit 0 tSDODZ Bit 0Bit N tSDODLY tSDODLY tSDOZD Bit 1 Bit 1 Bit 1 tSDIS tSDIH tCSS tCSH tCSRI tCSHIGH tCSFI N = 31 for 32-bit frame with CRC N = 23 for 24-bit frame without CRC SCLK SPI Mode 2 Figure 6-1. SPI Timing S = Start bit, Par = Parity bit, P = Stop bit UART Communication S UART Break Character tBAUD D1D0 D3 D2 D5 D4 D7 D6S Par PD1D0 D3 D2 D5 D4 D7 D6S Par P 11 • tBAUD Figure 6-2. UBM Timing www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: AFE78201 AFE88201

6.8 Typical Characteristics: VOUT DAC

at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Figure 6-3. DAC DNL vs Digital Input Code Figure 6-4. MIN and MAX DAC DNL Range vs Temperature Figure 6-5. DAC INL vs Digital Input Code Figure 6-6. MIN and MAX DAC INL Range vs Temperature Figure 6-7. DAC TUE vs Digital Input Code Figure 6-8. MIN and MAX DAC TUE vs Temperature AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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6.8 Typical Characteristics: VOUT DAC (continued)

at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Figure 6-9. Zero-code Impedance Figure 6-10. DAC Footroom Over Temperature and Load DAC at midcode Figure 6-11. DAC Source and Sink Current Capability Ideal reference Figure 6-12. DAC Output Voltage Long-Term Stability PVDD = 5.5 V Figure 6-13. DAC Glitch Impulse Rising Edge PVDD = 5.5 V Figure 6-14. DAC Glitch Impulse Falling Edge www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: AFE78201 AFE88201

at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Figure 6-15. DAC Gain Error vs Temperature Figure 6-16. DAC Offset Error vs Temperature Figure 6-17. DAC Full Scale Error vs Temperature Figure 6-18. DAC Zero Scale Error vs Temperature DAC at midcode PVDD = 5.5 V Figure 6-19. DAC Output Noise, 0.1 Hz to 10 Hz DAC at midcode PVDD = 5.5 V Figure 6-20. DAC Output Noise Density vs Frequency AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Figure 6-21. DAC Rising Settling Time Figure 6-22. DAC Falling Settling Time Figure 6-23. DAC Settling Time With Linear Slew Rate Control Figure 6-24. DAC Settling Time With Sinusoidal Slew Rate Control Figure 6-25. DAC RESET Response Figure 6-26. DAC Supply Power On, PVDD = 2.7 V www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: AFE78201 AFE88201

at TA = 25°C, PVDD = 2.7 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Internal Reference Figure 6-27. DAC AC PSRR vs Frequency AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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6.9 Typical Characteristics: ADC

at TA = 25°C, PVDD = 3.3 V, IOVDD = 1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Figure 6-28. ADC DNL vs Digital Input Code Figure 6-29. ADC INL vs Digital Input Code Figure 6-30. ADC DNL Range vs Temperature Figure 6-31. ADC INL Range vs Temperature Figure 6-32. ADC Offset Error vs Temperature Figure 6-33. ADC Gain Error vs Temperature www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: AFE78201 AFE88201

6.10 Typical Characteristics: Reference

at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Pre-soldered 30 units Figure 6-34. Reference Voltage Temperature Drift Post-soldered 30 units Figure 6-35. Reference Voltage Temperature Drift –40°C to +85°C cycles, 60 minutes per cycle, 30 units Figure 6-36. Multiple Temperature Cycle Hysteresis –40°C to +85°C cycles, 60 minutes per cycle Figure 6-37. Multiple Temperature Cycle Hysteresis Two minutes after 25°C to 85°C temperature step, 30 units Figure 6-38. Ambient Temperature Change Settling 30 units Figure 6-39. Reference Voltage Long-Term Stability AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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6.10 Typical Characteristics: Reference (continued)

at TA = 25°C, PVDD = IOVDD = 3.3 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Figure 6-40. Reference Output Noise, 0.1 Hz to 10 Hz Figure 6-41. Reference AC PSRR vs frequency Figure 6-42. Reference Source and Sink Current Capability Figure 6-43. Initial Accuracy Distribution www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: AFE78201 AFE88201

6.11 Typical Characteristics: Power Supply

at TA = 25°C, PVDD = IOVDD = 3.3 V, internal VREFIO, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or GND (unless otherwise noted) Figure 6-44. PVDD Supply Current vs Temperature Figure 6-45. IOVDD Supply Current vs Temperature Figure 6-46. VDD Voltage vs Load Current AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7 Detailed Description

7.1 Overview

The AFEx8201 feature a 16-bit ( AFE88201) or 14 ‑bit (AFE78201) string DAC with voltage output buffer. Both devices have a buffered voltage output and are designed for use in three ‑wire or four-wire sensor transmitters or analog output modules. The DAC has calibration registers for setting gain and offset values for adjusting the DAC outputs. The DAC also has different output slewing modes that allow for a programmable linear slew and a sinusoidal shaped output slew. The AFEx8201 also feature a 12 ‑bit SAR ADC that can be multiplexed to measure different inputs, including external nodes and internal nodes for diagnostic measurements on the device. The ADC is capable of making direct-mode measurements with on-demand conversions or auto-mode measurements through continuous conversions using a channel sequencer with a multiplexer. The devices have optional alarm configurations with fault detection and alarm actions. Device communication and programming are done through an SPI or through the UART break mode (UBM). With the SPI, a cyclic redundancy check (CRC) is implemented by default, which can be disabled. Additionally, communications can be monitored with a watchdog timer (WDT) that alerts the user if the device becomes unresponsive to periodic communication. The AFEx8201 feature a 1.25-V, onboard precision voltage reference, and an integrated precision oscillator. Throughout this data sheet, register and bit names are combined with a period to use the following format: <register_name>.<bit_name>. For example, the CLR bit in the DAC_CFG register is labeled DAC_CFG.CLR.

7.2 Functional Block Diagram

POL_SEL/AIN1 16-/14-Bit DAC VOUT Alarm Diagnostics Alarm Responses User Calibration Slew-Rate Control DAC Data Register Watchdog Timer CRC Frame Error Check ALARM SPI Interface UART Interface Control Logic PVDDVDD GND Internal Reference VREFIO REF_EN IOVDD Internal Oscillator IRQ (UARTOUT or SDO) Output Buffer Range Setting 2.7-V Comparator 1.8-V LDOPower- On Reset OTPIOVDD PVDD VDD VREF PVDD Bias Generator 0.6 V ZTAT ZTAT REF_GND NC GPIO0/CLK_OUT SCLK SCLR GPIO1 RESET GPIO5/SDI GPIO4/SDO GPIO3/UARTIN GPIO2/UARTOUT GPIO6/CS PVDD www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: AFE78201 AFE88201

7.3 Feature Description

7.3.1 Digital-to-Analog Converter (DAC) Overview

The AFEx8201 feature a 16-bit ( AFE88201) or 14 ‑bit ( AFE78201) string DAC followed by an output voltage buffer. Using an external circuit, the device output voltage can be translated to different output voltages and output currents for use in 3 ‑wire or 4-wire sensor transmitters or analog output modules. The DAC is configured to support a 0 ‑V to 2.5 ‑V range of operation. The alarm function is triggered when PVDD exceeds the valid configuration range of 2.7 V to 5.5 V; see also Table 7-5. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.1.1 DAC Resistor String

Figure 7-1 shows that the resistor string structure consists of a series of resistors, each of value R. The code loaded to the DAC determines the node on the string at which the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. The resistor string architecture has inherent monotonicity, voltage output, and low glitch. To Output Amplifier R R R R R Figure 7-1. DAC Resistor String

7.3.1.2 DAC Buffer Amplifier

The VOUT output pin is driven by the DAC output buffer amplifier. The output amplifier default settings are designed to drive capacitive loads as high as 100 pF without oscillation. The output buffer is able to source and sink 1 mA. The device implements short-circuit protection for momentary output shorts to ground and VDD supply. The source and sink short-circuit current thresholds are set to 5 mA. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: AFE78201 AFE88201

7.3.1.3 DAC Transfer Function

The following equation describes the DAC transfer function, which is the relationship between internal signal DAC_CODE and output voltage VOUT: VOUT = DAC_CODE 2N × FSR (1) where

DAC_CODE is an internal signal and the decimal equivalent of the gain and offset calibrated binary code loaded into the DAC_DATA register. DAC_CODE range = 0 to 2N – 1.
N = DAC_CODE resolution in bits (16 for the AFE88201 and 14 for the AFE78201).
FSR = VOUT full-scale range = 2.5 V.

7.3.1.4 DAC Gain and Offset Calibration

The AFEx8201 provide DAC gain and offset calibration capability to correct for end-point errors present in the system. Implement the gain and offset calibration using two registers, DAC_GAIN.GAIN and DAC_OFFSET.OFFSET. Update DAC_DATA register after gain or offset codes are changed for the new values to take effect. The DAC_GAIN can be programmed from 0.5 to 1.499985 using Equation 2. DAC_GAIN = 1 2 + GAIN 2N (2) where

N = DAC_GAIN resolution in bits: 16 for the AFE88201 and 14 for the AFE78201.
GAIN is the decimal value of the DAC_GAIN register setting.
GAIN data are left justified; the last two LSBs in the DAC_GAIN register are ignored for the AFE78201. The example DAC_GAIN settings for the AFE88201 are shown in Table 7-1. Table 7-1. DAC_GAIN Setting vs GAIN Code DAC_GAIN GAIN (HEX) 0.5 0x0000 1.0 0x8000 1.499985 0xFFFF AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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The DAC_OFFSET is stored in the DAC_OFFSET register using 2's-complement encoding. The DAC_OFFSET value can be programmed from –2(N–1) to 2(N–1) – 1 using Equation 3. DAC_OFFSET = − OFFSETMSB × 2 N − 1 + ∑ i = 0 N − 2 OFFSETi × 2 i (3) where

N = DAC_OFFSET resolution in bits: 16 for the AFE88201 and 14 for the AFE78201.
OFFSETMSB = MSB bit of the DAC_OFFSET register.
OFFSETi = The rest of the bits of the DAC_OFFSET register.
i = Position of the bit in the DAC_OFFSET register.
OFFSET data are left justified; the last two LSBs in the DAC_OFFSET register are ignored for the device. The most significant bit determines the sign of the number and is called the sign bit. The sign bit has the weight of –2(N–1) as shown in Equation 3. The example DAC_OFFSET settings for the AFE88201 are shown in Table 7-2. Table 7-2. DAC_OFFSET Setting vs OFFSET Code DAC_OFFSET OFFSET (HEX) 32767 0x7FFF 1 0x0001 0 0x0000 –1 0xFFFF –2 0xFFFE –32768 0x8000 The following transfer function is applied to the DAC_DATA.DATA based on the DAC_GAIN and DAC_OFFSET values: DAC_CODE = DATA × DAC_GAIN + DAC_OFFSET (4) where
DAC_CODE is the internal signal applied to the DAC.
DATA is the decimal value of the DAC_DATA register.
DAC_GAIN and DAC_OFFSET are the user calibration settings.
DATA data are left justified; the last two LSBs in the DAC_DATA register are ignored for the AFE78201. Substituting DAC_GAIN and DAC_OFFSET in Equation 4 with Equation 2 and Equation 3 results in: DAC_CODE = DATA × 1 2 + GAIN 2N − OFFSETMSB × 2 N − 1 + ∑ i = 0 N − 2 OFFSETi × 2 i (5) The multiplier is implemented using truncation instead of rounding. This truncation can cause a difference of one LSB if rounding is expected. Figure 7-2 shows the DAC calibration path. DAC_DATA Register 01h DAC_GAIN Register 04h DAC_OFFSET Register 05h DAC_CODE Gain = ½ + DAC_GAIN / 216 < 8000h: Gain < 1 = 8000h: Gain = 1 > 8000h: Gain > 1 Offset in 2’s-complement < 0000h: Negative offset 0000h: No offset > 0000h: Positive offset Figure 7-2. DAC Calibration Path www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: AFE78201 AFE88201

7.3.1.5 Programmable Slew Rate

The slew rate feature controls the rate at which the output voltage or current changes. This feature is disabled by default and is enabled by writing a logic 1 to the DAC_CFG.SR_EN bit. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by DAC_CFG.SR_STEP[2:0] and DAC_CFG.SR_CLK[2:0]. SR_CLK defines the rate at which the digital slew updates. SR_STEP defines the amount by which the output value changes at each update. Section 7.6.1 shows different settings for SR_STEP and SR_CLK. The time required for the output to slew is expressed as Equation 6: Slew Time = Delta Code Change Slew Step × Slew Clock Rate (6) where

Slew Time is expressed in seconds
Slew Step is controlled by DAC_CFG.SR_STEP
Slew Clock Rate is controlled by DAC_CFG.SR_CLK When the slew-rate control feature is enabled, the output changes at the programmed slew rate. This configuration results in a staircase formation at the output. If the clear code is asserted (see Section 7.3.1.6), the output slews to the DAC_CLR_CODE value at the programmed slew rate. When new DAC data are written, the output starts slewing to the new value at the slew rate determined by the current DAC code and the new DAC data. Two slew-rate control modes are available: linear (default) and sinusoidal. Figure 7-3 and Figure 7-4 show the typical rising and falling DAC output waveforms, respectively. 4 mA (0x0BA3) to 24 mA (0xF45D) measured on a 40-Ω shunt Figure 7-3. Linear Slew Rate: Rising 24 mA (0xF45D) to 4 mA (0x0BA3) measured on 40-Ω shunt Figure 7-4. Linear Slew Rate: Falling AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.1.6 DAC Register Structure and CLEAR State

The AFE88201 DAC has a 16-bit voltage output, and the AFE78201 DAC has a 14-bit voltage output. The output range is 0 V to 2.5 V. The AFEx8201 provide the option to quickly set the DAC output to the value set in the DAC_CLR_CODE register without writing to the DAC_DATA register, referred to as the CLEAR state. For register details, see Table 7-16. Transitioning from the DAC_DATA to the DAC_CLR_CODE is synchronous to the clock. If slew mode is enabled, the output slews during the transition. Figure 7-7 shows the full AFEx8201 DAC_DATA signal path. The devices synchronize the DAC_DATA code to the internal clock, causing up to 2.5 internal clock cycles of latency (2 μs) with respect to the rising edge of CS or the end of a UBM command. Update DAC_GAIN and DAC_OFFSET values when DAC_CFG.SR_EN = 0 to avoid an IRQ pulse generated by SR_BUSY. Set the DAC to CLEAR state either by: 1. Setting DAC_CFG.CLR. 2. Configuring the DAC to transition to the CLEAR state in response to an alarm condition. 3. Using the SDI pin in UBM or the SCLR pin in SPI mode as the CLEAR state input pin. Method 1 is a direct command to the AFEx8201 to set the DAC to CLEAR state. Set the DAC_CFG.CLR bit to 1h to set the DAC to CLEAR state. Method 2 is controlled by settings of ALARM_ACT register. For details of conditions and other masks required to use this method, see Table 7-25 and Section 7.3.3.2. Method 3 supports setting the DAC to CLEAR state without writing to the AFEx8201. This pin-based DAC CLEAR state function is available in SPI mode on the SCLR pin, or in UBM on the SDI pin. The SCLR pin must be tied to GND in UBM. For details of connection options based on communication modes and pins used in each mode, see Section 7.5.1. Set the appropriate pin high to drive the DAC to CLEAR state. DAC_DATA Register 01h DAC_CLR_CODE Register 06h DAC_CFG.CLR Register 03h (Method 1) ALARM_ACT Register 10h (Method 2) Clear Input Pin (Method 3) DAC_GAIN Register 04h DAC_OFFSET Register 05h DAC_CODE DAC_CFG.SR_MODE DAC_CFG.SR_STEP DAC_CFG.SR_CLK Register 03h DAC_OUT Slew Rate: Mode, Step Size, and Clock Timing DAC_CFG.SR_EN Register 03h Slew Enable Figure 7-7. DAC Data Path AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.2 Analog-to-Digital Converter (ADC) Overview

The AFEx8201 feature a monitoring system centered on a 12-bit successive approximation register (SAR) ADC and a highly flexible analog multiplexer. The monitoring system is capable of sensing up to two external inputs, as well as several internal device signals. The ADC uses the VREFIO pin voltage as a reference. The ADC timing signals are derived from an on-chip oscillator. The conversion results are accessed through the device serial interface.

7.3.2.1 ADC Operation

The device ADC supports direct-mode and auto-mode conversions. Both conversion modes use a custom channel sequencer to determine which of the input channels are converted by the ADC. The sequence order is fixed. The user selects the start channel and stop channel of the conversion sequence. The conversion method and channel sequence are specified in the ADC Configuration registers. The default conversion method is auto-mode. Figure 7-8 shows the ADC conversion sequence. START Set ADC_CFG.BUF_PD = 0, ADC_CFG.DIRECT_MODE = 0 or 1 TRIGGER.ADC =1? Yes No Set ADC mux to ADC_INDEX_CFG. START Convert ADC ADC idle state Increment ADC custom channel sequencer ADC_CFG. DIRECT_MODE =1? TRIGGER_ADC = 0? Yes No No No Yes ADC_INDEX.STOP (last conversion Completed)? Yes Figure 7-8. ADC Conversion Sequence www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: AFE78201 AFE88201

To use the ADC, first enable the ADC buffer by setting ADC_CFG.BUF_PD = 0. Then wait at least 210 μs before setting the trigger using the TRIGGER.ADC bit. An internal delay is forced if the trigger signal is sent before the timer has expired. Make sure the ADC is not converting before setting the ADC_CFG.BUF_PD = 1. If ADC_CFG.BUF_PD is set to 1 while the ADC is still converting, the internal timer delays this command. When the timer expires, the enable signal for the ADC is cleared, and the current conversion finishes before powering down the ADC and the ADC Buffer. A trigger signal must occur for the ADC to exit the idle state. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode conversion, the selected ADC input channels are converted on demand by issuing an ADC trigger signal. After the last enabled channel is converted, the ADC enters the idle state and waits for a new trigger. Read the results of the ADC conversion through the register map. Direct-mode conversion is typically used to gather the ADC data of any of the data channels. In direct-mode, use the ADC_BUSY bit to determine when a direct-mode conversion is complete and the ADC has returned to the idle state. Direct mode is set by writing ADC_CFG.DIRECT_MODE = 1. In auto-mode conversion, the selected ADC input channels are converted continuously. The conversion cycle is initiated by issuing an ADC trigger. Upon completion of the first conversion sequence, another sequence is automatically started. Conversion of the selected channels occurs repeatedly until the auto-mode conversion is stopped by clearing the ADC trigger signal. Auto-mode conversion is not typically used to gather the ADC data. Instead, auto-mode conversions are used in combination with upper and lower ADC data thresholds to detect when the data has exceeded the programmable out-of-range alarm thresholds. Auto mode is set by writing ADC_CFG.DIRECT_MODE = 0. Regardless of the selected conversion method, update the ADC configuration register only while the ADC is in the idle state. Do not change the ADC configuration bits while the ADC is converting channels. Before changing configuration bits, disable the ADC and verify that GEN_STATUS.ADC_BUSY = 0. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.2.2 ADC Custom Channel Sequencer

The device uses a custom channel sequencer to control the multiplexer of the ADC. The ADC sequencer allows the user to specify which channels are converted. The sequencer consists of 16 indexed slots with programmable start and stop index fields to configure the start and stop conversion points. In direct-mode conversion, the ADC converts from the start index to the stop index once and then stops. In auto-mode conversion, the ADC converts from the start to stop index repeatedly until the ADC is stopped. Figure 7-9 shows the indexed custom channel sequence slots available in the device. ADC OFFSET AIN0 AIN1 TEMP SD MUX GND GND VREF PVDD VDD ZTAT VOUT 4 - 8 ADC_INDEX_CFG.START ADC_INDEX_CFG.STOP Register 09h Custom Channel Sequencer (CCS) Pointer Self Diagnostic Multiplexer (SD MUX) Figure 7-9. ADC MUX Control Table 7-3 lists the ADC input channel assignments for the sequencer. Table 7-3. Indexed Custom Channel Sequence CCS POINTER CHANNEL CONV_RATE RANGE

0 OFFSET 2560 Hz VREF

1 AIN0 Programmable Programmable

2 AIN1 Programmable Programmable

3 TEMP 2560 Hz VREF

4 SD0 (VREF) 2560 Hz VREF

5 SD1 (PVDD) 2560 Hz VREF

6 SD2 (VDD) 2560 Hz VREF

7 SD3 (ZTAT) 2560 Hz VREF

8 SD4 (VOUT) 2560 Hz 2 × VREF

Use the ADC_INDEX_CFG register to select the channels. The order of the channels is fixed and shown in Table 7-3. Then, use ADC_INDEX_CFG.START and ADC_INDEX_CFG.STOP to select the range of indices to convert. If these two values are the same, then the ADC only converts a single channel. If the START and STOP values are different, then the ADC cycles through the corresponding indices. By default, all channels are configured to be converted; START = 0 and STOP = 8. If the AIN1 channel is not configured as an ADC input, then the result for this channel is 0x000. The minimum time for a conversion is still allotted to AIN1 if the channel is within the START and STOP range. If START is configured to be greater than STOP, then the device interprets the conversion sequence as if START = STOP. In direct mode, each selected channel in the ADC_INDEX_CFG register is converted once per TRIGGER.ADC command. In auto mode, each channel selected in the ADC_INDEX_CFG register is converted once; after the last channel, the loop is repeated as long as the ADC is enabled. In auto mode, writing to TRIGGER.ADC = 1 starts the conversions. Writing TRIGGER.ADC = 0 disables the ADC after the current channel being converted finishes. In direct mode, writing TRIGGER.ADC = 1 starts the sequence. When the sequence ends, then TRIGGER.ADC is self-cleared. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: AFE78201 AFE88201

A minimum of 20 clock cycles is required to perform one conversion. The ADC clock is derived from the internal oscillator and divided by 16, which gives an ADC clock frequency of 1.2288 MHz / 16 = 76.8 kHz, for a clock period = 13.02 μs. Each of the internal nodes has a fixed conversion rate. Pins AIN0 and AIN1 have programmable conversion rates (see also the ADC_CFG register). Pins AIN0 and AIN1 also have a configurable range. The input range can be either 0 V to 1.25 V or 0 V to 2.5 V, depending on the ADC_CFG.RANGE bit. If any ADC configuration bits are changed, the following sequence is recommended: 1. Disable the ADC 2. Wait for ADC_BUSY to go low 3. Change the configuration 4. Restart the conversions ADC_BUSY can be monitored in the GEN_STATUS register. If the ADC is configured for direct mode (ADC_CFG.DIRECT_MODE = 1), then after setting the desired channels to convert, write a 1 to TRIGGER.ADC. This bit is self-cleared when the sequence is finished converting. This command converts all the selected channels once. To initiate another conversion of the channels, send another TRIGGER.ADC command.

7.3.2.3 ADC Synchronization

The trigger signal must be generated for the ADC to exit the idle state and start conversions. The ADC trigger is generated through the TRIGGER.ADC bit. The ADC data registers have the latest available data. Accessing the data registers does not interfere with the conversion process, and thus provides continuous ADC operation. In direct-mode, use the GEN_STATUS.ADC_BUSY bit to determine when a direct-mode conversion is complete, and the ADC has returned to the idle state. Similarly, monitor the TRIGGER.ADC bit to see if the ADC has returned to the idle state.

7.3.2.4 ADC Offset Calibration

Channel 0 of the CCS pointer is named OFFSET. The OFFSET channel is used to calibrate and improve the ADC offset performance. Convert the OFFSET channel, and use the result as a calibration for the ADC offset in subsequent measurements. This ADC channel samples VREF / 2 and compares this result against 7FFh as a measure of the ADC offset. The data rate for the ADC measuring this channel is 2560 Hz. The ADC conversion for the OFFSET channel is subtracted from 7FFh and the resulting value is stored in ADC_OFFSET (28h). The offset can be positive or negative; therefore, the value is stored in 2’s complement notation. With the subtraction from 7FFh, ADC_OFFSET is the negative of the offset. This value is subtracted from conversions of the ADC by default. For direct measurements of the ADC, set ADC_BYP.OFST_BYP_EN to 1 to enable the offset bypass; see Section 7.3.2.8. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.2.5 External Monitoring Inputs

The AFEx8201 have two analog inputs for external voltage sensing. Channels 1 and 2 for the CCS pointer are for external monitoring inputs that can be measured by pins AIN0 and AIN1, respectively. The input range for the analog inputs is configurable to either 0 V to 1.25 V or 0 V to 2.5 V. The analog inputs conversion values are stored in straight binary format in the ADC registers. The ADC resolution can be computed by Equation 7:

1 L SB =

212 (7) where Figure 7-10 and Table 7-4 detail the transfer characteristics. NFSC+1 PFSC MC + 1 MC ADC Code (Hex) VINNFSC

1 LSB (VRANGE ±1 LSB)(VRANGE/2 + 1 LSB)VRANGE/2

Figure 7-10. ADC Transfer Characteristics Table 7-4. Transfer Characteristics INPUT VOLTAGE CODE DESCRIPTION IDEAL OUTPUT CODE ≤1 LSB NFSC Negative full-scale code 000

1 LSB to 2 LSB NFSC + 1 Negative full-scale code plus 1 001

(VRANGE / 2) to (VRANGE / 2) + 1 LSB MC Midcode 800 (VRANGE / 2) + 1 LSB to (VRANGE / 2) + 2 LSB MC + 1 Midcode plus 1 801 ≥ VRANGE – 1 LSB PFSC Positive full-scale code FFF For these external monitoring inputs, the ADC is configurable for both data rate and voltage range. The data rate is set to either 640 Hz, 1280 Hz, 2560 Hz, or 3840 Hz with the ADC_CFG.CONV_RATE bits. The range of the ADC measurement is set with the ADC_CFG.AIN_RANGE bit. The ADC range is 2 × VREF when the bit = 0; the ADC range is VREF when the bit = 1. When the ADC conversion is completed for AIN0 and AIN1, the resulting ADC data are stored in the ADC_AIN0.DATA and ADC_AIN1.DATA bits at 24h and 25h of the register map. If the external monitoring inputs are not used, connect the AIN0 and AIN1 pins to GND through a 1-kΩ resistor. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: AFE78201 AFE88201

7.3.2.6 Temperature Sensor

Channel 3 of the CCS is used to measure the die temperature of the device. The ADC measures an internal temperature sensor that measures a voltage complementary to the absolute temperature (CTAT). This CTAT voltage has a negative temperature coefficient. The ADC converts this voltage at a data rate of 2560 Hz. When the ADC conversion is completed, the data are found in the ADC_TEMP.DATA bits (address 26h). The relationship between the ambient temperature and the ADC code is shown in Equation 8: ADC Code = 2681 − 11 × T A °C (8)

7.3.2.7 Self-Diagnostic Multiplexer

In addition to the ADC offset, the two external monitoring inputs, and the temperature sensor, the ADC of the AFEx8201 has five other internal inputs to monitor the reference voltage, the power supplies, a static voltage, and the DAC output. These five voltages measurements are part of the self-diagnostic multiplexer (SD0 to SD4) measurements of the ADC, and are reported in the ADC_SD_MUX register at 27h; see also Section 7.6. Channel 4 (SD0) measures the reference voltage of the device. The ADC measures the reference voltage through a resistor divider (divide by two). Be aware that all ADC measurements are a function of the reference; using SD0 to measure the reference is not revealing as a diagnostic measurement. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 5 (SD1) measures the PVDD power supply of the device. The ADC measures the PVDD voltage through a resistor divider (divide by six). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 6 (SD2) measures the VDD power supply of the device. When channel 6 is selected, the ADC measures the VDD voltage through a resistor divider (divide by 2). The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 7 (SD3) is a ZTAT (zero temperature coefficient) voltage. This internal voltage is nominally 0.6 V with a low temperature drift and does not depend on the reference voltage. An ADC measurement of ZTAT voltage can be useful to determine the state of the reference voltage. The data rate for this conversion is 2560 Hz and the range of the ADC is set to VREF. Channel 8 (SD4) measures the VOUT of the DAC. The ADC measures the VOUT voltage through a resistor divider (divide by two). The data rate for this conversion is 2560 Hz and the range of the ADC is set to 2 × VREF. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.2.8 ADC Bypass

To test the offset, modify the ADC data path by programming the bypass data register, ADC_BYP.DATA (2Eh). This read/write register is used in two different ways. First, by setting the ADC_BYP.OFST_BYP_EN to 1, this bypass data register is used as a substitute for the ADC_OFFSET. However, if the ADC_BYP.DATA data must be stored in the ADC_OFFSET register, use the second method. Second, the ADC_BYP.DATA is used to set a known value into the ADC readback register of the channel being converted. Write the desired data into ADC_BYP.DATA, set the ADC_BYP.DATA_BYP_EN bit, and convert the selected channel. When ADC_BYP.DATA_BYP_EN bit is set to 1, the ADC conversion is bypassed, and the value of ADC_BYP.DATA is written into the selected ADC channel readback register. This setting is used to test the alarm settings of the ADC. When the ADC bypass is unused, set the ADC_BYP.DATA to 000h. Figure 7-11 shows the ADC bypass data flow. ADC_BYP.DATA Register 2Eh ADC_OFFSET Register 28h ADC_AIN0 Register 24h ADC_AIN1 Register 25h ADC_TEMP Register 26h ADC_SD_MUX Register 27h ADC_BYP. OFST_BYP_EN Register 2Eh ADC_BYP. DATA_BYP_EN Register 2Eh ADC Data From ADC MUX ADC. ADC_OUT Register 2Dh ADC MUX 07FFh – OFFSET Stored as 2’s Complement CCS Pointer Read and Writeable for Testing Figure 7-11. ADC Bypass Data Flow

7.3.3 Programmable Out-of-Range Alarms

The AFEx8201 are capable of continuously analyzing the supplies, external ADC inputs, DAC output voltage, reference, internal temperature, and other internal signals for normal operation. Normal operation for the conversion results is established through the lower- and upper-threshold registers. When any of the monitored inputs are out of the specified range, the corresponding alarm bit in the alarm status registers is set. The alarm bits in the alarm status registers are latched. The alarm bits are referred to as being latched because the alarm bits remain set until read by software. This design makes sure that out-of-limit events cannot be missed if the software is polling the device periodically. All bits are cleared when reading the alarm status registers, and all bits are reasserted if the out-of limit condition still exists on the next monitoring cycle. When the alarm event is cleared, the DAC is reloaded with the contents of the DAC active registers, which allows the DAC outputs to return to the previous operating point without any additional commands All alarms can be used to generate a hardware interrupt signal on the ALARM pin; see also Section 7.3.3.1. In addition, Section 7.3.3.2 describes how the alarm action can be individually configured for each alarm. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: AFE78201 AFE88201

7.3.3.1 Alarm-Based Interrupts

One or more of the available alarms can be set to activate the ALARM pin. Connect the ALARM pin as an optional hardware interrupt to the host. The host can query the alarm status registers to determine the alarm source upon assertion of the interrupt. Any alarm event activates the pin, as long as the alarm is not masked in the ALARM_STATUS_MASK register. When an alarm event is masked, the occurrence of the event sets the corresponding status bit in the alarm status registers, but does not activate the ALARM pin. Note The ALARM pin output depends on ALARM_STATUS and ALARM_STATUS_MASK register settings, independent of ALARM_ACT register settings.

7.3.3.2 Alarm Action Configuration Register

The AFEx8201 provides an alarm action configuration register: ALARM_ACT, Table 7-25 . Writing to this register selects the device action that automatically occurs for a specific alarm condition. The ALARM_ACT register determines how the main DAC responds to an alarm event from either an ADC conversion on the self-diagnostics channels (AIN0, AIN1, and TEMP), or from a CRC, WDT, VREF, TEMP_HI, or TEMP_LO fault. Only these faults cause a response by the DAC. Any other alarm status events trigger the ALARM pin. There are four options for alarm action. In case different settings are selected for different alarm conditions, the following low-to-high priority is considered when taking action:

0. → No action
1. → DAC CLEAR state
2. → VOUT alarm voltage
3. → VOUT Hi-Z If option 1 is selected when the alarm event occurs, then the DAC is forced to the clear code. This operation is done by controlling the input code to the DAC. If option 2 is selected when the alarm event occurs, then VOUT is forced to the alarm voltage. The alarm voltage is controlled by either pin or register bit. If SPECIAL_CFG.AIN1_ENB = 0, then the AIN1 pin controls alarm polarity. Also, register bit SPECIAL_CFG.ALMV_POL can be used. If either of these signals = 1, then the alarm voltage is high; otherwise, the alarm voltage is low. The SPECIAL_CFG register is only reset with POR, so the user setting remains intact through hardware or software resets. If option 3 is selected when the alarm event occurs, then the VOUT buffer is put into Hi-Z. If multiple events occur, then the highest setting takes precedence. Option 3 has the highest priority. To disable action response to an alarm, set the corresponding bits in ALARM_ACT to 0h. Alarm action response is cleared either when the triggered condition bit resets (behavior depends on whether the fault bit in ALARM_STATUS is sticky or not), or by changing the action configuration to 0h. Note An alarm action, as configured, executes when an alarm occurs depending on ALARM_STATUS and ALARM_ACT registers. Action response is independent of ALARM_STATUS_MASK settings. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.3.3 Alarm Voltage Generator

Figure 7-12 shows that the alarm voltage is generated independently from the DAC output voltage. The alarm polarity control logic selects the output level of the alarm voltage generator. The alarm action control logic selects between the DAC output and alarm voltage generator output voltages. The alarm action control logic also controls the output buffer Hi-Z switch. POL_SEL/ AIN1 VDD GND Alarm Voltage Generator OUT = 0.15 V OUT = 1.25 V DAC_DATA DAC ALARM_ACT Register 10h VOUT G G = 2 Hi-Z ALMV_POL 1DAC_CLR_CODE DAC_CODE RESET Figure 7-12. Alarm Voltage Generator Architecture During normal operation, the expected VOUT voltage depends on the DAC_CODE. The ADC thresholds for the SD4 (VOUT) diagnostic channel are set around the programmed DAC_CODE. During the alarm condition, if the alarm action changes the VOUT voltage to the alarm voltage, or switches the VOUT buffer into Hi-Z mode, the VOUT voltage no longer depends on the DAC_CODE. In this case, the SD4 (VOUT) diagnostic channel also reports the alarm. To clear this alarm, as long as all other alarm conditions are cleared, set the alarm action to either no action or to the DAC clear code. Applying either alarm action sets the VOUT voltage within the expected ADC thresholds and clears the alarm after the next ADC measurement of the SD4 (VOUT) channel. Give special consideration to the alarm logic during the transient events. When the new DAC_CODE goes beyond the SD4 (VOUT) alarm thresholds with the ADC monitoring the SD4 (VOUT) input in auto mode, the ADC conversion can occur while VOUT settles to a new value. This conversion can trigger a false alarm. There are two ways to prevent this false alarm: 1. Use direct mode and allow VOUT to settle before triggering the next ADC conversion. 2. Set ADC_CFG.FLT_CNT > 0. With this configuration, a single error in SD4 or any other measurement does not cause an alarm condition to be asserted.

7.3.3.4 Temperature Sensor Alarm Function

The AFEx8201 continuously monitor the internal die temperature. In addition to the ADC measurement, the temperature sensor triggers a comparator to show a thermal warning and a thermal error. A thermal warning alarm is set when the temperature exceeds 85°C. Additionally, a thermal error alarm is set when the die temperature exceeds 130°C. The thermal warning and thermal error alarms can be configured to set the ALARM pin and are indicated in the ALARM_STATUS register. These alarms can be masked with the ALARM_MASK register and also be configured to control the DAC output with the ALARM_ACT register.

7.3.3.5 Internal Reference Alarm Function

The devices provide out-of-range detection for the reference voltage. When the reference voltage exceeds ±5% of the nominal value, the reference alarm flag (VREF_FLT bit) is set. Make sure that a reference alarm condition has not been issued by the device before powering up the DAC output. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: AFE78201 AFE88201

7.3.3.6 ADC Alarm Function

The AFEx8201 provide independent out-of-range detection for each of the ADC inputs. Figure 7-13 shows the out-of-range detection block. When the measurement is out of range, the corresponding alarm bit is set to flag the out-of-range condition. AIN0_THRESHOLD [15:8] AIN1_THRESHOLD [15:8] TEMP_THRESHOLD [15:8] Register 12h, 13h, 14h Upper threshold AIN0_THRESHOLD [7:0] AIN1_THRESHOLD [7:0] TEMP_THRESHOLD [7:0] Register 12h, 13h, 14h Lower threshold ADC conversion value ALARM_STATUS ADC_AIN0_FLT, ADC_AIN1_FLT, ADC_TMP_FLT Register 20h [3],[4],[2] Figure 7-13. ADC Out-of-Range Alarm An alarm event is only registered when the monitored signal is out of range for N number of consecutive conversions, where N is configured in the ADC_CFG.FLT_CNT false alarm register settings. If the monitored signal returns to the normal range before N consecutive conversions, an alarm event is not issued. If an ADC input signal is out of range and the alarm is enabled, then the corresponding alarm bit is set to 1. However, the alarm condition is cleared only when the conversion result returns to a value less than the high-limit register setting and greater than the low-limit register setting by the number of codes specified by the hysteresis setting (see Figure 7-14). The hysteresis is a programmable value between 0 LSB to 127 LSB in the ADC_CFG.HYST register. High Threshold Low Threshold Over High Alarm Below Low Alarm Hysteresis Hysteresis Figure 7-14. ADC Alarm Hysteresis AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.3.3.7 Fault Detection

There are two fields within the ADC_CFG register: FLT_CNT and HYST. These fields are applied to the assertion and deassertion of alarm conditions for all the ADC channels. ADC_CFG.FLT_CNT determines the maximum number of accepted consecutive failures before an alarm condition is reported. For example, if ADC_CFG.FLT_CNT is set for two counts, then three consecutive conversions must be outside of the thresholds to trigger an alarm. Each failure counts towards the FLT_CNT limit even if the failures alternate between high threshold and low threshold. ADC_CFG.HYST sets the hysteresis used by the alarm-detection circuit. After an alarm is triggered, the hysteresis is applied before the alarm condition is released. In the case of the high threshold, the hysteresis is subtracted from the threshold value. In the case of the low threshold limit, the hysteresis is added to the threshold value. Channels AIN0, AIN1, and TEMP have high and low thresholds associated with them. If a conversion value falls outside of these limits (that is, if TEMP < low threshold or TEMP > high threshold), an alarm condition for that channel is set. The alarms are disabled by setting 0x000 for the low threshold and 0xFFF for the high threshold, respectively. These alarms are disabled by default. Because the configuration fields for the thresholds are only eight bits wide, the four LSBs are hardcoded for each threshold. The high thresholds four LSBs are hardcoded to 0xF, and the low thresholds four LSBs are hardcoded to 0x0. All the self diagnostic (SD) channels have fixed thresholds, except SD4, which measures the VOUT of the main DAC. The threshold for SD4 tracks the VOUT with respect to the DAC code. Table 7-5 shows the calculations used to determine the high and low ADC thresholds for each SD channel. The limits in the two right-most columns are determined by the threshold columns to the left and given some margin. The four LSBs are assigned as described previously. Table 7-5. Self Diagnostic (SD) Alarm ADC Thresholds SD ADC INPUT ACCEPTED LOW VALUE ACCEPTED HIGH VALUE LOW THRESHOLD HIGH THRESHOLD ADC LOW (HEX) ADC HIGH (HEX) SD0 VREF/2 VREF/2 – 9% – 25 mV VREF/2 + 9% + 25 mV 0.54375 V 0.70625 V 0x6D0 0x92F SD1 PVDD/6 1.65/6 – 25 mV 6/6 + 25 mV 0.25 V 1.025 V 0x310 0xD3F SD2 VDD/2 1.6/2 – 25 mV 2/2 + 25 mV 0.775 V 1.025 V 0x9C0 0xD3F SD4 VOUT/2 VOUT/2 – 6 mV VOUT/2 + 6 mV VOUT – 12 mV VOUT + 12 mV Expected – 0x040 Expected + 0x040 The alarm threshold for the SD4 input depends on the expected ADC measurement based on the DAC code. Equation 9 shows the expected ADC code for SD4. ADC Expected Code = DAC_CODE[MSB:MSB-11] (9) www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: AFE78201 AFE88201

7.3.4 IRQ

The devices include an interrupt request (IRQ) to communicate the occurrence of a variety of events to the host controller. The IRQ block initiates interrupts that are reported internally in a status register, externally on the IRQ pin if the function is enabled, or on the ALARM pin if the condition is from the ALARM_STATUS register. Figure 7-15 shows the IRQ block diagram. GEN_STATUS Register 21h ALARM_STATUS Register 20h GEN_STATUS_MASK Register 1Eh ALARM_STATUS_MASK Register 1Dh Interrupt Generation Maskable Status Bits D CLK Q Internal Oscillator D CLK Q CONFIG.IRQ_POL Register 02h CONFIG.IRQ_LVL Register 02h XOR IRQ Pulse Generation (813-ns Wide) IRQ Figure 7-15. IRQ Block Diagram There are two registers that can generate interrupts: GEN_STATUS and ALARM_STATUS. Each of these registers has a corresponding STATUS_MASK register. The mask register controls which of the events trigger an interrupt. Writing a 1 in the mask register masks, or disables, the event from triggering an interrupt. Writing a 0 in the mask register allows the event to trigger an IRQ. All bits are masked by default. Some status bits are sticky. Reading the corresponding register clears a sticky bit, unless the condition still exists. The IRQ is configured through CONFIG.IRQ_LVL to be edge- or level-sensitive. Set this bit to logic 1 to enable level-sensitive functionality (default). In edge-sensitive mode, the IRQ signal is a synchronous pulse, one internal clock period wide (813 ns). In level-sensitive mode, the IRQ is set and remains set as long as the condition exists. After the IRQ condition is removed, the condition is cleared by reading the corresponding status register. Trying to clear the bit while the condition still exists does not allow the bit to be cleared if the bit is sticky. CONFIG.IRQ_POL determines the active level of the IRQ. A logic 1 configures IRQ to be active high. When using edge-sensitive IRQ signals, there is a clock cycle delay for synchronization and edge detection. With a 307.2-kHz clock, this delay is up to 3.26 μs. For level-sensitive mode, the delay is approximately 10 ns to 20 ns. Most status bits have two versions within the design. The first version is an edge event that is created when the status is asserted. This signal is used to generate edge-sensitive IRQs. This edge detection prevents multiple status events from blocking one another. The second version is the sticky version of the status bit. This signal is set upon assertion of the status bit and cleared when the corresponding status register is read, as long as the status condition does not still persist. Signals GEN_IRQ and ALARM_IRQ are driven by the logical OR of the of the status bits within the corresponding register. If a status bit is unmasked and the sticky version of that bit has been asserted, and the IRQ is level-sensitive, then an interrupt is triggered as soon as the bit is unmasked. If the IRQ is edge-sensitive then a status event must occur after the bit has been unmasked to assert an interrupt.

7.3.5 Internal Reference

The AFEx8201 family of devices includes a 1.25-V precision band-gap reference. The internal reference is externally available at the VREFIO pin and sources up to 2.5 mA. For noise filtering, use a 100-nF capacitor between the reference output and GND. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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The internal reference circuit is enabled or disabled by using the REF_EN pin. A logic high on this pin enables the internal reference, and the VREFIO pin outputs 1.25 V. A logic low on this pin disables the internal reference, and the device expects to have 1.25 V from external VREF at the VREFIO pin. An invalid reference voltage asserts an alarm condition. The DAC response depends on the VREF_FLT setting in the ALARM_ACT register (10h).

7.3.6 Integrated Precision Oscillator

The internal time base of the device is provided by an internal oscillator that is trimmed to less than 0.5% tolerance at room temperature. The precision oscillator is the timing source for ADC conversions. At power up, the internal oscillator and ADC take roughly 300 µs to reach < 1% error stability. After the clock stabilizes, the ADC data output is accurate to the electrical specifications provided in Section 6.

7.3.7 Precision Oscillator Diagnostics

The AFEx8201 features two methods to continuously detect the functional status of the internal precision oscillator. The first method requires a connection from the AFEx8201 to the system controller. To use the first method, program the AFEx8201 to output a subdivided internal oscillator clock signal on the CLK_OUT pin. Write to the CONFIG.CLKO register field (see Table 7-15) to enable the output with the chosen divider or to disable the output. The output digital signal is compliant to the Section 6.5. The CLK_OUT pin is also a shared GPIO pin. For details on connecting CLK_OUT and CLK_OUT interoperability as a GPIO pin , see Section 7.5.1. The second method does not require a connection from the AFEx8201 and is a polled-communication-based method to determine the functionality of the internal oscillator using SPI communication. See Section 7.5.3.1 and Section 7.5.5 for SPI communication details and SDO status bits details, respectively. The OSC_DIV_2 bit reports the logical value of a subdivided internal oscillator signal (divided by 2) sampled at the CS falling edge. Use an appropriate SCLK frequency and interval between SPI frames to capture bit changes from frame to frame as a method of verifying the continued proper operation of the clock. Similar status reports of the logical value of a subdivided internal oscillator signal (divided by 1024) are available in UBM as the OSC_DIV_1024 bit. For details on UBM frames and timing, see Section 7.5.4.1.

7.3.8 One-Time Programmable (OTP) Memory

One-time programmable (OTP) memory in the device is used to store the device trim settings and is not accessible to users. The OTP memory data are loaded to the memory (OTP shadow load) at power up. The OTP memory CRC is performed to verify the correct data are loaded. The TRIGGER.SHADOWLOAD bit is available to initiate a reload of the OTP memory data if a CRC error is detected. The SPECIAL_CFG.OTP_LOAD_SW_RST bit controls whether the OTP memory data are reloaded with a software reset.

7.3.9 GPIO

AFEx8201 feature multiple GPIO pins, each independently configurable in either input only or output only or input-ouput mode through GPIO_CFG and GPIO registers. Select either push-pull or pseudo open drain sub modes supported when the GPIO is in output mode. No dedicated GPIO pins are present since the same pins are also configurable for communication interfaces. Based on the selection of the interface protocol and how many pins are used for communication purposes, the AFEx8201 have up to four available GPIOs. Refer to Section 7.5.1 for detailed diagrams of available GPIOs in each communication mode. If a GPIO pin is unused or undriven, the pin must be tied resistively to either IOVDD or GND according to the connection diagrams in Section 7.5.1. Unconnected floating input pins lead to unknown states for the communication interfaces and varying supply currents for the AFEx8201. When functioning as an output, each GPIO pin is capable of sourcing and sinking current and when functioning as an input the register address 0x1C reflects the digital state of the GPIO pins (for details of source and sink capabilities and input thresholds, see Section 6.5). The minimum pulse width for transition detection is t PULSE_GPIO. When a state transition occurs on a GPIO input, the new state must be held for a minimum of tPULSE_GPIO for detection by the AFEx8201. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: AFE78201 AFE88201

7.3.10 Timer

The AFEx8201 have an integrated timer for generating accurate time delays, pulse width modulation or oscillation. The devices have the ability to have timing parameters from the microseconds range to hours. The timer is brought out on the CLK_OUT pin by setting CONFIG.CLKO = Fh. The timer is controlled with three registers; TIMER_CFG_0, TIMER_CFG_1, and TIMER_CFG_2. In the first of the three registers, TIMER_CFG_0.ENABLE turns the timer function on and off. If the timer is off, then the output defaults to 0. TIMER_CFG_0.INVERT inverts the output of the timer. If the INVERT bit is set, the output defaults to 1. TIMER_CFG_0.CLK_SEL selects the clock frequency according to Table 7-6. If 2'b00 is selected, and no clock is applied, then the timer pauses if the timer has previously been enabled and counting. Table 7-6. Timer Select Range CLK_SEL Clock Frequency Resolution Range

00 No clock - -

01 1.2288 MHz 814 ns 53.3 ms 10 1.200 kHz 833 μs 54.6 s 11 1.171 Hz 853 ms 55,923 s The second timer register, TIMER_CFG_1.PERIOD sets the period of the timer. The period of the timer is PERIOD + 1 cycles of the clock period. The last timer register, TIMER_CFG_2.SET_TIME determines when the timer output goes to 1 (INVERT = 0). This effectively defines the duty cycle of the timer. The duty cycle can be calculated as (PERIOD – SET_TIME) × clock period.

7.3.11 Unique Chip Identifier (ID)

AFEx8201 include two read only registers: CHIP_ID_MSB (1Ah) and CHIP_ID_LSB (19h) where unique chip ID is stored. The 16-bit CHIP_ID_MSB register stores the encoded lot identification number while the CHIP_ID_LSB register stores the unique part number within each lot.

7.3.12 Scratch Pad Register

AFEx8201 feature a 16-bit Scratch Pad register to enable interface debug and verification without affecting the part functionality. This register is located at the address 18h. The readback value of the Scratch Pad register is the inverted code of the value stored in the register (for example, writing 0xAAAA results in 0x5555 while reading back ). AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.4 Device Functional Modes

7.4.1 Register Built-In Self-Test (RBIST)

The AFEx8201 feature a register built-in self-test (RBIST) that runs on all the registers listed in Table 7-7 through a CRC calculation in the order the registers are listed in Table 7-7. If the final CRC value is zero, then no error is present in the configuration of the registers. If a non-zero value is present at the end of the calculation, then there is a configuration error. The polynomial used has a Hamming distance (HD) of 4 for data packets up to 2048 bits. With HD = 4, the CRC detects any combination of 4-bit errors within the stored data. Independently calculate the expected CRC polynomial and store the output in the RBIST_CRC register at 3Fh. The final value of the CRC is read in the CRC_RD register at address 3Eh. This value is updated while either an RBIST or shadow load is running. Both the RBIST and OTP memory use the same CRC calculation engine and polynomial. The value in the CRC_RD register remains constant until another RBIST or SHADOWLOAD in TRIGGER register (0Ah) is triggered. Set TRIGGER.RBIST to 1 to initiate an RBIST. The TRIGGER.RBIST bit stays high as long as the RBIST is running and clears when the self-test is complete. While the RBIST is running, the registers cannot be written to or read. Send NOP commands and monitor the RBIST SDO status bit to determine if the RBIST has completed. In UBM, the RBIST does not interfere with register communication. UBM communication is slow enough that the RBIST completes before any following read or write command. Set the GEN_STATUS.RBIST_MODE bit to 1 to enable the RBIST. This bit is sticky until the GEN_STATUS register is read. The 16-bit CRC used to generate the RBIST is the openSAFETY (0x755B) with the following polynomial: x16 + x14 + x13 + x12 + x10 + x8 + x6 + x4 + x3 + x1 + 1. The list of registers covered by the RBIST is listed in Table 7-7. Not all registers feature the RBIST. Table 7-7. List of Registers Covered by RBIST ADDR (HEX) REGISTER RESET (HEX) 01h DAC_DATA 0000h 02h CONFIG 0036h 03h DAC_CFG 0B00h 04h DAC_GAIN 8000h 05h DAC_OFFSET 0000h 06h DAC_CLR_CODE 0000h 08h ADC_CFG 8810h 09h ADC_INDEX_CFG 0080h 0Bh SPECIAL_CFG 0000h 0Dh RESERVED 0100h 10h ALARM_ACT 8020h 11h WDT 0018h 12h AIN0_THRESHOLD FF00h 13h AIN1_THRESHOLD FF00h 14h TEMP_THRESHOLD FF00h 1Bh GPIO_CFG 00FFh 1Dh ALARM_STATUS_MASK EFDFh 1Eh GEN_STATUS_MASK FFFFh 3Fh RBIST_CRC 0000h www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: AFE78201 AFE88201

7.4.2 DAC Power-Down Mode

Power-down mode facilitates rapid turn-off of the voltage at the DAC output. The DAC can be set to enter and exit power-down mode through hardware, software, or automatically in response to an alarm event. The DAC output is specified for glitch-free performance when going into and out of power-down mode. Power-down mode is also be enabled by setting DAC_CFG.PD to 1. In power-down mode, the DAC output amplifier powers down and the DAC output pin is put into the Hi-Z configuration. The DAC output remains in power-down mode until the DAC output is re-enabled. Alarm control of the power-down mode is enabled by setting the alarm events as DAC power-down sources. The alarm events that trigger the DAC output power-down state must be specified in the ALARM_ACT register. After the alarm bit is cleared, the DAC returns to normal operation, as long as no other power-down controlling alarm event has been triggered. The DAC register does not change when the DAC enters power-down mode, which enables the device to return to the original operating point after return from the power-down mode. Additionally, the DAC register can be updated while the DAC is in power-down mode, thus allowing the DAC to output a new value upon return to normal operation.

7.4.3 Reset

There are three reset mechanisms in the device: a power-on reset (POR), a RESET pin, and the SW_RST command that can be sent through the either the SPI or by UBM. When power is first applied to the device, a POR circuit holds the device in reset until all supplies reach the specified operating voltages. The power-on reset returns the device to a known operating state in case a brownout event occurs (when the supplies have dipped below the minimum operating voltages). The POR starts all digital circuits in reset as the supply settles, and releases them to make sure that the device starts in the default condition and loads the OTP memory. After the OTP memory has been loaded, the ALARM pin is released. At this time, communication with the device is safe. This tPOR time is less than 100 µs. The devices also have a RESET pin that is used as a hardware reset to the device. Send the RESET pin low for a minimum of 100 ns (t RESET) to reset the device. A delay time of 10 μs (tRESETWAIT) is required before sending the first serial interface command as the device latches and releases the reset. The release of the internal reset state is synchronized to the internal clock. The RESET pin resets the SPI and the UART interfaces, the watchdog timer, the internal oscillator, and the device registers. RESET does not reload the OTP memory. The command to RESET.SW_RST = 0xAD resets the device as a software reset. The command is decoded at the rising edge of CS with an SPI command or during the stop bit of the last character of a UBM frame. Set UBM.REG_MODE again to put the device back into UBM when resetting the device in UBM. After sending the RESET command, no delay time is required before sending the first serial interface command as the device latches and releases the reset. The reset is synchronized to the falling edge of the internal clock and is released well before the next rising edge. The ALARM pin pulses low for the width of the internal reset. This pulse duration is less than 20 ns. This command resets the SPI and the UART interface, and the watchdog timer, but does not reset the internal oscillator. The software reset also reloads internal factory trim registers if properly configured in the SPECIAL_CFG register. The SPECIAL_CFG register is only reset with a POR. The POR and hardware reset place the internal oscillator into a reset condition, which holds the clock low. When these two signals are released, there is a delay of a few microseconds before the first rising edge of the clock. The hardware reset, RESET, pulse width must be at least 100 ns to allow the oscillator to properly reset. The SW_RST command is a short pulse. This pulse is not long enough to adequately reset the oscillator. The SW_RST is asserted with a falling edge of the clock. As a result of the long oscillator period, the design architecture provides that all devices are out of reset by the next rising edge. Figure 7-16 shows the reset tree. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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ALARM_STATUS GEN_STATUS SPECIAL_CFG Pin Reset Reset Command Power-On Reset Reset Command Power-On Reset CS Pin Reset Power-On Reset Software Reset Hardware Reset Reset WDT.WDT_EN CONFIG.UART_DIS Device Module Register Reset ALARM_STATUS Read Reset GEN_STATUS Read Power-On Reset Device Resets Other Registers Figure 7-16. Reset Conditions www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: AFE78201 AFE88201

7.5 Programming

The AFEx8201 communicate with the system controller through a serial interface that supports either a UART- compatible two-wire bus or an SPI-compatible bus. Based on the hardware configuration, either interface can be enabled. Figure 7-17 and Figure 7-18 show the configurations to enable SPI mode and UART break mode (UBM), respectively. The SPI supports an 8-bit frame-by-frame CRC that is enabled by default, but can be disabled by the user. UBM does not support CRC, but does support the UART protocol parity bit.

7.5.1 Communication Setup

After any reset or power up, the AFEx8201 wake up able to use the SPI or UART break mode (UBM). The devices include a robust mechanism that configures the interface between either an SPI-compatible or UART- compatible protocol based system, thus preventing protocol change during normal operation. The selection is based on initial conditions from the respective hardware configurations (see Figure 7-17 and Figure 7-18) and any subsequent user configuration.

7.5.1.1 SPI Mode

By default, the AFEx8201 can be fully accessed with the SPI (except UBM.REG_MODE). To set up the device in SPI mode: 1. Set CONFIG.UART_DIS = 1 (disables the UART communication). details, see Table 7-15. CLK_OUTMonitor SCLKClockSCLKClock Resistive tie for unused or undriven GPIO SDI SDOData In Data Out Chip Select CS GPIO3 UARTOUTInterrupt IOVDD RESET UART Interface Control LogicSPI Interface GPIO Interface GPIO1 System Controller AFE Isolation GND SCLR Reset Maximum Communication Functionality (Least GPIOs) Clear SDI SDO IOVDD Data In Data Out Chip Select CS GPIO3 GPIO2 IOVDD RESET UART Interface Control LogicSPI Interface GPIO Interface GPIO1 System Controller AFE Isolation GND SCLR Minimum Communication Functionality (Least GPIOs) GND GPIO0 Figure 7-17. SPI Mode Connections Figure 7-17 shows the SPI mode logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected , most GPIO pins available shown ) and maximum communication functionality (all communication pins connected , least GPIO pins available shown). If CONFIG.IRQ_PIN_EN = 1 is set, then the UARTOUT pin functions as the IRQ output. In SPI mode, set CONFIG.SDO_DSDO = 0 to enable the readback function. This function is disabled by default to save power. If the readback function not enabled, SDO remains in Hi-Z mode even during the subsequent frame after a read request. Enable each GPIO pin for use through proper register configuration. If a pin remains unused, tied the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor as indicated to avoid floating IOs. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.5.1.2 UART Mode

At power up, the UART interface is set to 9600 baud with UBM enabled. Any reset clears the UBM register, and the register must be set again to use UBM. To set up the device in UBM: 1. Using UBM, set UBM.REG_MODE = 1 at 9600 baud. This setting blocks the SPI from accessing the device and enables the UART interface access to the entire register map. 2. Optionally, set CONFIG.CLR_PIN_EN and CONFIG.IRQ_PIN_EN (See Table 7-15 for details). Figure 7-18 shows the UBM logical connections (through the isolation barrier, if used) for both minimum communication functionality (all optional communication pins disconnected , most GPIO pins available shown) and maximum communication functionality (all communication pins connected , least GPIO pins available shown ). If CONFIG.IRQ_PIN_EN = 1 is set, then the SDO pin functions as the IRQ output. If CONFIG.CLR_PIN_EN = 1 is set, then the SDI pin controls the clear pin function. Enable each GPIO pin for use through proper register configuration. If a GPIO pin remains unused, tie the pin to either IOVDD using a pullup resistor or to GND using a pulldown resistor to avoid floating I/Os. Resistive tie for unused or undriven GPIO SPI Interface UART Interface Control Logic SCLK GPIO4 GPIO5 UARTOUT UARTIN GPIO Interface Tx Rx System Controller AFE Isolation GND RESET GPIO6 GPIO0 SCLR IOVDD Minimum Communication Functionality (Most GPIOs) IOVDD RESET GPIO6 IOVDD UART Interface Control LogicSPI Interface SCLK SDO SDI UARTOUT UARTIN GPIO Interface Tx Clear Interrupt Rx System Controller AFE Isolation GND Reset Maximum Communication Functionality (Least GPIOs) GND SCLR CLK_OUTMonitor Figure 7-18. UBM (UART Interface) Connections

7.5.2 GPIO Programming

Seven physical pins are interoperable as GPIOs in the AFEx8201 when not used for communication. The state of these pins is set after the communication interface mode is determined (see Section 7.5.1 for power- up conditions and connection-diagram options for each communication mode supported by the AFEx8201). Configure any unused communication pins as GPIO, and resistively tie the pins to IOVDD or GND, respectively, as described in Section 7.5.1. Table 7-8 shows the pins and pin functions in UBM or SPI mode and lists the register configuration conditions to enable GPIO functionality for each pin. In addition to these register configurations, to use an available pin as GPIO, set the corresponding GPIO_CFG.EN bit. For a GPIO pin to be configured as an input, the following conditions must be met: 1. GPIO_CFG.ODE for the pin must = 1 2. GPIO.DATA for the pin must = 1 After initialization, the pin state is Hi-Z. Reading the GPIO.DATA register reads the pin value. If the previous conditions are not met, the pin is an output. In this case, the output drive type is determined by the GPIO_CFG.ODE bits to be push-pull or pseudo open drain. The GPIO output is driven by the GPIO.DATA bits. All reads of GPIO.DATA reports the values of the pins, regardless if the pins are configured as GPIO or not. Data written to the GPIO.DATA bits cannot be read directly. If a pin is available for use as GPIO, then the corresponding GPIO_CFG.EN bit must be set to enable GPIO functionality. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: AFE78201 AFE88201

Table 7-8. Pin Configuration in Each Interface Mode PIN UBM SPI REGISTER CONFIGURATION TO ENABLE GPIO (1) FUNCTION DIRECTION FUNCTION DIRECTION GPIO6/CS GPIO Input/Output CS Input (UBM.REG_MODE = 1) GPIO5/SDI CLR/GPIO Input/Output SDI Input (UBM.REG_MODE = 1) AND (CONFIG.CLR_PIN_EN = 0) GPIO4/SDO IRQ/GPIO Input/Output SDO Output (UBM.REG_MODE = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO3/UARTIN UARTIN Input GPIO Input/Output (CONFIG.UART_DIS = 1) GPIO2/UARTOUT UARTOUT Output IRQ/GPIO Input/Output (CONFIG.UART_DIS = 1) AND (CONFIG.IRQ_PIN_EN = 0) GPIO1 GND N/A GPIO Input/Output (CONFIG.UART_DIS = 1) GPIO0/CLK_OUT CLKO/GPIO Input/Output GPIO/CLKO Input/Output (CONFIG.CLKO = 0) AND ((UBM.REGMODE = 1) OR (CONFIG.UART_DIS = 1)) (1) Required by pin in addition to the corresponding GPIO_CFG.EN bit. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.5.3 Serial Peripheral Interface (SPI)

The AFEx8201 are controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and CS). The interface operates at clock rates of up to 12.5 MHz and is compatible with SPI, QSPI, Microwire, and digital signal processing (DSP) standards. The SPI communication command consists of a read or write address, a data word, and an optional CRC byte. The SPI can access all register addresses except for the UBM register. Read-only and read-write capability is defined by register (see Table 7-11). The SPI supports both SPI Mode 1 (CPOL = 0, CPHA = 1) and SPI Mode 2 (CPOL = 1, CPHA = 0). The default SCLK value is low for SPI Mode 1 and high for SPI Mode 2. See Section 6.7 for timing diagrams in each mode. The serial clock, SCLK, can be continuous or gated.

7.5.3.1 SPI Frame Definition

Subject to the timing requirements listed in the Timing Requirements, the first SCLK falling edge immediately following the falling edge of CS captures the first frame bit. Subject to the same requirements, the last SCLK falling edge before the rising edge of CS captures the last bit of the frame. Figure 7-19 shows that the SPI shift register frame is 32-bits wide, and consists of an R/W bit, followed by a 7-bit address, and a 16-bit data word. The 8-bit CRC is optional (enabled by default) and is disabled by setting CONFIG.CRC_EN = 0 (see also SDO SDI Don’t Care Valid DataHi-Z Output Frame (n-1) Status Details CRC_ERR Next Frame (n+1), Command or NOP CS RESET RBIST OSC_DIV_2 1'b0 GEN_IRQ ALARM_IRQ Address (7b) Data Word (16b) CRC (8b)R/W (1b) R/W (1b) Status (7b) Data Word (16b) CRC (8b) Output Frame (n) Input Frame (n) SCLK 31 30~24 23~8 7~0 Figure 7-19. SPI Frame Details (Default, CRC Enabled) SDO SDI R/W (1b) Don’t Care Valid DataHi-Z Output Frame (n-1) Status (7b) Data Word (16b) Address (7b) Data Word (16b)R/W (1b) Next Frame (n+1), Command or NOP CS Output Frame (n) Input Frame (n) SCLK 23 22~16 15~0 Figure 7-20. SPI Frame Details (CRC Disabled) For a valid frame, a full frame length of data (24 bits if CRC is disabled or 32 bits if CRC is enabled) must be transmitted before CS is brought high. If CS is brought high before the last falling SCLK edge of a full frame, then the data word is not transferred into the internal registers. If more than a full frame length of falling SCLK edges are applied before CS is brought high, then the last full frame length number of bits are used. In other words, if the number of falling SCLK edges while CS = 0 is 34, then the last 32 SCLK cycles (or 24 if CRC is disabled) are treated as the valid frame. The device internal registers are updated from the SPI shift register on www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: AFE78201 AFE88201

the rising edge of CS. To start another serial transfer, bring CS low again. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is high impedance.

7.5.3.2 SPI Read and Write

The SDI input bit is latched on the SCLK falling edge. The SDI pin receives right-justified data. At the rising edge of CS, the right-most (last) bits are evaluated as a frame. Extra clock cycles (exceeding frame length) during the frame begin to output on SDO the SDI data delayed by one frame length. A read operation is started when R/W bit is 1. The data word input for SDI is ignored in the read command frame. Send the subsequent read or write command frame into SDI to clock out the data of the addressed register on SDO. If no other read or write commands are needed, then issue a NOP command to retrieve the requested data. The read register value is output most significant bit first on SDO on successive edges (rising or falling based on CONFIG.FSDO setting) of SCLK. A write operation starts when R/W bit is 0. The SDO output to a write command, delivered in the next frame, contains status bits, data described in Table 7-9, and if the CRC is enabled, an 8-bit CRC for the output frame. Table 7-9. Command Functions COMMAND BIT SDI INPUT DATA WORD SDO RESPONSE DATA WORD(1) Write (R/W = 0) Data to be written (16b) 0x0000 Read (R/W = 1) Ignored(2) Register output data (16b) (1) Response data portion in next frame output. (2) The input bits are included in the calculation for CRC, if enabled (see Section 7.5.3.3). Valid SDO output is driven only when CS = 0 and CONFIG.DSDO = 0; otherwise, the SDO pin remains Hi-Z to save power. The SDO data bits are left-justified within the frame, meaning the most significant bit is produced on the line (subject to timing details) when CS is asserted low (bit is driven by falling edge of CS). The subsequent bits in the frame are driven by the rising SCLK edge when CONFIG.FSDO = 0 (default). To drive the SDO data on the falling edge of SCLK, set CONFIG.FSDO = 1. This setting effectively gives the SDO data an additional ½ clock period for setup time, but at the expense of hold time. The frame output on SDO contains the command bit of the input that generated the frame (previous input frame), followed by seven status bits (see Figure 7-19 ). When an input frame CRC error is detected, the status bit CRC_ERR = 1. If there is no input frame CRC error, then CRC_ERR = 0. See Table 7-10 for details.

7.5.3.3 Frame Error Checking

If the AFEx8201 are used in a noisy environment, use the CRC to check the integrity of the SPI data communication between the device and the system controller. This feature is enabled by default and is controlled by the CONFIG.CRC_EN bit. If the CRC is not required in the system, disable frame error checking through the CRC_EN bit, and switch from the default 32-bit frame to the 24-bit frame. Frame error checking is based on the CRC-8-ATM (HEC) polynomial: x8 + x2 + x + 1 (9'b100000111). For the output register readback, the AFEx8201 supply the calculated 8-bit CRC for the 24 bits of data provided, as part of the 32-bit frame. The AFEx8201 decodes 24-bits of the input frame data and the 8-bit CRC to compute the CRC remainder. If no error exists in the frame, the CRC remainder is zero. When the remainder is nonzero (that is, the input frame has single-bit or multiple-bit errors) the ALARM_STATUS.CRC_ERR_CNT bits are incremented. A bad CRC value prevents execution of commands to the device. When the CRC error counter reaches the limit programmed in CONFIG.CRC_ERR_CNT, the CRC_FLT status bit is set in the ALARM_STATUS register. The fault is reported (as long as the corresponding mask is not set) as an ALARM_IRQ on SDO during the next frame. The ALARM pin asserts low if enabled by the alarm action configuration (see Section 7.3.3.2). The CRC_ERR status bit (see Figure 7-19 ) in the SDO frame is not sticky and is only reported for the previous frame. The ALARM_STATUS.CRC_FLT bit is sticky and is only cleared after a successful read of AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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the ALARM_STATUS register. Read the GEN_STATUS or ALARM_STATUS registers to clear any sticky bits that are set. The sticky status bits are cleared at the start of the readback frame and are latched again at the end of the readback frame. Therefore, if the fault condition previously reported in the status register is no longer present at the end of the readback frame, and the data are received by the microcontroller with the CRC error, the fault information is lost. If a robust monitoring of the status bits is required in a noisy environment, use the IRQ pin in combination with the status mask bits to find out the status of each fault before clearing the status bits. Set the CONFIG.IRQ_LVL bit to monitor the signal level on the IRQ pin, and unmask each status bit one at a time to retrieve the information from the status registers.

7.5.3.4 Synchronization

The AFEx8201 register map runs on the internal clock domain. Both the SPI and UBM packets are synchronized to this domain. This synchronization adds a latency of 0.4 µs to 1.22 µs (1.5 internal clocks), with respect to the rising edge of CS or the STOP bit of the last byte of the UBM packet. The effect of clock synchronization on UBM communication is not evident because of the lower speed and asynchronous nature of UBM communication. In SPI mode, if changing register bits CONFIG.DSDO, CONFIG.FSDO, or CONFIG.CRC_EN, keep CS high for at least two clock cycles before issuing the next frame. Frame data corruption can occur if the two extra cycles are not used. The following are examples of frame corruption:

Setting CONFIG.DSDO = 0: SDO begins to drive in the middle of the next frame.
Changing CONFIG.FSDO: The launching edge of SDO changes in the middle of the next frame.
Setting CONFIG.CRC_EN = 1: The next frame has a CRC error because the CRC is enabled in the middle of the frame. Send a NOP command (SDI = 0x00_0000) after setting the DSDO, FSDO, and CRC_EN bits to prevent the corrupted frames from impacting communication. Sending a NOP after CONFIG.CRC_EN is set still generates a CRC error, and is reported in the STATUS portion of SDO. To avoid false errors, wait approximately 2 µs after setting CONFIG.CRC_EN before sending the next frame. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: AFE78201 AFE88201

7.5.4 UART Interface

In UART mode, the device expects 1 start bit, 8 data bits, 1 odd parity bit, and 1 stop bit, or an 8O1 UART character format.

7.5.4.1 UART Break Mode (UBM)

In UART break mode (UBM), the microcontroller issues a UART break to start communication. The device interprets the UART break as the start to receive commands from the UART. A communication UART character consists of one start bit, eight data bits, one odd parity bit, and at least one stop bit. A UART break character is all 11 bits (including start, data, parity and stop bit) held low by the microcontroller on the UARTIN pin and by the AFEx8201 on the UARTOUT pin. When a valid break character is detected on UARTIN by the AFEx8201, no parity (even though parity is odd) or stop bit errors are flagged for this character. The parity and stop bit differences between valid UBM break and communication characters must be managed by the system microcontroller when receiving these characters from the UARTOUT pin of the AFEx8201. See Figure 6-2 for UBM break character, communication timing details, and bit order. AFEx8201 UART break mode communication is supported at 9600 baud. Set UBM.REG_MODE = 1 to enable register map access through the UART. By default, this bit is set to 0. The entire register map can only be accessed with SPI, except for the UBM register. The UBM register can only be accessed with UBM. After UBM.REG_MODE is set to 1, the SPI does not have access to the register map, and the full register map is accessible by UBM. A UBM data output packet is initiated by AFEx8201 on UARTOUT in two cases. See Figure 7-23 for packet structure details. If the R/IRQn status bit is 0 an IRQ event initiated the break command. If the R/IRQn status bit is 1, the break command is a response to the prior read request. To enable IRQ events, set CONFIG.UBM_IRQ_EN = 1. When IRQ is enabled, the AFEx8201 triggers a break command followed by data on UARTOUT (see Figure 7-23). The contents of the data are listed in order of priority below. 1. If ALARM_IRQ bit is set, then the contents of the ALARM_STATUS register are output. 2. If GEN_IRQ is set, then the contents of the GEN_STATUS register are output. 3. If none of the previous bits are set, then an IRQ is not generated. A break byte is followed by three bytes. These three bytes have information identical to the SPI frame without the CRC (see Figure 7-20). The CRC cannot be enabled for UBM. All communication characters on the UART bus are transmitted least significant data bit (D0) first. Figure 7-21 shows the data structure of the UBM write command, and Figure 7-22 shows the data structure of the UBM read command. S = Start bit, Par = Parity bit, P = Stop bit UART Break UART Write Data MSB Address [0:6] S P UART Break Write Par 1'b0 (Write) Data [8:15] S P Par UART Write Data LSB Data [0:7] P Par UARTIN S Figure 7-21. UARTIN Break Write Data Format AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.5.5 Status Bits

Every response, in SPI mode and UBM, from the AFEx8201 includes a set of status bits. For SPI mode bit order, Table 7-10. Status Bits STATUS BIT DESCRIPTION NOTES / REFERENCE ALARM_IRQ 1h = ALARM_IRQ asserted 0h = Normal operation From the GEN_STATUS(1) register (Table 7-39). Also see Section 7.3.4. CRC_ERR (CRC enabled SPI only) 1h = CRC error detect in input frame 0h = No CRC error detected Generated by the SPI on a frame by frame basis. See Section 7.5.3.3. GEN_IRQ 1h = GEN_IRQ asserted 0h = Normal Operation From the ALARM_STATUS(1) register (Table 7-38). Also see Section 7.3.4. OSC_DIV_1024 (UBM mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 1024) sampled at the falling edge of the status byte start bit. Also see Section 7.3.7. OSC_DIV_2 (SPI mode) 1h = Sampled signal is high 0h = Sampled signal is low Subdivided internal oscillator clock signal (frequency divided by 2) sampled at CS falling edge. Also see Section 7.3.7. R/IRQn (UBM only) 1h = Read request 0h = IRQ event Generated by the UART interface on a frame by frame basis. See Section 7.5.4.1 for details. RBIST 1h = RBIST busy (registers not readable) 0h = RBIST done (registers readable) RBIST running status. See Section 7.4.1 for details. RESET 1h = First readback after RESET 0h = All other readbacks From the GEN_STATUS register (Table 7-39). Also see Section 7.4.3. (1) ALARM_STATUS, and GEN_STATUS registers contain cross-readable IRQ flags for the other register. The ALARM_STATUS register has the GEN_IRQ bit. GEN_STATUS has the ALARM_IRQ bit. This functionality enables the system microcontroller to always get full status information by reading only one register, and thus save power.

7.5.6 Watchdog Timer

The AFEx8201 include a watchdog timer (WDT) that is used to make sure that communication between the system controller and the device is not lost. The WDT checks that the device received a communication from the system controller within a programmable period of time. To enable this feature, set WDT.WDT_EN to 1. The WDT monitors both SPI and UBM communications. The WDT has two limit fields: WDT.WDT_UP and WDT.WDT_LO. The WDT_UP field sets the upper time limit for the WDT. The WDT_LO field sets the lower time limit. If the WDT_LO is set to a value other than 2’b00, then the WDT acts as a window comparator. If the write occurs too quickly (less than the WDT_LO time), or too slowly (greater than the WDT_UP time), then a WDT error is asserted. When acting as a window comparator, in the event of a WDT error, the WDT resets only when a write to the WDT register occurs. If the WDT_LO is set to 2'b00, then a write to any register resets the WDT time counter. In this mode, the WDT error is asserted when the timer expires. If enabled, the chip must have any SPI or UBM write to the device within the programmed timeout window. Otherwise, the ALARM pin asserts low, and the ALARM_STATUS.WD_FLT bit is set to 1. The WD_FLT bit is sticky. After a WD_FLT has been asserted, WDT.WDT_EN must be set to 0 to clear the WDT condition. Then the WDT can be re-enabled. The WDT condition is also cleared by issuing a software or hardware reset. After the WDT condition is clear, WD_FLT is cleared by reading the ALARM_STATUS register. When using multiple AFEx8201 devices in a daisy-chain configuration, connect the open-drain ALARM pins of all devices together to form a wired-OR network. The watchdog timer can be enabled in any number of the devices in the chain; although, enabling the watchdog timer in one device in the chain is usually sufficient. The wired-OR ALARM pin can be pulled low in response to the simultaneous presence of different trigger conditions in the devices in the daisy-chain. The host processor must read the ALARM_STATUS register of each device to know all the fault conditions present in the chain. The watchdog timeout period is based on a 1200-Hz clock (1.2288 MHz / 1024). AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6 Register Maps

Table 7-11 lists the memory-mapped registers for the AFEx8201 registers. Consider all register offset addresses not listed in Table 7-11 as reserved locations; do not modify these register contents. Table 7-11. Register Map ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h NOP NOP [15:0] 01h DAC_DATA DATA [15:0] 02h CONFIG CRC_ERR_CNT [1:0] CLKO [3:0] UBM_ IRQ_EN IRQ_ PIN_EN CLR_ PIN_EN UART_DIS RESERVED CRC_EN IRQ_POL IRQ_LVL DSDO FSDO 03h DAC_CFG RESERVED PD SR_CLK [2:0] SR_STEP [2:0] SR_EN SR_MODE RESERVED CLR RESERVED 04h DAC_GAIN GAIN [15:0] 05h DAC_OFFSET OFFSET [15:0] 06h DAC_CLR_ CODE CODE [15:0] 07h RESET RESERVED SW_RST [7:0] 08h ADC_CFG BUF_PD HYST [6:0] FLT_CNT [2:0] AIN_ RANGE EOC_ PER_CH CONV_RATE [1:0] DIRECT_ MODE 09h ADC_INDEX_ CFG RESERVED STOP [3:0] START [3:0] 0Ah TRIGGER RESERVED RBIST RESERVED SHADOW LOAD ADC 0Bh SPECIAL_ CFG (1) RESERVED OTP_ LOAD_ SW_RST ALMV_ POL AIN1_ENB 10h ALARM_ACT SD_FLT [1:0] TEMP_FLT [1:0] AIN1_FLT [1:0] AIN0_FLT [1:0] CRC_WDT_FLT [1:0] VREF_FLT [1:0] THERM_ERR_FLT [1:0] THERM_WARN_FLT [1:0] 11h WDT RESERVED WDT_UP [2:0] WDT_LO [1:0] WDT_EN 12h AIN0_ THRESHOLD Hi [7:0] Lo [7:0] 13h AIN1_ THRESHOLD Hi [7:0] Lo [7:0] 14h TEMP_ THRESHOLD Hi [7:0] Lo [7:0] 16h UBM (2) RESERVED REG_ MODE 18h SCRATCH DATA [15:0] 19h CHIP_ID_LSB ID [15:0] 1Ah CHIP_ID_MSB ID [15:0] 1Bh GPIO_CFG RESERVED EN [6:0] RESERVED ODE [6:0] 1Ch GPIO RESERVED DATA [6:0] 1Dh ALARM_ STATUS_MASK RESERVED SD_FLT OSC_FAIL RESERVED OTP_ CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_ AIN1_FLT ADC_ AIN0_FLT ADC_ TEMP_ FLT THERM_ ERR_FLT THERM_ WARN_ FLT 1Eh GEN_ STATUS_MASK RESERVED RBIST_ DONE RBIST_ FAIL RESERVED SR_ BUSYn ADC_ EOC RESERVED BREAK_ FRAME_ ERR BREAK_ PARITY_ ERR UART_ FRAME_ ERR UART_ PARITY_ ERR www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: AFE78201 AFE88201

Table 7-11. Register Map (continued) ADDR (HEX) REGISTER BIT DESCRIPTION 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20h ALARM_ STATUS GEN_ IRQ RESERVED SD_FLT OSC_FAIL CRC_CNT [1:0] OTP_ LOADEDn OTP_ CRC_ERR CRC_FLT WD_FLT VREF_FLT ADC_ AIN1_FLT ADC_ AIN0_FLT ADC_ TEMP_ FLT THERM_ ERR_FLT THERM_ WARN_ FLT 21h GEN_ STATUS ALARM_ IRQ RESERVED OTP_ BUSY RBIST_ MODE RBIST_ DONE RBIST_ FAIL RESET SR_ BUSYn ADC_ EOC ADC_ BUSY PVDD_HI BREAK_ FRAME_ ERR BREAK_ PARITY_ ERR UART _FRAME _ERR UART_ PARITY_ ERR 23h ADC_FLAGS RESERVED SD4_FAIL SD3_FAIL SD2_FAIL SD1_FAIL SD0_FAIL TEMP_ FAIL AIN1_ FAIL AIN0_ FAIL RESERVED 24h ADC_AIN0 RESERVED DATA [11:0] 25h ADC_AIN1 RESERVED DATA [11:0] 26h ADC_TEMP RESERVED DATA [11:0] 27h ADC_SD_MUX RESERVED DATA [11:0] 28h ADC_OFFSET RESERVED DATA [11:0] 2Ch DAC_OUT DATA [15:0] 2Dh ADC_OUT RESERVED DATA [11:0] 2Eh ADC_BYP DATA_ BYP_EN OFST_ BYP_EN DIS_GND_ SAMP RESERVED DATA [11:0] 2Fh FORCE_FAIL CRC_FLT VREF_FLT THERM_ ERR_FLT THERM_ WARN_ FLT RESERVED SD4_HI_ FLT SD4_LO_ FLT SD3_HI_ FLT SD3_LO_ FLT SD2_HI_ FLT SD2_LO_ FLT SD1_HI_ FLT SD1_LO_ FLT SD0_HI_ FLT SD0_LO_ FLT 3Bh TIMER_CFG_0 RESERVED CLK_SEL [1:0] INVERT ENABLE 3Ch TIMER_CFG_1 PERIOD [15:0] 3Dh TIMER_CFG_2 SET_TIME [15:0] 3Eh CRC_RD CRC [15:0] 3Fh RBIST_CRC CRC [15:0] (1) The SPECIAL_CFG register can only be reset with POR, and does not respond to the RESET pin or SW_RST command. (2) The UBM register can only be accessed with a UBM command. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1 AFEx8201 Registers

Complex bit access types are encoded to fit into small table cells. The following table shows the codes that are used for access types in this section. Table 7-12. AFEx8201 Access-Type Codes Access Type Code Description Read Type R R Read Write Type W W Write W WO Write only W WSC Write self clear Reset or Default Value -n Value after reset or the default value Register Array Variables i,j,k,l,m,n When used in a register name, an offset, or an address, these variables refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. y When used in a register name, an offset, or an address, this variable refers to the value of a register array.

7.6.1.1 NOP Register (Offset = 0h) [Reset = 0000h]

Return to the Register Map. Table 7-13. NOP Register Field Descriptions Bit Field Type Reset Description 15-0 NOP WO 0h No operation. Data written to this field have no effect. Always reads zeros.

7.6.1.2 DAC_DATA Register (Offset = 1h) [Reset = 0000h]

Return to the Register Map. DAC code for VOUT. Table 7-14. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W 0h Data. DAC code for VOUT. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: AFE78201 AFE88201

7.6.1.3 CONFIG Register (Offset = 2h) [Reset = 0036h]

Return to the Register Map. Table 7-15. CONFIG Register Field Descriptions Bit Field Type Reset Description 15-14 CRC_ERR_CNT R/W 0h CRC Errors Count Limit Sets the numbers of consecutive SPI CRC frames that must have errors before the status bits is set. 0h = 1 (default); 1h = 2; 2h = 4; 3h = 8 13-10 CLKO R/W 0h CLKO Enable Enable the CLK_OUT pin and set the divider value. 0h = CLKO disabled (default); 1h = 1.2288 MHz; 2h = 1.2288 / 2 MHz; 3h = 1.2288 / 4 MHz; 4h = 1.2288 / 8 MHz; 5h = 1.2288 / 16 MHz; 6h =1.2288 / 32 MHz; 7h = 1.2288 / 64 MHz; 8h = 1.2288 / 128 MHz; 9h = 1.2288 / 256 MHz; Ah = 1.2288 / 512 MHz; Bh = 1.2288 / 1024 MHz; Ch = 1'b0; Dh = 1'b0; Eh = 1'b0; Fh = Timer

9 UBM_IRQ_EN R/W 0h UBM IRQ Enable

Enable IRQ to be sent on UARTOUT through UBM. 0h = Disabled (default); 1h = Enabled

8 IRQ_PIN_EN R/W 0h IRQ Pin Enable

Enable IRQ pin functionality. 0h = Disabled (default); 1h = Enabled

7 CLR_PIN_EN R/W 0h Clear Input Pin Enable

Enable pin-based transition to the CLEAR state in UBM and SPI. 0h = Disabled (default); 1h = SCLR pin enabled in SPI mode or SDI pin configured as clear input pin in UBM

6 UART_DIS R/W 0h UART Disable

Disable UART functionality. 0h = Disabled (default); 1h = Enabled 5 RESERVED R 1h Reserved. Always set this bit to 1h for proper functionality.

4 CRC_EN R/W 1h CRC Enable

Enable CRC for SPI. 0h = Disabled; 1h = Enabled (default)

3 IRQ_POL R/W 0h IRQ Polarity

0h = Active low (default); 1h = Active high

2 IRQ_LVL R/W 1h IRQ Level

0h = Edge sensitive 1h = Level sensitive (default)

1 DSDO R/W 1h SDO Hi-Z

0h = Drive SDO during CS = 0 1h = SDO always Hi-Z (default)

0 FSDO R/W 0h Fast SDO

SDO is driven on negative edge of SCLK. 0h = drive SDO on rising edge of SCLK (launching edge) (default) 1h = drive SDO on falling edge of SCLK (capture edge 1/2 clock early) AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1.4 DAC_CFG Register (Offset = 3h) [Reset = 0B00h]

Return to the Register Map. Table 7-16. DAC_CFG Register Field Descriptions Bit Field Type Reset Description 15-13 RESERVED R/W 0h

12 PD R/W 0h DAC Output Buffer Power-down

DAC output set to Hi-Z in power-down. 0h = DAC output buffer enabled (default) 1h = DAC output buffer disabled 11-9 SR_CLK R/W 5h Slew Clock Rate 0h = 307.2 kHz 1h = 153.6 kHz 2h = 76.8 kHz 3h = 38.4 kHz 4h = 19.2 kHz 5h = 9600 Hz (default) 6h = 4800 Hz 7h = 2400 Hz 8-6 SR_STEP R/W 4h Slew Step Size 0h = 1 code 1h = 2 codes 2h = 4 codes 3h = 8 codes 4h = 16 codes (default) 5h = 32 codes 6h = 64 codes 7h = 128 codes

5 SR_EN R/W 0h Slew Enable

Enables slew on the output voltage. 0h = Disabled (default) 1h = Enabled

4 SR_MODE R/W 0h Slew Mode

Output slew rate mode select. 0h = Linear Slew (default) 1h = Sinusoidal Slew

3 RESERVED R 0h

2 CLR R/W 0h CLEAR State

0h = Normal operation (default) 1h = Force the DAC to the CLEAR state 1-0 RESERVED R 0h www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 59 Product Folder Links: AFE78201 AFE88201

7.6.1.5 DAC_GAIN Register (Offset = 4h) [Reset = 8000h]

Return to the Register Map. Table 7-17. DAC_GAIN Register Field Descriptions Bit Field Type Reset Description 15-0 GAIN R/W 8000h Gain Set the gain of the DAC output from 0.5 – 1.499985. For example: 0000h = 0.5 8000h = 1.0 (default) FFFFh = 1.499985

7.6.1.6 DAC_OFFSET Register (Offset = 5h) [Reset = 0000h]

Return to the Register Map. Table 7-18. DAC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-0 OFFSET R/W 0h Offset Adjust the offset of the DAC output, 2's complement number. For example: 0000h = 0 (default) FFFFh = –1

7.6.1.7 DAC_CLR_CODE Register (Offset = 6h) [Reset = 0000h]

Return to the Register Map. Table 7-19. DAC_CLR_CODE Register Field Descriptions Bit Field Type Reset Description 15-0 CODE R/W 0h CLEAR State DAC Code

7.6.1.8 RESET Register (Offset = 7h) [Reset = 0000h]

Return to the Register Map. Table 7-20. RESET Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-0 SW_RST WSC 0h Software Reset Write ADh to initiate software reset. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1.9 ADC_CFG Register (Offset = 8h) [Reset = 8810h]

Return to the Register Map. Table 7-21. ADC_CFG Register Field Descriptions Bit Field Type Reset Description

15 BUF_PD R/W 1h ADC Buffer Power-down

0h = ADC buffer enabled; 1h = ADC buffer powered down (default) 14-8 HYST R/W 8h Hysteresis The number of codes of hysteresis used when a threshold is exceeded for an ADC measurement of AIN0/AIN1/TEMP. 7-5 FLT_CNT R/W 0h Fault Count Number of successive faults to trip an alarm. Number of successive faults is programmed value + 1 (1-8 faults).

4 AIN_RANGE R/W 1h ADC Analog Input Range

Can only be set if PVDD ≥ 2.7 V to use 2.5-V range for AIN0 and AIN1 inputs. 0h = 2 × VREF; 1h = 1 × VREF (default)

3 EOC_PER_CH R/W 0h ADC End-of-Conversion for Every Channel

Sends an EOC pulse at the end of each channel instead of at the end of all the channels. 0h = EOC after last channel (default); 1h = EOC for every channel 2-1 CONV_RATE R/W 0h ADC Conversion Rate This setting only affects the conversion rate for channels AIN0 and AIN1. Rates are based on a 76.8-kHz ADC clock. All other channels use 2560 Hz. 0h = 3840 Hz (default) 1h = 2560 Hz 2h = 1280 Hz 3h = 640 Hz

0 DIRECT_MODE R/W 0h Direct Mode Enable

0h = Auto mode (default); 1h = Direct mode

7.6.1.10 ADC_INDEX_CFG Register (Offset = 9h) [Reset = 0080h]

Return to the Register Map. The ADC custom channel sequencing configuration is shown in Table 7-22. Table 7-22. ADC_INDEX_CFG Register Field Descriptions Bit Field Type Reset Description 15-8 RESERVED R 0h 7-4 STOP R/W 8h Custom Channel Sequencer Stop Index CCS index to stop ADC sequence. Must be ≥ START. If not, STOP is forced to = START. 0h = OFFSET 1h = AIN0 2h = AIN1 3h = TEMP 4h = SD0 (VREF) 5h = SD1 (PVDD) 6h = SD2 (VDD) 7h = SD3 (ZTAT) 8h = SD4 (VOUT) (default) 9h through Fh = GND 3-0 START R/W 0h Custom Channel Sequencer Start Index CCS index to start ADC sequence. 0h through Fh = Same as STOP field (0h is default) www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: AFE78201 AFE88201

7.6.1.11 TRIGGER Register (Offset = Ah) [Reset = 0000h]

Return to the Register Map. Table 7-23. TRIGGER Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED R 0h

3 RBIST WSC 0h RBIST Trigger

This trigger initiates a Register BIST. This BIST runs a CRC calculation through the configuration registers (Table 7-7) and compares the result to a stored CRC value in the RBIST_CRC register.

2 RESERVED R 0h

1 SHADOWLOAD WSC 0h Shadow Load Trigger

This trigger initiates the loading of the OTP array into the parallel latches. If an OTP CRC error is detected, assert this trigger to try and reload the OTP into the memory locations.

0 ADC WSC 0h ADC Trigger

In auto mode, this bit enables or disables the conversions. Manually set to 1 (enable) or 0 (disable). In direct mode, set this bit to start a conversion sequence. The bit is cleared at the end of the sequence. To stop a sequence prematurely, manually clear this bit.

7.6.1.12 SPECIAL_CFG Register (Offset = Bh) [Reset = 0000h]

Return to the Register Map. Table 7-24. SPECIAL_CFG Register Field Descriptions Bit Field Type Reset Description 15-3 RESERVED R 0h

2 OTP_LOAD_SW_RST R/W 0h OTP (One Time Programmable Factory Trimmed Registers) LOAD

OTP reloads with the assertion of a software reset (SW_RST). 0h = No reload with SW_RST 1h = Reload with SW_RST

1 ALMV_POL R/W 0h Alarm Voltage Polarity

This register bit is ORed with the POL_SEL/AIN1 pin (if AIN1_ENB bit is low) to control the VOUT during a hardware reset condition or if alarm is active and alarm action is set appropriately. The following Boolean function is implemented for the internal signal ALMV_POL_o that sets the VOUT voltage: ALMV_POL_o = ALMV_POL OR (POL_SEL/AIN1 AND NOT AIN1_ENB) 0h = Low (0 V) 1h = High (2.5 V)

0 AIN1_ENB R/W 0h AIN1 Pin Enable

This bit determines whether the POL_SEL/AIN1 pin acts as alarm voltage polarity control bit or an input channel to the ADC. 0h = AIN1 pin acts as alarm voltage polarity bit and ADC converts GND 1h = AIN1 pin is an active channel to the ADC AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1.13 ALARM_ACT Register (Offset = 10h) [Reset = 8020h]

Return to the Register Map. Table 7-25. ALARM_ACT Register Field Descriptions Bit Field Type Reset Description 15-14 SD_FLT R/W 2h Self-Diagnostic Fault Action These bits set the device action after a self-diagnostic fault. 0h = No Action 1h = Set DAC to CLEAR state 2h = Switch to alarm voltage determined by ALMV_POL (default) 3h = Place DAC into Hi-Z (power-down) 13-12 TEMP_FLT R/W 0h TEMP Fault Action These bits set the device action if the ADC temperature is outside the TEMP_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 11-10 AIN1_FLT R/W 0h AIN1 Fault Action These bits set the device action if the ADC AIN1 channel is outside the AIN1_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 9-8 AIN0_FLT R/W 0h AIN0 Fault Action These bits set the device action if the ADC AIN0 channel is outside the AIN0_THRESHOLD Hi or Lo thresholds. 0h through 3h = Same as SD_FLT field (default 0h) 7-6 CRC_WDT_FLT R/W 0h CRC and WDT Fault Action These bits set the device action when a SPI CRC or SPI Watchdog Timeout error occurs. 0h through 3h = Same as SD_FLT field (default 0h) 5-4 VREF_FLT R/W 2h VREF Fault Action These bits set the device action when a fault is detected on VREF. 0h through 3h = Same as SD_FLT field a 3-2 THERM_ERR_FLT R/W 0h Thermal Error Fault Action These bits set the device action when a high temperature error occurs (> 130°C). 0h through 3h = Same as SD_FLT field (default 0h) 1-0 THERM_WARN_FLT R/W 0h Thermal Warning Fault Action These bits set the device action when a high temperature warning occurs (> 85°C). 0h through 3h = Same as SD_FLT field (default 0h) www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: AFE78201 AFE88201

7.6.1.14 WDT Register (Offset = 11h) [Reset = 0018h]

Return to the Register Map. Table 7-26. WDT Register Field Descriptions Bit Field Type Reset Description 15-6 RESERVED R 0h 5-3 WDT_UP R/W 3h Watchdog Timer (WDT) Upper Limit If the WDT is enabled and the timer exceeds the programmed value, a WDT error is asserted. All times are based on 1200-Hz clock (1.2288 MHz / 1024). 0h = 53 ms (64 clocks) 1h = 106 ms (128 clocks) 2h = 427 ms (512 clocks) 3h = 853 ms (1024 clocks, default) 4h = 1.7 s (2048 clocks) 5h = 2.56 s (3072 clocks) 6h = 3.41 s (4096 clocks) 7h = 5.12 s (6144 clocks) 2-1 WDT_LO R/W 0h WDT Lower Limit If the WDT is enabled and the WDT Lower Limit is enabled, then only a write to this register resets the WDT timer. If the write occurs before the WDT Lower Limit time, or after the WDT Upper Limit time, then a WDT error is asserted. If WDT Lower Limit is disabled, then a write to any register resets the timer. This is true for both SPI and UART Break modes. All times are based on 1200-Hz clock (1.2288 MHz / 1024). 0h = Disabled (default) 1h = 53 ms (64 clocks) 2h = 106 ms (128 clocks) 3h = 427 ms (512 clocks)

0 WDT_EN R/W 0h WDT Enable

0h = Disabled (default); 1h = Enabled

7.6.1.15 AIN0_THRESHOLD Register (Offset = 12h) [Reset = FF00h]

Return to the Register Map. Table 7-27. AIN0_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN0 {[11:4],4b1111} This value is compared (>) against AIN0 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN0 {[11:4],4b0000} This value is compared (<) against AIN0 data bits[11:0].

7.6.1.16 AIN1_THRESHOLD Register (Offset = 13h) [Reset = FF00h]

Return to the Register Map. Table 7-28. AIN1_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel AIN1 {[11:4],4b1111} This value is compared (>) against AIN1 data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel AIN1 {[11:4],4b0000} This value is compared (<) against AIN1 data bits[11:0]. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1.17 TEMP_THRESHOLD Register (Offset = 14h) [Reset = FF00h]

Return to the Register Map. Table 7-29. TEMP_THRESHOLD Register Field Descriptions Bit Field Type Reset Description 15-8 Hi R/W FFh High Threshold for Channel TEMP {[11:4],4b1111} This value is compared (>) against TEMP data bits[11:0]. 7-0 Lo R/W 0h Low Threshold for Channel TEMP {[11:4],4b0000} This value is compared (<) against TEMP data bits[11:0].

7.6.1.18 UBM Register (Offset = 16h) [Reset = 0000h]

Return to the Register Map. Table 7-30. UBM Register Field Descriptions Bit Field Type Reset Description 15-1 RESERVED R 0h

0 REG_MODE R/W 0h Register Mode

Configure the rest of the Register Map to be accessed by UART break mode (UBM) or SPI. This register can only be written by the UART Break communication. 0h = SPI Mode (default) 1h = UART Break Mode

7.6.1.19 SCRATCH Register (Offset = 18h) [Reset = FFFFh]

Return to the Register Map. Table 7-31. SCRATCH Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R/W FFFFh Scratch Data Data written is read back as the inverted value. For example, writing 0xAAAA is read back as 0x5555.

7.6.1.20 CHIP_ID_LSB Register (Offset = 19h)

Return to the Register Map. Table 7-32. CHIP ID LSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Unique part number within each lot

7.6.1.21 CHIP_ID_MSB Register (Offset = 1Ah)

Return to the Register Map. Table 7-33. CHIP ID MSB Register Field Descriptions Bit Field Type Reset Description 15-0 ID R Encoded lot identification number www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 65 Product Folder Links: AFE78201 AFE88201

7.6.1.22 GPIO_CFG Register (Offset = 1Bh) [Reset = 00FFh]

Return to the Register Map. Table 7-34. GPIO CONFIG Register Field Descriptions Bit Field Type Reset Description

15 RESERVED R 0h

14-8 EN R/W 00h GPIO per Pin Enable. (See Table 7-8 for additional configuration required specific to each pin and communication mode) [14] = GPIO6 [13] = GPIO5 [12] = GPIO4 [11] = GPIO3 [10] = GPIO2 [9] = GPIO1 [8] = GPIO0 0h = GPIO function disable 1h = GPIO function enabled For any pin used either for the communication function or not used as an active GPIO, set this bit to 0h.

7 RESERVED R 0h

6-0 ODE R/W FFh Pseudo Open Drain Enable GPIO output enable and pseudo open drain functionality on the GPIO pins. (See Table 7-8 for additional configuration required specific to each pin and communication mode.) [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 0h = Push-pull output enabled 1h = Pseudo open-drain output enabled

7.6.1.23 GPIO Register (Offset = 1Ch) [Reset = 007Fh]

Return to the Register Map. Table 7-35. GPIO Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 0h 6-0 DATA R/W 7Fh GPIO pin data. For GPIO input this bit must be written as 1 and GPIO_CFG.ODE = 1 and GPIO_CFG.EN = 1. Reading this register reads the pin value when the pin is correctly enabled. (See Table 7-8 for additional configuration required specific to each pin and communication mode) For GPIO output this bit sets the pin value. [6] = GPIO6 [5] = GPIO5 [4] = GPIO4 [3] = GPIO3 [2] = GPIO2 [1] = GPIO1 [0] = GPIO0 AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1.24 ALARM_STATUS_MASK Register (Offset = 1Dh) [Reset = EFDFh]

Return to the Register Map. Table 7-36. ALARM_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-14 RESERVED R 3h

13 SD_FLT R/W 1h SD Fault Mask

0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default). The status is always set if the condition exists.

12 OSC_FAIL R/W 0h OSC_FAIL Fault Mask

Same as SD Fault Mask (default 0h). 11-9 RESERVED R 7h

8 OTP_CRC_ERR R/W 1h OTP CRC Error Mask

Same as SD Fault Mask (default 1h).

7 CRC_FLT R/W 1h SPI CRC Fault Mask

Same as SD Fault Mask (default 1h).

6 WD_FLT R/W 1h Watchdog Fault Mask

Same as SD Fault Mask (default 1h).

5 VREF_FLT R/W 0h VREF Fault Mask

Same as SD Fault Mask (default 0h).

4 ADC_AIN1_FLT R/W 1h ADC AIN1 Fault Mask

Same as SD Fault Mask (default 1h).

3 ADC_AIN0_FLT R/W 1h ADC AIN0 Fault Mask

Same as SD Fault Mask (default 1h).

2 ADC_TEMP_FLT R/W 1h ADC TEMP Fault Mask

Same as SD Fault Mask (default 1h).

1 THERM_ERR_FLT R/W 1h Temperature > 130°C Error Mask

Same as SD Fault Mask (default 1h).

0 THERM_WARN_FLT R/W 1h Temperature > 85°C Warning Mask

7.6.1.25 GEN_STATUS_MASK Register (Offset = 1Eh) [Reset = FFFFh]

Return to the Register Map. Table 7-37. GEN_STATUS_MASK Register Field Descriptions Bit Field Type Reset Description 15-11 RESERVED R 1Fh

10 RBIST_DONE R/W 1h RBIST Done Mask

0h = Fault asserts IRQ 1h = The mask prevents IRQ or Alarm being triggered (default). The status is always set if the condition exists.

9 RBIST_FAIL R/W 1h RBIST Failed Fault Mask

Same as RBIST Done Mask (default 1h).

8 RESERVED R 1h

7 SR_BUSYn R/W 1h Slew Rate Not Busy Mask

Same as RBIST Done Mask (default 1h).

6 ADC_EOC R/W 1h ADC End Of Conversion Mask

Same as RBIST Done Mask (default 1h). 5-4 RESERVED R 3h

3 BREAK_FRAME_ERR R/W 1h Break Frame Error Fault Mask

Same as RBIST Done Mask (default 1h).

2 BREAK_PARITY_ERR R/W 1h Break Parity Error Fault Mask

Same as RBIST Done Mask (default 1h).

1 UART_FRAME_ERR R/W 1h UART Frame Error Fault Mask

Same as RBIST Done Mask (default 1h).

0 UART_PARITY_ERR R/W 1h UART Parity Error Fault Mask

Same as RBIST Done Mask (default 1h). AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1.26 ALARM_STATUS Register (Offset = 20h) [Reset = 0200h]

Return to the Register Map. Table 7-38. ALARM_STATUS Register Field Descriptions Bit Field Type Reset Description 15 GEN_IRQ R 0h General IRQ OR of all the unmasked bits in the GEN_STATUS register. 0h = All of the unmasked bits of the GEN_STATUS register are low 1h = At least one of the unmasked bits in the GEN_STATUS register is high

14 RESERVED R 0h

13 SD_FLT R 0h Self Diagnostic (SD) Fault

0h = All self diagnostic channels are within threshold limits 1h = At least one of the self diagnostic channels has failed 12 OSC_FAIL R 0h Oscillator Fault Oscillator failed to start. This bit holds ALARM low and does not feed IRQ. 0h = Oscillator started; 1h = Oscillator has failed to start 11-10 CRC_CNT R 0h CRC Fault Counter If counter limit ≤ 4 then bits[1:0] of the counter are shown here. If the counter limit = 8 then bits[2:1] of the counter are shown. 9 OTP_LOADEDn R 1h OTP NOT Loaded Clears when OTP has loaded at least once. Keeps ALARM asserted until OTP finishes loading. Does not feed IRQ. 0h = OTP has loaded at least once; 1h = OTP has not finished loading 8 OTP_CRC_ERR R 0h OTP CRC Error Maskable fault. An error occurred with the OTP CRC calculation. Sticky, cleared by reading register, unless condition still persist. 0h = No OTP CRC fault; 1h = OTP CRC fault 7 CRC_FLT R 0h CRC Fault Maskable fault. Invalid CRC value transmitted during SPI frame. Sticky, cleared by reading register, unless condition still persist. 0h = No CRC fault; 1h = CRC fault

6 WD_FLT R 0h Watchdog Timer Fault

Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = No watchdog fault; 1h = Watchdog fault 5 VREF_FLT R 0h Invalid Reference Voltage Maskable fault. OR with FORCE_FAIL.VREF_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Valid VREF voltage; 1h = Invalid VREF voltage 4 ADC_AIN1_FLT R 0h ADC AIN1 Fault. Maskable fault. 0h = AIN1 ADC measurement within threshold limits 1h = AIN1 ADC measurement outside threshold limits 3 ADC_AIN0_FLT R 0h ADC AIN0 Fault. Maskable fault. 0h = AIN0 ADC measurement within threshold limits 1h = AIN0 ADC measurement outside threshold limits 2 ADC_TEMP_FLT R 0h ADC Temp Fault. Maskable fault. 0h = TEMP ADC measurement within threshold limits 1h = TEMP ADC measurement outside threshold limits 1 THERM_ERR_FLT R 0h Temperature > 130°C error. Maskable fault. OR with FORCE_FAIL.THERM_ERR_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 130°C; 1h = Temperature > 130°C 0 THERM_WARN_FLT R 0h Temperature > 85°C warning. Maskable fault. OR with FORCE_FAIL.THERM_WARN_FLT bit. Active signal, set as long as condition is true. Direct input from analog circuit. 0h = Temperature ≤ 85°C; 1h = Temperature > 85°C www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 69 Product Folder Links: AFE78201 AFE88201

7.6.1.27 GEN_STATUS Register (Offset = 21h) [Reset = 1180h]

Return to the Register Map. Table 7-39. GEN_STATUS Register Field Descriptions Bit Field Type Reset Description 15 ALARM_IRQ R 0h Alarm IRQ OR of all the unmasked bits in the ALARM_STATUS register. 0h = All of the unmasked bits of the ALARM_STATUS register are low 1h = At least one of the unmasked bits in the ALARM_STATUS register is high 14-13 RESERVED R 0h 12 OTP_BUSY R 1h OTP Busy Status = 1h at power up while the OTP is being loaded into the trim latches. 0h = OTP has completed loading into the device 1h = OTP is being loaded into the device 11 RBIST_MODE R 0h Enables RBIST to run. 0h = RBIST disabled; 1h = RBIST enabled 10 RBIST_DONE R 0h RBIST Completed. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = RBIST has not completed; 1h = RBIST has completed 9 RBIST_FAIL R 0h RBIST Failed. Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = RBIST has passed; 1h = RBIST has failed 8 RESET R 1h Device Reset Occurred. Status only. Does not feed IRQ. Sticky, cleared by reading register, unless condition still persist. 0h = Device has not reset since last read of register 1h = Device has reset since last read of register 7 SR_BUSYn R 1h Slew Rate Not Busy. Maskable fault. 0h = DAC is slewing to the target code 1h = DAC_OUT has reached the DAC_DATA. If slew rate is disabled, then this signal produces a rising edge within 3 internal clock cycles. If slew rate is enabled, this signal creates an IRQ event when the DAC_OUT has reached the DAC_DATA. At this time, slew rate can be safely disabled. If slew rate is disabled prior to DAC_OUT = DAC_DATA then a jump of DAC_OUT occurs. This can cause an unwanted fast transition on VOUT. 6 ADC_EOC R 0h ADC End of Conversion (EOC). Maskable fault. Sticky, cleared by reading register, unless condition still persist. 0h = No EOC since last read of register; 1h = ADC end of conversion 5 ADC_BUSY R 0h ADC Busy. Status only. Does not feed IRQ. Active signal, set as long as condition is true. 0h = No ADC activity; 1h = ADC is actively converting 4 PVDD_HI R 0h PVDD High. Status only. Does not feed IRQ. Set as long as condition is true. 0h = PVDD < 2.7 V; 1h = PVDD ≥ 2.7V

3 BREAK_

FRAME_ERR R 0h Incorrect Stop Bit During Break Character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break frame error; 1h = Break frame error

2 BREAK_

PARITY_ERR R 0h Incorrect parity (ODD) bit during break character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No break parity error; 1h = Break parity error

1 UART_

FRAME_ERR R 0h Incorrect stop bit during UART character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART frame error; 1h = UART frame error

0 UART_

PARITY_ERR R 0h Incorrect parity (ODD) bit during UART character. Maskable fault. Applies to UARTIN. Sticky, cleared by reading register, unless condition still persist. 0h = No UART parity error; 1h = UART parity error AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

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7.6.1.28 ADC_FLAGS Register (Offset = 23h) [Reset = 0000h]

Return to the Register Map. The limits for Self Diagnostic (SD) Alarm ADC Thresholds are shown in Table 7-5. Table 7-40. ADC_FLAGS Register Field Descriptions Bit Field Type Reset Description 15-9 RESERVED R 0h

8 SD4_FAIL R 0h SD4 (VOUT) Limit Fail

7 SD3_FAIL R 0h SD3 (ZTAT) Limit Fail

6 SD2_FAIL R 0h SD2 (VDD) Limit Fail

5 SD1_FAIL R 0h SD1 (PVDD) Limit Fail

4 SD0_FAIL R 0h SD0 (VREF) Limit Fail

3 TEMP_FAIL R 0h TEMP Limit Fail

2 AIN1_FAIL R 0h AIN1 Limit Fail

1 AIN0_FAIL R 0h AIN0 Limit Fail

0 RESERVED R 0h

7.6.1.29 ADC_AIN0 Register (Offset = 24h) [Reset = 0000h]

Return to the Register Map. Table 7-41. ADC_AIN0 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN0

7.6.1.30 ADC_AIN1 Register (Offset = 25h) [Reset = 0000h]

Return to the Register Map. Table 7-42. ADC_AIN1 Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Pin AIN1

7.6.1.31 ADC_TEMP Register (Offset = 26h) [Reset = 0000h]

Return to the Register Map. Table 7-43. ADC_TEMP Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Temperature www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: AFE78201 AFE88201

7.6.1.32 ADC_SD_MUX Register (Offset = 27h) [Reset = 0000h]

Return to the Register Map. Table 7-44. ADC_SD_MUX Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h Converted Value of Voltage on Self-Diagnostic (SD) MUX Input

7.6.1.33 ADC_OFFSET Register (Offset = 28h) [Reset = 0000h]

Return to the Register Map. Table 7-45. ADC_OFFSET Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Comparator Offset This value reports the offset measured in the device, and can be used to adjust each conversion value. If ADC_BYP.OFST_BYP_EN is set, then the value in ADC_BYP.DATA is used as the offset. This value is not affected by ADC_BYP.

7.6.1.34 DAC_OUT Register (Offset = 2Ch) [Reset = 0000h]

Return to the Register Map. Table 7-46. DAC_OUT Register Field Descriptions Bit Field Type Reset Description 15-0 DATA R 0h DAC Code Applied to the Analog Circuit AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

7.6.1.35 ADC_OUT Register (Offset = 2Dh) [Reset = 0000h]

Return to the Register Map. Table 7-47. ADC_OUT Register Field Descriptions Bit Field Type Reset Description 15-12 RESERVED R 0h 11-0 DATA R 0h ADC Data for Each Conversion Does not include ADC_OFFSET.DATA adjustment. Is not affected by ADC_BYP.DATA.

7.6.1.36 ADC_BYP Register (Offset = 2Eh) [Reset = 0000h]

Return to the Register Map. ADC_BYP is shown in ADC_BYP Register Field Descriptions. Table 7-48. ADC_BYP Register Field Descriptions Bit Field Type Reset Description

15 DATA_BYP_EN R/W 0h Data Bypass Enable

Applies ADC_BYP.DATA to the ADC channel being converted. ADC_OFFSET is ignored. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. If OFST_BYP_EN is also set, DATA_BYP_EN takes priority over OFST_BYP_EN. After a channel is converted, the ADC_BYP.DATA value appears in the readback register for the converted channel and is used to calculate faults. 0h = Data bypass disabled (default) 1h = Data bypass enabled

14 OFST_BYP_EN R/W 0h Offset Bypass Enable

Overrides the offset register with the ADC_BYP.DATA value. When using this bit, the ADC_BYP.DATA field is processed as 2's complement. Do not set OFST_BYP_EN and DATA_BYP_EN at the same time. 0h = Offset bypass disabled (default) 1h = Offset bypass enabled

13 DIS_GND_SAMP R/W 0h Disable GND Sampling

This bit disables the sampling of GND during SAR activity. The sampling of GND is used to fully discharge the sampling CAP to reduce channel crosstalk. 0h = GND sampling enabled (default) 1h = GND sampling disabled

12 RESERVED R 0h

7.6.1.37 FORCE_FAIL Register (Offset = 2Fh) [Reset = 0000h]

Return to the Register Map. Force failures for fault detection. Table 7-49. FORCE_FAIL Register Field Descriptions Bit Field Type Reset Description

15 CRC_FLT R/W 0h Force CRC Failure on SDO by Inverting the CRC Byte

0h = No force failure of CRC (default) 1h = Force failure of CRC 14 VREF_FLT R/W 0h Force Reference Voltage Failure. Analog signal. 0h = No force failure of VREF (default) 1h = Force failure of VREF 13 THERM_ERR_FLT R/W 0h Force Temperature > 130°C Thermal Error. Analog signal. 0h = No force temperature > 130°C error (default) 1h = Force temperature > 130°C error 12 THERM_WARN_FLT R/W 0h Force Temperature > 85°C thermal Warning. Analog signal. 0h = No force temperature > 85°C warning (default) 1h = Force temperature > 85°C warning 11-10 RESERVED R/W 0h 9 SD4_HI_FLT R/W 0h SD4 (VOUT) High Limit Failure. ADC measurement. 0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 8 SD4_LO_FLT R/W 0h SD4 (VOUT) Low limit failure. ADC measurement. 0h = No force failure of SD4 (VOUT) (default) 1h = Force failure of SD4 (VOUT) 7 SD3_HI_FLT R/W 0h SD3 (ZTAT) High Limit Failure. ADC measurement. 0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 6 SD3_LO_FLT R/W 0h SD3 (ZTAT) Low Limit Failure. ADC measurement. 0h = No force failure of SD3 (ZTAT) (default) 1h = Force failure of SD3 (ZTAT) 5 SD2_HI_FLT R/W 0h SD2 (VDD) High Limit Failure. ADC measurement. 0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 4 SD2_LO_FLT R/W 0h SD2 (VDD) Low Limit Failure. ADC measurement. 0h = No force failure of SD2 (VDD) (default) 1h = Force failure of SD2 (VDD) 3 SD1_HI_FLT R/W 0h SD1 (PVDD) High Limit Failure. ADC measurement. 0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 2 SD1_LO_FLT R/W 0h SD1 (PVDD) Low Limit Failure. ADC measurement. 0h = No force failure of SD1 (PVDD) (default) 1h = Force failure of SD1 (PVDD) 1 SD0_HI_FLT R/W 0h SD0 (VREF) High Limit Failure. ADC measurement. 0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) 0 SD0_LO_FLT R/W 0h SD0 (VREF) Low Limit Failure. ADC measurement. 0h = No force failure of SD0 (VREF) (default) 1h = Force failure of SD0 (VREF) AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

7.6.1.38 TIMER_CFG_0 Register (Offset = 3Bh) [Reset = 0000h]

Return to the Register Map. TIMER Configuration 0. Table 7-50. TIMER CONFIG 0 Register Field Descriptions Bit Field Type Reset Description 15-4 RESERVED TO 0h 3-2 CLK_SEL R/W 0h Clock Select Selects the timer clock frequency. 0h = None (default) 1h = 1.2288 MHz 2h = 1.200 kHz 3h = 1.171 Hz

1 INVERT R/W 0h Invert Output

Invert the Timer output. By default, the output is set to 1 when the counter is ≥ SET_TIME (3Dh).

0 ENABLE R/W 0h Timer Enable

The CLK_OUT pin must also be configured to output the Timer.

7.6.1.39 TIMER_CFG_1 Register (Offset = 3Ch) [Reset = 0000h]

Return to the Register Map. TIMER Configuration 1. Table 7-51. TIMER CONFIG 1 Register Field Descriptions Bit Field Type Reset Description 15-0 PERIOD R/W 0h This field defines the period of the timer. The period is the product of (PERIOD + 1) and the clock period of CLK_SEL. For example, CLK_SEL = 2h (1200 Hz), The period is (PERIOD + 1) × 853 ms.

7.6.1.40 TIMER_CFG_2 Register (Offset = 3Dh) [Reset = 0000h]

Return to the Register Map. TIMER Configuration 2. Table 7-52. TIMER CONFIG 2 Register Field Descriptions Bit Field Type Reset Description 15-0 SET_TIME R/W 0h The SET_TIME determine when the output of the timer goes high. The bits define the duty cycle of the timer (PERIOD – SET_TIME). The timer starts out as 0 and transitions to 1 when the SET_TIME is met. The polarity of the timer can be inverted using the TIMER_CFG_0.INVERT bit. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: AFE78201 AFE88201

7.6.1.41 CRC_RD Register (Offset = 3Eh) [Reset = 0000h]

Return to the Register Map. CRC read. Table 7-53. CRC Read Register Field Descriptions Bit Field Type Reset Description 15-0 CRC R/O 0h Calculated CRC for RBIST or SHADOWLOAD. Final value is calculated internally. This value changes while RBIST or shadow load are running.

7.6.1.42 RBIST_CRC Register (Offset = 3Fh) [Reset = 0000h]

Return to the Register Map. RBIST CRC. Table 7-54. RBIST CRC Register Field Descriptions Bit Field Type Reset Description 15-0 RBIST CRC R/W 0h Calculated CRC for Register RBIST AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The AFEx8201 are extremely low-power 16-bit and 14-bit voltage output DACs. The DACs support an output range of 0 V to 2.5 V. These devices have an onboard oscillator and an optional precision internal reference. This DAC is designed for analog voltage or current output modules. These devices also feature a SAR ADC that is used to measure internal and external nodes for making diagnostic measurements with fault detection and alarm actions. Use these diagnostic measurements together with the CRC and watchdog timer monitoring for device and system monitoring for functional safety. The PVDD power supply has an operating range of 2.7 V to 5.5 V. The VDD is powered from an onboard LDO. Run the digital interface supply, IOVDD, from 1.71 V to 5.5 V.

8.1.1 Multichannel Configuration

Because CS low is required for communication and SDO can be set to a tri-state condition, only individual CS signals are required from the microcontroller for all the AFEx8201 devices in the system. The SDI, SDO, and SCLK signals can be combined. All the individual ALARM pins can be wired-OR together. This minimizes the number of microcontroller GPIO signals required for communication, as well as the number of isolation channels for isolated systems. The multichannel configuration block diagram is shown in Figure 8-1. Microcontroller AFE #1 GPIO1 SCLK DOUT DIN AFE #2 AFE #3 GPIO2 GPIO3 ALARM CS SCLK SDI SDO ALARM CS SCLK SDI SDO ALARM CS SCLK SDI SDO ALARM Figure 8-1. Multichannel Configuration www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 77 Product Folder Links: AFE78201 AFE88201

8.2 Typical Application

8.2.1 Analog Output Module

10 μF GND GND GND 3V3 GPIO5/SDI GPIO4/SDO SCLK GPIO2/UARTOUT GPIO3/UARTIN GPIO1 AIN0 POL_SEL/AIN1 NC VREFIO GPIO0/CLK_OUT GND REF_GND 3V3 GND GND 680 pF GND GND ROS 499 GND AFE88201 100 nF GND TLV333 GND VDD GND 0.1 μF GND VREFIO ALARM 100 k 680 pF AIN0 POL_SEL/ AIN1VOUT DAC_OUT SCLK CS PICO POCI RESET RESET GPIO6/CS VREFIO XTR305 VIN SET IMON NC IAOUT OD NC XTR_M2 XTR_OD 1 k1 k 1 k DAC_OUT 0.1 μFGND 47 nF DRV RG2 RG1 IAIN+ DGND PAD EFCM IAIN- EFLD 8.87 k 0.1 μF 2.2 k 2.2 k +15V –15V 0.1 μF V/I OUTPUT 0.1 μF –15V EFOT EFCM EFLD EFOT 10 k 10 k 10 k 3V3 GND GNDGND GND GND GND GND GND 1 M GND GND SCLR +15V RSET GND GPIO1 XTR_M2 XTR_OD 3V3 IOVDD PVDD REF_EN VDD Figure 8-2. AFE88201 With an XTR305 in an Analog Output Module This design example shows the construction of an analog output module capable of current and voltage outputs for a programmable logic controller (PLC). This example combines several circuit elements to create a subsystem that can support most analog output applications. This appliction requires supplies of 3.3 V and ±15 V. The circuit output sets a precision voltage or current with an accuracy of less than 0.1% full scale range (FSR) of total error at room temperature after calibration. The high integration in the system allows for a compact circuit, making this device an excellent choice for analog outputs for ac inverters and servo drives where space is a concern. Error flags and output load monitoring capability enable a robust design. Figure 8-2 shows the schematic diagram for the analog output module. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

8.2.1.1 Design Requirements

The design requirements are:

Bipolar analog output voltage range: ±11 V
Bipolar analog output current range: –25 mA to 25 mA
Operation with standard industrial automation supply voltages from 3.3 V and ±15 V
Current and voltage outputs with TUE less than 0.5% at 25°C after calibration

8.2.1.2 Detailed Design Procedure

Figure 8-3 shows a block diagram of an analog output module using the AFEx8201 and the XTR305. AFE88201 0 V to 2.5 V 1.25-V Reference RGAIN Microcontroller RLoad GND Current / Voltage Output ROS RSET (Unpopulated) VIN XTR305 SET DRV OD, M2 Set for Current or Voltage OutputGPIO Figure 8-3. Block Diagram of the Analog Output Module Using the AFEx8201 and XTR305 The AFE88201 sets an output voltage from 0 V to 2.5 V using a 16-bit code. Use the AFE78201 in this same application if 14-bit performance is required. This DAC voltage is converted to an output voltage or an output current by the XTR305. The XTR305 provides two basic functional blocks: an instrumentation amplifier (IA) and an operational amplifier (OPA) for an output driver. This application is a configurable current or voltage analog output. Figure 8-2 shows a schematic of the circuit. The AFE88201 DAC controls the XTR305, which is an industrial analog current or voltage output driver. The XTR305 takes an analog input control signal and drives a proportional analog output. The output is configured as a current output if M2 is high and M1 is low, and a voltage output if M2 and M1 are both low. The input-to-output gain of the XTR305 is set by R SET and R GAIN. The gain components in this design are selected for ±11-V or 0-mA to 25-mA output. During current-output mode, a precision current mirror generates an exact 1/10th copy of the output current, and this current is routed to the summing junction of the OPA to close the feedback loop. In voltage-output mode, the IA senses the output voltage and feeds back a current equal to 2 × V OUT / RGAIN to the summing junction of the OPA to close the feedback loop. A basic design procedure using the XTR305 as an output stage is described in the following list.

Leave RSET open for bipolar output
Select ROS for current-output transfer function
Select RGAIN for the voltage-output transfer function

8.2.1.2.1 XTR305

The XTR305 is a complete output driver for cost-sensitive industrial and process-control applications. Use the M2 pin to configure the application for current or voltage output, No external shunt resistor is required. Only external gain-setting resistors and a loop-compensation capacitor are required. The separate driver and receiver channels provide flexibility. The instrumentation amplifier can be used for remote voltage sensing or as a high-voltage, high-impedance measurement channel. In voltage-output mode, a copy of the output current is provided, allowing calculation of load resistance. The digital-output selection capability, error flags, and monitor pins make remote configuration and troubleshooting possible. Fault conditions on the output and on the IA input, as well as overtemperature conditions, are indicated by error flags. The monitoring pins provide continuous feedback about load power or impedance. In the current-output mode, a 0-V to 2.5-V control input is converted to a ±25-mA current output. As the input is unipolar, and the output is bipolar, a reference bias voltage (VREF) is required on the input stage of the XTR305. The bias voltage of 1.25 V is taken from a buffered VREFIO output from the AFE88201. Figure 8-4 shows the configuration of the XTR305 in current-output mode. IA Current Copy Digital Control Error Flags ROS RSET OPA XTR305 Input Signal VIN = 0 V to 2.5V CC GND GND VREF = 1.25V IOUT IMON VIN SET IAOUT OD EFCM EFLD EFOT DGND RG2 RG1 IAIN- IAIN+ DRV ICOPY IDRV IIA V+ V- H L H Figure 8-4. The XTR305 Standard Circuit for Current Output For current-output mode, OD is set high, M1 is set low, and M2 is set high. The normal transfer function for this circuit is given in Equation 10. IOUT = 10 × VIN RSET + VIN – V REF ROS (10) However, with the RSET resistor as an open circuit, the singular V IN term drops out. Using Equation 10, the ROS term sets the output. The transconductance gain is set by ROS according to Equation 11. ROS = 10 IoutFSR × V inFSR = 10 50 mA × 2.5 V = 500 Ω (11) AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

Select R OS = 499 Ω as a standard resistor value. This gives an I outFSR of 50.1 mA, with an output range of ±25.05 mA. The transfer function is given by Equation 12. IOUT = 10 ROS × Vin – V REF (12) Using the AFE88201, the transfer function from code to output current is shown in Equation 13. IOUT = 10 ROS × DAC_CODE × 2.5 V 216 – 1.25V (13) When using the current-output mode, the output load voltage can be monitored through an analog output For voltage-output mode, the 0-V to 2.5-V control input is translated to a ±11-V voltage output. Similar to current-output mode, a unipolar input is used to create a bipolar output. Figure 8-5 shows the configuration of the XTR305 in voltage-output mode. IA Current Copy Digital Control Error Flags ROS RSET OPA XTR305 Input Signal VIN = 0 V to 2.5V CC GND GND VREF = 1.25V IMON VIN SET IAOUT OD EFCM EFLD EFOT DGND RG2 RG1 IAIN- IAIN+ DRV ICOPY IDRV IIA V+ V- H L L RIMON GND LoadRGAIN Figure 8-5. The XTR305 Standard Circuit for Voltage Output For voltage-output mode, OD is set high, while M1 and M2 are set low. The normal transfer function for this circuit is given in Equation 14. VOUT = RGAIN 2 × VIN RSET + VIN – V REF ROS (14) Again, with R SET as an open circuit, the singular V IN term drops out. The gain is set by R OS and R GAIN as per Equation 15. RGAIN = 2 × V outFSR × R OS VinFSR = 2 × 22 × 499 2.5 = 8782 Ω (15) www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 81 Product Folder Links: AFE78201 AFE88201

Select RGAIN = 8870 Ω, which gives a V outFSR of 22.22 V, with an output range of ±11.11 V The transfer function is given by Equation 16. VOUT = RGAIN 2 × VIN – V REF ROS (16) Using the AFE88201, the transfer function from code to output voltage is shown in Equation 17. VOUT = RGAIN 2 × R OS × DAC_CODE × 2.5 V 216 – 1.25V (17) When using the voltage-output mode, the output load current can be monitored through an analog output the XTR305 has several additional diagnostic features. IA Common-Mode Overvoltage Range (EF CM): This flag goes low as soon as the input of the IA reach the limits of the linear operation for the input voltage. Overtemperature Flag (EFOT): This flag goes low if the chip temperature reaches 140°C and resets as soon as the temperature cools down to less than 125°C. Load Error (EFLD): Indicates fault conditions driving voltage or current into the load. In voltage-output mode, the device monitors the voltage limits of the output swing and the current limit condition caused from short or low load resistance. In current-output mode, the alarm indicates a saturation into the supply rails from a high-load resistance or open load. The fault flag helps detect whether the analog output wire is broken or shorted. This feature improves the reliability of the analog output function. In case of a short-circuited load, the output current is limited to ±20 mA in voltage-output mode, and ±32 mA in the current-output mode. All three fault flags are open collector, and therefore require pullup resistors. Analog Output Monitor : In current-output mode, the IA output is connected to a resistor through the IAOUT pin and the IMON pin is internally disconnected. IAOUT is proportional to the output voltage given by Equation 18. This current is converted into voltage across a 500 ‑Ω resistor that can be sensed by the ADC on the AFEx8201. This current measurement enables a monitor of the output power delivered to the load. If the load resistance is known, then the output current can be calculated and compared with the commanded value. IAOUT = 2 × V OUT RGAIN (18) During voltage-output mode, 1/10th of the output drive current is mirrored onto the IMON pin and IAOUT is internally disconnected. The IMON pin is connected to a 1-kΩ resistor. The voltage across this resistor is sensed by the ADC on the AFE88201. If the output load is known, then the output voltage can be calculated and compared with the commanded value. The output power delivered to the load can also be calculated. Output monitor functions help detect load changes enabling predictive maintenance, which increase reliability of the analog output function. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

8.2.1.3 Application Curves

Figure 8-6. DAC Code to XTR Output Current Figure 8-7. DAC Code to XTR Output Voltage www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 83 Product Folder Links: AFE78201 AFE88201

8.3 Initialization Setup

This section describes several recommendations to set up the AFEx8201. The AFEx8201 power up with the CRC enabled. If the device is intended to be run without the CRC, the CRC must be disabled by setting the CRC_EN bit to 0h in the CONFIG register. Be aware that the command to write to this register is first done with the CRC enabled. The CRC byte must be appended to the command for the device to interpret the command correctly. To disable the CRC after start up, write 0x02 0x00 0x26 0x24 to the device. The first three bytes write the command, while the last byte is the CRC byte. For more information on the CRC, see the communication description in Section 7.5.3.3. The AFEx8201 also power up with the SDO pin disabled. The SDO pin is required for reading from any of the device registers, as well as reading any data from the ADC in SPI mode. The SDO pin is enabled by writing 0h To enable the ADC, first enable the ADC buffer by writing 0h into the BUF_PD bit in the ADC_CFG register. For information about using the ADC in different modes of operation, see Section 7.3.2. AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

8.4 Power Supply Recommendations

The AFEx8201 can operate within a single-supply range of 2.7 V to 5.5 V applied to the PVDD pin. When 2.7 V to 5.5 V is provided to PVDD, an internal LDO is enabled that drives VDD internally. VDD pin must have 1 μF to 10 μF of capacitance for operation. The digital interface supply, IOVDD, can operate with a supply range of 1.71 V to 5.5 V. Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes. This noise can easily couple into the DAC output voltage or current through various paths between the power connections and analog output. To further reduce noise, include bulk and local decoupling capacitors. The current consumption on the PVDD and IOVDD pins, the short-circuit current limit for the voltage output, and the current ranges for the current output are listed in the Electrical Characteristics. The power supply must meet the requirements listed in the Recommended Operating Conditions.

8.5 Layout

8.5.1 Layout Guidelines

To maximize the performance of the AFEx8201 in any application, follow good layout practices and proper circuit design. The following recommendations are specific to the device:

For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane is not always practical. If ground-plane separation is necessary, make a direct connection of the planes at the DAC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops.
IOVDD and PVDD must have 100-nF decoupling capacitors local to the respective pins. VDD must have at least a 1-μF decoupling capacitor used for the internal LDO. Use a high-quality ceramic-type NP0 or X7R capacitor for best performance across temperature and a very low dissipation factor.
Place a 100-nF reference capacitor close to the VREFIO pin.
Avoid routing switching signals near the reference input.
Maintain proper placement for the digital and analog sections with respect to the digital and analog components. Separate the analog and digital circuitry for less coupling into neighboring blocks and to minimize the interaction between analog and digital return currents.
For designs that include protection circuits: – Place diversion elements, such as TVS diodes or capacitors, close to off-board connectors to make sure that return current from high-energy transients does not cause damage to sensitive devices – Use large, wide traces to provide a low-impedance path to divert high-energy transients away from the I/O pins. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 85 Product Folder Links: AFE78201 AFE88201

8.5.2 Layout Example

GPIO3/UART_IN GPIO2/UART_OUT GPIO1 SCLR REF_EN RESET SCLK GPIO5/SDI GPIO4/SDO GPIO6/CS CLK_OUT IOVDD Digital Signals IOVDD IOVDD Bypass Capacitor VDD Bypass Capacitor PVDD PVDD Bypass Capacitor ALARM Pullup Resistor IOVDD ALARM NC GND GND REF_GND VREFIO VOUT VREFIO Bypass Capacitor PVDD POL_SEL/AIN1 AIN0 GND VDD AFEx8201 Figure 8-8. Layout Example AFE78201, AFE88201 SLASF44 – MAY 2023 www.ti.com

Product Folder Links: AFE78201 AFE88201

9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, AFE882H1 Evaluation Module User's Guide
Texas Instruments, REF35 Ultra Low-Power, High-Precision Voltage Reference data sheet
Texas Instruments, XTR305 Industrial Analog Current or Voltage Output Driver data sheet
Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and Reference data sheet
Texas Instruments, TPS7A16 60-V, 5-µA IQ, 100-mA, Low-Dropout Voltage Regulator With Enable and Power-Good data sheet
Texas Instruments, TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response data sheet
Texas Instruments, ISO7021 Ultra-Low Power Two-Channel Digital Isolator data sheet
Texas Instruments, Isolated, Ultra-Low Power Design for 4- to 20-mA Loop Powered Transmitters design guide
Texas Instruments, Isolated Loop Powered Thermocouple Transmitter design guide
Texas Instruments, Small Form Factor, 2-Wire, 4- to 20-mA Current-Loop, RTD Temperature Transmitter design guide
Texas Instruments, Isolated Power and Data Interface for Low-power Applications reference design
Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power Applications design guide

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com AFE78201, AFE88201 SLASF44 – MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 87 Product Folder Links: AFE78201 AFE88201

www.ti.com 22-Jan-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples AFE78201RRUR ACTIVE UQFN RRU 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 AFE 78201 Samples AFE78201RRUT ACTIVE UQFN RRU 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 AFE 78201 Samples AFE88201RRUR ACTIVE UQFN RRU 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 AFE 88201 Samples AFE88201RRUT ACTIVE UQFN RRU 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -55 to 125 AFE 88201 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

www.ti.com 22-Jan-2024 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jan-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-Jan-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE78201RRUR UQFN RRU 24 3000 367.0 367.0 35.0 AFE78201RRUT UQFN RRU 24 250 210.0 185.0 35.0 AFE88201RRUR UQFN RRU 24 3000 367.0 367.0 35.0 AFE88201RRUT UQFN RRU 24 250 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE 4.1 3.9 4.1 3.9 0.7 0.6 0.01 0.00 2X 2.5 20X 0.5 2X 2.5 24X 0.6 0.4 24X 0.3 0.2 (0.2) TYP 24X (0.18) (0.1) TYP (0.663) (0.25) UQFN - 0.7 mm max heightRRU0024A PLASTIC QUAD FLATPACK - NO LEAD 4225850/A 04/2020 0.08 C

0.1 C A B

0.05 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA 0.05 C SEATING PLANE 0.01 C PIN 1 ID SYMM SYMM 7 12 1924 7X (45 X 0.087) SCALE 3.000 AB C

www.ti.com EXAMPLE BOARD LAYOUT 20X (0.5) (R0.05) TYP

0.05 MAX

0.05 MIN

24X (0.7) 24X (0.25) (3.7) (3.7) UQFN - 0.7 mm max heightRRU0024A PLASTIC QUAD FLATPACK - NO LEAD 4225850/A 04/2020 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SEE SOLDER MASK DETAIL 7 12 1924 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 24X (0.7) 24X (0.25) 20X (0.5) (3.7) (3.7) (R0.05) TYP UQFN - 0.7 mm max heightRRU0024A PLASTIC QUAD FLATPACK - NO LEAD 4225850/A 04/2020 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X SYMM SYMM 7 12 1924

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Product Information

AFE78201RRUT specifications and overview.

Summary

AFEx8201 16-Bit and 14-Bit Digital-to-Analog Converters (DACs) With Voltage Reference and Diagnostic ADC for Low-Power Applications MAY 2023

Description

AFEx8201 16-Bit and 14-Bit Digital-to-Analog Converters (DACs) With Voltage Reference and Diagnostic ADC for Low-Power Applications MAY 2023

Source title AFE78201RRUT Datasheet(PDF) - Texas Instruments

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