AFE7222 TI1 | Alldatasheet
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Analog FrontEnd Wideband Mixed-SignalTransceiver Check forSamples: AFE7222 ,AFE7225
1 INTRODUCTION
1.1 FEATURES
– TX Path Interpolationby 2 or 4• AFE7225 – RX Path Decimationby 2– Dual 12-Bit250MSPS TX DACs – 3.0V/1.8VSupplies,Low Power– Dual 12-Bit125MSPS RX ADCs – FastWakeup Modes forHalf-Duplex• AFE7222 – Coarse or FineDigitalMixer– Dual 12-Bit130MSPS TX DACs – QuadratureModulationCorrections– Dual 12-Bit65MSPS RX ADCs – Clock InputDivide/Multiply• OPTIONS – SerialLVDS or InterleavedParallelCMOS– Dual 12-BitAuxiliaryDACs Interface– Dual Input12-BitAuxiliaryADC – 64-PinQFN Package (9mm × 9mm)
1.2 APPLICATIONS
- Portable,Low Power Radio
- WirelessInfrastructure
- Point-to-PointRadio
- Pico-CellBTS
1.3 DESCRIPTION
The AFE7225/7222 isan analogfrontend designedforfull-orhalf-duplexradios.Over-samplingtransmit 12-bitDACs provideoutputfrequenciesfrom baseband toNyquist.Under-samplingreceive12-bitADCs allowanaloginputsfrombaseband to~230MHz. Most blockswithintheAFE7225/7222 areindependently controlledforoptimizationofpower consumptionversusutilization.Two auxiliarycontrol12-bitDACs and a dualinputauxiliarymonitoring12-bitADC areavailableviaserialinterface.DigitalfeaturesincludeQMC (quadraturemodulationcorrection),interpolation,decimation,RMS/peak power meter and mixerswith independentNCOs forRX and TX path. The AFE7225/7222 isavailableina 64-pin9x9mm QFN package (RGC). The AFE7225/7222 isbuilton Texas Instrument’s low power analogCMOS processand isspecifiedoverthefullindustrialtemperature range(–40°C to85°C). Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2011–2012,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.
SPI Interface, Registers and Control QMC Offset ±Fs/4 Coarse Mixer ±Fs/4 Coarse Mixer RX RMS / Peak Power MeterClock Divide/Multiply INP_A_ADC Serial LVDS or Parallel CMOS Serial LVDS or Parallel CMOS (8 deep FIFO) 12b RX ADC B 12b TX DAC A 12b TX DAC B IOUTP_A_DAC QMC Gain/ Phase Internal Reference 12b Aux DAC SYNC SYNC SYNC SYNC SYNC SYNC 12b RX ADC A 2x HBF Interpolation 2x HBF Interpolation /2 HBF Decimation INN_A_ADC INP_B_ADC INN_B_ADC CLKINP CLKINN IOUTN_A_DAC IOUTP_B_DAC IOUTN_B_DAC AUXDAC_A VCM AVDD3_DAC = 3 V 12b Aux DAC 12b Aux ADC AUXDAC_B AUXADC_A AUXADC_B PDN SYNC SEN SCLK SDATA SDOUT BIASJ RESET DVDD18_DAC = 1.8 V AVDD18_ADC = 1.8 V DVDD18 = 1.8 V AVDD3_AUX = 3 V DVDD18_CLK = 1.8 V SYNC SYNC SYNC QMC Offset SYNC Inverse SINC QMC Gain/ Phase SYNC 12-Bit ADC Outputs 12-Bit DAC Inputs ADC CLK DAC CLK Fine Mixer SYNC NCO SYNC Fine Mixer NCO SYNC Thermal Pad = Ground SYNC AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.
1.4 DETAILED BLOCK DIAGRAM
Figure1-1.Block Diagram ofAFE7222/AFE7225
2 INTRODUCTION Copyright© 2011–2012,Texas InstrumentsIncorporated
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AVDD3_AUX SCLK SDATA VCM INP_A_ADC INN_A_ADC CLKINP DVDD18_CLK 1617 18 19 20 21 22 23 24 3231302928272625 63 62 61 60 59 58 57 56 49 5052535455 5164
64 QFN
INP_B_ADC INN_B_ADC ADCDATA0 ADCDATA1 ADCDATA2 ADCDATA6 AVDD18_ADCAVDD18_ADC ADCDATA7 ADCDATA8 ADCDATA9 DVDD18 ADCDATA3 ADCDATA4 DVDD18 ADC_DCLKOUT DACDATA4 DAC_DCLKIN ADCDATA10 ADCDATA11 SYNCIN DACDATA0 DACDATA11 BIASJ AUXADC_A AUXADC_B DVDD18_DAC IOUTP_A_DAC AVDD3_DAC AUXDAC_A AUXDAC_B IOUTN_A_DAC IOUTP_B_DAC IOUTN_B_DAC AVDD3_DAC AVDD18_ADC CLKINN AVDD18_ADC DACDATA3 Thermal pad connected to ground 64-QFN (Top View) DACDATA10 DACDATA9 DACDATA8 DACDATA7 DACDATA6 DVDD18 DACDATA5 ADCDATA5 AVDD3_DAC AVDD18_ADC AVDD18_ADC AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
2 DEVICE INFORMATION
2.1 PACKAGE/ORDERING INFORMATION
SPECIFIED TRANSPORTPACKAGE PACKAGE ORDERINGPRODUCT PACKAGE-LEAD TEMPERATURE MEDIA,DESIGNATOR MARKING NUMBERRANGE QUANTITY AFE7222IRGCT Tape and Reel AFE7222 QFN-64 RGC –40°C to85°C AFE7222I AFE7222IRGCR Tape and Reel AFE7222IRGC25 Tape and Reel AFE7225IRGCT Tape and Reel AFE7225 QFN-64 RGC –40°C to85°C AFE7225I AFE7225IRGCR Tape and Reel AFE7225IRGC25 Tape and Reel
2.2 DEVICE PINOUT, CMOS INPUT/OUTPUT MODE
Figure2-1.Device Pinout,CMOS Input/OutputMode Copyright© 2011–2012,Texas InstrumentsIncorporated DEVICE INFORMATION 3 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Table2-1.Pin Configuration:CMOS Input/OutputMode PIN
DESCRIPTION
NO. NAME 1 AVDD18_ADC 1.8VsupplyforRX ADCs
2 INN_B_ADC RX ADC channelB analoginput,negative
3 INP_B_ADC RX ADC channelB analoginput,positive
4 AVDD18_ADC 1.8VsupplyforRX ADCs
5 INN_A_ADC RX ADC channelA analoginput,negative
6 INP_A_ADC RX ADC channelA analoginput,positive
7 AVDD18_ADC 1.8VsupplyforRX ADCs
8 CLKINN main clockinput,negativesideifdifferentialmode, TX sideifsingle-ended2 clockmode
9 CLKINP main clockinput,positivesideifdifferentialmode, RX sideifsingle-ended2 clockmode
10 DVDD18_CLK 1.8VsupplyforClockingcircuit
11 AVDD3_DAC 3V supplyforTX DACs
12 IOUTP_A_DAC TX DAC channelA currentoutput,positive(currentsinkDACs)
13 IOUTN_A_DAC TX DAC channelA currentoutput,negative(currentsinkDACs)
14 AVDD3_DAC 3V supplyforTX DACs
15 IOUTP_B_DAC TX DAC channelB currentoutput,positive(currentsinkDACs)
16 IOUTN_B_DAC TX DAC channelB currentoutput,negative(currentsinkDACs)
17 AVDD3_DAC 3V supplyforTX DACs
setstheTX DAC outputcurrent(resistorfrompintoground).Use 960 Ohm toseta fullscalecurrentof18 BIASJ 20 mA. 19 DVDD18_DAC 1.8VDAC digitalsupply 20 AUXDAC_A auxiliaryDAC channelA output,currentsourcingup to7.5mA (SPIprogrammable) 21 AUXDAC_B auxiliaryDAC channelB output,currentsourcingup to7.5mA (SPIprogrammable)
22 AVDD3_AUX 3V supplyforauxiliaryADC/DACs
23 AUXADC_A auxiliaryADC channelA input
24 AUXADC_B auxiliaryADC channelB input
25 AVDD18_ADC 1.8VsupplyforRX ADCs
26 DACDATA11 CMOS datainputforTX data,MSB ofTX DACs
27 DACDATA10 CMOS datainputforTX data
28 DACDATA9 CMOS datainputforTX data
29 DACDATA8 CMOS datainputforTX data
30 DACDATA7 CMOS datainputforTX data
31 DACDATA6 CMOS datainputforTX data
32 DVDD18 1.8Vsupplyfordigitalinterface
33 DACDATA5 CMOS datainputforTX data
34 DAC_DCLKIN CMOS clockinputforTX data.Send clockwithdata.
35 DACDATA4 CMOS datainputforTX data
36 DACDATA3 CMOS datainputforTX data
37 DACDATA2 CMOS datainputforTX data
38 DACDATA1 CMOS datainputforTX data
39 DACDATA0 CMOS datainputforTX data.LSB ofTX DACs 40 SYNCIN CMOS syncinput.Used toresetinternalclockdividersand resetTX dataFIFO pointer 41 DVDD18 1.8Vsupplyfordigitalinterface
42 ADCDATA11 CMOS dataoutputforRX data,MSB ofRX ADCs
43 ADCDATA10 CMOS dataoutputforRX data
44 ADCDATA9 CMOS dataoutputforRX data
45 ADCDATA8 CMOS dataoutputforRX data
46 ADCDATA7 CMOS dataoutputforRX data
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Table2-1.Pin Configuration:CMOS Input/OutputMode (continued) PIN NO. NAME
47 ADC_DCLKOUT CMOS clockoutputforRX data
48 ADCDATA6 CMOS dataoutputforRX data
49 DVDD18 1.8Vsupplyfordigitalinterface
50 ADCDATA5 CMOS dataoutputforRX data
51 ADCDATA4 CMOS dataoutputforRX data
52 ADCDATA3 CMOS dataoutputforRX data
53 ADCDATA2 CMOS dataoutputforRX data
54 ADCDATA1 CMOS dataoutputforRX data
55 ADCDATA0 CMOS dataoutputforRX data,LSB ofRX ADCs
Can be programmed as globalpowerdown (deepsleep),fastrecoverypowerdown (lightsleep)orTX/RX56 PDN switch.Activehigh. 57 SEN SPI enable(1.8VCMOS) 58 SDATA SPI datainput(1.8VCMOS) 59 SCLK SPI clockinput(1.8VCMOS) 60 SDOUT SPI dataoutput(1.8VCMOS) 61 RESET ResettheSPI.Activehigh(1.8VCMOS). 62 AVDD18_ADC 1.8VsupplyforRX ADCs Common mode voltageoutput.Outputstheidealcommon mode inputvoltagefortheADC. Nominally63 VCM around0.95V. 64 AVDD18_ADC 1.8VsupplyforRX ADCs Thermal VSS Connectthermalpad totheboardgroundpad Copyright© 2011–2012,Texas InstrumentsIncorporated DEVICE INFORMATION 5 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
AVDD3_AUX SCLK SDATA VCM INP_A_ADC INN_A_ADC CLKINP DVDD18_CLK 1617 18 19 20 21 22 23 24 333231302928272625 63 62 61 60 59 58 57 56 49 5052535455 5164 QFN AVDD18_ADC DACB_DATA_1N DACB_DATA_1P PDN INP_B_ADC INN_B_ADC ADCA_DATA_1P ADCA_DATA_1N ADCA_DATA_0P NC ADC_FCLKOUTN ADCB_DATA_0P ADCB_DATA_0N DVDD18 ADCA_DATA_0N ADC_DCLKOUTP DVDD18 ADC_FCLKOUTP DACB_DATA_0P DAC_DCLKINN ADCB_DATA_1P ADCB_DATA_1N SYNCINN SYNCINP DACA_DATA_1P BIASJ AUXADC_A AUXADC_B AVDD18_ADC IOUTP_A_DAC AUXDAC_A AUXDAC_B IOUTN_A_DAC IOUTP_B_DAC IOUTN_B_DAC AVDD3_DAC AVDD18_ADC AVDD3_DAC AVDD18_ADC AVDD18_ADCAVDD18_ADC CLKINN DACB_DATA_0N Thermal pad connected to ground DACA_DATA_1N DACA_DATA_0P DACA_DATA_0N DAC_FCLKINP DAC_FCLKINN DVDD18 DAC_DCLKINP ADC_DCLKOUTN AVDD3_DAC DVDD18_DAC 64-QFN (Top View) AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com
2.3 DEVICE PINOUT, LVDS INPUT/OUTPUT MODE
Figure2-2.Device Pinout,LVDS Input/OutputMode Table2-2.Pin Configuration:LVDS Input/OutputMode PIN NO. NAME 1 AVDD18_ADC 1.8VsupplyforRX ADCs 4 AVDD18_ADC 1.8VsupplyforRX ADCs 7 AVDD18_ADC 1.8VsupplyforRX ADCs
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Table2-2.Pin Configuration:LVDS Input/OutputMode (continued) PIN NO. NAME 10 DVDD18_CLK 1.8VsupplyforClockingcircuit setstheTX DAC outputcurrent(resistorfrompintoground).Use 960 Ohm toseta fullscalecurrentof18 BIASJ 20 mA. 19 DVDD18_DAC 1.8VDAC digitalsupply 20 AUXDAC_A auxiliaryDAC channelA output,currentsourcingup to7.5mA (SPIprogrammable) 21 AUXDAC_B auxiliaryDAC channelB output,currentsourcingup to7.5mA (SPIprogrammable) 25 AVDD18_ADC 1.8VsupplyforRX ADCs 26,27 LVDS Wire1 datainputforChannelA TX data– inactivein1-wiremode, LSB bytein2-wiremode
26 DAC_DATA_11 Positive
27 DAC_DATA_10 Negative
28,29 LVDS Wire0 datainputforChannelA TX data– activein1-wiremode, MSB bytein2-wiremode
28 DAC_DATA_9 Positive
29 DAC_DATA_8 Negative
30,31 LVDS frameclockinput
30 DAC_FCLKINP Positive
31 DAC_FCLKINN Negative
32 DVDD18 1.8Vsupplyfordigitalinterface 33,34 LVDS bitclockinput
33 DAC_DCLKINP Positive
34 DAC_DCLKINN Negative
35,36 LVDS Wire0 datainputforChannelB TX data– activein1-wiremode, LSB bytein2-wiremode
35 DACB_DATA_0P Positive
36 DACB_DATA_0N Negative
37,38 LVDS Wire1 datainputforChannelB TX data– inactivein1-wiremode, MSB bytein2-wiremode
37 DACB_DATA_1P Positive
38 DACB_DATA_1N Negative
39,40 LVDS SYNC input– Used toresetinternalclockdividersand resetTX dataFIFO pointer
39 SYNCINP Positive
40 SYNCINN Negative
41 DVDD18 1.8Vsupplyfordigitalinterface 42,43 LVDS Wire1 dataoutputforChannelB RX data– inactivein1-wiremode, MSB bytein2-wiremode
42 ADCB_DATA_1N Positive
43 ADCB_DATA_1P Negative
44,45 LVDS Wire0 dataoutputforChannelB RX data– activein1-wiremode, LSB bytein2-wiremode
44 ADCB_DATA_0N Positive
45 ADCB_DATA_0P Negative
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SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Table2-2.Pin Configuration:LVDS Input/OutputMode (continued) PIN NO. NAME 46,47 LVDS frameclockoutput
46 ADC_FCLKOUTN Positive
47 ADC_FCLKOUTP Negative
48 NC No Connect
49 DVDD18 1.8Vsupplyfordigitalinterface 50,51 LVDS bitclockoutput
50 ADC_DCLKOUTN Positive
51 ADCDCLKOUTP Negative
52,53 LVDS Wire0 dataoutputforChannelA RX data– activein1-wiremode, MSB bytein2-wiremode
52 ADCA_DATA_0N Positive
53 ADCA_DATA_0P Negative
54,55 LVDS Wire1 dataoutputforChannelA RX data– inactivein1-wiremode, LSB bytein2-wiremode
54 ADCA_DATA_1N Positive
55 ADCA_DATA_1P Negative
Can be programmed as globalpowerdown (deepsleep),fastrecoverypowerdown (lightsleep)orTX/RX56 PDN switch.Activehigh. 57 SEN SPI enable(1.8VCMOS) 58 SDATA SPI datainput(1.8VCMOS) 59 SCLK SPI clockinput(1.8VCMOS) 60 SDOUT SPI dataoutput(1.8VCMOS) 61 RESET ResettheSPI.Activehigh(1.8VCMOS). 62 AVDD18_ADC 1.8VsupplyforRX ADCs Common mode voltageoutput.Outputstheidealcommon mode inputvoltagefortheADC. Nominally63 VCM around0.95V. 64 AVDD18_ADC 1.8VsupplyforRX ADCs Thermal VSS Connectthermalpad totheboardgroundpad
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3 ELECTRICAL SPECIFICATIONS
3.1 ABSOLUTE MAXIMUM RATINGS (1)
overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Supplyvoltagerange,*VDD3* –0.3 3.6 V Supplyvoltagerange,*VDD18* –0.3 2.1 V Voltagebetweeen *VDD3* to*VDD18* –2.4 3.9 V INP_A_ADC, INM_A_ADC, INP_B_ADC, INM_B_ADC, AUXADC_A, AUXADC_B, CLKINN, CLKINP –0.3 2.1 V RESET, SCLK, SDATA SEN –0.3 3.9 V DAC*_DATA_nP/M, DAC_DCLK –0.3 2.1 V TA Operatingfree-airtemperaturerange –40 85 °C TJ Operatingjunctiontamperaturerange 125 °C Tstg Storagetemperaturerange –65 150 °C ESD ratingHuman Body Model (HBM) 2 kV (1) Stressesbeyond thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunderrecommended operating conditionsisnotimplied.Exposuretoabsolutemaximum ratedconditionsforextendedperiodsmay affectdevicereliability.
3.2 THERMAL INFORMATION
THERMAL METRIC RGC PACKAGE UNITS
64 PINS
θJA Junction-to-ambientthermalresistance 22.8 θJCtop Junction-to-case(top)thermalresistance 6.7 θJB Junction-to-boardthermalresistance 2.3 °C/W ψJT Junction-to-topcharacterizationparameter 0.1 ψJB Junction-to-boardcharacterizationparameter 2.2 θJCbot Junction-to-case(bottom)thermalresistance 0.2
3.3 RECOMMENDED OPERATING CONDITIONS
overoperatingfree-airtemperaturerange(unlessotherwisenoted) AFE7222 AFE7225 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Common mode voltageat VCM-0.05 VCM VCM+0.05 VCM –0.05 VCM VCM+0.05 VADC inputpins Common mode voltageat AVDD3 AVDD3 VDAC outputpins ADC_CLK speed(1) 2.5(2) 65 2.5(2) 125 MSPS DAC_CLK speed(1) 1 130 1 250 MSPS (1) See Table10-1and Table10-2forcorrespondingmaximum interfacerates. (2) Minimum ADC_CLK speed can be reducedto0.8MSPS by writingthefollowingserialinterfaceregisters:
- Registeraddress0x208,value0x8
- Registeraddress0x4,value0x8 Copyright© 2011–2012,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 9 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
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3.4 SUPPLY CHARACTERISTICS
IOUTFS=20mA, typicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, unlessotherwisenoted. PARAMETER TEST CONDITIONS AFE7225 POWER IN LVDS MODE Dual RX ADC, Dual TX DAC withInterpolateby 2, 2-wireLVDS interface FADCCLK = 125 MSPS UNIT fADCIN = 10 MHz FDACCLK = 250 MSPS fDACOUT = 10 MHz MIN TYP MAX Power dissipation,fullduplexmode RX and TX active,No inputsignalappliedon ADC and DAC 577 650 mW AVDD18_ADC, RX and TX active,No inputsignalappliedon ADC and DAC 115 DVDD18, RX and TX active,No inputsignalappliedon ADC and DAC 95 DVDD18_CLK, RX and TX active,No inputsignalappliedon ADC and DAC 12 Supplycurrent,fullduplexmode mA DVDD18_DAC, RX and TX active,No inputsignalappliedon ADC and DAC 7 AVDD3_DAC, RX and TX active,No inputsignalappliedon ADC and DAC 48 AVDD3_AUX, RX and TX active,No inputsignalappliedon ADC and DAC 7 Power dissipation,halfduplexRX RX active,TX inlightsleep,TX clockisoff,No inputsignalappliedon ADC and 362 417 mWmode DAC Power dissipation,halfduplexTX TX active,RX inlightsleep,RX clockison,No inputsignalappliedon ADC 419 482 mWmode and DAC Globalpowerdown enabled 12 40 Power dissipationinSleepmodes Fastrecoverypowerdown enabled,TX/RX sleeping,clockson 215 246 mW Fastrecoverypowerdown enabled,TX/RX sleeping,TX clockoff,RX clockon 177 231 PARAMETER TEST CONDITIONS AFE7222/AFE7225 POWER IN CMOS MODE Dual RX ADC, Dual TX DAC withInterpolateby 2, CMOS interface FADCCLK = 65 MSPS UNIT fADCIN = 10 MHz FDACCLK = 130 MSPS fDACOUT = 10 MHz MIN TYP MAX Power (AVDD18_ADC, 326 391 mWDVDD18_CLK, DVDD18_DAC,RX and TX active,No inputsignalappliedon AVDD3_DAC, AVDD3_AUX)Power dissipation,fullduplexmode ADC and DAC DigitalPower (1)(DVDD18) 72 mW TotalPower 398 mW AVDD18_ADC, RX and TX active,No inputsignalappliedon ADC and DAC 77 DVDD18, RX and TX active,No inputsignalappliedon ADC and DAC 40 DVDD18_CLK, RX and TX active,No inputsignalappliedon ADC and DAC 9 Supplycurrent,fullduplexmode mA DVDD18_DAC, RX and TX active,No inputsignalappliedon ADC and DAC 4 AVDD3_DAC, RX and TX active,No inputsignalappliedon ADC and DAC 48 AVDD3_AUX, RX and TX active,No inputsignalappliedon ADC and DAC 7 Power (AVDD18_ADC, 176 211DVDD18_CLK, DVDD18_DAC,Power dissipation,halfduplexRX RX active,TX inlightsleep,TX clockisoff, AVDD3_DAC, AVDD3_AUX) mWmode No inputsignalappliedon ADC and DAC DigitalPower(1)(DVDD18) 36 TotalPower 212 Power (AVDD18_ADC, 235 282DVDD18_CLK, DVDD18_DAC,Power dissipation,halfduplexTX TX active,RX inlightsleep,RX clockison, AVDD3_DAC, AVDD3_AUX) mWmode No inputsignalappliedon ADC and DAC DigitalPower(1)(DVDD18) 56 TotalPower 291 (1) These numbers belongtono-loadcapacitancepresenton board.The maximum DVDD18 currentwithCMOS interfacedepends on the actualloadcapacitanceon thedigitaloutputlines.
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3.5 SUPPLY CHARACTERISTICS (Continued)
IOUTFS=20mA, typicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, unlessotherwisenoted. PARAMETER TEST CONDITIONS AFE7222/AFE7225 POWER IN CMOS MODE Dual RX ADC, Dual TX DAC withInterpolateby 2, CMOS interface FADCCLK = 65 MSPS UNIT fADCIN = 10 MHz FDACCLK = 130 MSPS fDACOUT = 10 MHz MIN TYP MAX Globalpowerdown enabled 12 40 Power dissipationinSleepmodes Fastrecoverypowerdown enabled,TX/RX sleeping,clockson 140 165 mW Fastrecoverypowerdown enabled,TX/RX sleeping,TX clockoff,RX clockon. 120 165 Power Up and Power Down Time inDifferentModes Differentialinputclock 25 Globalpowerdown,RX recoverytime µs Single-endedinputclock 20 Globalpowerdown inLow power RX Differentialinputclock 25 CMOS mode, RX recoverytime(ADC µs Single-endedinputclock 13runningatlessthan40 MSPS) Differentialinputclock 25 Globalpowerdown,TX recoverytime µs Single-endedinputclock 4 RX recoverytimeinfastrecovery RX clockisON duringpowerdown 5 µsmode TX recoverytimeinfastrecovery 4 µsmode RX recoverytimefromRX RX clockison duringpowerdown 5 µs powerdown TX recoverytimefromTX powerdown 4 µs Copyright© 2011–2012,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 11 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
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3.6 RX ADC ELECTRICAL CHARACTERISTICS
TypicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, suppliesatnominalvoltages,50% clock dutycycle,LVDS outputinterface,–1dBFS differentialinput,unlessotherwisenoted. AFE7222 AFE7225 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Maximum Clock Rate 65 125 MSPS Resolution 12 12 bits ANALOG INPUTS Differentialinputrange 2 2 Vpp VCM Common mode outputvoltage 0.95 0.95 V Inputresistance(DC) Differential >1 >1 M Ω Inputcapacitance Differential 4 4 pF Analoginputbandwidth 550 550 MHz CMRR Common mode rejectionratio Fin= 10MHz 40 40 dB DYNAMIC ACCURACY Offseterror –15 2 15 –15 3 15 mV Offsettemperatureco-efficient >0.005 >0.005 mV/°C Gain erroras a resultofinternalreference –2.5 2.5 –2.5 2.5 %FSinaccuracyalone– EGREF Gain errorofchannelalone– EGCHAN ±1 ±1 %FS DYNAMIC AC CHARACTERISTICS Fin= 10MHz 67.5 70.5 67 70.7 dBFS SNR Signal-to-noiseratio(1) Fin= 70MHz 70 70.1 dBFS Fin= 140MHz 68.7 69.5 dBFS Fin= 10MHz 73 85 73 84 dBc SFDR Spuriousfreedynamicrange(1) Fin= 70MHz 81 79 dBc Fin= 140MHz 77 76 dBc (1) Up to65MSPS typicalSNR and SFDR performanceinCMOS interfaceissame as withLVDS interface.
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3.7 TX DAC ELECTRICAL CHARACTERISTICS
TypicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, 50% clockdutycycle,suppliesatnominal voltages,IOUTFS = 20 mA, DAC outputcommon mode voltageisAVDD3=3.0V, unlessotherwisenoted. AFE7222 AFE7225 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX Maximum clockoutputrate 130 250 MSPS Resolution 12 12 Bits ANALOG OUTPUTS Fullscaleoutputcurrent,perDAC 2 20 2 20 mA IOUTFS = 20 mA,Outputvoltagecompliancerange AVDD3_DAC –0.5 AVDD3_DAC+0.5 AVDD3_DAC –0.5 AVDD3_DAC+0.5 VCurrentsinkoutput Outputresistance 300 300 kΩ Outputcapacitance 5 5 pF Offseterror Mid code offset ±0.03 ±0.03 %FS (1) Gain error Internalreference ±1 ±1 %FS (1) Gain mismatch InternalreferencedualDAC ±0.5 ±0.5 %FS (1) DC PERFORMANCE INL Integralnon-linearity Fout= 10 MHz –2 ±1 2 –2 ±1 2 LSB DNL Differentialnon-linearity Fout= 10 MHz ±0.5 ±0.5 LSB AC PERFORMANCE Noisespectraldensity Fout= 10 MHz, 0 dBFS 145.5 149 148.5 151 dBc/Hz Fout= 10 MHz, 0 dBFS 70 76 70 76 dBc SFDR Spuriousfreedynamicrange Fout= 20 MHz, 0 dBFS 75 74 dBc Fout= 5.1/6.1MHz,IMD Inter-modulationdistortion 73 73 dBc–7 dBFS each DAC clock= 122.88MSPS, 75Fout= 30.72MHz ACLR Adjacentchannelleakageratio dB DAC clock= 245.76MSPS, 73Fout= 61.44MHz (1) %FS = % DifferentialFullScale
3.8 AUXILIARY ADC ELECTRICAL CHARACTERISTICS
TypicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, suppliesatnominalvoltages,unless otherwisenoted. PARAMETER TEST CONDITIONS AFE7222 /AFE7225 UNIT MIN TYP MAX Maximum Clock Rate 100 kSPS Resolution 12 Bits ANALOG INPUTS Inputvoltagerange 1.5 V Inputcapacitance 4 pF Maximum inputsignalfrequency 10 kHz DC PERFORMANCE INL Integralnon-linearity Staticconditions(nearDC input) –4.5 ±2 4.5 LSB Copyright© 2011–2012,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 13 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
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3.9 AUXILIARY DAC ELECTRICAL CHARACTERISTICS
TypicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, suppliesatnominalvoltages,IOUTFS = 5mA, 300 Ω termination,unlessotherwisenoted. AFE7222/AFE7225 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX ContinuousrefreshofAUX DAC ChannelA fromSDATAMaximum Clock Rate 3.33(1) MSPSand ChannelB fromSDOUT Resolution 12 Bits ANALOG OUTPUTS Outputcurrent,perauxDAC 2.5 7.5 mA Outputvoltagecompliancerange 1.5 V DYNAMIC PERFORMANCE INL Integralnon-linearity Staticconditions(nearDC input) –1.7 ±0.5 1.7 LSB DNL Differentialnon-linearity Staticconditions(nearDC input) ±0.3 LSB (1) 12 bitsx (1/SCLK)indirectaccessmode, SCLK max limitis40MHz
3.10 DIGITAL CHARACTERISTICS
The DC specificationsrefertotheconditionwhere thedigitaloutputsarenotswitching,butarepermanentlyata validlogic level0 or1.AVDD18*, DVDD18* = 1.8V,AVDD3* = 3.0V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS – RESET, SCLK, SDATA, SEN, PDN Allthesepinssupport1.8Vand 3V CMOSHigh-levelinputvoltage 1.3 Vlogiclevels. Low-levelinputvoltage 0.4 V DAC DIGITAL INPUTS IN CMOS INTERFACE MODE High-levelinputvoltage 1.8VCMOS logiclevelsonly 1.3 V Low-levelinputvoltage 0.4 V DAC DIGITAL INPUTS IN LVDS INTERFACE MODE StandardswingLVDS withexternal100ohmsVIDH High-leveldifferentialinputvoltage 350 mVtermination StandardswingLVDS withexternal100ohmsVIDL Low-leveldifferentialinputvoltage –350 mVtermination VICM Inputcommon-mode voltage 1.2 V DIGITAL OUTPUTS – CMOS INTERFACE – SDOUT, ADC OUTPUTS (INCMOS INTERFACE MODE) High-leveloutputvoltage DVDD18 – 0.1 DVDD18 V Low-leveloutputvoltage 0 0.1 V DIGITAL OUTPUTS – LVDS INTERFACE (ADC OUTPUTS IN LVDS MODE) VODH High-leveldifferentialoutputvoltage StandardswingLVDS 235 375 mV VODL Low-leveldifferentialoutputvoltage StandardswingLVDS –375 –235 mV VOCM Outputcommon-mode voltage 0.9 1.05 1.2 V
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3.11 TIMING REQUIREMENTS
TypicalvaluesatTA = 25°C, fulltemperaturerangeisTMIN = –40°C toTMAX = 85°C, unlessotherwisenoted. AFE7222 AFE7225 PARAMETER TEST CONDITIONS UNIT MIN TYP MAX MIN TYP MAX SCLK INPUT tSCLK CLOCK period 25 25 ns tSCLKH CLOCK pulsewidthhigh 12.5 12.5 ns Assuming 50/50dutycycle tSCLKL CLOCK pulsewidthlow 12.5 12.5 ns
3.12 TIMING REQUIREMENTS FOR RECEIVE PATH – LVDS AND CMOS MODES
Typicalvaluesareat25°C, AVDD3_DAC = 3.0V,AVDD3_AUX = 3.0V,AVDD18_ADC = 1.8V,DVDD18_CLK = 1.8V, DVDD18_DAC = 1.8V,DVDD18 = 1.8V,samplingfrequency= 125 MSPS, sinewave inputclock,1.5Vpp clockamplitude, C LOAD = 5 pF (1),R LOAD = 100 Ω (2),unlessotherwisenoted.Min and max valuesareacrossthefulltemperaturerangeTMIN = - 40°C toTMAX = 85°C, AVDD3_DAC = 3.0V,AVDD3_AUX = 3.0V,AVDD18_ADC = 1.8V,DVDD18_CLK = 1.8V, DVDD18_DAC = 1.8V,DVDD18 = 1.7V to1.9V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA Aperturedelay 2 ns Aperturedelaymatching Between two channelson thesame device ±120 ps Aperturedelaymatching Between two devicesatsame temperatureand DVDD18 supply ±450 ps Jitteradded by internalclockdistribution,specifiedas itrelatesTJ Aperturejitter 250 fsrmstothereceiveADC DefaultMode 16 MixerEnabled(RX_MIXER_EN = 1) 33 clockADC Latency(3) cyclesRX QMC Gain Phase CorrectionEnabled 22(RX_QMC_CORR_ENA=1, RX_QMC_CORR_ENB=1) LVDS OUTPUT INTERFACE 2-WIRE MODE, DDR CLOCK (4),Sampling frequency= 125MSPS tsu Data setuptime(5) Data valid(5)tozero-crossingofCLKOUTP 0.29 0.42 ns th Data holdtime(5) Zero-crossingofCLKOUTP todatabecoming invalid(5) 0.3 0.47 ns tPDI Clockpropagationdelay Inputclockrisingedge cross-overtooutputclockrisingedge tPDI = tDELAY ns cross-over10 MSPS ≤ Samplingfrequency≤ 125 MSPS Ts = tdelay 11.5 13.8 15.5 ns1/Samplingfrequency Variationoftdelay Between two devicesatsame temperatureand DVDD18 supply ±300 ps Dutycycleofdifferentialclock,(ADC_DCLKOUTP- LVDS bitclockdutycycle ADC_DCLKOUTM) 10 MSPS ≤ Samplingfrequency≤ 125 50% MSPS 2-WIRE MODE, SDR CLOCK (4),Sampling frequency= 65MSPS tsu Data setuptime(5) Data valid(5)tozero-crossingofCLKOUTP 0.85 1.08 ns th Data holdtime(5) Zero-crossingofCLKOUTP todatabecoming invalid(5) 1.08 1.21 ns Inputclockrisingedge cross-overtooutputclockrisingedge tPDI Clockpropagationdelay cross-over10 MSPS ≤ Samplingfrequency≤ 65 MSPS Ts = tPDI = 0.5*Ts+ tDELAY ns 1/Samplingfrequency tdelay 11.5 14 16.5 ns Variationoftdelay Between two devicesatsame temperatureand DVDD18 supply ±300 ps Dutycycleofdifferentialclock,(CLKOUTP-CLKOUTM) 10LVDS bitclockdutycycle 50%MSPS ≤ Samplingfrequency≤ 65 MSPS 1-WIRE MODE (DDR CLOCK ONLY) (4),Sampling frequency= 65MSPS tsu Data setuptime(5) Data valid(5)tozero-crossingofCLKOUTP 0.25 0.39 ns (1) C LOAD istheeffectiveexternalsingle-endedloadcapacitancebetween each outputpinand ground (2) R LOAD isthedifferentialloadresistancebetween theLVDS outputpair. (3) Athigherfrequencies,tPDI isgreaterthanone clockperiodand overalllatency= ADC latency+ 1. (4) Measurements aredone witha transmissionlineof100-Ω characteristicimpedance between thedeviceand theload.Setupand hold timespecificationstakeintoaccounttheeffectofjitteron theoutputdataand clock. (5) Data validreferstoLOGIC HIGH of+100.0mV and LOGIC LOW of-100.0mV. Copyright© 2011–2012,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 15 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Typicalvaluesareat25°C, AVDD3_DAC = 3.0V,AVDD3_AUX = 3.0V,AVDD18_ADC = 1.8V,DVDD18_CLK = 1.8V, DVDD18_DAC = 1.8V,DVDD18 = 1.8V,samplingfrequency= 125 MSPS, sinewave inputclock,1.5Vpp clockamplitude, C LOAD = 5 pF (1),R LOAD = 100 Ω (2),unlessotherwisenoted.Min and max valuesareacrossthefulltemperaturerangeTMIN = - 40°C toTMAX = 85°C, AVDD3_DAC = 3.0V,AVDD3_AUX = 3.0V,AVDD18_ADC = 1.8V,DVDD18_CLK = 1.8V, DVDD18_DAC = 1.8V,DVDD18 = 1.7V to1.9V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT th Data holdtime(5) Zero-crossingofCLKOUTP todatabecoming invalid(5) 0.26 0.4 ns Inputclockrisingedge cross-overtooutputclockrisingedge tPDI Clockpropagationdelay cross-over10 MSPS ≤ Samplingfrequency≤ 65 MSPS Ts = tPDI = 0.5*Ts+ tDELAY ns 1/Samplingfrequency tdelay 11.5 13.5 15.5 ns Variationoftdelay Between two devicesatsame temperatureand DVDD18 supply ±300 ps Dutycycleofdifferentialclock,(CLKOUTP-CLKOUTM) 10LVDS bitclockdutycycle 50%MSPS ≤ Samplingfrequency≤ 65 MSPS COMMON Risetimemeasured from-100mV to+100 mV FalltimetRISE, Data risetime,Data fall measured from+100 mV to-100mV 10 MSPS ≤ Sampling 0.08 nstFALL time frequency≤ 125 MSPS Risetimemeasured from-100mV to+100 mV FalltimetCLKRISE , Outputclockrisetime, measured from+100 mV to-100mV 10 MSPS ≤ Sampling 0.1 nstCLKFALL Outputclockfalltime frequency≤ 125 MSPS CMOS OUTPUT INTERFACE (6),Sampling frequency= 105MSPS (7) tsu Data setuptime(8) Data validtocross-overofADC_DCLKOUT (8) 0.5 1.4 ns th Data holdtime(8) Cross-overofADC_DCLKOUT todatabecoming invalid(8) 1.4 1.8 ns Inputclockrisingedge cross-overtooutputclockrisingedge tPDI Clockpropagationdelay cross-over10 MSPS ≤ Samplingfrequency≤ 105 MSPS Ts = tPDI = 0.5*Ts+ tDELAY ns 1/Samplingfrequency tdelay 14 16.5 19 ns Variationoftdelay Between two devicesatsame temperatureand DVDD18 supply ±350 ps Dutycycleofoutputclock,ADC_DCLKOUT 10 MSPS ≤Outputclockdutycycle 46%Samplingfrequency≤ 105 MSPS Risetimemeasured from20% to80% ofDVDD18 FalltimetRISE, Data risetime,Data fall measured from80% to20% ofDVDD18 1 ≤ Sampling 0.76 nstFALL time frequency≤ 105 MSPS Risetimemeasured from20% to80% ofDVDD18 FalltimetCLKRISE , Outputclockrisetime, measured from80% to20% ofDRVDD 1 ≤ Samplingfrequency 0.74 nstCLKFALL Outputclockfalltime ≤ 105 MSPS (6) ForFs > 105 MSPS, itisrecommended touse externalclockfordatacaptureand NOT thedeviceoutputclocksignal (ADC_DCLKOUT). (7) ForFs > 65MSPS, CMOS outputbuffersstrengthisincreasedby writingserialregisterbitsSTR_CTRL <1:0> = '10'. (8) Data validreferstoLOGIC HIGH of1.26V and LOGIC LOW of0.54V.
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Table3-1.LVDS Timings atLower Sampling Frequencies 2-WIRE MODE DDR CLOCK Setuptime,ns Holdtime,ns SamplingFrequency,MSPS MIN TYP MAX MIN TYP MAX 20 3.75 3.93 3.64 3.9 35 1.99 2.18 1.96 2.2 50 1.28 1.46 1.28 1.51 65 0.84 1.06 0.85 1.14 80 0.59 0.81 0.70 0.90 95 0.46 0.67 0.49 0.70 110 0.31 0.52 0.36 0.58 125 0.29 0.42 0.30 0.47 Clockpropagationdelay,tPDI = tDELAY tDELAY ,ns Fs ≤ 125MSPS 2-WIRE MODE, SDR CLOCK Setuptime,ns Holdtime,ns SamplingFrequency,MSPS MIN TYP MAX MIN TYP MAX 10 8.14 8.32 7.90 8.06 20 3.89 4.08 3.85 4.01 30 2.33 2.6 2.51 2.71 40 1.68 1.91 1.81 2.03 50 1.22 1.48 1.41 1.64 65 0.85 1.08 1.08 1.21 tDELAY ,ns Fs ≤ 65MSPS Clockpropagationdelay,tPDI = 0.5*Ts+ tDELAY 11.5 14 16.5 1-WIRE MODE, DDR CLOCK Setuptime,ns Holdtime,ns SamplingFrequency,MSPS MIN TYP MAX MIN TYP MAX 20 1.71 1.90 1.67 1.92 35 0.77 0.99 0.82 1.04 50 0.36 0.61 0.39 0.62 65 0.25 0.39 0.26 0.40 tDELAY ,ns Fs ≤ 65MSPS Clockpropagationdelay,tPDI = 0.5*Ts+ tDELAY MIN TYP MAX 11.50 13.50 15.50 Table3-2.CMOS Timings atLower Sampling Frequencies TimingsspecifiedwithrespecttoCLKOUT SamplingFrequency,MSPS Setuptime,ns Holdtime,ns MIN TYP MAX MIN TYP MAX 20 10.90 11.50 11.22 11.60 40 4.62 5.25 4.99 5.33 65 2.06 2.66 2.46 2.86 90 1 1.9 1.8 2.3 105 0.5 1.4 1.4 1.8 tDELAY ,ns Fs ≤ 105MSPS Clockpropagationdelay,tPDI = 0.5*Ts+ tDELAY MIN TYP MAX 14 16.50 19 Copyright© 2011–2012,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 17 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
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3.13 TIMING REQUIREMENTS FOR TRANSMIT PATH – LVDS AND CMOS MODES (1)
Typicalvaluesareat25°C, AVDD3_DAC = 3.0V,AVDD3_AUX = 3.0V,AVDD18_ADC = 1.8V,DVDD18_CLK = 1.8V, DVDD18_DAC = 1.8V,DVDD18 = 1.8V,sinewave inputclock,1.5Vpp clockamplitude,unlessotherwisenoted.Min and max valuesareacrossthefulltemperaturerangeTMIN = -40°C toTMAX = 85°C, AVDD3_DAC = 3.0V,AVDD3_AUX = 3.0V, PARAMETER TEST CONDITIONS MIN TYP MAX UNIT clockDAC Latency DefaultMode 16 cycles LVDS INPUT INTERFACE tsu Data setuptime Data valid(2)tozero-crossingofDAC_DCLKINP 0.5 ns th Data holdtime Zero-crossingofDAC_DCLKINP todatabecoming invalid(2) 0.3 ns CMOS INPUT INTERFACE tsu Data setuptime Data validtocross-overofDAC_DCLKIN (3) 0.3 ns th Data holdtime Cross-overofDAC_DCLKIN todatabecoming invalid(3) 0.5 ns (1) Timingparametersareensuredby designand characterizationand nottestedinproduction. (2) Data validreferstoLOGIC HIGH of+100 mV and LOGIC LOW of-100mV. (3) Data validreferstoLOGIC HIGH of1.26V and LOGIC LOW of0.54V.
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(A11:A0) SDATA SCLK SEN REGISTER DATA (D7:D0) AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
4 SERIAL PERIPHERAL INTERFACE
4.1 DESCRIPTION
The SPI (serialperipheralinterface)isused toprogram theAFE7225/7222.Itisused toread datafrom and writedatatotheregisters,from therms/peakpower meter and theauxiliaryADC. Itisalsoused to send datatotheauxiliaryDACs. The interfaceisformed withpinsSEN (SerialInterfaceEnable),SCLK (SerialInterfaceClock),SDATA (Serialinterfaceinputdata)and SDOUT (Serialinterfaceoutputdata). The serialshiftofbitsintothedeviceisenabledwhen SEN islow.SerialdataSDATA islatchedatevery risingedge ofSCLK when SEN isactive(low).The SPI uses a 20-bitserialarrangement– thefirst12-bits aretheregisteraddress,and thelast8-bitsrepresentthedatafortheaddress. The interfacecan work withSCLK frequencyfrom a frequencyof40MHz down toa few Hertzand also withnon-50% SCLK dutycycle. Directaccess modes existforreadingfrom theauxiliaryADC and writingtotheauxiliaryDACs by using theSPI pins. Figure4-1.Timing Address bits(A11:A8)are referredtoas thePage addressoftheregister,and addressbits(A7:A0)are referredtoas theRow addressoftheregister.
4.2 SPI REGISTER READOUT
Data storedin a registercorrespondingto a page can be read out by programming the readoutbit correspondingto thatpage. The read out bitfora registeraddressedby (A11:A0)isthe D0 bitof the registerwiththePage addressof(A11:A8)and row addressof00000000. To readouta particularregister,thefollowingstepshave tobe followed: 1. ConfigureSDOUT as a digitaloutputpinusingbits 2. Settheregisterspecificreadoutbit.Thisbitcan be setby writingthefollowing20-bitsequence – A11:A8,00000000,00000001where (A11..A8)isthepage addressoftheregisterwhose contentsare desiredtobe readout 3. Once inthereadoutmode, writetheaddressoftheregistertobe readoutas below.The new data writeisignored.The datacontentsoftheregistercome outseriallyon theSDOUT pin(withMSB first format)as shown below. Copyright© 2011–2012,Texas InstrumentsIncorporated SERIAL PERIPHERAL INTERFACE 19 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
(A11:A0) SDATA SCLK SEN REGISTER DATA (D7:D0) SDOUT Contents of addressed register (D7..D0) Ignored AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Figure4-2.Timing 4. Ifthenextregistertobe readouthas thesame page address,thenrepeatStep3 withthenew addresstobe readout. 5. To exittheregisterreadoutmode, writeA11:A8,00000000,00000000.
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(CMIX) 2x Interpolation TxFIR2 2x Interpolation TxFIR1 Inverse SINC QMC Gain/ Phase Fine Mixer 8 deep FIFO NCO SYNC SYNC SYNCSYNC SYNC TX A input (I channel) TX B input (Q channel) TX A output TX B output DAC_DCLKIN DAC_CLK %1,2,4DAC_CLK AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
5 REGISTER DESCRIPTIONS
5.1 TRANSMIT DIGITAL SIGNAL CHAIN REGISTERS
Figure5-1.SignalChain Inputdataisshiftedintothe8-deep FIFO attherateofDAC_DCLKIN. At itsoutput,theFIFO hands off thedatausinga dividedversionoftheDAC_CLK (basedon theinterpolationfactor).The restofthesignal chainrunsoffDAC_CLK and itsdividedderivatives. RegisterName – CONFIG0 – Address 0x103,Default= 0x00 Tx_BYP_SRC TX_BYP TX_ChB_PDN_SRC TX_CHB_PDN TX_CHA_PDN_SRC TX_CHA_PDN TX_DIS TX_DIS – DisablesthedigitalsignalchainofbothchannelsinTX .Allblocksindigitalsignalchainare powered down, and theoutputisDAC mid-code.Note:theDACs arenotpowered down inthismode. TX_CHA_PDN – Powers down digitalsignalchainofChannel A inTx .Outputofthechannelismid code. SetTX_CHA_PDN_SRC forthistotakeeffect. TX_CHA_PDN_SRC – Settingthiscausesthevalueprogrammed intoTX_CHA_PDN totakeeffect. TX_CHB_PDN – Powers down digitalsignalchainofChannel B inTx .Outputofthechannelismid code. SetTX_CHB_PDN_SRC forthistotakeeffect. TX_CHB_PDN_SRC – Settingthiscausesthevalueprogrammed intoTX_CHB_PDN totakeeffect. Note thatwhen indefaultmode ofoperation(noneoftheregister-selectabledigitalfeaturesenabled),all4 ofabove bits(TX_CHA_PDN, TX_CHA_PDN_SRC, TX_CHB_PDN, TX_CHB_PDN_SRC) have tobe set togetherto'1'forthem totakeeffect.However,ifany ofthedigitalfeatures(likeinterpolation,Finemixer, Coarse mixer,or QMC gain/phaseor offset)are enabled,then the channelA can be independently powered down usingbitsTX_CHA_PDN and TX_CHA_PDN_SRC, and channelB can be independently powered down usingbitsTX_CHB_PDN and TX_CHB_PDN_SRC. TX_BYP – The inputstoboththeTx channelsaredirectlypassed totheoutputs.FIFO isbypassed.Set TX_BYP_SRC forthistotakeeffect. TX_BYP_SRC – Settingthiscausesthevalueprogrammed intoTX_BYP totakeeffect. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 21 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
INP_A_ADC Serial LVDS or Parallel CMOS 12b RX ADC B 12b TX DAC A 12b TX DAC B IOUTP_A_DAC 12b RX ADC AINN_A_ADC INP_B_ADC INN_B_ADC IOUTN_A_DAC IOUTP_B_DAC IOUTN_B_DAC 12-bit ADC Output RX DIGITAL SIGNAL CHAIN TX DIGITAL SIGNAL CHAIN Serial LVDS or Parallel CMOS 12-bit DAC Input MUXMUX AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG1 – Address 0x104,Default= 0x10 TX_CHA_8_IP_EN – Enablethe8-sample mode FIFO mode forChannel A .The 8 samples writteninto theregs0x11F to0x12E arerepeatedlycycledthrough,and senttotheDAC A.Thisisa usefuldiagnostic mode. TX_CHB_8_IP_EN – Enablethe8-sample mode FIFO mode forChannel B .The 8 samples writteninto theregs0x12F to0x13E arerepeatedlycycledthrough,and senttotheDAC B. MASK_2_AWAY_DET – ReferCONFIG58 fora descriptionofthecollisionconditionintheFIFO.Setting the MASK_2_AWAY_DET preventsthe 2-away conditionfrom triggeringcollisiondetection.Ifcollision detectionisenabled,and 2-away conditionoccurs,theoutputsamples willbe forcedtoDAC mid code, unlessMASK_2_AWAY_DET isset. RegisterName – CONFIG2 – Address 0x105,Default= 0x00 STORE_FIFO_PTRS RX_TX_LPBK_SRC RX_TX_LPBK STORE_FIFO_PTRS – When set,theFIFO Read and Writepointersarewrittenintotheregister0x141 at the rateof the dividedDAC_CLK. The pointersare no longerwrittento the serialinterfaceregs when Registerreadoutisenabled. RX_TX_LPBK – When thisbitand RX_TX_LPBK_SRC are bothset,theinputtotheTX signalchainis tappedfromthethefinaloutputoftheRX signalchain.As isobvious,theADC_CLK and DAC_CLK rates shouldbe thesame when usingthismode. RX_TX_LPBK_SRC – When thisbitand RX_TX_LPBK are bothset,theinputtotheTX signalchainis tappedfromthethefinaloutputoftheRX signalchain The RX toTX loopbackisshown below.The dottedarrowsillustratetheloopbackpath. Note thatthough the data goingintothe TX digitalsignalchainisloopedback internallyfrom the RX Digitalsignalchain,itisstillrequiredtogivean activeDAC_DCLKIN inthismode because theTx FIFO requiresitforproperdatatransfer. Figure5-2.Loopback
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RegisterName – CONFIG3 – Address 0x106,Default= 0x00 FIR2B_MODE FIR1B_MODE FIR2A_MODE FIR1A_MODE TX_INT_MODE_SRC TX_INT_MODE(1:0) TX_INT_MODE(1:0) – Specifiestheinterpolationfactor.To use thismode, setTX_INT_MODE_SRC to1. VALUE INTERPOLATION FACTOR 0 1 1 2 2 4 3 4 Whileinterpolatingby a factorof2,theDAC_DCLKIN rateshouldbe settohalfoftheDAC_CLK rate. Whileinterpolatingby a factorof4,theDAC_DCLKIN rateshouldbe settoone fourthoftheDAC_CLK rate.Ininterpolateby 2 mode ,TxFIR1 aloneisused.InInterpolateby 4 mode, bothTxFIR1,and TxFIR2 areused. TX_INT_MODE_SRC – Needs tobe setto1 when programmingTX_INT_MODE(1:0) FIR1A_MODE – SpecifieswhetherTxFIR1 inChannel A isinlow pass orhighpass mode .Set thisbitto configurethefilterinhighpass mode. Ininterpolateby 4 mode, alwayssetTxFIR1 tolowpass mode. FIR2A_MODE – SpecifieswhetherTxFIR2 inChannel A isinlow pass orhighpass mode. Set thisbitto configurethefilterinhighpass mode FIR1B_MODE – SpecifieswhetherTxFIR1 inChannel B isinlow pass orhighpass mode. Set thisbitto configurethefilterinhighpass mode FIR2B_MODE – SpecifieswhetherTxFIR2 inChannel B isinlow pass orhighpass mode .Set thisbitto configurethefilterinhighpass mode RegisterName – CONFIG4 – Address 0x107,Default= 0x00 TX_CMIX_PHASE(1:0) TX_CMIX_PHASE_INCR TX_CMIX_MODE(1:0) TX_CMIX_EN TX_CMIX_EN – EnablestheTx Coarse Mixer. TX_CMIX_MODE (1:0)– Specifiesthemode inwhich theTX CMIX isconfigured.Set TX_CMIX_EN for thistotakeeffect. VALUE MIXING MODE
0 Normal(Lowpass )
1 Fs /2(HighPass )– realmixingmode
2 + Fs/4– complexmixingmode 3 – Fs/4– complexmixingmode TX_CMIX_PHASE_INCR – Thisbitisa method tocontrolthemixingphase withoutusingtheSYNC pin.A 0 to1 transitionon thisbitcausesthephase ofmixingintheTX CMIX tobe incrementedby 1 withrespect tothecurrentphase ofmixing.To incrementthephase ofmixingmore thanonce,clearand thensetthis bitonce again.Syncingneeds tobe disabledforTx CMIX forthismode towork.(Thismeans thatglobal syncingshouldbe disabled,and CMIX-specifcsyncingshouldalsobe disabled). TX_CMIX_PHASE (1:0)– The valueprogrammed intothisisappliedas the currentTX CMIX phase, when theCMIX issynced,Syncingneeds tobe enabledforCMIX forthismode towork.Thismode is meant tosynchronizethephase ofmixingacrossmultiplechips. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 23 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG5 – Address 0x108,Default= 0x00 Tx_INV_SINC_FIL_EN_SRC Tx_INV_SINC_FIL_EN TX_DIV_PHASE_ TX_DIV_PHASE(1:0) TX_DATA_ROUTE_ INCR ORDER (1:0) TX_DATA_ROUTE_ORDER (1:0)– Specifiesthe orderinwhich the A and B outputsof the TX Signal ChainareroutedtotheDACs VALUE ROUTING ORDER
0 Normal – DACA getsTX OutputA and DACB getsTX OutputB
1 BothDACs getTX OutputA
2 BothDACs getTX OutputB
3 Swapped – DACA getsTX OutputB and DACB getsTX OutputA
TX_DIV_PHASE (1:0)– The valueprogrammed intothisisappliedas the TX Dividerphase,when the dividerissynced.The dividerherereferstotheclockdividerthatdividestheDAC_CLK dependingon the interpolationfactor.For divisionby 2,thereare2 possiblephases ofthedividedclock.For divisionby 4, thereare 4 possiblephases.Ifthedividerphase isnotsynced acrosschips,thenitwillcause a phase uncertaintyintheDAC analogoutput,and can alsocause uncertaintyintheCMIX operation. TX_DIV_PHASE_INCR – Thisbitisa method tocontrolthephase ofthedividedclockwithoutusingthe SYNC pin.A 0 to1 transitionon thisbitcauses thephase ofdivisionintheTX Dividertobe incremented by 1 withrespectto the currentphase of division.To incrementthe phase of divisionmore than once, clearand thensetthisbitonce again.Globalsyncingas wellas SyncingfortheTx Dividerneeds tobe disabledforthismode towork. Tx_INV_SINC_FIL_EN – EnablestheTx InverseSincFilter.Set Tx_INV_SINC_FIL_EN_SRC forthisto takeeffect. Tx_INV_SINC_FIL_EN_SRC – When set,thisallowsTx_INV_SINC_FIL_EN totakeeffect. RegisterName – CONFIG6 – Address 0x10B, Default= 0x00 SRC SYNC_DIS SYNC_DIS SYNC_DIS SYNC_DIS SYNC_DIS SYNC_DIS TX_FIFO_SYNC_DIS – Disables Syncing of the FIFO. This takes effect only when TX_GLOBAL_SYNC_DIS isset.Thisisonlya enable/disablebit– theactualsync sourcecan be setto pinorserialinterface.When theFIFO issynced,thereadand writepointersareinitializedsuch thatthey areseparatedby 4 positions.Thismode iscommon forbothchannels. TX_CMIX_SYNC_DIS – Disables Syncing of the Tx CMIX .This takes effect only when TX_GLOBAL_SYNC_DIS isset.CMIX syncingrefersto settingthe phase of the complex mixing.This mode iscommon forbothchannels. TX_DIV_SYNC_DIS – Disables Syncing of the Tx Dividerphase .This takes effectonly when TX_GLOBAL_SYNC_DIS isset.Common forbothchannels. TX_QMC_OFF_SYNC_DIS – DisablesSyncingofTx QMC OffsetCorrection.Thistakeseffectonlywhen TX_GLOBAL_SYNC_DIS isset.Thismode iscommon forbothchannels. TX_QMC_GAIN_PH_SYNC_DIS – DisablesSyncingofTx QMC Gain Phase Correction.Thistakeseffect onlywhen TX_GLOBAL_SYNC_DIS isset.Thismode iscommon forbothchannels. TX_GLOBAL_SYNC_DIS – When set,disablesglobalsyncingof TX and enablesblocklevelsyncing. When cleared,a risingedge on theselectedsyncsourcecausesallTX blockstobe synced.
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 TX_CMIX_SYNC_SRC – Specifiesthesync sourceforTX CMIX. When cleared,SYNC pinisused as the sync source.When set,a risingedge on serialinterfacebitTX_CMIX_SER_IF_SYNC inRegister0x10D isused as the sync sourceforTX CMIX. Thisisapplicablewhen TX_GLOBAL_SYNC_DIS issetand TX_CMIX_SYNC_DIS iscleared. VALUE SYNC SOURCE
0 Pin
1 Serialinterfacebit
RegisterName – CONFIG7 – Address 0x10C, Default= 0x00 SYNC_SRC SYNC_SRC SRC SRC SRC TX_FIFO_SYNC_SRC – Specifiesthe Sync source for TX FIFO. It is applicablewhen TX_GLOBAL_SYNC_DIS issetand TX_FIFO_SYNC_DIS iscleared. VALUE SYNC SOURCE When the valueprogrammed is1, a risingedge on the serialinterfacebitTX_FIFO_SER_IF_SYNC in register0x10D isused as thesyncsourcefortheFIFO. TX_DIV_SYNC_SRC – Specifiesthesync sourceforTX Divider.When cleared,SYNC pinisused as the sync source.When set,a risingedge on serialinterfacebitTX_DIV_SER_IF_SYNC inregister0x10D is used as the sync sourceforTX Divider.Thisisapplicablewhen TX_GLOBAL_SYNC_DIS issetand TX_DIV_SYNC_DIS iscleared. TX_QMC_OFF_SYNC_SRC – Specifiesthe sync sourceforTX QMC OffsetCorrection.When cleared, SYNC pin is used as the sync source. When set, a risingedge on serialinterfacebit TX_QMC_OFF_SER_IF_SYNC in register0x10D is used as the sync source forTX QMC Offset Correction.Thisisapplicablewhen TX_GLOBAL_SYNC_DIS issetand TX_QMC_OFF_SYNC_DIS is cleared. TX_QMC_GAIN_PH_SYNC_SRC – Specifiesthesync sourceforTX QMC Gain Phase Correction.When cleared,SYNC pin is used as the sync source.When set,a risingedge on serialinterfacebit TX_QMC_GAIN_PH_SER_IF_SYNC in register0x10D isused as the sync source forTX QMC Gain Phase Correction. This is applicable when TX_GLOBAL_SYNC_DIS is set and TX_QMC_GAIN_PH_SYNC_DIS iscleared. TX_GLOBAL_SYNC_SRC – Specifies the sync source for TX. This is applicablewhen TX_GLOBAL_SYNC_DIS iscleared. VALUE SYNC SOURCE
0 AllblockssyncedfromtheSYNC pin
1 AllblockssyncedusingserialInterfacebit
When serialinterfaceis specifiedto be the sync source,a risingedge on the serialinterfacebit TX_GLOB_SER_IF_SYNC inregister0x10D isused as thesyncsource. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 25 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG8 – Address 0x10D, Default= 0x00 IF_SYNC SER_IF_SYNC SER_IF_SYNC IF_SYNC IF_SYNC IF_SYNC TX_FIFO_SER_IF_SYNC – A risingedge on thisbitisused as the sync sourceforTX FIFO. Thisis applicablewhen TX_GLOBAL_SYNC_DIS is set, and TX_FIFO_SYNC_DIS is cleared, and TX_FIFO_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheFIFO. TX_CMIX_SER_IF_SYNC – A risingedge on thisbitisused as the sync sourceforTX CMIX. Thisis applicablewhen TX_GLOBAL_SYNC_DIS is set, and TX_CMIX_SYNC_DIS is cleared,and TX_CMIX_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheTX CMIX. TX_DIV_SER_IF_SYNC – A risingedge on thisbitisused as the sync sourceforTX Divider.Thisis applicablewhen TX_GLOBAL_SYNC_DIS is set, and TX_DIV_SYNC_DIS is cleared, and TX_DIV_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheTX Divider. TX_QMC_OFF_SER_IF_SYNC – A risingedge on thisbitisused as thesync sourceforTX QMC Offset correctionblock.Thisisapplicablewhen TX_GLOBAL_SYNC_DIS isset,and TX_QMC_OFF_SYNC_DIS iscleared,and TX_QMC_OFF_SYNC_SRC specifiesserialinterfacebittobe thesync sourcefortheTX QMC Offsetcorrection. TX_QMC_GAIN_PH_SER_IF_SYNC – A risingedge on thisbitisused as thesync sourceforTX QMC Gain Phase correctionblock. This is applicablewhen TX_GLOBAL_SYNC_DIS is set, and TX_QMC_GAIN_PH_SYNC_DIS is cleared,and TX_QMC_GAIN_PH_SYNC_SRC specifiesserial interfacebittobe thesyncsourcefortheTX QMC Gain Phase correction. TX_GLOBAL_SER_IF_SYNC – A risingedge on thisisused as thesyncsourceforTX. Thisisapplicable when TX_GLOBAL_SYNC_DIS iscleared,and TX_GLOBAL_SYNC_SRC(1:0) specifiesserialinterface bittobe thesyncsourceforTX. RegisterName – CONFIG9 – Address 0x10E,Default= 0x00 ENA ENA SYNC_NEEDED SYNC_NEEDED TX_QMC_OFF_SYNC_NEEDED – Specifiesifsyncingisneeded forTX QMC OffsetCorrection.Ifset, QMC Offsetvaluesprogrammed in the serialinterfaceregistersare not appliedto the QMC Offset correctionblockuntila syncisapplied. TX_QMC_GAIN_PH_SYNC_NEEDED – Specifiesifsyncing is needed for TX QMC Gain Phase Correction.Ifset,QMC gainand Phase valuesprogrammed intothe serialinterfaceregistersare not appliedtotheQMC Gain Phase correctionblockuntila syncisapplied. TX_QMC_OFFSET_ENA – EnablesTX QMC OffsetCorrection.Common forbothchannels. TX_QMC_CORR_ENA – EnableTX QMC Gain Phase Correction.Common forbothchannels.Note that by default,the TX_QMC_GAINA(2:0) and TX_QMC_GAINB(2:0) are set to 0. So when TX_QMC_CORR_ENA is written,the outputgoes to zero untilthe time TX_QMC_GAINA(2:0) and TX_QMC_GAINB(2:0) arewrittentothedesiredvalue. RegisterName – CONFIG10 – Address 0x10F Default= 0x00 (OptionallySynced) TX_QMC_OFFSETA(12:5) TX_QMC_OFFSETA(12:5) – Upper 8 bitsofDAC A OffsetCorrection.The lower5 bitsareinCONFIG11 Register.Offsetisa signedvalue(2scomplement).
26 REGISTER DESCRIPTIONS Copyright© 2011–2012,Texas InstrumentsIncorporated
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RegisterName – CONFIG11 – Address 0x110 Default= 0x00 (OptionallySynced ) TX_QMC_OFFSETA(4:0) TX_QMC_GAINA(2:0) TX_QMC_OFFSETA(4:0) – Lower 5 bitsofDAC A OffsetCorrection. TX_QMC_GAINA(2:0) – Lower 3 bitsofthe11 bitQMC Gain word forDAC A. The upper 8 bitsare in CONFIG12 register.Thefull11 bitTX_QMC_GAINA(10:0) word isformattedas UNSIGNED witha range or0 to1.9990.The implieddecimalpointforthemultiplicationisbetween bits(9)and (10). RegisterName – CONFIG12 – Address 0x111 Default= 0x00 (Synced ) TX_QMC_GAINA(10:3) TX_QMC_GAINA(10:3) –Upper 8 bitsifthe11 bitQMC Gain word forDAC A. RegisterName – CONFIG13 – Address 0x112 Default= 0x00 (Synced) TX_QMC_OFFSETB(12:5) TX_QMC_OFFSETB(12:5) –Upper 8 bitsofDAC B OffsetCorrection.The lower5 bitsareinCONFIG14 Register. RegisterName – CONFIG14 – Address 0x113 Default= 0x00 (Synced) TX_QMC_OFFSETB(4:0) TX_QMC_GAINB(2:0) TX_QMC_OFFSETB(4:0) – Lower 5 bitsofDAC B OffsetCorrection. TX_QMC_GAINB(2:0) – Lower 3 bitsofthe11 bitQMC Gain word forDAC B. The upper 8 bitsare in CONFIG15 register.Thefull11 bitTX_QMC_GAINB(10:0) word isformattedas UNSIGNED witha range or0 to1.9990. RegisterName – CONFIG15 – Address 0x114 Default= 0x00 (Synced) TX_QMC_GAINB(10:3) TX_QMC_GAINB(10:3) – Upper 8 bitsifthe11 bitQMC Gain word forDAC B. RegisterName – CONFIG16 – Address 0x115 Default= 0x00 (Synced) TX_QMC_PHASE(9:2) TX_QMC_PHASE(9:2) – Upper Upper 8 bitsifthe10 bitQMC Phase word.The lowertwo bitsareinthe CONFIG17 register.The fullQMC_PHASE(9:0) correctionword is formattedas 2s complement and scaledto occupy a range of -0.125to 0.12475.To acomplishQMC Phase correction,thisvalue is multipliedby thecurrentQ sample,thensummed totheIsample. RegisterName – CONFIG17 – Address 0x116 Default= 0x00 (Synced) TX_QMC_PHASE(1:0) TX_QMC_PHASE(1:0) – Lower 2 bitsofthe10 bitQMC Phase word . Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 27 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG18 – Address 0x117 Default= 0x00 (Synced) TX_NCO_FREQ_WORD(31:24) TX_NCO_FREQ_WORD(31:24) – See CONFIG21 below. RegisterName – CONFIG19 – Address 0x118 Default= 0x00 (Synced) TX_NCO_FREQ_WORD(23:16) TX_NCO_FREQ_WORD(23:16) – See CONFIG21 below. RegisterName – CONFIG20 – Address 0x119 Default= 0x00 (Synced) TX_NCO_FREQ_WORD(15:8) TX_NCO_FREQ_WORD(15:8) – See CONFIG21 below. RegisterName – CONFIG21 – Address 0x11A Default= 0x00 (Synced) TX_NCO_FREQ_WORD(7:0) TX_NCO_FREQ_WORD(7:0) – This isused to determinethe frequency,Fmix of the NCO. The twos complement formattedvaluecan be positiveornegative,and theLSB isequaltoFs/232 RegisterName – CONFIG22 – Address 0x11B Default= 0x00 (Synced) TX_NCO_PHASE_OFF(15:8) TX_NCO_FREQ_WORD(15:8) – See CONFIG23 below. RegisterName – CONFIG23 – Address 0x11C Default= 0x00 (Synced) TX_NCO_PHASE_OFF(7:0) TX_NCO_PHASE_OFF(7:0) – Thisisthe 2s complement Phase offsetadded to the NCO accumulator justbeforethegenerationoftheSIN and COS values. RegisterName – CONFIG24 – Address 0x11D, Default= 0x00 TX_MIXER_EN TX_MIXER_GAIN(1:0) TX_MIXER_GAIN(1:0) – The finemixerrealizesthefunctions{Acos(ωmixt)– B sin(ωmixt)}and {Asin(ωmixt) + Bcos(ωmixt)}Thiscan cause thefinemixeroutputtobe up to3 dB higherthantheindividualinputs.The mixergaincan restorethesignalleveltothedesiredlevelby providinga programmableattenuation. VALUE GAIN 0 –2.5dB (default)– use when complexmixing 1 –6 dB 2 0 dB – use when one inputiszero 3 0 dB TX_MIXER_EN – Thisenablesthefinemixer,whichalsocausestheNCO tobe enabled.
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RegisterName – CONFIG25 – Address 0x11E Default= 0x00 DIS SRC SYNC NEEDED TX_NCO_SYNC_NEEDED – Specifiesifsyncingisneeded forTX NCO. Ifset,NCO Frequency and Offsetwords programmed intothe serialinterfaceregistersare not appliedto the NCO untila sync is applied TX_NCO_SER_IF_SYNC – A risingedge on thisbitisused as the sync sourceforTX NCO. Thisis applicablewhen TX_GLOBAL_SYNC_DIS is set, and TX_NCO_SYNC_DIS is cleared, and TX_NCO_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheNCO. TX_NCO_SYNC_SRC – Specifiesthesync sourceforTX NCO. When cleared,SYNC pinisused as the sync source.When set,a risingedge on serialinterfacebitTX_NCO_SER_IF_SYNC isused as thesync sourceforTX NCO. Thisisapplicablewhen TX_GLOBAL_SYNC_DIS isset. TX_NCO_SYNC_DIS – Disables Syncing of the Tx NCO. This takes effect only when TX_GLOBAL_SYNC_DIS isset. RegisterName – CONFIG26 – Address 0x11F,Default= 0x00 CHA_REG1(15:8) CHA_REG1(15:8) – Upper 8 bitsforsample 1 forDAC A in8-sampleFIFO mode .TX_CHA_8_IP_EN in CONFIG 1 needs tobe setforRegs CONFIG26 toCONFIG41 totakeeffect. RegisterName – CONFIG27 – Address 0x120,Default= 0x00 CHA_REG1(7:0) CHA_REG1(7:0) – Lower 8 bitsforsample 1 forDAC A RegisterName – CONFIG28 – Address 0x121,Default= 0x00 CHA_REG2(15:8) CHA_REG2(15:8) – Upper 8 bitsforsample 2 forDAC A . RegisterName – CONFIG29 – Address 0x122,Default= 0x00 CHA_REG2(7:0) CHA_REG2(7:0) – Lower 8 bitsforsample 2 forDAC A RegisterName – CONFIG30 – Address 0x123,Default= 0x00 CHA_REG3(15:8) CHA_REG3(15:8) – Upper 8 bitsforsample 3 forDAC A RegisterName – CONFIG31 – Address 0x124,Default= 0x00 CHA_REG3(7:0) CHA_REG3(7:0) – Lower 8 bitsforsample 3 forDAC A Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 29 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG32 – Address 0x125,Default= 0x00 CHA_REG4(15:8) CHA_REG4(15:8) – Upper 8 bitsforsample 4 forDAC A . RegisterName – CONFIG33 – Address 0x126,Default= 0x00 CHA_REG4(7:0) CHA_REG4(7:0) – Lower 8 bitsforsample 4 forDAC A RegisterName – CONFIG34 – Address 0x127,Default= 0x00 CHA_REG5(15:8) CHA_REG5(15:8) – Upper 8 bitsforsample 5 forDAC A RegisterName – CONFIG35 – Address 0x128,Default= 0x00 CHA_REG5(7:0) CHA_REG5(7:0) – Lower 8 bitsforsample 5 forDAC A . RegisterName – CONFIG36 – Address 0x129,Default= 0x00 CHA_REG6(15:8) CHA_REG6(15:8) – Upper 8 bitsforsample 6 forDAC A RegisterName – CONFIG37 – Address 0x12A, Default= 0x00 CHA_REG6(7:0) CHA_REG6(7:0) – Lower 8 bitsforsample 6 forDAC A RegisterName – CONFIG38 – Address 0x12B, Default= 0x00 CHA_REG7(15:8) CHA_REG7(15:8) – Upper 8 bitsforsample 7 forDAC A RegisterName – CONFIG39 – Address 0x12C, Default= 0x00 CHA_REG7(7:0) CHA_REG7(7:0) – Lower 8 bitsforsample 7 forDAC A. RegisterName – CONFIG40 – Address 0x12D, Default= 0x00 CHA_REG8(15:8) CHA_REG8(15:8) – Upper 8 bitsforsample 8 forDAC A
30 REGISTER DESCRIPTIONS Copyright© 2011–2012,Texas InstrumentsIncorporated
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RegisterName – CONFIG41 – Address 0x12E,Default= 0x00 CHA_REG8(7:0) CHA_REG8(7:0) – Lower 8 bitsforsample 8 forDAC A RegisterName – CONFIG42 – Address 0x12F,Default= 0x00 CHB_REG1(15:8) CHB_REG1(15:8) – Upper 8 bitsforsample 1 forDAC B .TX_CHB_8_IP_EN inCONFIG 1 needs tobe setforRegs CONFIG42 toCONFIG57 totakeeffect. RegisterName – CONFIG43 – Address 0x130,Default= 0x00 CHB_REG1(7:0) CHB_REG1(7:0) – Lower 8 bitsforsample 1 forDAC B RegisterName – CONFIG44 – Address 0x131,Default= 0x00 CHB_REG2(15:8) CHB_REG2(15:8) – Upper 8 bitsforsample 2 forDAC B. RegisterName – CONFIG45 – Address 0x132,Default= 0x00 CHB_REG2(7:0) CHB_REG2(7:0) – Lower 8 bitsforsample 2 forDAC B RegisterName – CONFIG46 – Address 0x133,Default= 0x00 CHB_REG3(15:8) CHB_REG3(15:8) – Upper 8 bitsforsample 3 forDAC B. RegisterName – CONFIG47 – Address 0x134,Default= 0x00 CHB_REG3(7:0) CHB_REG3(7:0) – Lower 8 bitsforsample 3 forDAC B RegisterName – CONFIG48 – Address 0x135,Default= 0x00 CHB_REG4(15:8) CHB_REG4(15:8) – Upper 8 bitsforsample 4 forDAC B. RegisterName – CONFIG49 – Address 0x136,Default= 0x00 CHB_REG4(7:0) CHB_REG4(7:0) – Lower 8 bitsforsample 4 forDAC B. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 31 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG50 – Address 0x137,Default= 0x00 CHB_REG5(15:8) CHB_REG5(15:8) – Upper 8 bitsforsample 5 forDAC B. RegisterName – CONFIG51 – Address 0x138,Default= 0x00 CHB_REG5(7:0) CHB_REG5(7:0) – Lower 8 bitsforsample 5 forDAC B RegisterName – CONFIG52 – Address 0x139,Default= 0x00 CHB_REG6(15:8) CHB_REG6(15:8) – Upper 8 bitsforsample 6 forDAC B. RegisterName – CONFIG53 – Address 0x13A, Default= 0x00 CHB_REG6(7:0) CHB_REG6(7:0) – Lower 8 bitsforsample 6 forDAC B. RegisterName – CONFIG54 – Address 0x13B, Default= 0x00 CHB_REG7(15:8) CHB_REG7(15:8) – Upper 8 bitsforsample 7 forDAC B. RegisterName – CONFIG55 – Address 0x113C, Default= 0x00 CHB_REG7(7:0) CHB_REG7(7:0) – Lower 8 bitsforsample 7 forDAC B RegisterName – CONFIG56 – Address 0x13D, Default= 0x00 CHB_REG8(15:8) CHB_REG8(15:8) – Upper 8 bitsforsample 8 forDAC B. RegisterName – CONFIG57 – Address 0x13E,Default= 0x00 CHB_REG8(7:0) CHB_REG8(7:0) – Lower 8 bitsforsample 8 forDAC B RegisterName – CONFIG58 – Address 0x13F,Default= 0x00 EN_IP_CLK_STOP_DET EN_FIFO_COLLISION_DET EN_FIFO_COLLISION_DET – On RESET (andwhen synced),thereadand writepointersoftheFIFO are set4 positionsaway. The read pointerincrementsat the DAC_DCLKIN ratewhereas the writepointer incrementsatthedividedDAC_CLK rate.Whilethefrequenciesofthese2 clocksareexpectedtobe the same, relativephase driftscan cause thisrelativedifferenceof 4 positionsto drift.When the EN_FIFO_COLLISION_DET bitis set,a collisionconditionis detectedwhen the relativedifference
32 REGISTER DESCRIPTIONS Copyright© 2011–2012,Texas InstrumentsIncorporated
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(CMIX) RX RMS / Peak Power Meter QMC Gain/ Phase SYNC SYNC SYNC /2 HBF Decimation QMC Offset SYNC RX Output A (I Channel) Fine Mixer NCO SYNC RX Output B (Q Channel) RX Input A RX Input B AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 between the read and writepointersbecomes either0,1 or 2. Detectionof thiscollisioncondition automaticallycauses masks the DACs to giveout an outputcorrespondingto mid code.The read and writepointerdifferingby 2 isreferredto as 2-way detection.2-away detectioncan be preventedfrom triggeringcollisionby settingMASK_2_AWAY_DET inCONFIG 1.Collisiondetectionisdone once every 8 inputsamples. EN_IP_CLK_STOP_DET – When set,theconditionofinputclockbeingstoppedcauses theDAC outputs tobe forcedtomid code. RegisterName – CONFIG59 – Address 0x140,Default= 0x00 (Read Only) FIFO_ERROR FIFO_COLLISION FIFO_1_AWAY FIFO_2_AWAY INP_CLK_STOP These arerefreshedattherateofthedividedDAC_CLK. INP_CLK_STOP – Ifset,itindicatesthattheinputclockhas been detectedas havingbeen stopped. FIFO_2_AWAY – Ifset,itindicatesthatthe conditionof the read and writepointersbeing2 locations away fromeach otherhas been detected. FIFO_1_AWAY – Ifset,itindicatesthattheconditionofthereadand writepointersbeing1 locationaway fromeach otherhas been detected. FIFO_COLLISION – Ifset,thisindicatesthatthe read and writepointershave been detectedas overlappingwitheach other FIFO_ERROR – Ifset,thisindicatesthateitherCollision, or 1-away or 2-away conditionhas been detected. RegisterName – CONFIG60 – Address 0x141,Default= 0x00 (Read Only) FIFO_INP_PTR(2:0) FIFO_OP_PTR(2:0) FIFO_OP_PTR(2:0) – Containtsthe FIFO read pointervalue.Itswrittenintothe registerwhen STORE_FIFO_PTRS isset in CONFIG2. Itisnot updated once the deviceisconfiguredintoreadout mode. FIFO_INP_PTR(2:0) – Containtsthe FIFO writepointervalue.Itswrittenintothe registerwhen STORE_FIFO_PTRS isset in CONFIG2. Itisnot updated once the deviceisconfiguredintoreadout mode.
5.2 RECEIVE DIGITAL SIGNAL CHAIN REGISTERS
Figure5-3.SignalChain Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 33 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
INP_A_ADC Serial LVDS or Parallel CMOS 12b RX ADC B 12b TX DAC A 12b TX DAC B IOUTP_A_DAC 12b RX ADC AINN_A_ADC INP_B_ADC INN_B_ADC IOUTN_A_DAC IOUTP_B_DAC IOUTN_B_DAC 12-bit ADC Output RX DIGITAL SIGNAL CHAIN TX DIGITAL SIGNAL CHAIN Serial LVDS or Parallel CMOS 12-bit DAC Input MUX MUX AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG61 – Address 0x165,Default= 0x00 SRC EN_SRC EN RX_DEC_FIL_EN – Enables the decimationfilterin the RX path in both the A and B channels.Set RX_DEC_FIL_EN_SRC forthistotakeeffect.Outputclockautomaticallysetto0.5X. RX_DEC_FIL_EN_SRC – When set,thisallowsRX_DEC_FIL_EN totakeeffect. RX_DECA_MODE – When set,configuresthe decimationfilterin Channel A in high pass mode. By default,thefilterisinlowpass mode. RX_DECB_MODE – When set,configuresthe decimationfilterin Channel B in high pass mode. By default,thefilterisinlowpass mode. TX_RX_LPBK – When thisbitand TX_Rx_LPBK_SRC arebothset,theinputtotheRX signalchainis tappedfromthethefinaloutputoftheTX signalchain. TX_Rx_LPBK_SRC – When thisbitand TX_RX_LPBK arebothset,theinputtotheRX signalchainis tappedfromthethefinaloutputoftheTX signalchain. The TX toRX loopbackisillustratedbelow.The dottedarrowsshow theloopbackmode. Figure5-4.SignalChain RegisterName – CONFIG62 – Address 0x166,Default= 0x00 RX_DIV_PHASE_INV RX_DIV_PHASE RX_CMIX_PHASE(1:0) RX_CMIX_PHASE_ RX_CMIX_MODE(1:0) RX_CMIX_EN INCR RX_CMIX_EN – EnablestheRX Coarse mixer. RX_CMIX_MODE(1:0) – Specifiesthe mode in which the RX Coarse mixer is configured. Set RX_CMIX_EN forthistotakeeffect. VALUE MIXING MODE
1 Fs /2(HighPass )
3 – Fs/4
34 REGISTER DESCRIPTIONS Copyright© 2011–2012,Texas InstrumentsIncorporated
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RX_CMIX_PHASE_INCR – Thisbitcan be used to controlthe mixingphase withoutthe need forthe SYNC pin.A 0 to1 transitionon thisbitcauses thephase ofmixingintheRX CMIX tobe incrementedby 1 withrespecttothecurrentphase ofmixing.To incrementthephase ofmixingmore thanonce,clear and thensetthisbitonce again.Syncingneeds tobe disabledforRX CMIX forthismode towork.(This means thatbothglobalsyncing,as wellas blocklevelsyncingneeds tobe disabledforCMIX ) RX_CMIX_PHASE(1:0) – The valueprogrammed intothisisappliedas theRX CMIX phase,when the CMIX issynced,Syncingneeds tobe enabledforCMIX forthismode towork. RX_DIV_PHASE – The valueprogrammed intothisisappliedas theRX Dividerphase,when thedivider issynced.Ifdividerisnotsynced,thenoutputlatencycan differby 1 withrespecttothesamplingclock. The RX dividerisused whenever thedecimationfilterisenabled. RX_DIV_PHASE_INV – Thisbitisused tocontrolthephase oftheRX dividerwithouttheneed forthe SYNC pin.A 0 to1 transitionon thisbitcauses thephase ofdivisionintheRX Dividertobe invertedby 1 withrespecttothecurrentphase ofdivision.To invertthephase ofdivisionmore thanonce,clearand thensetthisbitonce again.Syncingneeds tobe disabledforRX Dividerforthismode towork. RegisterName – CONFIG63 – Address 0x167,Default= 0x00 RX_BYP_SRC RX_BYP RX_CHB_PDN_SRC RX_CHB_PDN RX_CHA_PDN RX_CHA_PDN_S RX_DIS RC RX_DIS – DisablestheRX signalchainofbothchannels.Allblocksinthesignalchainarepowered down, and theRX outputismid-code. RX_CHA_PDN_SRC – Settingthiscausesthevalueprogrammed intoRX_CHA_PDN totakeeffect. RX_CHA_PDN – Powers down Channel A inRx signalchain.Outputof the channelismid code.Set RX_CHA_PDN_SRC forthistotakeeffect.Outputclockisnotpowered down. RX_CHB_PDN – Powers down Channel B inRx signalchain.Outputof the channelismid code.Set RX_CHB_PDN_SRC forthistotakeeffect.Outputclockisnotpowered down. RX_CHB_PDN_SRC – Settingthiscausesthevalueprogrammed intoRX_CHB_PDN totakeeffect. Note thatwhen indefaultmode ofoperation(noneoftheregister-selectabledigitalfeaturesenabled),all4 ofabove bits(RX_CHA_PDN, RX_CHA_PDN_SRC, RX_CHB_PDN, RX_CHB_PDN_SRC) have tobe set togetherto‘1’forthem totakeeffect.However,ifany ofthedigitalfeatures(likeinterpolation,Finemixer, Coarse mixer,or QMC gain/phaseor offset)are enabled,then the channelA can be independently powered down usingbitsRX_CHA_PDN and RX_CHA_PDN_SRC, and channelB can be independently powered down usingbitsRX_CHB_PDN and RX_CHB_PDN_SRC. RX_BYP – The inputstoboththeRx channelsaredirectlypassed totheoutputs.Set RX_BYP_SRC for thistotakeeffect.Use thismode tooperatetheRx withlowestlatency. RX_BYP_SRC – Settingthiscausesthevalueprogrammed intoRX_BYP totakeeffect. RegisterName – CONFIG64 – Address 0x168,Default= 0x00 DIS DIS DIS DIS DIS RX_CMIX_SYNC_DIS – DisablesSyncing of the Rx Coarse mixer.This takes effectonly when RX_GLOBAL_SYNC_DIS isset. RX_DIV_SYNC_DIS – Disables Syncing of the Rx clock divider.This takes effectonly when RX_GLOBAL_SYNC_DIS isset. RX_QMC_OFF_SYNC_DIS – DisablesSyncingofRx QMC OffsetCorrection.Thistakeseffectonlywhen RX_GLOBAL_SYNC_DIS isset. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 35 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RX_QMC_GAIN_PH_SYNC_DIS – DisablesSyncingofRx QMC Gain Phase Correction. Thistakeseffectonlywhen RX_GLOBAL_SYNC_DIS isset. RX_GLOBAL_SYNC_DIS – When set,disablesglobalsyncingofRX signalchain.When cleared,a rising edge on theselectedsyncsourcecausesRX blockstobe synced. RegisterName – CONFIG65 – Address 0x169,Default= 0x00 SRC SRC SRC SRC SRC RX_CMIX_SYNC_SRC – Specifiesthesync sourcefortheRX Coarse mixer.When cleared,SYNC pinis used as the sync source. When set,a risingedge on serialinterfacebitRX_CMIX_SER_IF_SYNC in Register 0x16A is used as the sync source for RX CMIX. This is applicablewhen RX_GLOBAL_SYNC_DIS isset,and RX_CMIX_SYNC_DIS iscleared. RX_DIV_SYNC_SRC – Specifiesthesync sourcefortheRX Divider.When cleared,SYNC pinisused as thesyncsource.When set,a risingedge on serialinterfacebitRX_DIV_SER_IF_SYNC inregister0x16A isused as thesync sourceforRX Divider.Thisisapplicablewhen RX_GLOBAL_SYNC_DIS issetand RX_DIV_SYNC_DIS iscleared. RX_QMC_OFF_SYNC_SRC – Specifiesthesync sourceforRX QMC OffsetCorrection.When cleared, SYNC pin is used as the sync source . When set , a risingedge on serialinterfacebit RX_QMC_OFF_SER_IF_SYNC in register0x16A is used as the sync source forRX QMC Offset Correction.Thisisapplicablewhen RX_GLOBAL_SYNC_DIS issetand RX_QMC_OFF_SYNC_DIS is cleared. RX_QMC_GAIN_PH_SYNC_SRC – Specifiesthesync sourceforRX QMC Gain Phase Correction.When cleared,SYNC pin is used as the sync source.When set,a risingedge on serialinterfacebit RX_QMC_GAIN_PH_SER_IF_SYNC in register0x16A isused as the sync source forRX QMC Gain Phase Correction. This is applicable when RX_GLOBAL_SYNC_DIS is set and RX_QMC_GAIN_PH_SYNC_DIS iscleared. RX_GLOBAL_SYNC_SRC – Specifiesthesync sourceforRX. When cleared,SYNC pinisused as the sync source.When set,a risingedge on serialinterfacebitRX_GLOB_SER_IF_SYNC inregister0x16A isused as thesyncsourceforRX. Thisisapplicablewhen RX_GLOBAL_SYNC_DIS iscleared. RegisterName – CONFIG66 – Address 0x16A, Default= 0x00 IF_SYNC SER_ IF_SYNC IF_SYNC IF_SYNC SYNC RX_CMIX_SER_IF_SYNC – A risingedge on thisbitisused as the sync sourceforRX CMIX. Thisis applicablewhen RX_GLOBAL_SYNC_DIS is set, and RX_CMIX_SYNC_DIS is cleared,and RX_CMIX_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheRX CMIX. RX_DIV_SER_IF_SYNC – A risingedge on thisbitisused as the sync sourceforRX Divider.Thisis applicablewhen RX_GLOBAL_SYNC_DIS is set, and RX_DIV_SYNC_DIS is cleared, and RX_DIV_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheRX Divider. RX_QMC_OFF_SER_IF_SYNC – A risingedge on thisbitisused as thesync sourceforRX QMC Offset correction block. This is applicable when RX_GLOBAL_SYNC_DIS is set, and RX_QMC_OFF_SYNC_DIS iscleared,and RX_QMC_OFF_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheRX QMC Offsetcorrection. RX_QMC_GAIN_PH_SER_IF_SYNC – A risingedge on thisbitisused as thesync sourceforRX QMC Gain Phase correctionblock. This is applicablewhen RX_GLOBAL_SYNC_DIS is set, and RX_QMC_GAIN_PH_SYNC_DIS is cleared,and RX_QMC_GAIN_PH_SYNC_SRC specifiesserial interfacebittobe thesyncsourcefortheRX QMC Gain Phase correction.
36 REGISTER DESCRIPTIONS Copyright© 2011–2012,Texas InstrumentsIncorporated
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RX_GLOBAL_SER_IF_SYNC – A risingedge on thisis used as the sync source forRX . This is applicablewhen RX_GLOBAL_SYNC_DIS is cleared,and RX_GLOBAL_SYNC_SRC specifiesserial interfacebittobe thesyncsourceforRX. RegisterName – CONFIG67 – Address 0x16B, Default= 0x00 ENA ENA NEEDED NEEDED RX_QMC_OFF_SYNC_NEEDED – Specifiesifsyncingisneeded forRX QMC OffsetCorrection.Ifset, QMC Offsetvaluesprogrammed intothe serialinterfaceregistersare not appliedto the QMC Offset correctionblockuntila Sync isapplied. RX_QMC_GAIN_PH_SYNC_NEEDED – Specifiesifsyncing is needed for RX QMC Gain Phase Correction.Ifset,QMC gainand Phase valuesprogrammed intothe serialinterfaceregistersare not appliedtotheQMC Gain Phase correctionblockuntila syncisapplied. RX_QMC_OFFSET_ENA – EnablesRX QMC OffsetCorrection. RX_QMC_CORR_ENA – EnableRX QMC Gain Phase Correction. RegisterName – CONFIG68 – Address 0x16C, Default= 0x00 (Synced) RX_QMC_OFFSETA(12:5) RX_QMC_OFFSETA(12:5) – Upper 8 bitsofADC A OffsetCorrection.The lower5 bitsareinCONFIG69 Register. RegisterName – CONFIG69 – Address 0x16D, Default= 0x00 (Synced) RX_QMC_OFFSETA(4:0) RX_QMC_GAINA(2:0) RX_QMC_OFFSETA(4:0) – Lower 5 bitsofADC A OffsetCorrection. RX_QMC_GAINA(2:0) – Lower 3 bitsofthe11 bitQMC Gain word forADC A. The upper 8 bitsare in CONFIG70 register.Thefull11 bitRX_QMC_GAINA(10:0) word isformattedas UNSIGNED witha range or0 to1.9990.The implieddecimalpointforthemultiplicationisbetween bits(9)and (10). RegisterName – CONFIG70 – Address 0x16E,Default= 0x00 (Synced) RX_QMC_GAINA(10:3) RX_QMC_GAINA(10:3) – Upper 8 bitsifthe11 bitQMC Gain word forADC A RegisterName – CONFIG71 – Address 0x16F,Default= 0x00 (Synced) RX_QMC_OFFSETB(12:5) RX_QMC_OFFSETB(12:5) – Upper 8 bitsofADC B OffsetCorrection.The lower5 bitsareinCONFIG72 Register. RegisterName – CONFIG72 – Address 0x170,Default= 0x00 (Synced) RX_QMC_OFFSETB(4:0) RX_QMC_GAINB(2:0) RX_QMC_OFFSETB(4:0) – Lower 5 bitsofADC B OffsetCorrection. RX_QMC_GAINB(2:0) – Lower 3 bitsofthe11 bitQMC Gain word forADC B. The upper 8 bitsare in CONFIG73 register.Thefull11 bitRX_QMC_GAINB(10:0) word isformattedas UNSIGNED witha range or0 to1.9990. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 37 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG73 – Address 0x171,Default= 0x00 (Synced) RX_QMC_GAINB(10:3) RX_QMC_GAINB(10:3) – Upper 8 bitsofthe11 bitQMC Gain word forADC B. RegisterName – CONFIG74 – Address 0x172,Default= 0x00 RX_QMC_PHASE(9:2) RX_QMC_PHASE(9:2) – Upper 8 bitsof the 10 bitQMC Phase word. The lowertwo bitsare in the CONFIG75 register.The fullQMC_PHASE(9 :0)correctionword isformattedas 2s complement and scaledto occupy a range of -0.125to 0.12475.To acomplishQMC Phase correction,thisvalue is multipliedby thecurrentQ sample,thensummed totheIsample. RegisterName – CONFIG75 – Address 0x173,Default= 0x00 (Synced) RX_QMC_PHASE(1:0) RX_QMC_PHASE(1:0) – Lower 2 bitsofthe10 bitQMC Phase word. RegisterName – CONFIG76 – Address 0x174,Default= 0x00 (Synced) RX_NCO_FREQ_WORD(31:24) RX_NCO_FREQ_WORD(31:24) – See CONFIG79 below. RegisterName – CONFIG77 – Address 0x175,Default= 0x00 (Synced) RX_NCO_FREQ_WORD(23:16) RX_NCO_FREQ_WORD(23:16) – See CONFIG79 below. RegisterName – CONFIG78 – Address 0x176,Default= 0x00 (Synced) RX_NCO_FREQ_WORD(15:8) RX_NCO_FREQ_WORD(15:8) – See CONFIG79 below. RegisterName – CONFIG79 – Address 0x177,Default= 0x00 (Synced) RX_NCO_FREQ_WORD(7:0) RX_NCO_FREQ_WORD(7:0) – This32-bitword specifiesthe frequencyof the NCO used by the fine mixer.The twoscomplement formattedvaluecan be positiveornegative,and theLSB isequalto(Fs/232). RegisterName – CONFIG80 – Address 0x178,Default= 0x00 (Synced) RX_NCO_PHASE_OFF(15:8) RX_NCO_PHASE_OFF(15:8) – See CONFIG81 below.
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RegisterName – CONFIG81 – Address 0x179,Default= 0x00 (Synced) RX_NCO_PHASE_OFF(7:0) RX_NCO_PHASE_OFF(7:0) – Thisisthe Phase offsetadded to the NCO accumulatorjustbeforethe generationoftheSIN and COS values. RegisterName – CONFIG82 – Address 0x17A, Default= 0x00 PWR_MTR_COARSE_SAMPLES(2:0) RX_MIXER_EN RX_MIXER_GAIN(1:0) RX_MIXER_GAIN(1:0) – This specifiesthe gain to be appliedto the mixer outputto preventitfrom saturating. VALUE GAIN 0 -2.5dB 1 -6dB 2 0 dB 3 0 dB RX_MIXER_EN – ThisenablestheFullmixer,whichalsocausestheNCO tobe enabled. PWR_MTR_COARSE_SAMPLES(2:0) – Specifiesthenumber ofsamples,‘N ’overwhichpower istobe computed when thepower meter isconfiguredinthecoarsemode. Keeps refreshingevery‘N ’samples but writesto serialinterfaceregisteronlywhen serialclockisavailable– which requiresa writeto this page.Stopsrefreshingonce you getintoreadoutmode. VALUE NUMBER OF SAMPLES 0 16 1 32 2 64 3 128 4 256 5 512 6 1024 7 16 RegisterName – CONFIG83 – Address 0x17B, Default= 0x00 SYNC_DIS SYNC_SRC SER_IF_SYNC SYNC_NEEDED SYNC_DIS SYNC_SOURCE IF_SYNC SYNC_ NEEDED RX_NCO_SYNC_NEEDED – Specifiesifsyncingisneeded forRX NCO. Ifset, NCO Frequency and Offsetwords programmed intothe serialinterfaceregistersare not appliedto the NCO untila sync is applied RX_NCO_SER_IF_SYNC – A risingedge on thisbitisused as the sync sourceforRX NCO. Thisis applicablewhen RX_GLOBAL_SYNC_DIS is set, and RX_NCO_SYNC_DIS is cleared,and RX_NCO_SYNC_SRC specifiesserialinterfacebittobe thesyncsourcefortheNCO. RX_NCO_SYNC_SRC – Specifiesthesync sourceforRX NCO. When cleared,SYNC pinisused as the sync source.When set,a risingedge on serialinterfacebitRX_NCO_SER_IF_SYNC isused as thesync sourceforRX NCO. Thisisapplicablewhen RX_GLOBAL_SYNC_DIS isset RX_NCO_SYNC_DIS – Disables Syncing of the RX NCO .This takes effect only when RX_GLOBAL_SYNC_DIS isset Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 39 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com PWR_MTR_SYNC_NEEDED – Specifiesifsyncingisneeded forthe RX Power Meter . Ifset,power computationbeginsa programmablenumber ofcyclesafterthedetectionofa sync pulse.Appliesforboth thecoarseand finepower meters. PWR_MTR_SER_IF_SYNC – A risingedge on thisbitisused as thesync sourceforRX Power Meter. This isapplicablewhen RX_GLOBAL_SYNC_DIS isset,and PWR_MTR_SYNC_DIS iscleared,and PWR_MTR_SYNC_SRC specifiesserialinterfacebittobe thesyncsourceforthePower Meter. PWR_MTR_SYNC_SRC – Specifiesthesync sourceforRX Power Meter .When cleared,SYNC pinis used as thesync source.When set,a risingedge on serialinterfacebitPWR_MTR_SER_IF_SYNC is used as thesyncsourceforRX Power Meter.Thisisapplicablewhen RX_GLOBAL_SYNC_DIS isset PWR_MTR_SYNC_DIS – DisablesSyncing of the RX Power Meter .Thistakes effectonly when RX_GLOBAL_SYNC_DIS isset. RegisterName – CONFIG84 – Address 0x17C, Default= 0x00 INTGR_CNT (20:13) INTGR_CNT(20:13) – Upper 8 bitsofthe21 bitIntegrationcountforthefinepower meter.Integrationis done over(8N + 3)sampleswhere N istheunsignedintegerrepresentedby INTGR_CNT (20:0) RegisterName – CONFIG85 – Address 0x17D, Default= 0x00 INTGR_CNT(12:5) INTGR_CNT(12:5) – Middle8 bitsofthe21 bitIntegrationcountforthePower meter. RegisterName – CONFIG86 – Address 0x17E,Default= 0x00 INTGR_CNT(4:0) SYNC_CNT(8:6) SYNC_CNT(8:6) – Upper 3 bitsofthe9 bitSync countforthefinepower meter.Afterthedetectionofa sync pulse,thereisa delayof8N +4 cyclesbeforeIntegrationbegins,where N istheunsignedinteger representedby SYNC_CNT(8:0) INTGR_CNT(4:0) – Lower 5 bitsofthe21 bitIntegrationcountforthefinepower meter. RegisterName – CONFIG87 – Address 0x17F,Default= 0x00 SYNC_CNT(5:0) SYNC_CNT(5:0) – Lower 3 bitsofthe9 bitSync count. RegisterName – CONFIG88 – Address 0x180,Default= 0x00 INTRV_CNT (20:13) INTRV_CNT (20:13)– Upper 8 bitsof the 21 bitIntervalcount forthe finepower meter.The actual Intervalperiodis(8N + 3)sampleswhere N istheunsignedintegerrepresentedby INTRV_CNT (20:0)
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RegisterName – CONFIG89 – Address 0x181,Default= 0x00 INTRV_CNT(12:5) INTRV_CNT(12:5) – Middle8 bitsofthe21 bitIntervalcountforthePower meter RegisterName – CONFIG90 – Address 0x182,Default= 0x00 INTRV_CNT (4:0) PWR_MTR_MODE PWR_MTR_FINE PWR_MTR_EN INTRV_CNT(4:0) – Lower 4 bitsofthe21 bitIntervalcountforthePower meter PWR_MTR_EN – Enablesthepower meter.Common forfineand coarsepower meters. PWR_MTR_FINE – When cleared,configuresthe power meter in ‘Fine ‘ mode where itgiveslinear output.When set,configuresitinthecoarsemode, where itgivesoutputinthedb scale.Incoarsemode, the number of samples over which power is computed is specified in the PWR_MTR_COARSE_SAMPLES(2:0) inCONFIG82. PWR_MTR_MODE – When cleared,configuresthepower meterintherealmode – OutputI= I2,Output Q = Q 2.When set,configuresitincomplexmode – Output= I2 + Q 2. RegisterName – CONFIG91 – Address 0x183,Default= 0x00 (Read Only) PWR_OP_I(57:50) PWR_OP_I(57:50) – Upper 8 bitsofthePower meteroutputforIchannelwhen itisconfiguredintheFine mode. Thisrepresentspower ofIchannelwhen configuredintherealmode, and thecomplexpower when configuredinthecomplexmode. RegisterName – CONFIG92 – Address 0x184,Default= 0x00 (Read Only) PWR_OP_I(49:42) PWR_OP_I(49:42) RegisterName – CONFIG93 – Address 0x185,Default= 0x00 (Read Only) PWR_OP_I(41:34) PWR_OP_I(41:34) RegisterName – CONFIG94 – Address 0x186,Default= 0x00 (Read Only) PWR_OP_I(33:26) PWR_OP_I(33:26) RegisterName – CONFIG95 – Address 0x187,Default= 0x00 (Read Only) PWR_OP_I(25:18) PWR_OP_I(25:18) Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 41 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG96 – Address 0x188,Default= 0x00 (Read Only) PWR_OP_I(17:10) PWR_OP_I(17:10) RegisterName – CONFIG97 – Address 0x189,Default= 0x00 (Read Only) PWR_OP_I(9:2) PWR_OP_I(9:2) RegisterName – CONFIG98 – Address 0x18A, Default= 0x00 (Read Only) PWR_OP_I(1:0) PWR_OP_Q(57:52) PWR_OP_Q(57:0) – Power meter outputforQ channelwhen itisconfiguredinthe Fine mode . This representspower of Q channelwhen configuredinthe realmode. In the complex mode, thisdoes not containany information.For a 12-bitoutput(as isthe case inAFE722x), the lowereightbitswillnot containany information;so itissufficienttoreadoutPWR_OP_Q(57:8). PWR_OP_I(57:0) – Power meter outputforI channelwhen itisconfiguredinthe Fine realmode. This representthepower oftheIchannel,and inthecomplex mode, itrepresentsthecomplex power.For a 12-bitoutput(as isthe case inAFE722x), the lowereightbitswillnot containany information;so itis sufficienttoreadoutPWR_OP_I(57:8). RegisterName – CONFIG99 – Address 0x18B, Default= 0x00 (Read Only) PWR_OP_Q(51:44) PWR_OP_Q(51:44) RegisterName – CONFIG100 – Address 0x18C, Default= 0x00 (Read Only) PWR_OP_Q(43:36) PWR_OP_Q(43:36) RegisterName – CONFIG101 – Address 0x18D, Default= 0x00 (Read Only) PWR_OP_Q(35:28) PWR_OP_Q(35:28) RegisterName – CONFIG102 – Address 0x18E,Default= 0x00 (Read Only) PWR_OP_Q(27:20) PWR_OP_Q(27:20) RegisterName – CONFIG103 – Address 0x18F,Default= 0x00 (Read Only) PWR_OP_Q(19:12)
42 REGISTER DESCRIPTIONS Copyright© 2011–2012,Texas InstrumentsIncorporated
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 PWR_OP_Q(19:12) RegisterName – CONFIG104 – Address 0x190,Default= 0x00 (Read Only) PWR_OP_Q(11:4) PWR_OP_Q(11:4) RegisterName – CONFIG105 – Address 0x191,Default= 0x00 (Read Only) PWR_OP_I_RDY – Setwhen theveryfirstcomputationfromthe‘I’power meteriscomplete. PWR_OP_Q_RDY – Setwhen theveryfirstcomputationfromthe‘Q ’power meteriscomplete. PWR_OP_Q(3:0) – Lowest two bitsofthepower meter outputforQ channelwhen itisconfiguredtodo finepower computationintherealmode. RegisterName – CONFIG106 – Address 0x1B2, Default= 0x00 (Read Only) COARSE_PWR_OP_I(3:0) COARSE_PWR_OP_Q(3:0) COARSE_PWR_OP_Q(3:0) – Representsthepower intheQ channelwhen power meterisconfiguredin thecoarsepower computationmode. Incomplex power computationmode, thisoutputshouldbe ignored. The mapping ofthisvaluetothedb scaleisgivenbelowtable. COARSE_PWR_OP_I(3:0) – Representsthepower intheIchannelwhen power meter isconfiguredin the coarsepower computationmode. In complex power computationmode, thisoutputrepresentsthe complexpower. Note – In complex power computationmode, the fullscaleis twiceof what itis in the realpower computationmode. VALUE POWER IN DB SCALE
15 Greaterthan–1 dbFS
14 Greaterthan–2 dbFS
13 Greaterthan–3 dbFS
12 Greaterthan–4 dbFS
11 Greaterthan–5 dbFS
10 Greaterthan–6 dbFS
9 Greaterthan–7 dbFS
8 Greaterthan–8 dbFS
7 Greaterthan–9 dbFS
6 Greaterthan–10 dbFS
5 Greaterthan–11 dbFS
4 Greaterthan–12 dbFS
3 Greaterthan–13 dbFS
2 Greaterthan–14 dbFS
1 Greaterthan–15 dbFS
0 Lesserthan–15 dbFS
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5.3 CHIP CONTROL REGISTERS
RegisterName – CONFIG107 – Address 0x000,Default= 0x00 SOFTWARE_RESET SOFTWARE_RESET:- Registerbittoresetthedevice.Once set,thebitgeneratesa resetpulse,which resetsalltheregisterbitsincludingitself. RegisterName – CONFIG108 – Address 0x207,Default= 0x00 REG_PDNFRM_REG REG_PDN_FAST REG_PDN_GBL REG_PDNQ REG_PDNI REG_PDN_RX REG_PDN_TX REG_PDN_FRM_REG :SpecifieswhetherthePDN controlisthroughPIN orregisterbit.When cleared, PDN pinisused as themastercontrol. Forallthebelowpower down modes towork,eithersetREG_PDN_FRM_REG orpullPDN pinto‘High’. REG_PDN_FAST : When REG_PDN_FRM_REG is low, thisbitconfiguresthe PDN pin for fast powerdown control.When REG_PDN_FRM_REG ishigh,thisbitdirectlycontrolsthe fastpowerdown mode. When set,itpower downs both transmitterand receiverbut keeps certainblockslikereference circuitryactive.AlsotheRx outputclockisstillactive.Thismode can be used where fastwake up times arerequired. REG_PDN_GBL : When REG_PDN_FRM_REG is low, thisbitconfiguresthe PDN pin forglobal powerdown control.When REG_PDN_FRM_REG ishigh,thisbitdirectlycontrolstheglobalpowerdown mode. When set,itpowers down almostallcircuitryinsidethechip.Thus thismode can be used when lowestpower isdesired.The wakeup timesinthismode are much higherthan inthe fastpowerdown mode. REG_PDNQ :Power downs Q channelofbothtransmitterand reciever. REG_PDNI :Power down Ichannelofbothtransmitterand reciever. REG_PDN_RX :Power downs recieveri.eboththeADC ’s.Clockpathisstillactive. REG_PDN_TX :Power downs transmitteri.eboththeDAC ’s. REG_PDN_FRM_REG has a similarroleto play for the above modes (REG_PDNQ, REG_PDNI, REG_PDN_RX, REG_PDN_TX). When REG_PDN_FRM_REG islow,itconfiguresthe PDN pinto the functionof the bitthatis set.When REG_PDN_FRM_REG is high,the set bitdirectlycontrolsthe describedpowerdown mode. At20 MHz Fs,thetypicalpower consumptionindifferentmodes areas follows: CURRENT ON 1.8V SUPPLY CURRENT ON 3 V SUPPLYCONDITION (mA) (mA) Normal 63 58 GlobalPower down (REG_PDN_GBL = 1) 2.4 3 Fastpower down (REG_PDN_FAST = 1) 25 13 Rx_power down (REG_PDN_RX = 1) 27 58 Tx power down (REG_PDN_TX = 1) 62 13 BothRx and Tx (REG_PDN_TX = 1,REG_PDN_RX = 1) 25 13 RegisterName – CONFIG109 – Address 0x208,Default= 0x00 REG_PDNI_TX REG_PDNQ_TX REG_PDNI_RX REG_PDNQ_RX MODE_LP_CMOS REG_SINGLE
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 REG_PDNI_TX :Power downs TX ChannelA (IChannel)alone. REG_PDNQ_TX :Power downs TX ChannelB (Q Channel)alone. REG_PDNI_RX :Power downs RX ChannelA (IChannel)alone. REG_PDNQ_RX :Power downs RX ChannelB (Q Channel)alone. REG_PDN_FRM_REG has a similarroletoplayfortheabove modes (REG_PDNI_TX, REG_PDNQ_TX, REG_PDNI_RX, REG_PDNQ_RX). When REG_PDN_FRM_REG islow,itconfiguresthePDN pintothe functionof the bitthatis set.When REG_PDN_FRM_REG is high,the set bitdirectlycontrolsthe describedpowerdown mode. MODE_LP_CMOS : Low power RX CMOS mode. When theRX interfaceissettoCMOS interface,the devicepower can be loweredby about20 mW by settingthisbit.Use thismode onlyforFs lessthan40 MSPS. RefertosectionLow power RX CMOS mode . REG_SINGLE : Settingthisbitpower downs one ADC (ChannelA) and One DAC (ChannelA).The outputdataformatisSDR. Inthismode DAC ChannelB and ADC ChannelB areactive. RegisterName – CONFIG110 – Address 0x209,Default= 0x00 LVDS_ CHB LVDS_ CHA LVDS_CLK CMOS_ CLK CMOS_DAT REG_OEZ_CMOS_DAT: 3-stateRX CMOS data buffers(use forHalfDuplex TX mode when using CMOS interface) REG_OEZ_CMOS_CLK: 3-stateRX CMOS clockbuffer(useforHalfDuplexTX mode when usingCMOS interface) REG_OEZ_LVDS_CLK: 3-stateRX LVDS clockbuffer(useforHalfDuplex TX mode when usingLVDS interface) REG_OEZ_LVDS_CHA: 3-stateRX LVDS databuffersforChannelA (useforHalfDuplexTX mode when usingLVDS interface) REG_OEZ_LVDS_CHB: 3-stateRX LVDS databuffersforChannelB (useforHalfDuplexTX mode when usingLVDS interface) RegisterName – CONFIG111 – Address 0x20A, Default= 0x00 REG_SE_CLK REG_LVDS_TX REG_LVDS_RX WHAT_IS_SDOUT <1:0> REG_SE_CLK: When set,the deviceisconfiguredto expecttwo singleended clockson CLKINP and CLKINN. DAC_CLK getsderivedfrom theclockon CLKINN and ADC_CLK from theclockon CLKINP. The differentialclockbufferisturnedoff,savingabout6mA ofcurrenton the1.8V supply. REG_LVDS_TX: By defaultboth RX and TX interfacesare inCMOS mode, thisbitsetsthe TX input interfaceinLVDS mode REG_LVDS_RX: thisbitsetstheRX outputinterfaceinLVDS mode. Inadditiontosettingthisbit,alsoset bitMASTER_OVERRIDE_RX (inCONFIG131) forproperLVDS settings. WHAT_IS_SDOUT <1:0>:ConfigurestheSDOUT pin. WHAT_IS_SDOUT <1:0> Mode
00 Floating
01 Analogtesto/p(Do notuse)
10 Digitalo/p(Use forAux ADC and registerreadout)
11 Digitali/p(Use forAux DAC inputmode)
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5.4 TX DAC CONTROL REGISTERS
RegisterName – CONFIG112 – Address 0x237,Default= 0x00 DACQ_GAIN <7:0> DACQ_GAIN <7:0>:FinecontrolofChannelB (DACQ) outputcurrent. Outputcurrentrangeis0.04*FSto-0.04*FS,where FS isFullscalecurrentofDACQ. The word isin2’s complement format. DACQ_GAIN <7:0>(decimalequivalent) OUTPUT CURRENT 0 FS 127 FS+.04*FS 128 FS-.04*FS RegisterName – CONFIG113 – Address 0x238,Default= 0x00 DACI_GAIN <7:0> DACI_GAIN <7:0>:FinecontrolofChannelA (DACI)outputcurrent.SimilartoDACQ_GAIN <7:0>. RegisterName – CONFIG114 – Address 0x239,Default= 0x00 DACI_COARSEZ <3:0> DACQ_COARSEZ <3:0> DACI_COARSEZ <3:0>: Coarse controlof the Channel A (DACI) outputcurrent.Let FS be fullscale currentthen, DACI_COARSEZ <3:0> OUTPUT CURRENT 0000 FS 0001 15*FS/16 0010 14*FS/16 0011 13*FS/16 0100 12*FS/16 0101 11*FS/16 0110 10*FS/16 0111 9*FS/16 1000 8*FS/16 1001 7*FS/16 1010 6*FS/16 1011 5*FS/16 1100 4*FS/16 1101 3*FS/16 1110 2*FS/16
1111 FS/16
DACQ_COARSEZ <3:0>: Coarse controlof the Channel B (DACQ) output current- similarto DACI_COARSEZ <3:0>.
46 REGISTER DESCRIPTIONS Copyright© 2011–2012,Texas InstrumentsIncorporated
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5.5 CLOCKING CONTROL REGISTERS
RegisterName – CONFIG115 – Address 0x23C, Default= 0x00 STR_CTRL <1:0>:ControlsthestrengthoftheRX CMOS outputclock(ADC_DCLKOUT) and databuffers (increasesthestrength).When runningatFs higherthan90 MSPS, setto‘10’togetmore timingmargins. Enablingthismode mightincreasethedigitalnoisecoupledtoanalogand may degradetheADC SNR by up toa dB. DIV_ADC <1:0>:DividestheclockgoingtotheADC. DIV_ADC <1:0> DIVISION FACTOR
00 Default(nodivision)
DIV_DAC <1:0>:DividestheclockgoingtotheDAC. DIV_ADC <1:0> DIVISION FACTOR RegisterName – CONFIG116 – Address 0x23D, Default= 0x00 PLL_ENABLE PLL_DIVM <1:0> PLL_DIVN PLL_ENABLE: SettingthisbitenablesthePLL. OutputclockofthePLL iseither2X or 4X ofFs (input clockrate). PLL_DIVN: Selectsmultiplicationby 4 (defaultismultiplicationby 2). PLL_DIVM <1:0>: Differentvaluesas listedinthe below tableneed to be programmed fordifferentFs ranges. PLL_DIVM <1:0> FS inMSPS Multiplicationby 2 Multiplicationby 4 15-20 3 2 20-35 2 1 35-80 1 0 > 80-180 0 Out ofrange WhileoperatingPLL witha multiplicationfactorsetby PLL_DIVN = X, therecan be significantspursat (NFs/X+/-Fin)where N isan integer.AtFin= 10 MHz, thesespurscan be about-60dBc. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 47 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RegisterName – CONFIG117A – Address 0xDB, Default= 0x00 ENABLE_DCC_CHB ENABLE_DCC_CHB: Enablesthedutycyclecorrectioncircuit(DCC) fortheADC_CLK forADC Channel B.Itisrecommended touse theDCC when operatingatfrequenciesofADC_CLK higherthan65 MSPS. RegisterName – CONFIG117B – Address 0xF2,Default= 0x00 ENABLE_DCC_CHA ENABLE_DCC_CHA: Enablesthedutycyclecorrectioncircuit(DCC) fortheADC_CLK forADC Channel A.Itisrecommended touse theDCC when operatingatfrequenciesofADC_CLK higherthan65 MSPS.
5.6 AUX DAC REGISTERS
RegisterName – CONFIG118 – Address 0x242,Default= 0x00 AUX_DAC_TERM_N <2:0> EN_AUXDACB EN_AUXDACA AUX_DAC_TERM_N <2:0>:TerminationresistorforthenegativeterminaloftheAUX DAC (internalnode). Choose ittobe closetotheterminationresistoron thepin. AUX_DAC_TERM_N <2:0> TERMINTION RESISTOR (ohm) 0 200 (default) 1 infinite 10 67 11 100 100 133 101 400 110 57 111 80 EN_AUXDACB: EnablesAUXDACB. EN_AUXDACA: EnablesAUXDACA. RegisterName – CONFIG119 – Address 0x243,Default= 0x00 REG_AUXDACA_IN <11:4> REG_AUXDACA_IN <11:4> – RegisterbitsforDACA datainRegisterAccess mode RegisterName – CONFIG120 – Address 0x244,Default= 0x00 REG_AUXDACA_IN <3:0> REG_AUXDACA_IN <3:0> – RegisterbitsforDACA datainRegisterAccess mode.
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RegisterName – CONFIG121 – Address 0x245,Default= 0x00 REG_AUXDACB_IN <11:4> REG_AUXDACB_IN <11:4> – RegisterbitsforDACB datainRegisterAccess mode RegisterName – CONFIG122 – Address 0x246,Default= 0x00 REG_AUXDACB_IN <3:0> REG_AUXDACB_IN <3:0> – RegisterbitsforDACB datainRegisterAccess mode RegisterName – CONFIG123 – Address 0x248,Default= 0x00 FS_AUXDACI <3:0> FS_AUXDACI <3:0> – SetsfullscaleoutputcurrentforAUXDACA. The 16 levelsinmA are: FS_AUXDACI <3:0> OUTPUT CURRENT(mA) 0000 5 0001 5.5 0010 4 0011 4.5 0100 7 0101 7.5 0110 6 0111 6.5
1000 Do notuse
1001 Do notuse
1010 Do notuse
1011 Do notuse
1101 3.5
1110 Do notuse
1111 2.5 RegisterName – CONFIG124 – Address 0x249,Default= 0x00 FS_AUXDACQ <3:0> FS_AUXDACQ <3:0> – Sets fullscaleinputcurrentforAUXDACB. This registerissimilarto Register 0x248.
5.7 LVDS TX INPUT INTERFACE REGISTERS
RegisterName – CONFIG125 – Address 0x30B, Default= 0x00 TWOWIRE_TX RESOLUTION_TX <2:0> MSB_FIRST_TX SERIALIZATION_TX <1:0> SDR_TX Allthe modes of register0x30B works onlyifMASTER_OVERRIDE_TX (Bit<2> inAddress 0x30C) is enabled. TWOWIRE_TX: Setstwo wiremodes inthetransmitterside. RESOLUTION_TX <2:0>:To settheinputresolutionoftheTransmitter. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 49 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RESOLUTION_TX <2:0> RESOLUTION 000 12 MSB_FIRST_TX <1:0>:DecideswhetherLSB firstorMSB first.DefaultisLSB first.. MSB_FIRST_TX DATA PATTERN
0 LSB first
1 MSB first
SERIALIZATION_TX <1:0>:Setsserializationfactorofthetransmitter. SERIALIZATION_TX <1:0> SERIALIZATION FACTOR 00 12x (default) 01 14x 10 16x SDR_TX: By settingthisTx expectsSDR inputpattern,where as thedefaultisDDR. Bitclockisdouble rateinSDR mode. RegisterName – CONFIG126 – Address 0x30C, Default= 0x00 MASTER_OVERRIDE_TX BITWISE_TX DFS_TX Allthe modes of register0x30C works onlyifMASTER_OVERRIDE_TX (Bit<2> inAddress 0x30C) is enabled. MASTER_OVERRIDE_TX: Masterbitforvariousoverridemodes BITWISE_TX: To setthedeviceinbitwisemode. DFS_TX: Determinesthedataformatoftheincomingdata. DFS_TX DATA FORMAT 0 2’s complement (default) 1 straightoffsetbinary RegisterName – CONFIG127 – Address 0x30d,Default= 0x00 WORDWISE_TX Allthe modes of register0x30D works onlyifMASTER_OVERRIDE_TX (Bit<2> inAddress 0x30C) is enabled. WORDWISE_TX: Ifset,TX expectsword mode formatdata.
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5.8 LVDS RX OUTPUT INTERFACE REGISTERS
RegisterName – CONFIG128 – Address 0x337,Default= 0x00 OVR_EN_RX WORDWISE_ RX PATTERN_SEL_RX <2:0> Allthe modes of register0x337 work onlyifMASTER_OVERRIDE_RX (Bit<7> inAddress 0x33A) is enabled. OVR_EN_RX: Overrangeindicatorenablebit.When 0 – Overrangeisnotsentalongwithdata.If1 – D0 isreplacedby Overrangeindicatorbit. WORDWISE_RX: When selected,wordwisemode isenabled. PATTERN_SEL_RX <2:0>:To selecttheoutputpatternfromtheserializer PATTERN_SEL <2:0> OUTPUT PATTERN
000 Normal ADC pattern
001 AllZeros
010 Allones
011 alternatebetween 1 and 0 (D11..D0alternatesbetween 010101010101 and 101010101010)
100 Data ramp pattern
(D11..D0ramps continuouslyevery4 clockcyclesinstepsof1 LSB)
101 Outputcustom pattern
110 Deskew pattern– D11..D0replacedby 010101010101 111 Sync pattern– D11..D0replacedby 111111000000 in1-wiremode and by 111000111000 in2-wiremode RegisterName – CONFIG129 – Address 0x338,Default= 0x00 CUSTOM PATTERN <15:8> RegisterName – CONFIG130 – Address 0x339,Default= 0x00 CUSTOM PATTERN <7:0> RegisterName – CONFIG131 – Address 0x33A, Default= 0x00 MASTER_OVERRIDE_RX SERIALIZATION_RX <1:0> DFS_RX MSB_FIRST_RX TWOWIRE_RX SDR_RX Allthe modes of register0x33A work onlyifMASTER_OVERRIDE_RX (Bit<7> inAddress 0x33A) is enabled. MASTER_OVERRIDE_RX: Master overridebitforRX interfaceregisters.Thisbitneeds to be setto 1 whenever theRX interfacemode ischosen tobe LVDS interface. SERIALIZATION_RX <1:0>:Setstheserializationfactor. SERIALIZATION_RX <1:0> SERIALIZATION 00 12 01 14 10 16 Intwo wiremode for14x serializationtheframeclockis0.5X,where as 12X and 16X frameclockisstill 1X. DFS_RX: Setstheoutputdataformat. Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 51 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com DFS_RX DATA FORMAT 0 2s-complememt 1 straightoffsetbinary MSB_FIRST_RX: FlipstheoutdataordertoMSB first. MSB_FIRST_RX DATA ORDER TWOWIRE_RX: Configurethedevicetogivedataintwo wiremode. SDR_RX: ConfigurethedevicetogivedatainSDR mode. RegisterName – CONFIG132 – Address 0x33B, Default= 0x00 HALFX_IN_2WIRE_RX BITWISE_RX Allthe modes of register0x33B work onlyifMASTER_OVERRIDE_RX (Bit<7> inAddress 0x33A) is enabled. BITWISE_RX: Configurethedevicetogivedatainbitwisemode. HALFX_IN_2WIRE_RX: Makes theframeclockoutput0.5X (defaultis1X).To be used when inwordwise mode. RegisterName – CONFIG133 – Address 0x23A, Default= 0x00 CLK_STR_2X DATA_STR_2X CLK_STR_RX: When set,theLVDS clockbuffershas doublestrength(tobe used with50 ohms external termination) DATA_STR_2X: When set,allthe LVDS clockbuffershave doublestrength(tobe used with50 ohms externaltermination) RegisterName – CONFIG134 – Address 0x001,Default= 0x00 LVDS_SWING <5:0>
5.9 AUX ADC REGISTERS
RegisterName – CONFIG135 – Address 0x364,Default= 0x00 SHIGH_WIDTH <1:0> NO_OF_SAMPLES_AVGED <1:0> NO_OF_SAMPLES <2:0> CONV_START SHIGH_WIDTH <1:0>:No. ofclockcycleswidthofsamplingclock. SHIGH_WIDTH <1:0> NO.OF CLOCK CYCLE WIDTH 00 15(default) 01 30 10 60 11 150 NO_OF_SAMPLES <2:0>:No. ofsamplestoconvertin1 conversioncycle.
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 NO_OF_SAMPLES <2:0> NO.OF SAMPLES TO CONVERT 000 1 001 2 010 4 011 8 100 16
101 Continuous
110 Continuous
111 Continuous
NO_OF_SAMPLES_AVERAGED <1:0>:No. ofsampleswithinthesame conversioncycletobe averaged. Shouldbe lessthanorequaltoNO_OF_SAMPLES. NO_OF_SAMPLES_AVERAGED <1:0> NO. OF SAMPLES TO BE AVERAGED
00 No averaging
Ifaveragingisset,thentheAux ADC outputisupdatedonce ineveryX samples where X isequaltothe no.ofsamplestobe averaged. CONV_START: StartsConversion. RegisterName – CONFIG136 – Address 0x36F,Default= 0x00 BYPASSZ_BUF RANGE_AUXADC BYPASSZ_BUF: Enablesthehighimpedance inputbuffer. RANGE_AUXADC: SetstheinputfullscalerangeoftheAux ADC. Defaultis0-1.5V.Settingthisbitto1 makes theinputfullscalerange0-DVDD18. RegisterName – CONFIG137 – Address 0x370,Default= 0x00 EN_AUX_ADC MODE_INPUT <1:0> EN_AUX_ADC: Staticcontrolbitthat“wakes up”theAux ADC. MODE_INPUT <1:0>: selectswhich ofthe4 inputs(2 externaland 2 internal)ismultiplexedintotheAux ADC. DefaultisAUXADC_A. MODE_INPUT <1:0> AUX_ADC_INPUT
00 AUX_ADC_A
01 AUX_ADC_B
5.10 HALF DUPLEX MODE REGISTERS
RegisterName – CONFIG138 – Address 0x24D, Default= 0x00 REG_HALF_DUPLEX_ THRU_PIN Copyright© 2011–2012,Texas InstrumentsIncorporated REGISTER DESCRIPTIONS 53 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com REG_HALF_DUPLEX_THRU_PIN: ConfiguresthePDN pinas a togglepinbetween halfduplexRX mode and halfduplexTX mode. When thisbitisset,a ‘1’on thePDN pinputsthedeviceinhalfduplexRX mode (TX shutdown),and a ‘0’on thePDN pinputsthedeviceinhalfduplexTX mode (RX shutdown).
5.11 LOW POWER RX CMOS MODE REGISTERS
InLow power CMOS mode, thereare variousways tomove outputdataofADC withrespecttooutput clocktoachieverequiredsetupand holdtime.Thiscan be done usingfollowingregister. RegisterName – CONFIG139 – Address 0x33D, Default= 0x00 DELAY_CLK_LP_CMOS <1:0>: Programmable delayfortheoutputclock(ADC_DCLKOUT) when inlow power CMOS mode. DELAY_CLK_LP_CMOS <1:0> DELAY (1)(ns) 00 4*X -0.3 01 5*X -0.3 10 2*X -0.3 11 3*X -0.3 (1) X istheunitdelayprogrammed by CHANGE_UNIT_DELAY <2:0> bits. RegisterName – CONFIG140 – Address 0x33F,Default= 0x00 DELAY_DATA_LP_CMOS <2:0> CHANGE_UNIT_DELAY <2:0> CHANGE_UNIT_DELAY <2:0>: Changes the delay step for the DELAY_CLK_LP_CMOS and DELAY_DATA_LP_CMOS programmingwhen inlowpower CMOS mode (MODE_LP_CMOS= ’1’). CHANGE_UNIT_DELAY <2:0> DELAY UNIT "X" (ns) 000 1.12 001 1.5 010 0.55 011 0.9 100 1.85 101 2.2 110 1.25 111 1.62 DELAY_DATA_LP_CMOS <2:0>: Programmable delayforthe outputdata when in low power CMOS mode (MODE_LP_CMOS= ’1’). DELAY_DATA_LP_CMOS <2:0> DELAY (1)(ns) 000 4*X -0.3 001 5*X -0.3 010 6*X -0.3 011 7*X -0.3 100 NA 101 1*X -0.3 110 2*X -0.3 111 3*X -0.3 (1) X istheunitdelayprogrammed by CHANGE_UNIT_DELAY <2:0> bits.
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−120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 6.5 13 19.5 26 32.5 Frequency (MHz) Amplitude (dBFS) SNR = 71.2dBFS SINAD = 71.1dBFS THD = 86.1dBc SFDR = 88.3dBc G001 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 6.5 13 19.5 26 32.5 Frequency (MHz) Amplitude (dBFS) SNR = 70.2dBFS SINAD = 69.6dBFS SFDR = 79.2dBc THD = 77.3dBc G002 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 6.5 13 19.5 26 32.5 Frequency (MHz) Amplitude (dBFS) Each Tone at −7dBFS Amplitude fIN1 = 50.1MHz fIN2 = 55.1MHz Two-Tone IMD = 77.5dBc G003 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 6.5 13 19.5 26 32.5 Frequency (MHz) Amplitude (dBFS) SNR = 71.2dBFS SINAD = 71.1dBFS THD = 86.1dBc SFDR = 88.3dBc G001 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
6 TYPICAL CHARACTERISTICS FOR AFE7222
6.1 RECEIVE PATH
AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,CMOS outputinterfaceforAFE7222, 32k pointFFT (unless otherwisenoted) AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure6-1.FFT Plot10MHz 65MSPS Figure6-2.FFT Plot70MHz 65MSPS AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure6-3.FFT Two-Tone Signal Figure6-4.Spectrum With DecimationFilterOFF Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR AFE7222 55 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
−120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 3.5 7 10.5 14 16.2 Frequency (MHz) Amplitude (dBFS) fIN = 10MHz SNR = 71.9dBFS SFDR = 92.8dBc G005 68.5 69.5 70.5 20 40 60 80 100 120 140 Frequency (MHz) SNR (dBFS) G006 20 40 60 80 100 120 140 Frequency (MHz) SFDR (dBc) G007 69.5 70.5 71.5 −40 −15 10 35 60 85 Temperature (°C) SNR (dBFS) AVDD18_ADC = 1.7V AVDD18_ADC = 1.8V AVDD18_ADC = 1.9V Input frequency = 10MHz G008 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,CMOS outputinterfaceforAFE7222, 32k pointFFT (unless otherwisenoted) AMPLITUDE SNR vs vs FREQUENCY INPUT FREQUENCY Figure6-5.Spectrum With DecimationFilterON Figure6-6.SNR vs InputFrequency SFDR SNR vs vs INPUT FREQUENCY TEMPERATURE Figure6-7.SFDR vs InputFrequency Figure6-8.SNR Across Temperature and ADC Analog Supply
56 TYPICAL CHARACTERISTICS FOR AFE7222 Copyright© 2011–2012,Texas InstrumentsIncorporated
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69.5 70.5 71.5 Supply Voltage (V) SNR (dBFS) SFDR (dBc) SNR SFDR Input Frequency = 10MHz G010 −40 −15 10 35 60 85 Temperature (°C) SFDR (dBc) AVDD18_ADC = 1.7V AVDD18_ADC = 1.8V AVDD18_ADC = 1.9V Input frequency = 10MHz G009 70.5 71.5 Common-Mode Input Voltage (V) SNR (dBFS) SFDR (dBc) SNR SFDR Input Frequency = 10MHz G011 70.5 71.5 72.5 73.5 100 Analog Input Amplitude (dB) SNR (dBFS) SFDR (dBc, dBFS) SNR SFDR(dBc) SFDR (dBFS) Input Frequency = 10MHz G012 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,CMOS outputinterfaceforAFE7222, 32k pointFFT (unless otherwisenoted) SFDR SNR and SFDR vs vs TEMPERATURE DVDD Supply Voltage Figure6-9.SFDR vs Temperature Figure6-10.Performance Across DVDD Supply Voltage SNR and SFDR SNR and SFDR vs vs COMMON-MODE INPUT VOLTAGE ANALOG INPUT AMPLITUDE Figure6-11.Performance Across Common-Mode Figure6-12.Performance Across InputAmplitude InputVoltage Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR AFE7222 57 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
68.5 69.5 70.5 71.5 Input Clock Amplitude, Differential (Vpp) SNR (dBFS) SFDR (dBc) SNR SFDR Input Frequency = 10MHz G013 25 30 35 40 45 50 55 60 65 70 75 69.5 70.5 71.5 72.5 Input Clock Duty Cycle (%) SNR (dBFS) THD (dBC) SNR THD Input Frequency = 10MHz G014 35 40 45 50 55 60 65 70 75 Input Clock Duty Cycle (%) SNR (dBFS) SNR DCC OFF SNR DCC ON Input Frequency = 10MHz G054 −0.3 −0.2 −0.1 0.1 0.2 0.3 250 750 1250 1750 2250 2750 3250 3750 Output Code (LSB) DNL (LSB) G015 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,CMOS outputinterfaceforAFE7222, 32k pointFFT (unless otherwisenoted) SNR and SFDR SNR and THD vs vs INPUT CLOCK AMPLITUDE INPUT CLOCK DUTY CYCLE Figure6-13.Performance Across InputClock Figure6-14.Performance Across InputClock Duty Amplitude Cycle SNR DNL vs vs InputClock Duty Cycle OUTPUT CODE Figure6-15.SNR vs InputClock Duty Cycle Figure6-16.DNL Plot
58 TYPICAL CHARACTERISTICS FOR AFE7222 Copyright© 2011–2012,Texas InstrumentsIncorporated
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−0.3 −0.2 −0.1 0.1 0.2 0.3 250 750 1250 1750 2250 2750 3250 3750 Output Code (LSB) INL (LSB) G016 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 5 15 25 35 45 55 Frequency (MHz) Amplitude (dBm) DAC Output Frequency = 10MHz SFDR = 75dBc G017 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 15 40 65 90 115 140 165 180 Frequency (MHz) Amplitude (dBm) DAC Output Frequency = 50MHz SFDR = 69dBc G018 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,CMOS outputinterfaceforAFE7222, 32k pointFFT (unless otherwisenoted) INL vs OUTPUT CODE Figure6-17.INL Plot
6.2 TRANSMIT PATH
AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,0 dBFS digitalinput,0 dB gain,CMOS inputinterfaceforAFE7222, 32k pointFFT (unlessotherwisenoted) AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure6-18.Spectrum AnalyzerPlotCMOS Mode Figure6-19.Spectrum AnalyzerPlotCMOS Mode 10MHz IF 50MHz IF Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR AFE7222 59 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
−155 −150 −145 −140 −135 −130 10 20 30 40 50 DAC Output Frequency (MHz) Noise Spectral Density (dBc/Hz) DAC Input Amplitude = −12dBFs DAC Input Amplitude = −6dBFs DAC Input Amplitude = 0dBFs G019 −155 −150 −145 −140 −135 −130 −125 −120 10 20 30 40 50 DAC Output Frequency (MHz) Noise Spectral Density (dBc/Hz) DAC Full-Scale = 2mA DAC Full-Scale = 10mA DAC Full-Scale = 20mA G020 10 20 30 40 50 60 DAC Output Frequency (MHz) SFDR (dBc) DAC Input = 0dBFS DAC Input = −6dBFS DAC Input = −12dBFS G021 10 20 30 40 50 DAC Output Frquency (MHz) SFDR (dBc) Interpolation = 1 Interpolation = 2 G022 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,0 dBFS digitalinput,0 dB gain,CMOS inputinterfaceforAFE7222, 32k pointFFT (unlessotherwisenoted) NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY vs vs DAC OUTPUT FREQUENCY DAC OUTPUT FREQUENCY Figure6-20.NSD vs Frequency Across InputScale Figure6-21.NSD Vs Iouts SFDR SFDR vs vs DAC OUTPUT FREQUENCY DAC OUTPUT FREQUENCY Figure6-22.SFDR vs Frequency Figure6-23.SFDR vs Interpolation
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DAC Output Frequency (MHz) SFDR (dBc) DAC Output Range = 2mA DAC Output Range = 10mA DAC Output Range = 20mA G023 10 20 30 40 50 DAC Output Frequency (MHz) HD2, HD3 (dB) HD2 HD3 DAC Interpolation by 2 G024 −90 −88 −86 −84 −82 −80 10 20 30 40 50 60 70 DAC Output Frequency (MHz) IMD3 (dBc) G025 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,0 dBFS digitalinput,0 dB gain,CMOS inputinterfaceforAFE7222, 32k pointFFT (unlessotherwisenoted) SFDR HD2, HD3 vs vs DAC OUTPUT FREQUENCY DAC OUTPUT FREQUENCY Figure6-24.SFDR Vs IOUTFS Figure6-25.HD2, HD3 Across Frequency IMD3 vs DAC OUTPUT FREQUENCY Figure6-26.IMD3 vs Frequency CMOS Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR AFE7222 61 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
−120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 12.5 25 37.5 50 62.5 Frequency (MHz) Amplitude (dBFS) SNR = 70.8dBFS SINAD = 70.7dBFS SFDR = 87.9dBc THD = 85.2dBc G026 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 12.5 25 37.5 50 62.5 Frequency (MHz) Amplitude (dBFS) SNR = 70.0dBFS SINAD = 69.5dBFS SFDR = 80.1dBc THD = 77.8dBc G027 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 12.5 25 37.5 50 62.5 Frequency (MHz) Amplitude (dBFS) Each Tone at −7dBFS Amplitude fIN1 = 50.1MHz fIN2 = 55.1MHz Two-Tone IMD = 83.7dBc G028 −120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 12.5 25 37.5 50 62.5 Frequency (MHz) Amplitude (dBFS) SNR = 70.8dBFS SINAD = 70.7dBFS SFDR = 87.9dBc THD = 85.2dBc G026 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com
7 TYPICAL CHARACTERISTICS FOR AFE7225
7.1 RECEIVE PATH
AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,LVDS outputinterfaceforAFE7225, 32k pointFFT (unlessotherwise noted) AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure7-1.FFT Plot10MHz 125MSPS Figure7-2.FFT Plot70MHz 125MSPS AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure7-3.FFT Two-Tone Signal Figure7-4.Spectrum With DecimationFilterOFF
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−120 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10.5 21 31.5 Frequency (MHz) Amplitude (dBFS) fIN = 10MHz SNR = 71.8dBFS SINAD = 71.8dBFS SFDR = 85.6dBc THD = 85.25dBc G030 50 100 150 200 Frequency (MHz) SNR (dBFS) G031 50 100 150 200 Frequency (MHz) SFDR (dBc) G032 Digital Gain (dB) SINAD (dBFS) fIN = 70MHz fIN = 140MHz G033 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,LVDS outputinterfaceforAFE7225, 32k pointFFT (unlessotherwise noted) AMPLITUDE SNR vs vs FREQUENCY INPUT FREQUENCY Figure7-5.Spectrum With DecimationFilterON Figure7-6.SNR vs InputFrequency SFDR SINAD vs vs INPUT FREQUENCY GAIN Figure7-7.SFDR vs InputFrequency Figure7-8.SINAD Across Gain Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR AFE7225 63 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
Digital Gain (dB) SFDR (dBc) fIN = 70MHz fIN = 140MHz G034 70.5 71.5 −40 −15 10 35 60 85 Temperature (°C) SNR (dBFS) AVDD18_ADC = 1.7V AVDD18_ADC = 1.8V AVDD18_ADC = 1.9V Input Frequency = 10MHz G035 Supply Voltage (V) SNR (dBFS) SFDR (dBc) SNR SFDR Input Frequency = 10MHz G037 −40 −15 10 35 60 85 Temperature (°C) SFDR (dBc) AVDD18_ADC = 1.7 V AVDD18_ADC = 1.8 V AVDD18_ADC = 1.9 V Input Frequency = 10MHz G036 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,LVDS outputinterfaceforAFE7225, 32k pointFFT (unlessotherwise noted) SFDR SNR vs vs GAIN TEMPERATURE Figure7-9.SFDR vs Gain Figure7-10.SNR Across Temperature and ADC Analog Supply SFDR SNR and SFDR vs vs TEMPERATURE DVDD SUPPLY VOLTAGE Figure7-11.SFDR Across Temperature and ADC Figure7-12.Performance Across DVDD Supply Analog Supply Voltage
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Common-Mode Input Voltage (V) SNR (dBFS) SFDR (dBc) SNR SFDR Input Frequency = 10MHz G038 69.5 70.5 71.5 72.5 100 Analog Input Amplitude (dBFS) SNR (dBFS) SFDR (dBc, dBFS) SNR SFDR (dBc) SFDR (dBFS) Input Frequency = 10MHz G040 25 30 35 40 45 50 55 60 65 70 75 Input Clock Duty Cycle (%) SNR (dBFS) THD (dBc) SNR THD Input Frequency = 10MHz G039 −0.3 −0.2 −0.1 0.1 0.2 0.3 255 755 1255 1755 2255 2755 3255 3755 Output Code (LSB) DNL (LSB) G041 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,LVDS outputinterfaceforAFE7225, 32k pointFFT (unlessotherwise noted) SNR and SFDR SNR and SFDR vs vs COMMON-MODE INPUT VOLTAGE INPUT CLOCK AMPLITUDE Figure7-13.Performance Across Common-Mode Figure7-14.Performance Across InputClock InputVoltage Amplitude SNR and SFDR DNL vs vs INPUT CLOCK DUTY CYCLE OUTPUT CODE Figure7-15.Performance Across InputClock Duty Figure7-16.DNL Plot Cycle Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR AFE7225 65 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
−0.3 −0.2 −0.1 0.1 0.2 0.3 350 850 1350 1850 2350 2850 3350 3750 Output Code (LSB) INL (LSB) G042 −110 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 Frequency (MHz) Amplitude (dBm) DAC Output Frequency = 10MHz SFDR = 74.5dBc G043 −100 −90 −80 −70 −60 −50 −40 −30 −20 −10 50 100 150 200 Frequency (MHz) Amplitude (dBm) DAC Output Frequency = 50MHz SFDR = 69.2dBc G044 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,–1 dBFS differentialanaloginput,0 dB gain,LVDS outputinterfaceforAFE7225, 32k pointFFT (unlessotherwise noted) INL vs OUTPUT CODE Figure7-17.INL Plot
7.2 TRANSMIT PATH
AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,0 dBFS digitalinput,0 dB gain,LVDS inputinterfaceforAFE7225, 32k pointFFT (unlessotherwisenoted) AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY Figure7-18.Spectrum AnalyzerPlotLVDS Mode Figure7-19.Spectrum AnalyzerPlotLVDS Mode 10MHz IF 50MHz IF
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−155 −150 −145 −140 −135 −130 −125 10 20 30 40 50 DAC Output Frequency (MHz) Noise Spectral Density (dBc/Hz) Input Amplitude = −12dBFs Input Amplitude = −6dBFs Input Amplitude = 0dBFs G045 −155 −150 −145 −140 −135 −130 −125 10 20 30 40 50 DAC Output Frequency (MHz) Noise Spectral Density (dBc/Hz) DAC Output Range = 2mA DAC Output Range = 10mA DAC Output Range = 20mA G046 10 20 30 40 50 60 DAC Output Frequency (MHz) SFDR (dBc) DAC Input Amplitude = −12dBFS DAC Input Amplitude = −6dBFS DAC Input Amplitude = 0dBFS G047 10 20 30 40 50 DAC Output Frquency (MHz) SFDR (dBc) Interpolation = 1 Interpolation = 2 G048 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,0 dBFS digitalinput,0 dB gain,LVDS inputinterfaceforAFE7225, 32k pointFFT (unlessotherwisenoted) NOISE SPECTRAL DENSITY NOISE SPECTRAL DENSITY vs vs DAC OUTPUT FREQUENCY DAC OUTPUT FREQUENCY Figure7-20.NSD vs Frequency Across InputScale Figure7-21.NSD Vs Iouts SFDR SFDR vs vs DAC OUTPUT FREQUENCY DAC OUTPUT FREQUENCY Figure7-22.SFDR vs Frequency Figure7-23.SFDR vs Interpolation Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR AFE7225 67 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
DAC Output Frequency (MHz) SFDR (dBc) DAC Output Range = 2mA DAC Output Range = 10mA DAC Output Range = 20mA G049 10 20 30 40 50 DAC Output Frequency (MHz) HD2, HD3 (dBc) HD2 HD3 G050 −100 −95 −90 −85 −80 −75 −70 20 40 60 80 100 Output Tone Frequency (MHz) IMD3 (dBc) Spacing Between Two Tones = 1MHz Each Tone Amplitude = −7dBFS G051 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com AVDD3_AUX=3.0V, maximum ratedclockfrequency,sinewave inputclock.1.5VPP differentialclockamplitude,50% clock dutycycle,0 dBFS digitalinput,0 dB gain,LVDS inputinterfaceforAFE7225, 32k pointFFT (unlessotherwisenoted) SFDR HD2, HD3 vs vs DAC OUTPUT FREQUENCY DAC OUTPUT FREQUENCY Figure7-24.SFDR Vs IOUTFS Figure7-25.HD2, HD3 Across Frequency IMD3 vs DAC OUTPUT FREQUENCY Figure7-26.IMD3 vs Frequency
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0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 10 30 50 70 90 110 130 Sampling Frequency (MSPS) Total Power (mW) Full Duplex Half Duplex RX On Half Duplex TX On Power Down I Channel Power Down Q Channel G052 100 150 200 250 300 350 400 450 500 550 600 650 10 40 70 100 130 160 190 220 250 Sampling Frequency (MSPS) Total Power (mW) Full Duplex Half Duplex RX On Half Duplex TX On Power Down I Channel Power Down Q Channel G053 AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
8 TYPICAL CHARACTERISTICS FOR COMMON PLOTS
SAMPLING FREQUENCY SAMPLING FREQUENCY Figure8-1.Power vs fclkCMOS Figure8-2.Power vs fclk2-WireLVDS Copyright© 2011–2012,Texas InstrumentsIncorporated TYPICAL CHARACTERISTICS FOR COMMON PLOTS 69 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
INP_A_ADC 12b RX ADC B 12b RX ADC AINN_A_ADC INP_B_ADC INN_B_ADC Coarse Mixer (CMIX) RX RMS / Peak Power Meter QMC Gain/ Phase SYNC SYNC SYNC /2 HBF Decimation QMC Offset SYNC RX Output A Fine Mixer (FMIX) NCO SYNC RX Output B AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com
9 APPLICATION INFORMATION
9.1 DEVICE DESCRIPTION
The AFE7225/7222 isdesignedto offersmallfootprint,high performance,low power and flexibilityin applicationsthatrequirehalforfullduplexsoftwaredefinedradios.The receivepathconsistsofdual12-bit 125MSPS ADCs, a digitalquadraturemodulationcorrectionblock,FCLK/4 digitalfrequencyshifterand /2 decimationfilter.The transmitpath consistsof dual 12-bit250MSPS DACs, a digitalquadrature modulationcorrectionblock,FCLK /4digitalfrequencyshifter,and x2/x4interpolationfiltersas wellas a FIFO. A peak/rmspower meter isavailabletothereceivepath.FineMixerswithNCOs are availablefor both receiveand transmitpath.These NCOs can be programmed independently.The primarydigital interfaceisselectableas eitherinterleavedparallelCMOS orserializedLVDS. Devicecontrolisprovided viaSPI (serialperipheralinterface). An auxiliary12-bit100kSPS ADC withtwo single-endedvoltageinputsviaa multiplexerisprovidedfor voltagemonitoring.A dualauxiliary12-bit2MSPS single-endedcurrentsourceoutputDAC isavailablefor controland/orboard calibration.Most blockscan be independentlypowered on/offas needed to save power.Allofthiscapabilityisavailableina small9mm x 9mm 64-pinQFN package.
9.2 RECEIVER SIGNAL CHAIN
Figure9-1.SignalChain
9.3 RECEIVE ADC
The dualreceiveADCs are createdusinga pipelinearchitectureand are powered from a 1.8V analog supply(AVDD18_ADC). The common-mode of the differentialinputsis0.95V.A VCM pin isprovided which outputsthe common-mode voltageforuse in settingup the properinputlevel.Ifthe VCM pin cannotbe used inyour application,ensure thatthe analoginputsare centeredat 0.95V.The fullscale rangeoftheinputsis2.0Vppdifferential,or0.95± 0.5Von bothINN and INP pins. The receiveADCs are capableof under-samplingintermediatefrequencies(IF)at highfrequency.The 3dB fullpower inputbandwidth(FPBW) isapproximately550MHz. Good distortionand noiseismaintained to~230MHz. The dualADCs can be used tocapturecomplex I/Qinputsfroma quadraturedemodulator, or two independentIFs or used in a diversityconfiguration.In orderto obey the Nyquist-Shannon samplingtheorem,ensurethatthebandwidthtobe sampled does notexceed FADCCLK/2. An external anti-aliasingfilterisrecommended thatconfinestheanaloginputenergytoa singleNyquistband (multiple ofFADCCLK/2) toavoidunwanted aliasingand reducedoverallperformance.
9.4 RECEIVE DECIMATION FILTER
The userhas theoptionofa decimationfilterinthereceivedatapath.The decimationfiltercan be used to reduce the ADC data sample rateby half.The extrasamplingbandwidthcouldbe used forprocessing gainand toease theroll-offrequirementsofan externalanti-aliasingfilter.The decimationfilterisa 43 tap half-bandfilter.The transitionband isfrom 0.38 to 0.62 of FADCCLK /4,and the stopband attenuationis greaterthan80dB. The pass-bandrippleislessthan0.1dB.Coefficients1 to22 arelisted.Coefficients23 to43 arethesame as thosefrom22 to1.
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-20 -40 -60 -80 -100 -120 -140 -160 -180 Normalized Frequency Frequency Response of Decimation Filter Frequency Response(dB) AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 RXFIR (decimationfilter) coefficients= [+9 0 –33 0 +88 0 –196 0 +387 0 –704 0 +1210 0 –2024 0 +3432 0 –6485 0 +20700 +32768] The frequencyresponseofthefilterisshown below. Figure9-2.DecimationFilterFrequency Response (from0 toFADCCLK /2)
9.5 RECEIVE FINE FREQUENCY MIXER (FMIX)
The finemixeruses a NumericallyControlledOscillator(NCO) togeneratetwo complementaryoutputsof a finelyprogrammable frequency,which isthen mixed withthe A and B inputsto generatecomplex outputs. The mixercomputes two outputsas follows: OutputI= {Acos(ωmixt)– B sin(ωmixt)}and OutputQ = {Asin(ωmixt)+ Bcos(ωmixt)} where ωmix istheprogrammed finefrequency. The NCO has a 32 bitfrequencyregister,and a 20 bitphase register.The 32 bitfrequencyregistercan be used tosetthemixingfrequencyovera rangeof±Fs/2instepsofFs/232.
9.6 RECEIVE COARSE FREQUENCY MIXER (CMIX)
The receivepathcontainsan optional±FADCCLK /4coarsedigitalfrequencymixer.An example ofitsuse is thecaptureofan IF centeredinthemiddleofa Nyquistband.The digitalmixercan move thecarrieror blockof carriersto baseband or near baseband.Ifthe totalbandwidthof the carrieror summation of carriersislessthan0.4× FADCCLK /4,thedecimationfiltercan alsobe employed. The CMIX blockdoes a complex mixingon theA and B channelsas shown below.The SYNC pincan be used toensurethatacrosschips,thephase ofmixingismaintained. Copyright© 2011–2012,Texas InstrumentsIncorporated APPLICATION INFORMATION 71 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
COARSE_PWR_OP_I (3:0) COARSE_PWR_OP_Q (3:0) PWR_METER_COARSE_SAMPLES(2:0) a*a + b*b a b Average Power in dB scale a*a + b*b a b Average Power in dB scale I Q Power Meter 1 Power Meter 2 Complex mode AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com MIXING MODE MIXING MIXING PATTERN (1) Iout= {+A, +A ,+A, +A }00 Normal (Low Pass,No Mixing) Qout = {+B, +B ,+B, +B } Iout= {+A, –A ,+A, –A }01 HighPass (Fs/2) Qout = {+B, –B ,+B, –B } Iout= {+A, –B ,–A,+B }10 +Fs/4 Qout = {+B, +A ,–B,–A } Iout= {+A, +B ,–A,–B }11 –Fs/4 Qout = {+B, –A ,–B,+A } (1) A and B aretheinputstotheCMIX block.Ioutand Qout aretheoutputs.
9.7 RMS POWER METER
The RX signalchainhas two power meters– thecoarsepower meterand finepower meter.
9.7.1 Coarse Power Meter
The finepower meter estimatesthetotalintegratedpower inlinearscalebased on a much largersetof samples.The resultingintegratedpower number isstoredina registerforreadout.The intervaltime(how oftento startintegration)and integrationtime(number of samples to integrate)isprogrammable.The power meter can be configuredin eitherrealmode (where the power of each channeliscalculated individually)orina complexmode {wherethepower of(I^2+Q^2)iscalculated}.Thisisillustratedbelow. Figure9-3.Coarse Power Meter
9.7.2 FinePower Meter
The finepower meter estimatesthetotalintegratedpower inlinearscalebased on a much largersetof samples.The resultingintegratedpower number isstoredina registerforreadout.The intervaltime(how oftento startintegration)and integrationtime(number of samples to integrate)isprogrammable.The power meter can be configuredin eitherrealmode (where the power of each channeliscalculated individually)orina complexmode {wherethepower of(I2+Q 2)iscalculated}.Thisisillustratedbelow.
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PWR_OP_I (57:0) PWR_OP_Q (57:0) INTGR_CNT(20:0)SYNC_CNT(8:0) INTRV_CNT(20:0) I Q Power Meter 1 Power Meter 2 Complex mode AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Figure9-4.FinePower Meter Power inthe finepower meter iscalculatedby squaringeach I (Iand Q forcomplex inputs)sample, summing, and then integratingthe summed-squared resultsinto a 58 bit accumulatorover a programmableintegrationperiod. The integrationperiodisprogrammed intothe21 bitcounter,in8 sample increments.The power storedin the58-bitregisteris: Power = [(I*I)x (Nx8 + 3)]forrealinputswhere N istheintegrationcount. Power = [(I*I+ Q*Q) x (Nx8 + 3)]forcomplexinputswhere N istheintegrationcount. The power meter operationcan be optionallysynced.Ifpower meter syncingisenabled,itwaitsfora programmable number ofcyclesaftera validsync,and thenstartscomputation.Ifsyncingisdisabled,it startscomputationas soon as thepower meter isenabled.Once thecomputationintervaliscompleted, the computed power iswrittento a set of serialinterfaceregisters,and the next computationinterval begins.The contentsoftheseregisterscan be readoutseriallythroughSDOUT. The processbeginswitha sync eventstartingthe9 bitdelaycounter.After(8xsync_delay+ 4)samples, theintegrationintervalisstarted.Integrationcontinuesuntiltheintegrationcountismet,atwhichpointthe 58 bitintegratorresultsare transferredtotheread onlyregister.A new measurement periodwillstartat theend oftheintervalperiod. A more detaileddiagram of the power meter isshown below (theI and Q are representedas 16-bit numbers). Copyright© 2011–2012,Texas InstrumentsIncorporated APPLICATION INFORMATION 73 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
(in 8 Sample Increments) Integration (in 8 Sample Increments) 21219 RMS Power I Q Interval (in 8 Sample Increments) INTRV_CNT(20:0) INTGR_CNT(20:0)SYNC_CNT(8:0) Interrupt QMC Offset Coarse Mixer (CMIX) 2x Interpolation TxFIR2 2x Interpolation TxFIR1 Inverse SINC QMC Gain/ Phase Fine Mixer 8 deep FIFO NCO SYNC SYNC SYNCSYNC SYNC TX A input (I channel) TX B input (Q channel) TX A output TX B output DAC_DCLKIN DAC_CLK %1,2,4DAC_CLK AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Figure9-5.Power Meter DetailedDiagram The power metertimingisshown below: Figure9-6.Power Meter Timing
9.8 TRANSMIT SIGNAL CHAIN
Figure9-7.TransmitSignalChain
9.9 TRANSMIT DAC
The transmitDAC isa current-steeringarchitecture,capableof clockratesup to 250MSPS and output currentsup to20mA. The DAC isstructuredas a currentsinkfrom theload.The DAC ispowered from AVDD3_DAC, a 3V analogsupply.Thisprovidesforan outputcompliancerangeofAVDD3_DAC ± 0.5V. To benefitfromthefull1V swingavailableon each DAC outputpin,a voltagedividerloadreferencedtoa highervoltagesupply,like5V, isrecommended. The current-steeringarchitecturewillsinkcurrentintothe + and – DAC outputs.The sum ofthecurrentwillalwaysbe equaltothefull-scalecurrent.The fullscale currentissetwitha resistor(RBIAS)togroundon theBIASJ pin,and willbe equalto
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IOUTP_A_DAC IOUTN_A_DAC External Termination I = 16 * (VREF/RBIAS), where VREF = 1.2 VOUTFS AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 IOUTFS = 16 × (VREF/RBIAS),where VREF = 1.2V. Figure9-8.CurrentSteeringArchitectureofDAC
9.10 FIFO
The 8-Deep FIFO is used to handoffthe data from the digitalclock(DAC_DCLKIN) domain to the DAC_CLK domain (orthedividedversionofDAC_CLK ifinterpolationisused).The FIFO has a readand writepointer,whichareinitializedto4 away fromeach otherwhen thechipiseitherresetorsynchronized. The writepointerincrementswithDAC_DCLKIN whereas thereadpointerincrementswithDAC_DCLKIN (orthedividedversion).Ideally,thereadand writepointersmaintainthedifferenceof4.However,ifthere isa driftintherelativephases ofthetwo clocks,theinstantaneousvaluesofthereadand writepointers can differfrom4.Ifthepointerscome towithin2 positionsofeach other,theFIFO can be settoidentify thatconditionas a possible"collision"conditionand can shutofftheDAC outputsby pullingittomid code. A stoppageoftheinputclockcan alsobe detectedby theFIFO.
9.11 TRANSMIT INTERPOLATION FILTERS
The AFE7225/7222 can enable 2x or 4x interpolationusingon-chiphalf-bandinterpolationfilters.The additionaloversamplingprovidedby interpolationcan be used toreducetheorderofthelow pass anti- aliasingfilterthatfollowsthetransmitDACs orso thatthedigitalcarriercan be blockshiftedby thecoarse mixertoa higheroutputIF. Whileinterpolatingby a factorof2,theDAC_DCLKIN rateshouldbe settohalfoftheinputclockrate. Whileinterpolatingby a factorof4,theDAC_DCLKIN rateshouldbe settoone fourthoftheinputclock rate. Each channelhas two filtersTxFIR1,and TxFIR2,ofwhichTxFIR1 aloneisenabledintheInterpolateby 2 mode, Both filtersare enabledinIntertpolateby 4 mode. The 2 filtersineach ofthetwo channelscan individuallybe configuredtooperateinthe‘low pass ‘or thehighpass mode. By default,allfiltersare configuredtoopearateinthelow pass mode. The followingtableliststheaddressand datamask values tobe programmed toconfigureeach ofthesefiltersinthehighpass mode. TXFIR1 isa 43 taphalf-bandfilter.The transitionband isfrom0.4to0.6ofFCLKFIR1 /2,and thestopband attenuationis70 dB. Pass band rippleislessthan0.1dB.Ithas thefollowingcoefficients(listedonlyup to themiddleone) TXFIR1 (interpolationfilter1) coefficients= [120 –33 0 73 0 –143 0 254 0 –426 0 685 0 –1090 0 1781 0 –3286 0 10365 16384 ] The frequencyresponseisshown below. Copyright© 2011–2012,Texas InstrumentsIncorporated APPLICATION INFORMATION 75 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
-20 -40 -60 -80 -100 -120 -140 -160 Normalized Frequency Frequency Response of Interpolation Filter 1 Frequency Response(dB) 0 0.2 0.4 0.6 0.8 1 Normalized Frequency -100 Individual and Composite Responses of Interpolation Filters 1.2 1.4 1.6 1.8 2 -50 -150 -200 Frequency Response(dB) AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Figure9-9.InterpolationFilter1 freqResponse (from0 toFDACCLK /2)(2X Interpolationmode) TXFIR2 isa 19 tap half-bandfilter.The transitionband isfrom 0.27 to 0.75 of FCLKFIR2 /2,and the stop band attenuationis70dB. Pass band rippleislessthan0.1dB.Ithas thefollowingcoefficients(listedonly up tothemiddleone). TXFIR2 (interpolationfilter2) coefficients= [110 –64 0 224 0 –648 0 2525 4096] Figure9-10.Interpolationfiltersindividualand composite responses – TXFIR1 response isshown in blue,TXFIR2 response isinred,and thecomposite response isingreen.(4X interpolationmode, from 0 toFDACCLK /2)
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9.12 TRANSMIT FINE FREQUENCY MIXER (FMIX)
The finemixeruses a NumericallyControlledOscillator(NCO) togeneratetwo complementaryoutputsof a finelyprogrammable frequency,which isthen mixed withthe A and B inputsto generatecomplex outputs. The mixercomputes two outputsas follows: OutputI= {Acos(ωmixt)– B sin(ωmixt)}and OutputQ = {Asin(ωmixt)+ Bcos(ωmixt)} where ωmix istheprogrammed finefrequency. The NCO has a 32 bitfrequencyregister,and a 20 bitphase register.The 32 bitfrequencyregistercan be used tosetthemixingfrequencyovera rangeof±Fs/2instepsofFs/232.
9.13 TRANSMIT COARSE FREQUENCY MIXER
The transmitpathcontainsan optional±FDACCLK /4coarsedigitalfrequencymixer.An example ofitsuse is theprocessingofan inputpatterntotheAFE7225/7222 atornearbaseband.The digitalmixercan move the carrieror blockof carriersto a higherIF afterinterpolation.Thisisusefulespeciallyinquadrature modulationas itcreatesmore separationbetween the wanted signaland itsimage,making iteasierto filtertheunwanted image atRF aftertheanalogquadraturemodulator. MIXING MODE MIXING MIXING PATTERN (1) Iout= {+A, +A ,+A, +A }00 Normal (Low Pass,No Mixing) Qout = {+B, +B ,+B, +B } Iout= {+A, –A ,+A, –A }01 HighPass (Fs/2) Qout = {+B, –B ,+B, –B } Iout= {+A, –B ,–A,+B }10 +Fs/4 Qout = {+B, +A ,–B,–A } Iout= {+A, +B ,–A,–B }11 –Fs/4 Qout = {+B, –A ,–B,+A } (1) A and B aretheinputstotheCMIX block.Ioutand Qout aretheoutputs.
9.14 TRANSMIT INVERSE SINC FILTER
The inverseSINC filteris9-tapand has a response thatisinverseof the naturalDAC droop versus frequency(due to sin(x)/xroll-offcaused by zero-orderhold of DAC sampling.Ituses the same coefficientsas inDAC5688. The inversesincfilterhas a gain> 1 atallfrequencies.Therefore,thesignal inputtotheinverseSINC must be reducedfromfullscaletopreventsaturationinthefilter.The amount of backoffrequireddepends on the signalfrequency,and isset such thatat the signalfrequenciesthe combinationoftheinputsignaland filterresponseislessthan1 (0dB).For example,ifthesignalinputto theinverseSINC filterisatFDACCLK /4,theresponseoftheinverseSINC is0.9dB, and thesignalmust be backed offfrom fullscaleby 0.9 dB. The gainfunctioninthe QMC blockcan be used to reduce the amplitudeoftheinputsignal.The coefficientsare same as thoseintheinverseSINC filterinDAC5688 (listedonlyup tothemiddleone). Coefficients= [1 –4 13 –50 592 ] Itsfrequencyresponseisshown below: Copyright© 2011–2012,Texas InstrumentsIncorporated APPLICATION INFORMATION 77 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
3.5 2.5 1.5 0.5 Normalized Frequency Frequency Response(dB) Frequency Response of Inverse SINC Filter x QMC_GAINA(10:0) A Data In /c83 QMC_GAINB(10:0) B Data In A Data Out B Data Out x x QMC_PHASE(9:0) AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Figure9-11.InverseSINC FilterFrequency Response (0toFdac/2)
9.15 QUADRATURE MODULATION CORRECTION (QMC) – SIMILAR FOR TRANSMIT AND
The QuadratureModulatorCorrection(QMC) blockprovidesa means forchangingthephase balanceof thecomplex signaltocompensate forIand Q imbalancepresentinan analogquadraturemodulator.The blockdiagramfortheQMC blockisshown below.The QMC blockcontains3 programmableparameters. RegistersQMC_GAINA(10:0) and QMC_GAINB(10:0) controltheIand Q pathgainsand are11 bitvalues witha rangeof0 to1.99.The gainadjustmentvalueisdeterminedby dividingtheregistervalueby 1024. A valueof1024 isthereforea gainof1,a valueof512 isa gainof0.5and a valueof2047 isa gainof 1.99.Note thatthe I and Q gain can alsobe controlledby settingthe DAC fullscaleoutputcurrent. RegisterQMC_PHASE(9:0) controlsthephase imbalancebetween Iand Q and isa 10-bitvaluewitha rangeof–0.125to+0.125thatismultipliedby theQ sample and added totheIsample. Figure9-12.QMC Block Diagram
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9.16 DIGITAL OFFSET CONTROL
RegistersQMC_OFFSETA(12:0) and QMC_OFFSETB(12:0) controltheA and B pathoffsetsand are13- bitvalueswitha rangeof-4096to4095.The offsetadjustmentvalueisgotby dividingtheregistervalue by 16,so therangeoftheoffsetadjustmentis±256 LSB. The DAC offsetvalueadds a digitaloffsettothe digitaldatabeforedigital-to-analogconversion.The dataand offsetvaluesareLSB aligned. Figure9-13.DigitalOffsetBlock Diagram
9.17 SYNCHRONIZING MULTIPLE CHIPS
The AFE722x has a SYNC pinthatcan be used tosynchronizemultiplechips.When such synchronization is not required,the SYNC pin can be tiedto ground (orin the case of differentialSYNC input,tie SYNCINP tologiclowand SYNCINN tologichigh). On thetransmitside,severalblocksneed tobe synchronized.These includetheclockdivider,FIFO read and writepointersm,coarsemixermixingphase,NCO phase,power meter,QMC gain/phase correction block.Note however thatalltheseblockscan functioneven withoutsynchronization. The simplestway tosynchronizeallblocksisusingtheglobalsynchronizingmode, which isenabledby default.The synchronizationsource,by default,isthe SYNC pin.A risingedge on the SYNC pinwill cause allblockstobe synced inan orderthatisinternallycontrolled.The synchronizationsourcecan also be setto a serialinterfacebit(TX_GLOBAL_SYNC_SRC and RX_GLOBAL_SYNC_SRC). When using theserialinterfacebit,a 0-1transitionon theregisterbittriggerssyncing. In most cases,globalsynchronizingmode is sufficient.However, each blockcan be independently synchronized by disablingthe global synchronizationmodes (TX_GLOBAL_SYNC_DIS and RX_GLOBAL_SYNC_DIS) and enablingthe block-specificsynchronizationregistercontrols.The block- specificsynchronizationcan alsobe done eitherusingtheSYNC pinor using0-1 transitionson specific registerbits. For some blocks,thereisan optiontospecifywhetheror notsyncingisneede.An example istheQMC offsetregistercontrol.When syncingisspecifiedas notneeded,thevaluesintheQMC offsetregisterare appliedas soon as theyarewritteninto.However when syncingisspecifiedas needed,thevalueswritten intothisregisterareappliedtotheblockonlywhen a validSYNC pulseisapplied. When applyingblockspecificsyncing,itisrecommended thatthefollowingorderbe followed: 1. Synchronizetheclockdividerfirst 2. SynchronizetheFIFO next 3. Synchronizeallotherotherblocksnextinno specificorder The effecton synchronizingon variousblocksislistedbelow:
- FIFO – thewritepointerisresettozeroand thereadpointerisresetto4.
- QMC offsetcorrection– The QMC offsetcorrectionvaluesprogrammed intothe serialinterface registersareloadedintotheblock
- QMC Gain/ Phase correctionblock – The gainand phase correctionvaluesprogrammed intothe serialinterfaceregistersareloadedintotheblock Copyright© 2011–2012,Texas InstrumentsIncorporated APPLICATION INFORMATION 79 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
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- Fine mixer – The NCO frequencyand phase registervaluesprogrammed intothe serialinterface registersare loadedintotheblock.AlsotheNCO phase accumulatorisinitializedtotheprogrammed phase offset.
- Coarse mixer – The phase programmed forthemixingisappliedon SYNC.
- Power meter – Aftera SYNC event,power computationbeginsaftera programmable number of cycles.
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10 DIGITAL INTERFACE
The digitalinterfaceis capable of operatingin two distinctmodes – interleavedparallelCMOS and serializedLVDS. The supportedmaximum speed of operationvariesdepending upon mode in which digitalinterfaceis operating.AFE722x has constraintson maximum frequenciesof ADC_CLK and DAC_CLK. Using theseconstraints,a comprehensivetableshowing maximum frequenciesof different clocksindifferentinterfacesislistedinTable10-1. The followingtableshows the maximum frequencyof operationof variousclocksof AFE7225 inLVDS interfacemode (set registerbit REG_LVDS_TX= ’1’ to put DAC in LVDS interfacemode, and MASTER_OVERRIDE_RX= ’1’and REG_LVDS_RX= ’1’toputADC inLVDS interfacemode.) Table10-1.Maximum InterfaceRates inLVDS Mode RX PATH Max ADCSDR or DecimationFactorWireMode Sampling Max ADC Frame Clock Max ADC BitClock Max SerialOutputDataDDR (registerbits(registerbit Clock (ADC_FCLKOUTP/N) (ADC_DCLKOUTP/N) Rate (ADCx_DATA_nP/N)(registerbit RX_DEC_FIL_EN,TWOWIRE_RX) (ADC_CLK (1)) MHz MHz Mbps, perwireSDR_RX) RX_DEC_FIL_EN_SRC) MHz 1 65 390 780 1-wire DDR 65 2 32.5 195 390 1 125 375 750 2-wire DDR 125 2 62.5 187.5 375 1 65 390 390 2-wire SDR 65 2 32.5 195 195 TX PATH SDR or InterpolationBy Max DACWireMode Max DAC Frame Clock Max DAC BitClock Max SerialInputData RateDDR (registerbits OutputClock(registerbit (DAC_FCLKINP/N) (DAC_DCLKINP/N) (ADCx_DATA_nP/N)(registerbit TX_INT_MODE(1:0), (DAC_CLK (1))TWOWIRE_TX) MHz MHz Mbps, perwireSDR_TX) TX_INT_MODE_SRC) MHz 1 65 65 390 780 1-wire DDR 2 130 65 390 780 4 250 62.5 375 750 1 65 65 390 390 2-wire SDR 2 130 65 390 390 4 250 62.5 375 375 1 130 130 390 780 2-wire DDR 2 250 125 375 780 4 250 62.5 187.5 375 (1) ADC_CLK and DAC_CLK arederivedfromclockson CLKINP and CLKINN (differentialclock,a single-endedclockortwo independent single-endedclocks).See Clockingsectionfordetails.ForFull-Duplexoperationrequiringtwo single-endedclocks,see sectionFull DuplexOperation– CouplingConsiderations. Copyright© 2011–2012,Texas InstrumentsIncorporated DIGITAL INTERFACE 81 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
ADC_DCLKOUT ADCDA T A <11:0> A B A B A BB ADC_DCLKOUT ADCDA T A <11:0> A B A th tsu th tsu tCLK AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Table10-2shows themaximum frequencyofoperationofvariousclocksofAFE7225 inCMOS interface mode (bydefaultafterreset,AFE722x operatesinCMOS interfacemode forbothRX and TX path). Table10-2.Maximum InterfaceRates inCMOS Mode RX PATH DecimationFactorLow Power CMOS Mode Max ADC SamplingClock(registerbits Max ADC_DCLKOUT Max ParallelOutputData Rate(registerbit (ADC_CLK (1))RX_DEC_FIL_EN, MHz Mbps, perpinMODE_LP_CMOS) MHzRX_DEC_FIL_EN_SRC) 1 105 210 Disabled(default) 105 2 52.5 105 1 40 80 Enabled 40 2 20 40 TX PATH InterpolationFactor Max DAC OutputClock(registerbits Max DAC_DCLKIN Max ParallelInputData Rate(DAC_CLK (1))TX_INT_MODE(1:0), MHz Mbps, perpinMHzTX_INT_MODE_SRC) 1 130 260 2 130 65 130 4 32.5 65 (1) ADC_CLK and DAC_CLK arederivedfromclockson CLKINP and CLKINN (differentialclock,a single-endedclockortwo independent single-endedclocks).See Clockingsectionfordetails.ForFull-Duplexoperationrequiringtwo single-endedclocks,see sectionFull DuplexOperation– CouplingConsiderations.
10.1 PARALLEL CMOS ADC RX DATA
The 12-bitADC-A and ADC-B data is interleaved(A then B) into one 12-bitword on pins ADCDATA0:ADCDATA11 at twicethe rateof each patternwitha DDR clock(datatransitionson rising and fallingedges).Thiscan be quadraturedata or two independentreceivechannels.Note thatinthe defaultRX CMOS mode, theedges oftheADC_DCLKOUT arealignedinthemiddleofthedatawindow. Figure10-1.RX CMOS InterleavedOutput
10.2 TIMING INFORMATION FOR PARALLEL CMOS ADC RX DATA
tCLK = Time periodofADC outputdataclock(same as timeperiodofADC samplingclockwhen decimationissetto 1). Figure10-2.RX CMOS Output Timing
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DAC_DCLKIN DACDA T A <11:0> A B A B A BB DAC_DCLKIN DACDA T A <11:0> A B A th tsu th tsu tCLK AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
10.3 PARALLEL CMOS DAC TX DATA
The 12-bitDAC-A and DAC-B data is interleaved(A then B) into one 12-bitword on pins DACDATA0:DACDATA11 at twicethe rateof each patternwitha DDR clock(datatransitionson rising and fallingedges).Thiscan be quadraturedataortwo independenttransmitchannels. Figure10-3.TX CMOS InterleavedInput
10.4 TIMING INFORMATION FOR PARALLEL CMOS DAC TX DATA
tCLK = Time periodofDAC inputdataclock(same as timeperiodofDAC outputclockwhen interpolationissetto1). Figure10-4.TX CMOS InputTiming
10.5 LOW POWER RX CMOS MODE
The defaultRX CMOS mode uses an internalPLL topositiontheclockedges inthemiddleofthedata window.Whileoperatingatspeeds lowerthan40 MSPS, a low power CMOS mode can be enabled(set bitMODE_LP_CMOS to1).Inthismode, thePLL isbypassed and theclockedges aresetrelativetothe data transitionsthroughdelayelements.Bypassingthe PLL saves about 20 mW of power. However, because thedelayelementsoperateinopen loop,thereisno tightcontrolon theprecisedelayand there can be a chiptochipvariation.At low speeds,therewillbe sufficientsetup and holdtimeinspiteofthe variationsintheclockedge relativetothedata.An advantageofthelow power RX CMOS mode isthat therecoveryoftheRX frompowerdown ismuch fasterbecause oftheabsence ofthePLL. For example, withthelow power RX CMOS mode enabled,theRX recoversfroma stateofOFF clocktoa stateofON clockin5 us (as compared to 20 us when indefaultRX CMOS mode). Anotheradvantageof thislow power RX CMOS mode isthattheminimum frequencyofoperationisextendeddown to2.5MSPS (from 10 MSPS).
10.6 SERIAL LVDS DAC TX INTERFACE
12-bitDAC inputdataisserializedontoone or two LVDS pairsper DAC. DACA and DACB datainputs can be quadraturedataortwo independentreceivechannels.Two serializationmodes areavailable.
- 1-Wiremode: 1 LVDS pairforthedatatoeach DAC. Itwilloperateina DDR fashionserializedtoa frequencyof 6x the patternword rate.A frame clock(DAC_FCLKINP/N) at the word rateand a bit clock(DAC_DCLKINP/N) at 6x.Example: 50MSPS 12-bitpatternwillserializeto 300MHz on each LVDS pair,frameclockof50MHz and bitclockof300MHz. Effectiveserialdatarateis600Mbps due to bittransitionson risingand fallingedge ofbitclock.Recommended maximum word rateis~65MSPS in thismode. Copyright© 2011–2012,Texas InstrumentsIncorporated DIGITAL INTERFACE 83 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
DAC_DCLK DACDATA Ch A Ch B th tsu th tsu tCLK/6 DAC_DCLK DAC_DATA Ch A Ch B th tsu th tsu t /3CLK AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com A. tCLK = Time periodofDAC inputdataclock(same as timeperiodofDAC outputclockwhen interpolationissetto1). B. th isminimum holdtimerequiredattheAFE722x input. C. tsu isminimum setuptimerequiredattheAFE722x input. Figure10-5.TX 1-WireMode Timing Diagram
- 2-Wiremode, DDR clock:2 LVDS pairsforthedatatoeach DAC. Itwilloperateina DDR fashion serializedtoa frequencyof3x thepatternword rate.A frameclock(DAC_FCLKINP/N) athalftheword rateand a bitclock(DAC_DCLKINP/N) at 3x. Example: 50MSPS 12-bitpatternwillserializeto 150MHz on each LVDS pair,frameclockof25MHz and bitclockof150MHz. Effectiveserialdatarate is 300Mbps on each LVDS pairdue to bittransitionson risingand fallingedge of bitclock. Recommended maximum word rateis~125MSPS inthismode. A. tCLK = Time periodofDAC inputdataclock(same as timeperiodofDAC outputclockwhen interpolationissetto1). B. th isminimum holdtimerequiredattheAFE722x input. C. tsu isminimum setuptimerequiredattheAFE722x input. Figure10-6.TX 2-WireMode, DDR Clock Timing Diagram
- 2-Wiremode, SDR clock:2 LVDS pairsforthedatatoeach DAC. Itwilloperateina SDR fashion serializedtoa frequencyof6x thepatternword rate.A frameclock(DAC_FCLKINP/N) attheword rate and a bitclock(DAC_DCLKINP/N) at6x.Example:50MSPS 12-bitpatternwillserializeto300MHz on each LVDS pair,frameclockof50MHz and bitclockof300MHz. Effectiveserialdatarateis300Mbps on each LVDS pairdue to bittransitionson risingedge of bitclock.Recommended maximum word rateis~65MSPS inthismode.
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DAC Frame Clock, DAC_FCLK Freq = 1X Fs Input Clock, CLK Freq = Fs SAMPLE N SAMPLE N+1 (D11) Data bit in LSB First mode Data bit in MSB First mode (D11) (D10) (D9) (D8) (D7) (D6) (D5) (D4) (D3) (D2) D10 (D1) D11 (D0) (D11) (D10) DAC Bit Clock, DAC_DCLK Freq = 6X Fs Input Data, DACB_DATA 0 DACA_DATA 0 Data rate = 12X Fs 12 bit serialization Input Data (LSB byte) DACA_DATA _1 DACB_DATA _0 DAC Frame Clock, DAC_FCLK Freq = 1X Fs (D5) (D4) (D3) (D2) (D1) (D0) Input Data (MSB byte) DACA_DATA _0 DACB_DATA _1 (D11) (D10) (D9) (D8) D10 (D7) D11 (D6) DAC Bit Clock – SDR DAC_DCLK Freq = 6X Fs DAC Bit Clock – DDR (def) DAC_DCLK Freq = 3X Fs (D11) (D9) (D7) (D5) (D3) D11 (D1) (D10) (D8) (D6) (D4) (D2) D10 (D0) in BYTE-WISE MODE (DEFAULT) in BIT-WISE MODE Input Clock, CLK Freq = Fs Data bit in LSB First mode Data bit in MSB First mode (D5) Input Data (Even bits) DACA_DATA _1 DACB_DATA _0 Input Data (Odd bits) DACA_DATA _0 DACB_DATA _1 (D5) (D4) (D3) (D2) (D1) (D0) (D11) (D10) (D9) (D8) D10 (D7) D11 (D6) (D11) (D9) (D7) (D5) (D3) D11 (D1) (D10) (D8) (D6) (D4) (D2) D10 (D0) Input Data (Sample N) DACA_DATA _1 DACB_DATA _0 Input Data (Sample N+1) DACA_DATA _0 DACB_DATA _1 in WORD-WISE MODE White cells – Sample N Grey cells – Sample N+1 Data rate = 6X Fs (D5) (D4) (D3) (D2) D10 (D1) D11 (D0) (D11) (D10) (D9) (D8) (D7) (D6) (D5) (D4) (D3) (D2) D10 (D1) D11 (D0) (D11) (D10) (D9) (D8) (D7) (D6) AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
10.6.1 LVDS TX Interface
Figure10-7.1-WIRE MODE Figure10-8.2-WIRE MODE Copyright© 2011–2012,Texas InstrumentsIncorporated DIGITAL INTERFACE 85 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
ADC_DCLK ADC_DATA Ch A Ch B th tsu th tsu t /6CLK ADC_DCLK ADC_DATA Ch A Ch B th tsu th tsu t /3CLK AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com
10.7 SERIAL LVDS ADC RX INTERFACE
Note:Set MASTER_OVERRIDE_RX bitto‘1’beforeenteringRX LVDS interface. The 12-bitADC outputdataisserializedontoone or two LVDS pairsper ADC. ADCA and ADCB data outputscan be quadraturedata or two independentreceivechannels.Two serializationmodes are available.
- 1-Wiremode: 1 LVDS pairforthedatafromeach ADC. Itwilloperateina DDR fashionserializedtoa frequencyof6x thepatternword rate.A frameclock(ADC_FCLKOUT) attheword rateand a bitclock (ADC_DCLKOUT) at6x.Example:50MSPS 12-bitpatternwillserializeto300MHz on each LVDS pair, frame clockof 50MHz and bitclockof 300MHz. Effectiveserialdata rateis600Mbps due to bit transitionson risingand fallingedge ofbitclock. A. tCLK = Time periodofADC outputframeclock. B. th isminimum holdtimerequiredattheAFE722x output. C. tsu isminimum setuptimerequiredattheAFE722x output. Figure10-9.RX 1-WireMode Timing Diagram
- 2-Wiremode, DDR clock:2 LVDS pairsforthedatafromeach ADC. Itwilloperateina DDR fashion serializedtoa frequencyof3x thepatternword rate.A frameclock(ADC_FCLKOUT) athalftheword rateand a bitclock(ADC_DCLKOUT) at3x.Example:50MSPS 12-bitpatternwillserializeto150MHz on each LVDS pair,frame clockof 25MHz and bitclockof 150MHz. Effectiveserialdata rateis 300Mbps on each LVDS pairdue tobittransitionson risingand fallingedge ofbitclock. A. tCLK = Time periodofADC outputframeclock. B. th isminimum holdtimerequiredattheAFE722x output. C. tsu isminimum setuptimerequiredattheAFE722x output. Figure10-10.RX 2-WireMode, DDR Clock Timing Diagram
- 2-Wiremode, SDR clock:2 LVDS pairsforthedatafromeach ADC. Itwilloperateina SDR fashion serializedtoa frequencyof6x thepatternword rate.A frameclock(ADC_FCLKOUT) attheword rate and a bitclock(ADC_DCLKOUT) at6x.Example:50MSPS 12-bitpatternwillserializeto300MHz on each LVDS pair,frameclockof50MHz and bitclockof300MHz. Effectiveserialdatarateis300Mbps on each LVDS pairdue tobittransitionson risingedge ofbitclock.
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ADC Frame Clock, ADC_FCLK Freq = 1X Fs Input Clock, CLK Freq = Fs SAMPLE N SAMPLE N+1 (D11) Data bit in LSB First mode Data bit in MSB First mode (D11) (D10) (D9) (D8) (D7) (D6) (D5) (D4) (D3) (D2) D10 (D1) D11 (D0) (D11) (D10) ADC Bit Clock, ADC_DCLK Freq = 6X Fs ADC Output Data, ADCB_DATA 0 ADCA_DATA 0 Data rate = 12X Fs 12 bit serialization Output Data (LSB byte) ADCA_DATA _1 ADCB_DATA _0 ADC Frame Clock, ADC_FCLK Freq = 1X Fs (D5) (D4) (D3) (D2) (D1) (D0) Output Data (MSB byte) ADCA_DATA _0 ADCB_DATA _1 (D11) (D10) (D9) (D8) D10 (D7) D11 (D6) ADC Bit Clock – SDR DCLK Freq = 6X Fs ADC Bit Clock – DDR (def) DCLK Freq = 3X Fs (D11) (D9) (D7) (D5) (D3) D11 (D1) (D10) (D8) (D6) (D4) (D2) D10 (D0) in BYTE-WISE MODE (DEFAULT) in BIT-WISE MODE Input Clock, CLK Freq = Fs Data bit in LSB First mode Data bit in MSB First mode (D5) Output Data (Even bits) ADCA_DATA _1 ADCB_DATA _0 Output Data (Odd bits) ADCA_DATA _0 ADCB_DATA _1 (D5) (D4) (D3) (D2) (D1) (D0) (D11) (D10) (D9) (D8) D10 (D7) D11 (D6) (D11) (D9) (D7) (D5) (D3) D11 (D1) (D10) (D8) (D6) (D4) (D2) D10 (D0) Output Data (Sample N) ADCA_DATA _1 ADCB_DATA _0 (D5) (D4) (D3) (D2) D10 (D1) D11 (D0) Output Data (Sample N+1) ADCA_DATA _0 ADCB_DATA _1 (D11) (D10) (D9) (D8) (D7) (D6) in WORD-WISE MODE (D5) (D4) (D3) (D2) D10 (D1) D11 (D0) (D11) (D10) (D9) (D8) (D7) (D6) White cells – Sample N Grey cells – Sample N+1 Data rate = 6X Fs AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012
10.7.1 LVDS RX Interface
Figure10-11.1-WIRE MODE Figure10-12.2-WIRE MODE Copyright© 2011–2012,Texas InstrumentsIncorporated DIGITAL INTERFACE 87 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
%1,2,4 Clock Divider %1,2,4 PLL X2,4 ADC_CLK DAC_CLK MUX MUX MUX PLL_ENABLE REG_SE_CLK DIV_ADC<1:0> DIV_DAC<1:0> DCC (Duty Cycle Correction) MUX ENABLE_DCCSingle- ended Buffer Single- ended Buffer Differential Buffer AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com
10.7.2 CLOCKING
The clockinputsare versatile.The AFE7225/7222 can be drivenby a differentialclock,a single-ended clockor two independentsingle-endedclocks.Low voltageCMOS forsingle-endedand LVDS for differentialare supportedclocklevels.Since routingsingle-endedclockson the printedcircuitboard is differentfromsystemtosystem,itispossibletosee some performancedegradationinthedataconverters iftheclockbecomes corruptedpriortoenteringtheAFE7225/7222.Thisislesslikelytooccurifusinga differentialclockroutedon the board due to the common-mode noiserejectionof the differentialclock receiver. The fullblockdiagramoftheclockingtotheADC and DAC isshown below. Figure10-13.Clocking Depending on theADC inputfrequencyand thetargetSNR ofthereceiver,itmay be importanttoprovide a lowjitterclocksourcetotheAFE7225/7222.A good estimateforrequiredclockjittertoachievea certain SNR can be found using SNR = 20*log10(2*pi*FINadc*JITTERtotal).The JITTERtotalis the rms summation of the externalclockjitterand the internalAFE7225/7222 RX ADC clockingaperturejitter, specifiedinthetimingcharacteristicstable.A good targetforthetotaljitterisa valuethatallowsan SNR thatmeets orexceedstheADC SNR so thattheclocksourcejitterwillnotdegradetheSNR. Note thatthe SNR isdependenton theanaloginputfrequencyand nottheclockfrequency. When differentrateclocksare requiredfortheADC and theDAC (forexample,DAC_CLK is2X rateof ADC_CLK), itisstronglyrecommended thattheinputclockbe atthehigherofthetwo rates.Dividingthe highspeed clocktoderivethehalfrateclockalwaysgivesmuch lowerjitterthanusingthePLL tomultiply the lower rateclockto derivethe higherrateinsidethe chip.Use the PLL only when performance requirementsarerelaxedand theadditionaljitteristolerable(usuallywhen theanalogI/Ofrequenciesare low). The equivalentcircuitmodel ofthedifferentialbufferisshown below.Note thateven withthesingleended bufferisenabled,theloadingfromthepassivecomponents inthedifferentialbuffercircuit(includingthe2 pF differentialcap,thetwo 5 kOhm resistorsand theequivalentinputload,Ceq arestillpresent).
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~ 1 nH Cbond ~ 1 pF Lpkg ~ 1 nH Cbond ~ 1 pF Resr ~100 /c87 Resr CLKINN Differential Clock buffer Ceq Ceq Ceq ~ 1 to 3 pF, equivalent input capacitance of differential clock buffer 100 /c87 12-Bit SAR ADC AUXADC_A AUXADC_B Serializer SDOUT SCLK SCLK MODE_INPUT<1:0> SHIGH BYP ASSZ_BUF Input Buffer AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Figure10-14.InputClock EquivalentCircuit
10.8 AuxiliaryADC
The schematicoftheAuxiliaryADC isshown below. Figure10-15.AuxiliaryADC Schematic The AuxiliaryADC comprisesa 12-bitSAR ADC witha highimpedance inputbufferthatisbypassed by default(BYPASSZ_BUF=0). The AuxiliaryADC can selectitsinputfrom 2 externalpins called AUXADC_A and AUXADC_B. Thisselectionisdone usingthebitsMODE_INPUT <1:0>.The conversion isstartedby settingbitCONV_START to1,and SCLK isused as theconversionclock.The SAR ADC convertsthe selectedinputand the 12-bitoutputisserializedusingthe SCLK and givenout on the SDOUT pin.AftersettingCONV_START to 1, the AuxiliaryADC can be configuredforeithera single conversion,multipleconversionsorincontinuousconversionmode. Withtheinputbufferbypassed,theinputrangeoftheAuxiliaryADC is0-1.5Vwhen RANGE_AUXADC is setto0.When theAuxiliaryADC isconverting,theSAR ADC draws switchingcurrentfromtheinputpinif theinputbufferisbypassed.Thismay notbe desirableforapplicationswhere thevoltagebeingmonitored does not have drivecapability.With the inputbufferintroducedinthe path of the input,the AUXADC inputsare highimpedance and do notdraw current.However, theinputvoltagerange (attheAUXADC pins)isslightlyreducedto0.1-1.5V. WithRANGE_AUXADC setto1,theinputrangeisincreasedto0-DVDD18 withthebufferbypassed and 0.1-(DVDD18-0.1)Vwiththebufferenabled. Copyright© 2011–2012,Texas InstrumentsIncorporated DIGITAL INTERFACE 89 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SET CONVERSION START=1 SDATA SCLK SEN DO11DO10 DO9 DATA LATENCY = 27.5 CLOCKS tPER Write Address: 364 Data: 01 SHIGH (INTERNAL SAMPLING CLOCK) DO8 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 AUXADC input sampled here AUXADC goes back to sampling mode SDOUT 20 clocks DATA PROPAGATION DELAY = 20 ns AUXDAC_A (Pin) AUXDAC_A_N (Internal node) REXTRINT IAUX_DAC AVDD3_AUX (3 V) AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com
10.8.1 EnablingtheAuxiliaryADC
The AuxiliaryADCs aredisabledby default. Below isthetimingdiagramillustratingtheAux ADC operation. Beforestartingconversion,setbitEN_AUX_ADC to '1'.Also setWHAT_IS_SDOUT <1:0> to configure SDOUT as a digitaloutputpin. Figure10-16.AUX ADC Timing Diagram Note thatthroughouttheAux ADC conversion,SEN iskeptlow (active).Alsokeep SDATA low once the CONV_START bithas been written. To getoutofAux ADC conversionmode, pullSEN high,thenpullitlow againand writethebittomake CONV_START=0.
10.9 AuxiliaryDAC
The schematicoftheAuxiliaryDAC (forchannelA) isshown below. Figure10-17.AuxiliaryDAC Schematic The AuxiliaryDAC is a 12-bitcurrentoutputDAC withthe currentsteeredintothe AUXDAC_A pin dependenton thedigitalcode.The dataformatoftheAuxiliaryDAC inputisoffsetbinary. R EXT istheexternalconnectedtotheAUXDAC_A pinand alongwiththevalueofthefullscalecurrent, setsthefullscaleoutputvoltagerange.Forzeroinputcode,voltageon AUXDAC_A isequalto0 V. Formaximum inputcode,voltageon AUXDAC_A isequaltoIAUX_DAC *REXT . IAUX_DAC isthefullscalecurrentoftheAuxiliaryDAC, and can be programmed from 2.5mA to7.5mA (usingbitsFS_AUXDACI <3:0>). For bestlinearity,limitthemaximum voltageatAUXDAC_A to1.5V.For example,withIAUX_DAC setto5 mA, and R EXT setto300 Ohm, thevoltageon AUXDAC_A willswingfrom0 to1.5V.
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0 1 0 0 0 1 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 AUX DAC B INPUT1 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0DB11 SDOUT AUXDAC_A AUXDAC_B DELAY FOR FIRST UPDATE = 22 CLOCKS DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DA11 DB11 DB0 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DB10 DB9 DB8 DB7 DB6 DB5 DB4DB11 DA11 DELAY FOR SUBSEQUENT UPDATE = 12 CLOCKS AUX DAC A INPUT2 AUX DAC B INPUT2 tPER tSETTLE tSETTLE AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 AUXDAC_A_N istheinternalcomplementarynode and has an internalresistor,R INT programmablefrom 57 Ohm to 400 Ohm (usingbitsAUX_DAC_TERM_N <2:0>).For bestlinearity,choose a valueof this resistortobe as closetoR EXT as possible.
10.10 EnablingtheAuxiliaryDAC
The AuxiliaryDACs aredisabledby default. Note thataddressof the 20 bitserialinterfacewritebus isthe 1st12 bitsout of which the 1st4 bits determinetheaccessmode fortheAuxiliaryDAC. Letus denotethisaddressas ADDR <11:0>. FollowingareAux DAC modes: IfADDR <11:8> = 0100, then we enterDirectAccess mode forDAC. In thismode, DAC data is dynamicallywrittenthroughSDATA (andSDOUT). IfADDR <11:8> = 0101,thenwe entertheRegisterAccess mode. Inthismode, DAC isloadedwiththe datafromcontentsofpre-loadedregisters. Indirectaccessmode IfADDR <7:6> = 01:DAC_A willgetwrittenwiththe12 serialbitsfromSDATA, DAC_B willgetwritten withthe12 serialbitsfromSDOUT (bothattherisingedge ofSCLK) IfADDR <7:6> = 10: DAC_A willget 12 bitsfrom SDATA, DAC_B willget next12 bitsfrom SDATA (bothattherisingedge ofSCLK) IfADDR <7:6> = 11:DAC_A willget12 bitsfromSDATA attherisingedge ofSCLK, DAC_B willget12 bitsfromSDATA atthefallingedge ofSCLK. Inregisteraccessmode: ADDR <7:6> = 01:OnlyDAC_A willbe loadedwiththeregister ADDR <7:6> = 10:OnlyDAC_B willbe loaded ADDR <7:6> = 11:BothDAC_A and DAC_B areloaded. For eitherdirectaccessorregisteraccessmodes, onlythe1st6 bitsoftheaddressneed tobe writtenfor theserialinterfacestatemachine.Remainigbitsareconsideredas applicabletotheDAC data. Below diagramshows theAux DAC timingforthedirectaccess mode where DAC_A iswrittenthrough SDATA and DAC_B throughSDOUT. Startby alreadysettingEN_AUXDACA and EN_AUXDACB bitshigh. Figure10-18.Aux DAC Timing Diagram: DAC_A isWrittenThrough SDATA and DAC_B Through SDOUT tPER = SCLK period> 25 ns tSETTLE = SettlingtimeofAux DAC forfullscaleoutput(0-1.5V)= 40 ns Copyright© 2011–2012,Texas InstrumentsIncorporated DIGITAL INTERFACE 91 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
0 1 0 0 0 1 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 AUXDAC_A AUXDAC_B DELAY FOR FIRST UPDATE = 34 CLOCKS DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4DA11 AUX DAC B INPUT1 tPER tSETTLE AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Thereforefastestupdatetime: Firstupdate= 22*25ns+ 40ns = 590 ns Subsequentupdate= 12*25ns= 300 ns For the directaccess mode where DAC_A and DAC_B are both writtenthroughSDATA, the timingis shown infigurebelow. Figure10-19.Aux DAC Timing Diagram: DAC_A and DAC_B areBoth WrittenThrough SDATA Thereforefastestupdatetime: Firstupdate= 34*25ns+ 40ns = 890 ns Subsequentupdate= 24*25ns= 600 ns AfterthefirstAux DAC refresh,subsequentrefreshoftheAux DAC outputsintheabove mentioneddirect access mode takes place afterevery 24 clocks.Note thatthe Aux DAC takes about 12 mA on AVDD3_AUX (when fullscaleoutputissetto5 mA each Aux DAC).
10.11 FullDuplex Operation– Coupling Considerations
When operatingthetransmitand receivechannelssimultaneously,severalfactorsneed tobe considered inordertominimizethecouplingbetween thetransmitand receivechannels.Ina generalcase,theDAC and ADC clockscan be atarbitraryrates,withorwithoutharmonicrelationstoeach other.Insuch a case, thereexistseriouspossibilitiesofcouplingbetween theADC and DAC. As faras possible,we recommend drivingthe ADC and DAC withthe same clockrateexternally,and use the internalclockdivisionand multiplicationtoadjusttotherequiredADC and DAC clockratesinternally. The internalblockdiagramoftheclockingpathisrepeatedbelow.
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%1,2,4 Clock Divider %1,2,4 PLL X2,4 ADC_CLK DAC_CLK MUX MUX MUX PLL_ENABLE REG_SE_CLK DIV_ADC<1:0> DIV_DAC<1:0> DCC (Duty Cycle Correction) MUX ENABLE_DCCSingle- ended Buffer Single- ended Buffer Differential Buffer AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Figure10-20.Block Diagram ofClockingPath Threecasesareconsidered: Case 1:DAC_CLK and ADC_CLK are atsame rate:Inthiscase,eitherCLKINP and CLKINN shouldbe drivenby a differentialclock(common toboththeADC and DAC) ortwo singleended clocks,bothatthe same rate. Case 2:DAC_CLK and ADC_CLK are atdifferentratessuch thatthe higherrateis2X or 4X of the lower rate:Inthiscase,we againrecommend drivingCLKINP/CLKINN differentially(orby two equalrate singleended clocks)at the higherof two ratesand dividnginternallyby the factorof 2 (or4) on the channelthatrequiresthelowerrateclock. Case 3:DAC_CLK and ADC_CLK are atdifferentrateswiththe DAC_CLK being at8X or 16X of the ADC_CLK: Inthiscase,we recommend drivingCLKINP/CLKINN differentially(orby two equalratesingle ended clocks)at4X ofADC_CLK rate,dividingitby 4 fortheADC, and multiplyingitby 2 (or4) forthe DAC. Case 4:DAC_CLK and ADC_CLK areatdifferentratesthatareharmonicallyrelatedbut not atrates covered by Case 2 or Case 3:Inthiscase,thereisno alternativebuttodriveCLKINP and CLKINN with two differentrateclocks.Ifphase controlofthetwo clocksispossible,we recommend thatthephases be adjustedsuch thatthetwo clockshave rise/falledges thatdo notcome within5 ns ofeach other.We also recommend thatthedrivingclockratesbe as closetoeach otheras possible. Case 5:DAC_CLK and ADC_CLK are atdifferentratesthatare non-harmonicallyrelated:Thisisthe worstcase and itisrecommended toavoidoperatingtheAFE infullduplexmode withsuch clockrates. The presenceofnon-harmonicallyrelatedclocksattwo adjacentpinscan cause periodicmodulationin thesamplinginstantthatcan resultinhuge spursthatgetworse athigherADC inputfrequencies(and DAC outputfrequencies).At70 MHz IF,thesespurlevelscouldbe as largeas –45 dBc.
10.12 HalfDuplex Operation– Coupling Considerations
IftheADC and DAC aredrivenexternallyby unequalrateclocks,thenensurethattheseclocksarenoton simultaneously.For example,inhalfduplexmode withthe Tx active,ensure thatthe ADC clockto the deviceisshutoff.IftheADC and DAC are drivenby equalrateclocks,thenitisnotrequiredtoshutoff theADC clockwhen theTx isactive(andDAC clockwhen theRx isactive).
10.13 HalfDuplex OperationThrough a Common I/OInterface
IftheAFE7222/7225 istobe alwaysoperatedinHalfDuplexmode througha common I/Ointerfaceforthe RX and TX (toreusethesame bus),thentheRX and TX dataand clockscan be tiedon theboard as illustratedbelow: Copyright© 2011–2012,Texas InstrumentsIncorporated DIGITAL INTERFACE 93 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
CMOSRX CLK ADC_DCLKOUT CMOS TX DATA DACDATA CMOS TX CLK DAC_DCLKIN ADC DAC TO FPGA REG_OEZ_CMOS_DAT REG_OEZ_CMOS_CLK REG_PDN_RX REG_PDN_TX AFE7222/ 7225 AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com Figure10-21.I/OInterface To enabletheTX inHalfDuplexmode, set: REG_PDN_RX=1, REG_OEZ_CMOS_DAT=1, REG_OEZ_CMOS_CLK=1, and drivethe DACDATA and DAC_DCLKIN pinsas TX inputpins. To enabletheRX inHalfDuplexmode, set: REG_PDN_TX=1 and receivedataand clockfromtheRX on thesame bus. For a pin controlto be able to togglebetween RX halfduplex and TX halfduplex modes, set bit REG_HALF_DUPLEX_THRU_PIN. When thismode isset,thePDN pinservesas a togglepin– when the PDN pinishigh,thedeviceoperatesinHalfduplexRX mode and when thePDN pinislow,thedevice operatesinHalfduplexTX mode. Note thathalfduplexmode througha common I/Ointerfaceand thefullduplexmode willrequiredifferent boardconfigurations,sinceintheformermode, theI/Obus isshared.
11 QUICK GUIDE
Supplies: We recommend drivingtheDevicewith3 supplies: 3V supply– Tiepins11,14,17,22 tothissupply 1.8Vanalogsupply– Tiepins1,4,7,10,19,25,62,64 tothissupply 1.8Vdigitalsupply– Tiepins32,41,49 tothissupply Power up sequence: Power on the3V and 1.8Vsuppliesinany sequence Applya highgoingpulseon RESET ofminimum width100 ns toresettheinternalregistersofthedevice. SoftwareRESET: InadditiontothehardwareRESET pin,thedevicealsohas a softwareRESET bit.Thisisa self-clearing bit,so itneeds tobe onlyassertedwhenever thedeviceneeds tobe reset.The softwareRESET can be appliedby programmingregisteraddress000,Data 02.
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ADC_DCLKOUT ADCDA T A <11:0> A B A B A BB AFE7222 AFE7225 www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Clocking: By default,thedeviceexpectsa differentialclockon CLKINP and CLKINN. Thisdifferentialclockisused todriveboththeADC and DAC. Incase theclocksourceissingleended,thenshortCLKINN toa voltageof0.95V and applythesingle ended clocksourceon CLKINP – alternatively,CLKINP can be drivenwitha voltageof 0.95V and the singleended clocksourcecan be appliedon CLKINN. A thirdalternativeistouse thesingleended clockbufferinsidethedevice.Thismode saves about9 mW ofpower sincethedifferentialclockbufferisshutdown. By settingregister(address20A, Data 20),the singleended clockbuffercan be enabled.Inthatcase,Pin8 providesthesingleended clockfortheDAC whereas Pin 9 providesthesingleended clockfortheADC – ifa singleclocksourceistobe used for both,thentiepins8 and 9 tothisclocksource. BiasingtheADC inputs: The common mode oftheADC inputpinsshouldsettoVCM, which isnominally0.95V (measured after programming the initializationregisters).Deviatingfrom thisinputcommon mode can cause degraded performance.The fullscaleinputswing on the inputsis2 Voltdifferentialpeak-to-peak.When biased optimallyat 0.95V,the devicegivesa fullscaleoutputcode when the positiveinputswings between recommended tooperatetheADC atan inputthatisatleast1 dB belowfullscale. ADC outputformat: The ADC givesouta 12-bitoutputin2s complement format.For themost negativeinput,theADC gives outa code of100000000000.Forthemost positiveinput,theoutputcode is011111111111. RX dataoutputcapture(CMOS mode) : The RX outputdata formatisDDR (Dualdata rate)CMOS. The outputof the ADC channelA can be capturedusingtherisingedge ofADC_DCLKOUT. The outputofADC channelB can be capturedusing thefallingedge ofADC_DCLKOUT. The clockrateofADC_DCLKOUT matches withtheinputclockrate (onCLKINP, CLKINN). Figure11-1.RX CMOS Output Interface A varietyoftestpatternscan be outputby thedeviceinordertodebug issueswiththecapture.To enable the testpatterns,program registeraddress 042, Data 08. Once thisregisterisprogrammed, we can change theoutputpatternas follows: TO REPLACE NORMAL DATA WITH THE FOLLOWING ..ON CHANNEL A WRITE ..ON CHANNEL B WRITE Allbits0 Address031,Data 01 Address037,Data 01 Allbits1 Address031,Data 02 Address037,Data 02 Allbitstogglebetween 0 and 1 Address031,Data 03 Address037,Data 03 Linearlyrampingcode thatramps throughmin tomax code Address031,Data 04 Address037,Data 04 12-bitCustom code Address031,Data 05 Address037,Data 05 The 12 bitsforthecustom code (C<11 :0>)can be set(common forChannel A and B) usingthefollowing bits: C <11> = BitD5 ofregsteraddress03F C <10> = BitD4 ofregsteraddress03F C <9> = BitD3 ofregsteraddress03F Copyright© 2011–2012,Texas InstrumentsIncorporated QUICK GUIDE 95 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
DAC_DCLKIN DACDA T A <11:0> A B A B A BB AFE7222 AFE7225 SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com C <8> = BitD2 ofregsteraddress03F C <7> = BitD1 ofregsteraddress03F C <6> = BitD0 ofregsteraddress03F C <5> = BitD7 ofregsteraddress040 C <4> = BitD6 ofregsteraddress040 C <3> = BitD5 ofregsteraddress040 C <2> = BitD4 ofregsteraddress040 C <1> = BitD3 ofregsteraddress040 C <0> = BitD2 ofregsteraddress040 For example,programming registers(Address03F Data 29) and (Address040 Data 34) replacesthe normalADC dataforbothchannelswiththestaticbinarycode 101001001101. DAC inputformat: The DAC inputformatisalso2s complement similartotheADC. FullscaleDAC current: The fullscaleDAC current(IOUTFS) issetby theresistor(ofvalueRBIASJ) on theBIASJ pin. IOUTFS = 19.2/RBIASJ. ForRBIASJ=960 Ω,IOUTFS = 20 mA For the 12-bitinputcode (where CODE isthe decimalrepresentationof the DAC data inputword in straightoffsetbinaryformat): IOUTP = IOUTFS × CODE /4096 IOUTN = IOUTFS × (4096– CODE) /4096 TX datainput(CMOS mode): The TX inputdataformatisalsoDDR CMOS. The risingedge oftheDAC_DCLKIN latchestheChannel A data insidethe AFE7225/7222, and the fallingedge latchesthe Channel B data.The clockrateof DAC_DCLKIN issame as theinputclockratewhen interpolationisnotset.When 2X interpolationisset,it shouldbe halftheinputclockrate,and when 4X interpolationisset,itshouldbe one-fourththeinputclock rate. Figure11-2.TX CMOS InputInterface Interpolation: Whileinterpolatingby a factorof2,theDAC_DCLKIN rateshouldbe settohalfoftheinputclockrate. The 2X interpolationmode on theTX sidecan be setby thefollowingregister:Address106,Data 05. Powerdown modes: The devicehas severalpowerdown modes whichprovidea tradeoffbetween power consumed and speed ofrecoveryfrom powerdown. The natureofthepowerdown mode can be setthroughtheregisters.Also theassertionofthepowerdown can be done eitherthroughthePDN pinorthrougha registerbit. WhileusingthePDN pintocontrolthepowerdown state,thefollowingaretheregisterconfigurations(see specificationstableforrecoverytimes) Globalpowerdown mode through PDN pin :Set Address207,Data 20,and controlPDN pintoassert/ de-assertglobalpowerdown mode. Most functionsareshutdown.
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www.ti.com SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 Fast recoverypowerdown mode through PDN pin :Set Address207,Data 40,and controlPDN pinto assert/de-assertfastrecoverypowerdown mode. RX and TX arebothputtolightsleep,forfastrecovery. Powerdown TX through PDN pin :Set Address207,Data 02,and controlPDN pintoassert/de-assert TX powerdown mode. Inthismode, theTX pathisshutdown and theRX isfullyactive,butTX iswaiting forfastrecovery. Powerdown RX through PDN pin :Set Address207,Data 04,and controlPDN pintoassert/de-assert RX powerdown mode. Inthismode, theRX pathisshutdown and theTX isfullyactive,butRX iswaiting forfastrecovery. In the above cases,the PDN pinwas used to assert/de-assertthe powerdown state.Alternatively,a registerbitcan be used toassert/de-assertthepowerdown state.ThisisbitD7 ofregisteraddress207. The correspondingregisterconfigurationstoassert/de-assertthepowerdown throughtheregisterbitare as follows(inthiscase,keep thePDN pinlow). MODE TO ASSERT POWERDOWN WRITE TO DE-ASSERT POWERDOWN WRITE Globalpowerdown throughregister Address207,Data A0 Address207,Data 20 Fastrecoverypowerdown throughregister Address207,Data C0 Address207,Data 40 TX powerdown throughregister Address207,Data 82 Address207,Data 02 RX powerdown throughregister Address207,Data 84 Address207,Data 04 Copyright© 2011–2012,Texas InstrumentsIncorporated QUICK GUIDE 97 SubmitDocumentationFeedback ProductFolderLink(s):AFE7222 AFE7225
SLOS711B –NOVEMBER 2011–REVISED MARCH 2012 www.ti.com RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from Original(November 2011)toRevisionA Page Changes from RevisionA (December 2011)toRevisionB Page
- Added RX and TX active,No inputsignalappliedon ADC and DAC toSupply current,fullduplex mode
- Added RX and TX active,No inputsignalappliedon ADC and DAC toSupply current,fullduplex mode
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www.ti.com 13-Jan-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) AFE7222IRGC25 ACTIVE VQFN RGC 64 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR AFE7222IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR AFE7222IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR AFE7225IRGC25 ACTIVE VQFN RGC 64 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR AFE7225IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR AFE7225IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 13-Jan-2012 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) AFE7222IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 AFE7222IRGCT VQFN RGC 64 250 336.6 336.6 28.6 AFE7225IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 AFE7225IRGCT VQFN RGC 64 250 336.6 336.6 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2012 Pack Materials-Page 2
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