AFE5805ZCFT

Texas Instruments

FULLY-INTEGRATED,8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/?숰z, 12-Bit, 50MSPS, 122mW/Channel

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LNA8□Channels SPI IN1 IN8 . CH1 LVDS OUT CH8 VCA/PGA Clamp and LPF Logic/Controls Reference CW□Switch□Matrix□(8 10)/c180 I (10)OUT 12-Bit ADC AFE5805 AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 FULLY-INTEGRATED,8-CHANNELANALOGFRONT-ENDFORULTRASOUND 0.85nV/√Hz,12-Bit,50MSPS,122mW/Channel Check forSamples: AFE5805 1FEATURES DESCRIPTION 23• 8-ChannelComplete Analog Front-End: The AFE5805 isa completeanalogfront-enddevice specificallydesigned for ultrasoundsystems that– LNA, VCA, PGA, LPF, and ADC requirelowpower and smallsize.• Ultra-Low,Full-ChannelNoise: The AFE5805 consistsofeightchannels,includinga– 0.85nV/√Hz (TGC) low-noise amplifier (LNA), voltage-controlled– 1.1nV/√Hz (CW) attenuator(VCA), programmable gain amplifier

Low Power: (PGA), low-pass filter(LPF), and a 12-bit analog-to-digitalconverter(ADC) with low voltage– 122mW/Channel (40MSPS) differentialsignaling(LVDS) dataoutputs.– 74mW/Channel (CW Mode) The LNA gainissetfor20dB gain,and has excellent• Low-Noise Pre-Amp (LNA): noiseand signalhandlingcapabilities,includingfast– 0.75nV/√Hz overloadrecovery.VCA gaincan varyover a 46dB – 20dB FixedGain rangewitha 0V to1.2V controlvoltagecommon toall channelsoftheAFE5805.– 250mV PP LinearInputRange
Variable-GainAmplifier: The PGA can be programmed forgains of 20dB, 25dB, 27dB, and 30dB. The internallow-passfilter– Gain ControlRange: 46dB can alsobe programmed to10MHz or15MHz.• PGA Gain Settings:20dB, 25dB, 27dB, 30dB The LVDS outputsoftheADC reducethenumber of• Low-Pass Filter: interfacelinestoan ASIC orFPGA, therebyenabling– SelectableBW: 10MHz, 15MHz the high system integrationdensitiesdesiredfor – 2nd-Order portablesystems.The ADC can eitherbe operated withinternalor externalreferences.The ADC also• Gain Error:±0.5dB featuresa signal-to-noiseratio(SNR) enhancement• Channel Matching:±0.25dB mode thatcan be usefulathighgains.
Distortion,HD2: –65dBFS at5MHz The AFE5805 is availablein a 15mm × 9mm,• Clamping Control 135-ball BGA package that is Pb-free
FastOverload Recovery:Two Clock Cycles (RoHS-compliant)and green. It is specifiedfor operationfrom0°C to+70°C.• 12-BitAnalog-to-DigitalConverter: – 10MSPS to50MSPS – 69.5dB SNR at10MHz – SerialLVDS Interface
IntegratedCW Switch Matrix
15mm × 9mm, 135-BGA Package: – Pb-Free(RoHS-Compliant)and Green

APPLICATIONS

MedicalImaging,Ultrasound – PortableSystems Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Infineonisa registeredtrademarkofInfineonTechnologies. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2008–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. PACKAGING/ORDERING INFORMATION (1)(2) OPERATING PACKAGE TEMPERATURE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE NUMBER MEDIA, QUANTITY ECO STATUS AFE5805ZCFR Tape and Reel,1000 AFE5805 mFBGA-135 ZCF 0°C to+70°C AFE5805ZCFT Tape and Reel,250 Pb-Free,Green AFE5805ZCF Tray,160 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. (2) These packagesconformtoLead (Pb)-freeand greenmanufacturingspecifications.Additionaldetailsincludingspecificmaterialcontent can be accessedatwww.ti.com/leadfree. GREEN: TIdefinesGreen tomean Lead (Pb)-Freeand inaddition,uses lesspackage materialsthatdo notcontainhalogens,including bromine(Br),orantimony(Sb)above 0.1%oftotalproductweight.N/A:Not yetavailableLead (Pb)-Free;forestimatedconversion dates,go towww.ti.com/leadfree.Pb-FREE: TIdefinesLead (Pb)-Freetomean RoHS compatible,includinga leadconcentrationthat does notexceed 0.1% oftotalproductweight,and,ifdesignedtobe soldered,suitableforuse inspecifiedlead-freesoldering processes. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange,unlessotherwisenoted. AFE5805 UNIT Supplyvoltagerange,AVDD1 –0.3to+3.9 V Supplyvoltagerange,AVDD2 –0.3to+3.9 V Supplyvoltagerange,AVDD_5V –0.3to+6 V Supplyvoltagerange,DVDD –0.3to+3.9 V Supplyvoltagerange,LVDD –0.3to+2.2 V Voltagebetween AVSS1 and LVSS –0.3to+0.3 V Voltageatanaloginputs –0.3tominimum [3.6,(AVDD2 + 0.3)] V ExternalvoltageappliedtoREFT-pin –0.3to+3 V ExternalvoltageappliedtoREFB-pin –0.3to+2 V Voltageatdigitalinputs –0.3tominimum [3.9,(AVDD2 + 0.3)] V Peak soldertemperature(2) +260 °C Maximum junctiontemperature,TJ +125 °C Storagetemperaturerange –55 to+150 °C Operatingtemperaturerange 0 to+70 °C HBM 2000 V ESD ratings CDM 1000 V MM 100 V (1) Stressesabove theseratingsmay cause permanentdamage. Exposuretoabsolutemaximum conditionsforextendedperiodsmay degradedevicereliability.These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thosespecifiedisnotsupported. (2) DevicecomplieswithJSTD-020D.

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010

ELECTRICAL CHARACTERISTICS

AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupled(1.0mF), VCNTL = 1.0V,fIN = 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffer setting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PREAMPLIFIER (LNA) Gain A SE-inputtodifferentialoutput 20 dB Inputvoltage VIN Linearoperation(HD2 ≤ –40dB) 250 mV PP blankMaximum inputvoltage Limitedby internaldiodes 600 mV PP Inputvoltagenoise(TGC) en (RTI) R S = 0Ω,f= 1MHz 0.75 nV/√Hz Inputcurrentnoise In (RTI) 3 pA/√Hz Common-mode voltage,input VCMI Internallygenerated 2.4 V Bandwidth BW Small-signal,–3dB 70 MHz Inputresistance(1) Atf= 4MHz 8 kΩ Inputcapacitance(1) IncludesinternalESD and clampingdiodes 16 pF FULL-SIGNAL CHANNEL (LNA+VCA+LPF+ADC) Inputvoltagenoise(TGC) en R S = 0Ω,f= 2MHz, PGA = 30dB 0.85 nV/√Hz R S = 0Ω,f= 2MHz, PGA = 20dB 1.08 nV/√Hz Noisefigure NF R S = 200Ω,f= 5MHz 1.5 dB Low-passfilterbandwidth LPF at–3dB,selectablethroughSPI 10,15 MHz Bandwidthtolerance ±10 % High-passfilter HPF (First-order,due tointernalac-coupling) 200 kHz Group delayvariation ±3 ns Overloadrecovery ≤ 6dB overloadtowithin1% 2 ClockCycles ACCURACY Gain (PGA) SelectablethroughSPI 20,25,27,30 dB Totalgain,max (2) LNA + PGA gain,VCNTL = 1.2V 48 49.5 51 dB Gain range VCNTL = 0V to1.2V 46 dB VCNTL = 0.1Vto1.0V 40 dB Gain error,absolute(3) 0V < VCNTL < 0.1V ±0.5 dB 1.0V< VCNTL < 1.2V ±0.5 dB Gain matching Channel-to-channel –0.5 ±0.25 +0.5 dB Offseterror VCNTL = 1.0V,PGA = 30dB –39 +39 LSB Offseterrordrift(tempco) ±5 ppm/°C Clamp level CL = 0 1.7 VPP CL = 1 (clampdisabled) 2.8 VPP GAIN CONTROL (VCA) Inputvoltagerange VCNTL Gain range= 46dB 0 to1.2 V Gain slope VCNTL = 0.1Vto1.0V 44.4 dB/V Inputresistance 25 kΩ Response time VCNTL = 0V to1.2Vstep;to90% signal 0.5 ms DYNAMIC PERFORMANCE Signal-to-noiseratio SNR fIN = 2MHz; –1dBFS, PGA = 30dB 59.8 dBFS fIN = 5MHz; –1dBFS, PGA = 30dB 59.6 dBFS fIN = 10MHz; –1dBFS, PGA = 30dB 58.8 dBFS (1) See Figure33. (2) ExcludesdigitalgainwithinADC. (3) Excludeserrorofinternalreference. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupled(1.0mF), VCNTL = 1.0V,fIN = 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffer setting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE (continued) Second-harmonicdistortion HD2 fIN = 2MHz; –1dBFS, PGA = 30dB –70 dBFS fIN = 5MHz; –1dBFS, PGA = 30dB –54 –65 dBFS fIN = 5MHz; –6dBFS, PGA = 20dB –61 –69 dBFS Third-harmonicdistortion HD3 fIN = 2MHz; –1dBFS, PGA = 30dB –58 dBFS fIN = 5MHz; –1dBFS, PGA = 30dB –51 –59 dBFS fIN = 5MHz; –6dBFS, PGA = 20dB –56 –78 dBFS f1 = 4.99MHz at–6dBFS,Intermodulationdistortion IMD3 58.5 dBcf2 = 5.01MHz at–32dBFS Crosstalk fIN = 5MHz, –1dBFS, PGA = 30dB –67 dBc CW — SIGNAL CHANNELS Inputvoltagenoise(CW) en R S = 0Ω,f= 1MHz 1.1 nV/√Hz Outputnoisecorrelationfactor Summing ofeightchannels 0.6 dB Outputtransconductance AtVIN = 100mV PP 14 15.6 18 mA/V(IOUT /VIN) Dynamic CW outputcurrent, IOUTAC 2.9 mA PPmaximum StaticCW outputcurrent(sink) IOUTDC 0.9 mA Outputcommon-mode VCM 2.5 Vvoltage(4) Outputimpedance 50 kΩ Outputcapacitance 10 pF INTERNAL REFERENCE VOLTAGES (ADC) Referencetop VREFT 0.5 V Referencebottom VREFB 2.5 V VREFT – VREFB 1.95 2 2.05 V Common-mode voltage VCM 1.425 1.5 1.575 V(internal) VCM outputcurrent ±2 mA EXTERNAL REFERENCE VOLTAGES (ADC) Referencetop VREFT 2.4 2.5 2.6 V Referencebottom VREFB 0.4 0.5 0.6 V VREFT – VREFB 1.9 2.1 V Switchingcurrent(5) 2.5 mA (4) CW outputsrequirean externallyappliedbiasvoltageof+2.5V. (5) Currentdrawn by theeightADC channelsfromtheexternalreferencevoltages;sourcingforVREFT, sinkingforVREFB.

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupled(1.0mF), VCNTL = 1.0V,fIN = 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffer setting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY Supply Voltages AVDD1, AVDD2, DVDD Operating 3.15 3.3 3.47 V AVDD_5V Operating 4.75 5 5.25 V LVDD 1.7 1.8 1.9 V Supply Currents IAVDD1 (ADC) at40MSPS 99 110 mA IAVDD2 (VCA) TGC mode 146 156 mA CW mode 79 85 mA IAVDD_5V (VCA) TGC mode 8 10 mA CW mode 55 61 mA IDVDD (VCA) 1.5 3.0 mA ILVDD (ADC) At40MSPS 70 80 mA Power dissipation,total Allchannels,TGC mode, no signal 980 1080 mW Allchannels,CW mode ,no signal(6) 580 620 mW TGC mode, no clockapplied,no signal 615 mW POWER-DOWN MODES Power-down dissipation,total Completepower-down mode 64 85 mW Power-down responsetime(7) 1.0 ms Power-upresponsetime(7) PD tovalidoutput(90% level) 50 ms Power-down dissipation(7) Partialpower-down mode 233 mW THERMAL CHARACTERISTICS Temperaturerange 0 +70 °C Thermalresistance TJA 32 °C/W TJC 4.2 °C/W (6) The ADC sectionispowered down duringCW mode operation. (7) WithVCA_PD and ADC_PD pins= high.The ADC_PD pinisconfiguredforpartialpower-down (seethePower-Down Modes section). Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com DIGITAL CHARACTERISTICS DC specificationsrefertotheconditionwhere thedigitaloutputsarenotswitching,butarepermanentlyata validlogiclevel '0'or'1'.AtC LOAD = 5pF(1),IOUT = 3.5mA (2),R LOAD = 100Ω(2),and no internaltermination,unlessotherwisenoted. AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-levelinputvoltage 1.4 3.3 V Low-levelinputvoltage 0 0.3 V High-levelinputcurrent 10 mA Low-levelinputcurrent(3) –10 mA Inputcapacitance 3 pF LVDS OUTPUTS High-leveloutputvoltage 1375 mV Low-leveloutputvoltage 1025 mV Outputdifferentialvoltage,|VOD | 350 mV VOS outputoffsetvoltage(2) Common-mode voltageofOUTP and OUTM 1200 mV Outputcapacitanceinsidethedevice,Outputcapacitance 2 pFfromeitheroutputtoground FCLKP and FCLKM 10 1x (clockrate) 50 MHz LCLKP and LCLKM 60 6x (clockrate) 300 MHz CLOCK Clockinputrate 10 50 MSPS Clockdutycycle 50 % Clockinputamplitude,differential Sine-wave,ac-coupled 3 VPP(VCLKP – VCLKM) LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP Clockinputamplitude,single-ended (VCLKP) High-levelinputvoltage,VIH CMOS 2.2 V Low-levelinputvoltage,VIL CMOS 0.6 V (1) C LOAD istheeffectiveexternalsingle-endedloadcapacitancebetween each outputpinand ground. (2) IOUT referstotheLVDS buffercurrentsetting;R LOAD isthedifferentialloadresistancebetween theLVDS outputpair. (3) ExceptpinJ3 (INT/EXT),whichhas an internalpull-upresistor(52kΩ)to3.3V.

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1x□ADCLK 6x□ADCLK IN1 OUT1P OUT1M LCLKP LCLKM FCLKP FCLKM 12x□ADCLK 12-Bit ADC Serializer DigitalLPFPGA Digital Reference REFT INT/ EXT CW[0:9] REFB CM OUT8P OUT8M ISET Registers SDATA CS SCLK ADC Control PD Clock Buffer CLKPAVSS2AVDD2 (3.3V) CLKMAVDD1 (3.3V)LVDD (1.8V) Power- Down T est□P atterns Drive□Current Output□F ormat Digital□Gain(0dB□to□12dB) /c188/c188/c188 VCALNA /c188 IN8 VCNTL LPFPGAVCA CW□Switch□Matrix (8x10) LNA /c188 /c188 /c188 /c188/c188 /c188Channels 2□to□7 ADC_ RESET /c188 /c188 T SCLK AVDD_5V DVDD(3.3V) AVSS1 20,25,27 30dB 10,15MHz AFE5805 /c188 AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 FUNCTIONAL BLOCK DIAGRAM Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):AFE5805

D AVSS2AVSS2AVDD2 DVDDCW9 C AVSS2AVSS2VCNTL DVDDCW8 B AVSS2AVSS2AVDD_5V AVSS2CW7 A IN8IN4IN2 VCA_PDIN3IN1 E 87 9 VBL5VBL7 VBL6 CW0AVSS2 AVDD2 CW1AVSS2 VB2 CW2VB4 AVDD_5V IN5IN7 IN6 AVSS2AVSS2AVDD2 AVSS2VCMCW5 J SCLKVCA_CSDNC RSTADS_PD H AVSS2AVSS2AVDD1 AVSS2AVSS1 G AVDD1DNCDNC AVDD1AVDD1CLKM F AVSS2AVSS2VB1 AVSS2VB5CW6 K Rows AVSS2 VB3 AVSS2 CW4VREFL AVDD2 ADS_ RESETCS SDA T A REFBAVDD1 REFT ISETAVDD1 CM CW3VREFH VB6 AVSS1AVSS1DNC AVSS1AVSS1DNC P L VDDL VSSLCLKM L VSSLCLKP N OUT5POUT1POUT3P L VDDOUT4P M OUT5MOUT1MOUT3M L VSSOUT2MOUT4M L AVSS1AVSS1AVDD1 AVSS1AVSS1CLKP R L VSS OUT2P DNC INT/EXT DNCAVSS1 DNC FCLKPL VDD FCLKM OUT8POUT6P OUT7P OUT8MOUT6M OUT7M EN_SMAVSS1 AVDD1 AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com PIN CONFIGURATION ZCF PACKAGE 135-BGA BOTTOM VIEW

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R OUT8M OUT7M OUT6M OUT5M LVSS OUT1M OUT2M OUT3M OUT4M 9 8 7 6 5 4 3 2 1 P OUT8P OUT7P OUT6P OUT5P LVDD OUT1P OUT2P OUT3P OUT4P N FCLKP FCLKM LVDD LVDD LVSS LVSS LVSS LCLKM LCLKP M DNC DNC AVSS1 AVSS1 AVSS1 AVSS1 AVSS1 DNC DNC L EN_SM AVDD1 AVSS1 AVSS1 AVSS1 AVSS1 AVSS1 AVDD1 CLKP K ISET CM AVDD1 AVDD1 AVDD1 DNC AVDD1 DNC CLKM J REFB REFT AVDD1 AVSS2 AVSS2 AVSS2 INT/ EXT AVDD1 AVSS1 H ADS_RESET SDATA CS SCLK RST VCA_ CS DNC DNC ADS_PD G CW4 AVDD2 VREFL AVSS2 AVSS2 AVSS2 VCM AVDD2 CW5 F CW3 VB6 VREFH AVSS2 AVSS2 AVSS2 VB5 VB1 CW6 E CW2 AVDD_5V VB4 AVSS2 AVSS2 AVSS2 VB3 AVDD_5V CW7 D CW1 VB2 AVSS2 AVSS2 DVDD AVSS2 AVSS2 VCNTL CW8 C CW0 AVDD2 AVSS2 AVSS2 DVDD AVSS2 AVSS2 AVDD2 CW9 B VBL5 VBL6 VBL7 VBL8 DNC VBL4 VBL3 VBL2 VBL1 A IN5 IN6 Legend: AVDD1 +3.3V;□Analog AVDD2 +3.3V;□Analog +3.3V;□Analog +1.8V;□Digital +5V;□Analog DVDD LVDD AVDD_5V Analog□Ground Analog□Ground Digital□Ground AVSS1 AVSS2 LVSS IN7 IN8 VCA_PD IN4 IN3 IN2 IN1 AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 ZCF PACKAGE 135-BGA CONFIGURATION MAP (TOP VIEW) Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com Table1. TERMINAL FUNCTIONS PIN NO. PIN NAME FUNCTION DESCRIPTION H7 CS Input Chipselectforserialinterface;activelow H1 ADS_PD Input Power-down pinforADS; activehigh.See thePower-Down Modes sectionformore information. H9 ADS_ RESET Input RESET inputforADS; activelow H6 SCLK Input Serialclockinputforserialinterface H8 SDATA Input Serialdatainputforserialinterface J2,L2,K7,J7, AVDD1 POWER 3.3VanalogsupplyforADSK3,L8,K5,K6 L3,M3, L4,M4, L5,M5, L6,M6, AVSS1 GND AnaloggroundforADS L7,M7, J1 P5,N6, N7 LVDD POWER 1.8VdigitalsupplyforADS N3, N4, N5, R5 LVSS GND DigitalgroundforADS C5, D5 DVDD POWER 3.3VdigitalsupplyfortheVCA; connecttothe3.3Vanalogsupply(AVDD2). C2, C8, G2, G8 AVDD2 POWER 3.3VanalogsupplyforVCA E2,E8 AVDD_5V POWER 5V supplyforVCA C3, D3, C4, D4, E4,F4,G4, E5, F5,G5, C6, D6, AVSS2 GND AnaloggroundforVCA E6,F6,G6, C7, D7, J4,J5,J6 K1 CLKM Input NegativeclockinputforADS (connecttoGround insingle-endedclockmode) L1 CLKP Input PositiveclockinputforADS K8 CM Input/Output 1.5Vcommon-mode I/OforADS. Becomes inputpininone oftheexternalreferencemodes. C9 CW0 Output CW output0 D9 CW1 Output CW output1 E9 CW2 Output CW output2 F9 CW3 Output CW output3 G9 CW4 Output CW output4 G1 CW5 Output CW output5 F1 CW6 Output CW output6 E1 CW7 Output CW output7 D1 CW8 Output CW output8 C1 CW9 Output CW output9 L9 EN_SM Input EnablesaccesstotheVCA register.Activehigh.Connectpermanentlyto3.3V(AVDD1). N8 FCLKM Output LVDS frameclock(negativeoutput) N9 FCLKP Output LVDS frameclock(positiveoutput) A1 IN1 Input LNA inputChannel1 A2 IN2 Input LNA inputChannel2 A3 IN3 Input LNA inputChannel3 A4 IN4 Input LNA inputChannel4 A9 IN5 Input LNA inputChannel5 A8 IN6 Input LNA inputChannel6 A7 IN7 Input LNA inputChannel7 A6 IN8 Input LNA inputChannel8 J3 INT/EXT Input Internal/externalreferencemode selectforADS; internal= high(internalpull-upresistor) K9 ISET Input CurrentbiaspinforADS. Requires56kΩ toground. N2 LCLKM Output LVDS bitclock(6x);negativeoutput N1 LCLKP Output LVDS bitclock(6x);positiveoutput R4 OUT1M Output LVDS dataoutput(negative),Channel1 P4 OUT1P Output LVDS dataoutput(positive),Channel1 R3 OUT2M Output LVDS dataoutput(negative),Channel2 P3 OUT2P Output LVDS dataoutput(positive),Channel2 R2 OUT3M Output LVDS dataoutput(negative),Channel3

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 Table1. TERMINAL FUNCTIONS (continued) PIN NO. PIN NAME FUNCTION DESCRIPTION P2 OUT3P Output LVDS dataoutput(positive),Channel3 R1 OUT4M Output LVDS dataoutput(negative),Channel4 P1 OUT4P Output LVDS dataoutput(positive),Channel4 R6 OUT5M Output LVDS dataoutput(negative),Channel5 P6 OUT5P Output LVDS dataoutput(positive),Channel5 R7 OUT6M Output LVDS dataoutput(negative),Channel6 P7 OUT6P Output LVDS dataoutput(positive),Channel6 R8 OUT7M Output LVDS dataoutput(negative),Channel7 P8 OUT7P Output LVDS dataoutput(positive),Channel7 R9 OUT8M Output LVDS dataoutput(negative),Channel8 P9 OUT8P Output LVDS dataoutput(positive),Channel8 J9 REFB Input/Output 0.5VNegativereferenceofADS. Decouplingtoground.Becomes inputinexternalrefmode. J8 REFT Input/Output 2.5VPositivereferenceofADS. Decouplingtoground.Becomes inputinexternalrefmode. H5 RST Input RESET inputforVCA. ConnecttotheVCA_ CS pin(H4). H4 VCA_ CS Output ConnecttoRST –pin(H5) F2 VB1 Output Internalbiasvoltage.Bypass togroundwith2.2mF. D8 VB2 Output Internalbiasvoltage.Bypass togroundwith0.1mF. E3 VB3 Output Internalbiasvoltage.Bypass togroundwith0.1mF. E7 VB4 Output Internalbiasvoltage.Bypass togroundwith0.1mF F3 VB5 Output Internalbiasvoltage.Bypass togroundwith0.1mF. F8 VB6 Output Internalbiasvoltage.Bypass togroundwith0.1mF. B1 VBL1 Input ComplementaryLNA inputChannel1;bypasstogroundwith0.1mF. B2 VBL2 Input ComplementaryLNA inputChannel2;bypasstogroundwith0.1mF. B3 VBL3 Input ComplementaryLNA inputChannel3;bypasstogroundwith0.1mF. B4 VBL4 Input ComplementaryLNA inputChannel4;bypasstogroundwith0.1mF. B9 VBL5 Input ComplementaryLNA inputChannel5;bypasstogroundwith0.1mF. B8 VBL6 Input ComplementaryLNA inputChannel6;bypasstogroundwith0.1mF. B7 VBL7 Input ComplementaryLNA inputChannel7;bypasstogroundwith0.1mF. B6 VBL8 Input ComplementaryLNA inputChannel8;bypasstogroundwith0.1mF. A5 VCA_PD Input Power-down pinforVCA; low= normalmode, high= power-down mode. G3 VCM Output VCA referencevoltage.Bypass togroundwith0.1mF. D2 VCNTL Input VCA controlvoltageinput F7 VREFH Output Clamp referencevoltage(2.7V).Bypass togroundwith0.1mF. G7 VREFL Output Clamp referencevoltage(2.0V).Bypass togroundwith0.1mF. B5,H2, H3, K2, K4,M1, M2, DNC Do notconnect M8, M9 Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):AFE5805

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Sample n Sample n□+□12 tPROP t (A)D 12□clocks□latency ADC Input (1) Clock Input 6X□FCLK LCLKM LCLKP 1X□FCLK FCLKM FCLKP SERIAL DATA OUTP OUTM tSAMPLE Sample n□+□13 tH1 tSU1 tH2 tSU2 LCLKM LCLKP OUTM OUTP t =□min(t ,□t ) t =□min(t ,□t ) SU SU1 SU2 H H1 H2 AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com LVDS TIMING DIAGRAM (1)ReferencedtoADC Input(internalnode)forillustrationpurposesonly. DEFINITION OF SETUP AND HOLD TIMES TIMING CHARACTERISTICS (1) AFE5805 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tD(A) ADC aperturedelay 1.5 4.5 ns AperturedelayvariationChannel-to-channelwithinthesame device(3s) ±20 ps tJ Aperturejitter 400 fS,rms Time tovaliddataaftercoming outof 50 msCOMPLETE POWER-DOWN mode Time tovaliddataaftercoming outofPARTIAL tWAKE Wake-up time POWER-DOWN mode (withclockcontinuingto 2 ms runduringpower-down) Time tovaliddataafterstoppingand restarting 40 mstheinputclock ClockData latency 12 cycles (1) Timingparametersareensuredby designand characterization;notproductiontested.

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 LVDS OUTPUT TIMING CHARACTERISTICS (1)(2) Typicalvaluesareat+25°C, minimum and maximum valuesoverspecifiedtemperaturerangeofTMIN = 0°C toTMAX = +70°C, sampling frequency= as specified,C LOAD = 5pF (3),IOUT = 3.5mA,R LOAD = 100Ω(4),and no internaltermination,unlessotherwisenoted. AFE5805 40MSPS 50MSPS PARAMETER TEST CONDITIONS (5) MIN TYP MAX MIN TYP MAX UNIT tSU Data setuptime(6) Data valid(7)tozero-crossingofLCLKP 0.67 0.47 ns Zero-crossingofLCLKP todatabecomingtH Data holdtime(6) 0.85 0.65 nsinvalid(7) ADC inputclockrisingedge cross-overtotPROP Clockpropagationdelay 10 14 16.6 10 12.5 14.1 nsoutputclock(FCLKP) risingedge cross-over Dutycycleofdifferentialclock,LVDS bitclockdutycycle 45.5 50 53 45 50 53.5(LCLKP – LCLKM) Bitclockcycle-to-cyclejitter 250 250 ps,pp Frame clockcycle-to-cyclejitter 150 150 ps,pp (1) Allcharacteristicsareatthemaximum ratedspeed foreach speed grade. (2) Timingparametersareensuredby designand characterization;notproductiontested. (3) C LOAD istheeffectiveexternalsingle-endedloadcapacitancebetween each outputpinand ground. (4) IOUT referstotheLVDS buffercurrentsetting;R LOAD isthedifferentialloadresistancebetween theLVDS outputpair. (5) Measurements aredone witha transmissionlineof100Ω characteristicimpedance between thedeviceand theload. (6) Setupand holdtimespecificationstakeintoaccounttheeffectofjitteron theoutputdataand clock.These specificationsalsoassume thatdataand clockpathsareperfectlymatched withinthereceiver.Any mismatchinthesepathswithinthereceiverwouldappearas reducedtimingmargin. (7) Data validreferstoa logichighof+100mV and a logiclowof–100mV. LVDS OUTPUT TIMING CHARACTERISTICS (1)(2) Typicalvaluesareat+25°C, minimum and maximum valuesoverspecifiedtemperaturerangeofTMIN = 0°C toTMAX = +70°C, sampling frequency= as specified,C LOAD = 5pF (3),IOUT = 3.5mA,R LOAD = 100Ω(4),and no internaltermination,unlessotherwisenoted. AFE5805 30MSPS 20MSPS 10MSPS PARAMETER TEST CONDITIONS (5) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT Data valid(7)tozero-crossingoftSU Data setuptime(6) 0.8 1.5 3.7 nsLCLKP Zero-crossingofLCLKP todatatH Data holdtime(6) 1.2 1.9 3.9 nsbecoming invalid(7) ADC inputclockrisingedge risingedge cross-over Dutycycleofdifferentialclock,LVDS bitclockdutycycle 46.5 50 52 48 50 51 49 50 51(LCLKP – LCLKM) Bitclockcycle-to-cycle 250 250 750 ps,ppjitter Frame clockcycle-to-cycle 150 150 500 ps,ppjitter (1) Allcharacteristicsareatthespeeds otherthanthemaximum ratedspeed foreach speed grade. (2) Timingparametersareensuredby designand characterization;notproductiontested. (3) C LOAD istheeffectiveexternalsingle-endedloadcapacitancebetween each outputpinand ground. (4) IOUT referstotheLVDS buffercurrentsetting;R LOAD isthedifferentialloadresistancebetween theLVDS outputpair. (5) Measurements aredone witha transmissionlineof100Ω characteristicimpedance between thedeviceand theload. (6) Setupand holdtimespecificationstakeintoaccounttheeffectofjitteron theoutputdataand clock.These specificationsalsoassume thatdataand clockpathsareperfectlymatched withinthereceiver.Any mismatchinthesepathswithinthereceiverwouldappearas reducedtimingmargin. (7) Data validreferstoa logichighof+100mV and a logiclowof–100mV. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):AFE5805

V (V) CNTL 0 1.2 Gain□(dB) /c45 40/c176 C+50 C/c176 +85 C/c176 +25 C/c176 /c454 /c4510 0.0 0.1 1.2 Gain□(dB) V (V)CNTL 30dB 25dB 20dB 27dB 3000 2500 2000 1500 1000 500 Channel Gain□(dB) Channel-to-Channel 3000 2500 2000 1500 1000 500 Channel Gain□(dB) Channel-to-Channel AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith0.1mF, VCNTL = 1.0V,fIN = 5MHz, clamp disabled,LPF = 15MHz, clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,and LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. GAIN vs VCNTL GAIN vs VCNTL vs TEMPERATURE Figure1. Figure2. GAIN MATCH AT VCNTL = 0.1V GAIN MATCH AT VCNTL = 0.6V Figure3. Figure4.

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20722024 2032 2048 20562060 2068206420522044204020362028 3500 3000 2500 2000 1500 1000 500 Channel Gain□(dB) Channel-to-Channel V (V) CNTL 0 1.2 SNR□and□SINAD□(dBFS) SNR SINAD Input□= 45dBm Frequency□=□5MHz /c45 PGA□=□30dB PGA□=□20dB 1.2 1.0 0.8 0.6 0.4 0.2 Gain□Setting□(PGA) 20dB Noise□(nV/ ) /c214Hz 25dB 30dB 27dB R =□0 V =□1.2V /c87S CNTL 2MHz5MHz10MHz2MHz2MHz 2MHz 10MHz10MHz 10MHz 5MHz5MHz 5MHz 130 120 110 100 V (V) CNTL 0 1.2 Noise□(nV/ ) /c214Hz Frequency□=□2MHz PGA□=□30dB PGA□=□20dB 130 120 110 100 V (V) CNTL 0 1.2 Noise□(nV/ ) /c214Hz Frequency□=□5MHz PGA□=□30dB PGA□=□20dB AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith0.1mF, VCNTL = 1.0V,fIN = 5MHz, clamp disabled,LPF = 15MHz, clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,and LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. GAIN MATCH AT VCNTL = 1.0V OUTPUT OFFSET Figure5. Figure6. SNR AND SINAD vs VCNTL INPUT-REFERRED NOISE vs PGA Figure7. Figure8. INPUT-REFERRED NOISE vs VCNTL INPUT-REFERRED NOISE vs VCNTL Figure9. Figure10. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):AFE5805

V (V) CNTL 0 1.2 Noise□(nV/ ) /c214Hz Frequency□=□2MHz PGA□=□30dB PGA□=□20dB 300 250 200 150 100 V (V) CNTL 0 1.2 Noise□(nV/ ) /c214Hz Frequency□=□5MHz PGA□=□30dB PGA□=□20dB 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 Frequency□(MHz) 1 10 Noise□(nV/ ) /c214Hz R =□1k /c87S R =□400 /c87S R =□200 /c87S R =□50 /c87S V =□1.2VCNTL 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Frequency□(MHz) 1 10 Noise□(nV/ ) /c214Hz R =□1k /c87S R =□400 /c87S R =□200 /c87S R =□50 /c87SV =□1.2VCNTL 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 Current□Noise□(pA/ ) /c214Hz Frequency□(MHz) R =S 400/c87 R =S 1k/c87 R =□200 /c87S V =□1.2VCNTL 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Frequency□(MHz) 1 10 Noise□Figure□(dB) R =□1k /c87S R =□400 /c87S R =□200 /c87S R =□50 /c87S PGA□=□30dB V =□1.2VCNTL AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith0.1mF, VCNTL = 1.0V,fIN = 5MHz, clamp disabled,LPF = 15MHz, clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,and LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. OUTPUT-REFERRED NOISE vs VCNTL OUTPUT-REFERRED NOISE vs VCNTL Figure11. Figure12. OUTPUT-REFERRED NOISE vs FREQUENCY vs R S INPUT-REFERRED NOISE vs FREQUENCY vs R S Figure13. Figure14. CURRENT NOISE vs FREQUENCY OVER R SOURCE NOISE FIGURE vs FREQUENCY vs R S Figure15. Figure16.

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1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 Frequency□(Hz) 100k 20M Noise□(nV/ ) /c214Hz 10M1M 4000 3500 3000 2500 2000 1500 1000 500 Channel Transconductance□(mA/V) /c4550 /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Distortion□(dBFS) PGA□=□20dB Output□= 6dBFS/c45 2MHz 5MHz 10MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Distortion□(dBFS) PGA□=□20dB Output□= 6dBFS/c45 2MHz 5MHz 10MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Distortion□(dBFS) PGA□=□30dB Output□= 1dBFS/c45 2MHz 5MHz 10MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Distortion□(dBFS) PGA□=□30dB Output□= 1dBFS/c45 2MHz 5MHz 10MHz AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith0.1mF, VCNTL = 1.0V,fIN = 5MHz, clamp disabled,LPF = 15MHz, clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,and LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. CW INPUT-REFERRED NOISE vs FREQUENCY CW ACCURACY Figure17. Figure18. 2ND HARMONIC vs VCNTL vs FREQUENCY 3RD HARMONIC vs VCNTL vs FREQUENCY Figure19. Figure20. 2ND HARMONIC vs VCNTL vs FREQUENCY 3RD HARMONIC vs VCNTL vs FREQUENCY Figure21. Figure22. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):AFE5805

/c45 /c45 /c45 /c45 /c45 /c45 Output□Level□(dBFS) /c4540 0 Distortion□(dBc) /c4530 /c4520 /c4510 PGA□=□30dB Frequency□=□5MHz V =□0.7VCNTL V =□1VCNTL V =□0.4VCNTL /c45 /c45 /c45 /c45 /c45 /c45 Output□Level□(dBFS) /c4540 0 Distortion□(dBc) /c4530 /c4520 /c4510 PGA□=□30dB Frequency□=□5MHz V =□1VCNTL V =□0.7VCNTL V =□0.4VCNTL /c4550 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Crosstalk□(dBc) Adjacent□Channels PGA□=□20dB 1dBFS/c45 10MHz 5MHz 2MHz /c4550 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Crosstalk□(dBc) Adjacent□Channels PGA□=□25dB 1dBFS/c45 10MHz 5MHz 2MHz /c4550 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Crosstalk□(dBc) Adjacent□Channels PGA□=□27dB 1dBFS/c45 10MHz 5MHz 2MHz /c4550 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 V (V) CNTL 0.6 1.2 Crosstalk□(dBc) Adjacent□Channels PGA□=□30dB 1dBFS/c45 10MHz 5MHz 2MHz AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith0.1mF, VCNTL = 1.0V,fIN = 5MHz, clamp disabled,LPF = 15MHz, clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,and LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. 2ND HARMONIC vs VCNTL vs OUTPUT LEVEL 3RD HARMONIC vs VCNTL vs OUTPUT LEVEL Figure23. Figure24. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure25. Figure26. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure27. Figure28.

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/c452 /c454 /c456 /c458 /c4510 /c4512 /c4514 /c4516 /c4518 /c4520 0 35 Magnitude□(dB) Frequency□(MHz) 5 10 15 20 25 30 /c452 /c454 /c456 /c458 /c4510 /c4512 /c4514 /c4516 /c4518 /c4520 0 35 Magnitude□(dB) Frequency□(MHz) 5 10 15 20 25 30 /c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 1.80 2.20 Magnitude□(dBFS) 1.951.901.85 2.00 PGA□=□30dB V =□1.0V IMD3□=□54.2dB CNTL 2.05 2.10 2.15 /c4532 /c456 /c4586.2 /c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 4.80 5.20 Magnitude□(dBFS) 4.954.904.85 5.00 PGA□=□30dB V =□1.0V IMD3□=□58.5dB CNTL 5.05 5.10 5.15 /c4532 /c456 /c4590.5 12k 10k 100M Magnitude□( ) /c87 100 /c45 100 Phase□( ) /c176 /c45 80 /c45 20 /c45 40 /c45 60 Frequency□(Hz) 100k 1M 10M Magnitude□(Z )IN Phase 1.0 0.5 /c45 /c45 0.5 1.0 Sample□Points 0 80 Output□( Full-Scale) /c177 302010 40 V =□1V (+12dBFS) PGA□=□20dB V =□0.54V IN PP CNTL 50 60 70 90 100 110 120 AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith0.1mF, VCNTL = 1.0V,fIN = 5MHz, clamp disabled,LPF = 15MHz, clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,and LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. 10MHz LOW-PASS FILTER RESPONSE 15MHz LOW-PASS FILTER RESPONSE Figure29. Figure30. INTERMODULATION DISTORTION INTERMODULATION DISTORTION (1.99MHz and 2.01MHz) (4.99MHz and 5.01MHz) Figure31. Figure32. INPUT IMPEDANCE vs FREQUENCY LNA OVERLOAD Figure33. Figure34. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):AFE5805

1.0 0.5 /c45 /c45 0.5 1.0 Sample□Points 0 80 Output□( Full-Scale) /c177 302010 40 V =□0.5V (+6dBFS) PGA□=□30dB V =□1.0V IN PP CNTL 50 60 70 90 100 110 120 1.0 0.5 0.5 1.0 /c45 /c45 Time□( s)/c109 0 15 Output□( Full-Scale) /c177 5 10 PGA□=□30dB V =□1.0V V =□250mV ,□0.25mV CNTL IN PP PP 1.0 0.5 /c45 /c45 0.5 1.0 Time□( s)/c109 0 10 Output□( Full-Scale) /c177 PGA□=□30dB V =□0V□to□1.2VCNTL VCNTL 1.0 0.5 /c45 /c45 0.5 1.0 Time□( s)/c109 0 20 Output□( Full-Scale) /c177 PGA□=□30dB V =□0.4VCNTL 305 15 25 PD 170 150 130 110 Clock□Frequency□(MSPS) 5 55352515 45 ILVDD IAVDD1 Zero□Input□on□All□Channels I ,□I (mA)AVDD1 LVDD 995 990 985 980 975 970 965 960 955 950 945 T emperature□( C)/c176 /c45 40 85 T otal□Power□(mW) 0 25 TGC□Mode 50 70 AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith0.1mF, VCNTL = 1.0V,fIN = 5MHz, clamp disabled,LPF = 15MHz, clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,and LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. FULL CHANNEL OVERLOAD OVERLOAD RECOVERY Figure35. Figure36. VCNTL RESPONSE TIME POWER-UP/POWER-DOWN RESPONSE TIME Figure37. Figure38. AVDD1 AND LVDD POWER-SUPPLY CURRENTS vs CLOCK FREQUENCY POWER DISSIPATION vs TEMPERATURE Figure39. Figure40.

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(connect□externally) VCA_CS RST [H4] [H9] VCA_SCLK VCA_SDATA ADS_CS ADS_SCLK ADS_SDATA ADS_RESET ADS_RESET [H8]SDATA [H7]CS [H6]SCLK [L9] EN_SM Tie□to: +3.3V□(AVDD1) [H5] AFE5805 SPI□Interface□and□Register AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 SERIAL INTERFACE The AFE5805 has a setofinternalregistersthatcan be accessedthroughtheserialinterfaceformedby pinsCS (chipselect,activelow),SCLK (serialinterfaceclock),and SDATA (serialinterfacedata).When CS islow,the followingactionsoccur:

Serialshiftofbitsintothedeviceisenabled
SDATA (serialdata)islatchedateveryrisingedge ofSCLK
SDATA isloadedintotheregisteratevery24thSCLK risingedge Iftheword lengthexceeds a multipleof24 bits,theexcessbitsareignored.Data can be loadedinmultiplesof 24-bitwords withina singleactiveCS pulse.The firsteightbitsformtheregisteraddressand theremaining16 bitsformtheregisterdata.The interfacecan work withSCLK frequenciesfrom20MHz down toverylow speeds (afew hertz)and alsowitha non-50% SCLK dutycycle. RegisterInitialization Afterpower-up,the internalregistersmust be initializedto the respectivedefaultvalues.Initializationcan be done inone oftwo ways: 1. Througha hardwarereset,by applyinga low-goingpulseon theADS_ RESET pin;or 2. Through a softwarereset;usingthe serialinterface,setthe S_RST bithigh.Settingthisbitinitializesthe internalregistersto the respectivedefaultvalues and then self-resetsthe bitlow. In thiscase, the ADS_ RESET pinstayshigh(inactive). Itisrecommended toprogram thefollowingregistersaftertheinitializationstage.The power-supplyrippleand clockjittereffectscan be minimized. ADDRESS DATA 01 0010 D1 0140 DA 0001 E1 0020 02 0080 01 0000 SerialPortInterface(SPI)Information Figure41. TypicalConnection Diagram fortheSPI ControlLines Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):AFE5805

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK SDATA Data□latched□on□rising□edge□of□SCLK Start□Sequence End□Sequence D0 D39VCA_SDA T A VCA_SCLK AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com SERIAL INTERFACE TIMING AFE5805 PARAMETER DESCRIPTION MIN TYP MAX UNIT t1 SCLK period 50 ns t2 SCLK hightime 20 ns t3 SCLK lowtime 20 ns t4 Data setuptime 5 ns t5 Data holdtime 5 ns t6 CS falltoSCLK rise 8 ns t7 Time between lastSCLK risingedge toCS risingedge 8 ns Internally-GeneratedVCA ControlSignals VCA_SCLK and VCA_SDATA signalsaregeneratedif:

Registerswithaddress16,17,or18 (Hex)arewritteninto,and
EN_SM pinisHIGH

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 SERIAL REGISTER MAP Table2.SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1)(2)(3)(4) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT 00 X S_RST Self-clearingsoftwareRESET. Inactive RES_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VCA VCA_SDATA D5 = 116 X X X X X X X X X X X X X X 1 1 See Table4 information<0:15> (TGC mode) VCA_SDATA17 X X X X X X X X X X X X X X X X See Table4 information<16:31> VCA_DATA18 X X X X X X X X See Table4 information<32:39> Channel-specificADCX X X X PDN_CH <1:4> Inactivepower-down mode. Channel-specificADCx X X X X PDN_CH <8:5> Inactivepower-down mode. Partialpower-down mode (fast0F X PDN_PARTIAL Inactiverecoveryfrompower-down). Registermode forcomplete0 X PDN_COMPLETE Inactivepower-down (slowerrecovery). ConfiguresthePD pinfor CompleteX 0 PDN_PIN_CFG partialpower-down mode. power-down LVDS currentdrive X X X ILVDS_LCLK <2:0> programmabilityforLCLKM 3.5mA drive and LCLKP pins. LVDS currentdriveILVDS_FRAME11 X X X programmabilityforFCLKM 3.5mA drive<2:0> and FCLKP pins. LVDS currentdrive X X X ILVDS_DAT <2:0> programmabilityforOUTM and 3.5mA drive OUTP pins. Enablesinternaltermination TerminationX EN_LVDS_TERM forLVDS buffers. disabled Programmable terminationfor Termination1 X X X TERM_LCLK <2:0> LCLKM and LCLKP buffers. disabled TERM_FRAME Programmable terminationfor Termination1 X X X <2:0> FCLKM and FCLKP buffers. disabled Programmable terminationfor Termination1 X X X TERM_DAT <2:0> OUTM and OUTP buffers. disabled Channel-specific, X X X X LFNS_CH <1:4> low-frequencynoise Inactive suppressionmode enable. Channel-specific, x X X X X LFNS_CH <8:5> low-frequencynoise Inactive suppressionmode enable. Enablesa repeatingfull-scaleX 0 0 EN_RAMP Inactiveramp patternon theoutputs. Enablesthemode whereintheDUALCUSTOM_0 X 0 outputtogglesbetween two InactivePAT definedcodes. Enablesthemode whereintheSINGLE_CUSTOM0 0 X outputisa constantspecified Inactive25 _PAT code. 2MSBs fora singlecustom BITS_CUSTOM1 pattern(andforthefirstcodeX X Inactive<11:10> ofthedualcustom pattern). <11> istheMSB. BITS_CUSTOM2 2MSBs forthesecond code ofX X Inactive<11:10> thedualcustom pattern. 10 lowerbitsforthesingle BITS_CUSTOM1 custom pattern(andforthe26 X X X X X X X X X X Inactive<9:0> firstcode ofthedualcustom pattern).<0> istheLSB. 10 lowerbitsforthesecondBITS_CUSTOM227 X X X X X X X X X X code ofthedualcustom Inactive<9:0> pattern. (1) The unused bitsineach register(identifiedas blanktablecells)must be programmed as '0'. (2) X = Registerbitreferencedby thecorrespondingname and description(defaultsettingislistedabove). (3) Bitsmarked as '0'shouldbe forcedto0,and bitsmarked as '1'shouldbe forcedto1 when theparticularregisterisprogrammed. (4) Multiplefunctionsina registershouldbe programmed ina singlewriteoperation. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com Table2.SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1)(2)(3)(4) (continued) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT X X X X GAIN_CH4 <3:0> Programmable gainchannel4. 0dB gain X X X X GAIN_CH3 <3:0> Programmable gainchannel3. 0dB gain X X X X GAIN_CH2 <3:0> Programmable gainchannel2. 0dB gain X X X X GAIN_CH1 <3:0> Programmable gainchannel1. 0dB gain X X X X GAIN_CH5 <3:0> Programmable gainchannel5. 0dB gain X X X X GAIN_CH6 <3:0> Programmable gainchannel6. 0dB gain X X X X GAIN_CH7 <3:0> Programmable gainchannel7. 0dB gain X X X X GAIN_CH8 <3:0> Programmable gainchannel8. 0dB gain Single-1 1 X DIFF_CLK Differentialclockmode. ended clock Enablestheduty-cycle1 1 X EN_DCC Disabledcorrectioncircuit. External42 Drivestheexternalreference reference1 1 X EXT_REF_VCM mode throughtheVCM pin. drivesREFT and REFB Controlsthephase ofLCLK1 1 X X PHASE_DDR <1:0> 90 degreesoutputrelativetodata. 0 X PAT_DESKEW Enablesdeskew patternmode. Inactive X 0 PAT_SYNC Enablessyncpatternmode. Inactive Binarytwo's complement Straight1 1 X BTC_MODE formatforADC output. offsetbinary SerializedADC outputcomes LSB-first1 1 X MSB_FIRST outMSB-first. output EnablesSDR outputmode DDR output1 1 X EN_SDR (LCLK becomes a 12x input46 modeclock). ControlswhethertheLCLK Risingedgerisingorfallingedge comes in ofLCLK in1 1 1 1 FALL_SDR themiddleofthedatawindow middleofwhen operatinginSDR output datawindowmode. SUMMARY OF FEATURES POWER IMPACT (RelativetoDefault) FEATURES DEFAULT SELECTION AT fS = 50MSPS ANALOG FEATURES Internalorexternalreference N/A Pin Internalreferencemode takesapproximately20mW more power on AVDD1(drivenon theREFT and REFB pins) Externalreferencedrivenon theCM pin Off Register42 Approximately8mW lesspower on AVDD1 Dutycyclecorrectioncircuit Off Register42 Approximately7mW more power on AVDD1 WithzeroinputtotheADC, low-frequencynoisesuppressioncausesdigitalswitchingLow-frequencynoisesuppression Off Register14 atfS/2,therebyincreasingLVDD power by approximately5.5mW/channel Single-endedordifferentialclock Single-ended Register42 Differentialclockmode takesapproximately7mW more power on AVDD1 Power-down mode Off Pinand register0F RefertothePower-Down Modes sectionintheElectricalCharacteristicstable DIGITAL FEATURES Programmable digitalgain(0dB to12dB) 0dB Registers2A and 2B No difference StraightoffsetorBTC output Straightoffset Register46 No difference LVDS OUTPUT PHYSICAL LAYER LVDS internaltermination Off Register12 Approximately7mW more power on AVDD1 LVDS currentprogrammability 3.5mA Register11 As perLVDS clockand databuffercurrentsetting LVDS OUTPUT TIMING LSB- orMSB-firstoutput LSB-first Register46 No difference DDR orSDR output DDR Register46 SDR mode takesapproximately2mW more power on LVDD (atfS = 30MSPS) LCLK phase relativetodataoutput RefertoFigure43 Register42 No difference

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 DESCRIPTION OF SERIAL REGISTERS SOFTWARE RESET ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

00 X S_RST

Softwareresetisappliedwhen theRST bitissetto'1';settingthisbitresetsallinternalregistersand self-clears to'0'. Table3.VCA RegisterInformation ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RES_V03 0 0 0 0 0 0 0 0 0 0 0 0 0 0CA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA 1(1) 1(1)

16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA17 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 VCA VCA VCA VCA VCA VCA VCA VCA18 D39 D38 D37 D36 D35 D34 D33 D32 (1) BitsD0 and D1 ofregister16 areforcedto'1'. space

VCA_SCLK and VCA_SDATA become activeonlywhen one oftheregisters16,17,or 18 oftheAFE5805 arewritteninto.
The contentsofallthreeregisters(total40 bits)are writtenon VCA_SDATA even ifonlyone oftheabove registersiswritteninto.Thisconditionisonlyvalidifthecontentoftheregisterhas changed because ofthe most recentwrite.Writingcontentsthatare the same as existingcontentsdoes not triggeractivityon VCA_SDATA.
For example,ifregister17 iswrittenintoaftera RESET isapplied,thenthecontentsofregister17 as wellas thedefaultvaluesofthebitsinregisters16 and 18 arewrittenintoVCA_SDATA.
Ifregister16 isthenwrittento,thenthenew contentsofregister16,thepreviouslywrittencontentsofregister 17, and the defaultcontentsof register18 are writtenintoVCA_SDATA. Note thatregardlessof what is writtenintoD0 and D1 ofregister16,therespectiveoutputson VCA_SDATA arealways‘1’.
Alternatively,allthreeregisters(16,17 and 18) can alsobe writtenwithinone writecycleof the serial interface.Inthatcase,therewouldbe 48 consecutiveSCLK edges withinthesame CS activewindow.
VCA_SCLK isgeneratedusingan oscillator(runningat approximately6MHz) insidethe AFE5805, but the oscillatorisgatedso thatitisactiveonlyduringthewriteoperationofthe40 VCA bits.
To ensure the SDATA transferreliability,a ≥ 1ms gap isrecommended between programming two VCA registersconsecutively. VCA Reset
VCA_ CS shouldbe permanentlyconnectedtotheRST-input.
When VCA_ CS goes high(eitherbecause ofan activelow pulseon ADS_ RESET formore than10ns oras a resultorsettingbitRES_VCA), thefollowingfunctionsareperformedinsidetheAFE5805: – BitsD0 and D1 ofregister16 areforcedto‘1’ – Allotherbitsinregisters16,17 and 18 areRESET totherespectivedefaultvalues(‘0’forallbitsexcept D5 ofregister16 whichissettoa defaultof‘1’). – No activityon signalsVCA_SCLK and VCA_SDATA.
IfbitRES_VCA has been setto‘1’,thenthestatemachine isintheRESET stateuntilRES_VCA issetto‘0’. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com INPUT REGISTER BIT MAPS Table4.VCA RegisterMap BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 D0:D7 D8:D11 D12:D15 D16:D19 D20:D23 D24:D27 D28:D31 D32:D35 D36:D39 Control CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 Table5.Byte 1— ControlByte RegisterMap BIT NUMBER BIT NAME DESCRIPTION D0 (LSB) 1 Startbit;thisbitispermanentlysethigh= 1 D1 WR Writebit;thisbitispermanentlysethigh= 1 D2 PWR 1= Power-down mode enabled. D3 BW Low-passfilterbandwidthsetting(seeTable10) D4 CL Clamp levelsetting(seeTable10) D5 Mode 1 = TGC mode (default),0 = CW Dopplermode D6 PG0 LSB ofPGA gaincontrol(seeTable11) D7 (MSB) PG1 MSB ofPGA gaincontrol Table6.Byte 2— FirstData Byte BIT NUMBER BIT NAME DESCRIPTION D8 (LSB) DB1:1 Channel1,LSB ofmatrixcontrol D9 DB1:2 Channel1,matrixcontrol D10 DB1:3 Channel1,matrixcontrol D11 DB1:4 Channel1,MSB ofmatrixcontrol D12 DB2:1 Channel2,LSB ofmatrixcontrol D13 DB2:2 Channel2,matrixcontrol D14 DB2:3 Channel2,matrixcontrol D15 (MSB) DB2:4 Channel2,MSB ofmatrixcontrol Table7.Byte 3— Second Data Byte BIT NUMBER BIT NAME DESCRIPTION D16 (LSB) DB3:1 Channel3,LSB ofmatrixcontrol D17 DB3:2 Channel3,matrixcontrol D18 DB3:3 Channel3,matrixcontrol D19 DB3:4 Channel3,MSB ofmatrixcontrol D20 DB4:1 Channel4,LSB ofmatrixcontrol D21 DB4:2 Channel4,matrixcontrol D22 DB4:3 Channel4,matrixcontrol D23 (MSB) DB4:4 Channel4,MSB ofmatrixcontrol

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 Table8.Byte 4— ThirdData Byte BIT NUMBER BIT NAME DESCRIPTION D24 (LSB) DB5:1 Channel5,LSB ofmatrixcontrol D25 DB5:2 Channel5,matrixcontrol D26 DB5:3 Channel5,matrixcontrol D27 DB5:4 Channel5,MSB ofmatrixcontrol D28 DB6:1 Channel6,LSB ofmatrixcontrol D29 DB6:2 Channel6,matrixcontrol D30 DB6:3 Channel6,matrixcontrol D31 (MSB) DB6:4 Channel6,MSB ofmatrixcontrol Table9.Byte 5— FourthData Byte BIT NUMBER BIT NAME DESCRIPTION D32 (LSB) DB7:1 Channel7,LSB ofmatrixcontrol D33 DB7:2 Channel7,matrixcontrol D34 DB7:3 Channel7,matrixcontrol D35 DB7:4 Channel7,MSB ofmatrixcontrol D36 DB8:1 Channel8,LSB ofmatrixcontrol D37 DB8:2 Channel8,matrixcontrol D38 DB8:3 Channel8,matrixcontrol D39 (MSB) DB8:4 Channel8,MSB ofmatrixcontrol Table10.Clamp Leveland LPF Bandwidth Setting FUNCTION BW D3 = 0 Bandwidthsetto15MHz (default) BW D3 = 1 Bandwidthsetto10MHz CL D4 = 0 Clamps theoutputsignalatapproximately–1.4dBbelowthefull-scaleof2VPP . CL D4 = 1 Clamp transparent(disabled) Table11.PGA Gain Setting PG1 (D7) PG0 (D6) FUNCTION 0 0 SetsPGA gainto20dB (default) 0 1 SetsPGA gainto25dB 1 0 SetsPGA gainto27dB 1 1 SetsPGA gainto30dB Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):AFE5805

Channel□1 Input V/I Converter VCA_SDATA CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 AVDD_5V VCA_SCLK Decode Logic (T o□Other□Channels) AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com Table12.CW Switch MatrixControlforEach Channel DBn:4 (MSB) DBn:3 DBn:2 DBn:1 (LSB) LNA INPUT CHANNEL n DIRECTED TO 0 0 0 0 OutputCW0 0 0 0 1 OutputCW1 0 0 1 0 OutputCW2 0 0 1 1 OutputCW3 0 1 0 0 OutputCW4 0 1 0 1 OutputCW5 0 1 1 0 OutputCW6 0 1 1 1 OutputCW7 1 0 0 0 OutputCW8 1 0 0 1 OutputCW9 1 0 1 0 ConnectedtoAVDD_5V 1 0 1 1 ConnectedtoAVDD_5V 1 1 0 0 ConnectedtoAVDD_5V 1 1 0 1 ConnectedtoAVDD_5V 1 1 1 0 ConnectedtoAVDD_5V 1 1 1 1 ConnectedtoAVDD_5V Figure42. Basic CW Cross-PointSwitch MatrixConfiguration

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 POWER-DOWN MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X PDN_CH <1:4> X X X X PDN_CH <8:5> 0F X PDN_PARTIAL

0 X PDN_COMPLETE

X 0 PDN_PIN_CFG Each oftheeightADC channelswithintheAFE5805 can be individuallypowered down. PDN_CH <N > controls thepower-down mode fortheADC channel<N >. In additionto channel-specificpower-down, the AFE5805 also has two globalpower-down modes: partial power-down mode and completepower-down mode. In additionto programming the device for eitherof these two power-down modes (througheitherthe PDN_PARTIAL or PDN_COMPLETE bits,respectively),the ADS_PD pinitselfcan be configuredas eithera partialpower-down pinora completepower-down pincontrol.Forexample,ifPDN_PIN_CFG = 0 (default),when theADS_PD pinishigh,thedeviceenterscompletepower-down mode. However,ifPDN_PIN_CFG = 1,when theADS_PD pinishigh,thedeviceenterspartialpower-down mode. The partialpower-down mode functionallowsthe AFE5805 to be rapidlyplacedina low-powerstate.In this mode, most amplifiersinthe signalpath are powered down, whilethe internalreferencesremain active.This configurationensuresthattheexternalbypass capacitorsretaintherespectivecharges,minimizingthewake-up responsetime.The wake-up responseistypicallylessthan50ms,providedthattheclockhas been runningforat least50ms beforenormaloperatingmode resumes.The power-down timeisinstantaneous(lessthan1.0ms). In partialpower-down mode, the parttypicallydissipatesonly233mW, representinga 76% power reduction compared to the normal operatingmode. Thisfunctioniscontrolledthroughthe ADS_PD and VCA_PD pins, whicharedesignedtointerfacewith3.3V low-voltagelogic.Ifseparatecontrolofthetwo PD pinsisnotdesired, then both can be tiedtogether.In thiscase,the ADS_PD pin shouldbe configuredto operateas a partial power-down mode pin[seefurtherinformation(PDN_PIN_CFG) above]. For normaloperationthePD pinsshouldbe tiedtoa logiclow (0);a high(1)placestheAFE5805 intopartial power-down mode. To achievethe lowestpower dissipationof only64mW, the AFE5805 can be placedincompletepower-down mode. Thismode iscontrolledthroughtheserialinterfaceby settingRegister16 (bitD2) and Register0F (bit D9:D10). In complete power-down mode, all circuits(includingreferences)withinthe AFE5805 are powered-down, and the bypass capacitorsthen discharge.Consequently,the wake-up time from complete power-down mode depends largelyon thetimeneeded torechargethebypass capacitors.Anotherfactorthat affectsthewake-up timeistheelapsedtimethattheAFE5805 spends inshutdownmode. LVDS DRIVE PROGRAMMABILITY ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X ILVDS_LCLK <2:0>

11 X X X ILVDS_FRAME <2:0>

X X X ILVDS_DAT <2:0> The LVDS drivestrengthofthebitclock(LCLKP or LCLKM) and theframe clock(FCLKP or FCLKM) can be individuallyprogrammed. The LVDS drivestrengthsof allthe data outputsOUTP and OUTM can also be programmed tothesame value. Allthreedrivestrengths(bitclock,frame clock,and data)are programmed usingsetsof threebits.Table 13 detailsan example ofhow thedrivestrengthofthebitclockisprogrammed (themethod issimilarfortheframe clockand datadrivestrengths). Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com Table13.BitClock DriveStrength(1) ILVDS_LCLK <2> ILVDS_LCLK <1> ILVDS_LCLK <0> LVDS DRIVE STRENGTH FOR LCLKP AND LCLKM 0 0 0 3.5mA (default) 0 0 1 2.5mA 0 1 0 1.5mA 0 1 1 0.5mA 1 0 0 7.5mA 1 0 1 6.5mA 1 1 0 5.5mA 1 1 1 4.5mA (1) Currentsettingslowerthan1.5mA arenotrecommended. LVDS INTERNAL TERMINATION PROGRAMMING ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X EN_LVDS_TERM

1 X X X TERM_LCLK <2:0>

1 X X X TERM_FRAME <2:0>

1 X X X TERM_DAT <2:0>

The LVDS buffershave high-impedancecurrentsources thatdrivethe outputs.When drivingtraceswith characteristicimpedances thatare notperfectlymatched withtheterminationimpedance on thereceiverside, theremay be reflectionsback totheLVDS outputpinsoftheAFE5805 thatcause degradedsignalintegrity.By enablingan internaltermination(betweenthe positiveand negativeoutputs)forthe LVDS buffers,the signal integritycan be significantlyimproved in such scenarios.To set the internalterminationmode, the EN_LVDS_TERM bitshouldbe setto'1'.Once thisbitisset,theinternalterminationvaluesforthebitclock, frame clock,and data bufferscan be independentlyprogrammed usingsetsof threebits.Table 14 shows an example ofhow theinternalterminationoftheLVDS bufferdrivingthebitclockisprogrammed (themethod is similarfortheframe clockand datadrivestrengths).These terminationvaluesare onlytypicalvaluesand can varyby severalpercentacrosstemperatureand fromdevicetodevice. Table14.BitClock InternalTermination INTERNAL TERMINATION BETWEEN TERM_LCLK <2> TERM_LCLK <1> TERM_LCLK <0> LCLKP AND LCLKM IN Ω 0 0 0 None 0 0 1 260 0 1 0 150 0 1 1 94 1 0 0 125 1 0 1 80 1 1 0 66 1 1 1 55

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 LOW-FREQUENCY NOISE SUPPRESSION MODE ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X LFNS_CH <1:4> X X X X LFNS_CH <8:5> The low-frequencynoisesuppressionmode isespeciallyusefulinapplicationswhere good noiseperformanceis desiredinthefrequencyband of0MHz to1MHz (arounddc).Settingthismode shiftsthelow-frequencynoiseof the AFE5805 to approximatelyfS/2,therebymoving the noise flooraround dc to a much lower value. LFNS_CH <8:1> enablesthismode individuallyforeach channel. LVDS TEST PATTERNS ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X 0 0 EN_RAMP

0 X 0 DUALCUSTOM_PAT

25 0 0 X SINGLE_CUSTOM_PAT X X BITS_CUSTOM1 <11:10> X X BITS_CUSTOM2 <11:10>

26 X X X X X X X X X X BITS_CUSTOM1 <9:0>

27 X X X X X X X X X X BITS_CUSTOM2 <9:0>

0 X PAT_DESKEW

X 0 PAT_SYNC The AFE5805 can outputa varietyoftestpatternson theLVDS outputs.These testpatternsreplacethenormal ADC dataoutput.SettingEN_RAMP to'1'causes allthechannelstooutputa repeatingfull-scaleramp pattern. The ramp incrementsfrom zero code to full-scalecode instepsof 1LSB everyclockcycle.Afterhittingthe full-scalecode,itreturnsback tozerocode and ramps again. The devicecan alsobe programmed tooutputa constantcode by settingSINGLE_CUSTOM_PAT to'1',and programmingthedesiredcode inBITS_CUSTOM1 <11:0>.Inthismode, BITS_CUSTOM <11:0> taketheplaceof the 12-bitADC data at the output,and are controlledby LSB-firstand MSB-firstmodes inthe same way as normalADC dataare. The devicemay alsobe made totogglebetween two consecutivecodes by programmingDUAL_CUSTOM_PAT to'1'.The two codes arerepresentedby thecontentsofBITS_CUSTOM1 <11:0> and BITS_CUSTOM2 <11:0>. Inadditiontocustom patterns,thedevicemay alsobe made tooutputtwo presetpatterns: 1. Deskew patten:Set usingPAT_DESKEW, thismode replacesthe 12-bitADC outputD <11:0> withthe 010101010101 word. 2. Sync pattern:SetusingPAT_SYNC, thenormalADC word isreplacedby a fixed111111000000 word. Note thatonlyone oftheabove patternscan be activeatany giveninstant. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com PROGRAMMABLE GAIN ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X GAIN_CH4 <3:0> X X X X GAIN_CH3 <3:0> X X X X GAIN_CH2 <3:0> X X X X GAIN_CH1 <3:0> X X X X GAIN_CH5 <3:0> X X X X GAIN_CH6 <3:0> X X X X GAIN_CH7 <3:0> X X X X GAIN_CH8 <3:0> The AFE5805, throughitsregisters,allowsfora digitalgain to be programmed foreach channel.This programmable gaincan be settoachievethefull-scaleoutputcode even witha loweranaloginputswing.The programmablegainnotonlyfillstheoutputcode rangeoftheADC, butalsoenhances theSNR ofthedeviceby usingquantizationinformationfrom some extrainternalbits.The programmable gainforeach channelcan be individuallysetusinga setoffourbits,indicatedas GAIN_CHN <3:0> forChannel N. The gainsettingiscoded in binaryfrom0dB to12dB,as shown inTable15. Table15.Gain SettingforChannel 1 GAIN_CH1 <3> GAIN_CH1 <2> GAIN_CH1 <1> GAIN_CH1 <0> CHANNEL 1 GAIN SETTING 0 0 0 0 0dB 0 0 0 1 1dB 0 0 1 0 2dB 0 0 1 1 3dB 0 1 0 0 4dB 0 1 0 1 5dB 0 1 1 0 6dB 0 1 1 1 7dB 1 0 0 0 8dB 1 0 0 1 9dB 1 0 1 0 10dB 1 0 1 1 11dB 1 1 0 0 12dB 1 1 0 1 Do notuse 1 1 1 0 Do notuse 1 1 1 1 Do notuse

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VREFT□=□1.5V□+ VCM 1.5V VREFB□=□1.5V /c45 VCM 1.5V AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 CLOCK, REFERENCE, AND DATA OUTPUT MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME 1 1 X DIFF_CLK 1 1 X EN_DCC 1 1 X EXT_REF_VCM 1 1 X X PHASE_DDR <1:0> 1 1 X BTC_MODE 1 1 X MSB_FIRST 1 1 X EN_SDR 1 1 1 1 FALL_SDR INPUT CLOCK The AFE5805 isconfiguredby defaulttooperatewitha single-endedinputclock;CLKP isdrivenby a CMOS clockand CLKM istiedto'0'.However,by programmingDIFF_CLK to'1',thedevicecan be made towork witha differentialinputclockon CLKP and CLKM. Operatingwitha low-jitterdifferentialclockgenerallyleads to improvedSNR performance. Incaseswhere thedutycycleoftheinputclockfallsoutsidethe45% to55% range,itisrecommended toenable an internaldutycyclecorrectioncircuit.Enablethiscircuitby settingtheEN_DCC bitto'1'. EXTERNAL REFERENCE The AFE5805 can be made tooperateinexternalreferencemode by pullingtheINT/EXT pinto'0'.Inthismode, theREFT and REFB pinsshouldbe drivenwithvoltagelevelsof2.5V and 0.5V,respectively,and must have enough drivestrengthto drivethe switchedcapacitanceloadingof the referencevoltagesby each ADC. The advantageofusingtheexternalreferencemode isthatmultipleAFE5805 unitscan be made tooperatewiththe same externalreference,therebyimprovingparameterssuch as gain matchingacrossdevices.However, in applicationsthatdo not have an availablehighdrive,differentialexternalreference,the AFE5805 can stillbe drivenwitha singleexternalreferencevoltageon the CM pin.When EXT_REF_VCM isset as '1'(and the INT/EXT pinissetto'0'),theCM pinisconfiguredas an inputpin,and thevoltageson REFT and REFB are generatedas shown inEquation1 and Equation2. (1) (2) Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com BIT CLOCK PROGRAMMABILITY The outputinterfaceoftheAFE5805 isnormallya DDR interface,withtheLCLK risingedge and fallingedge transitionsinthemiddleofalternatedatawindows.Figure43 shows thisdefaultphase. Figure43. LCLK DefaultPhase The phase of LCLK can be programmed relativeto the output frame clock and data using bits PHASE_DDR <1:0>.Figure44 shows theLCLK phase modes. Figure44. LCLK Phase ProgrammabilityModes

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 Inadditiontoprogrammingthephase ofLCLK intheDDR mode, thedevicecan alsobe made tooperateinSDR mode by settingtheEN_SDR bitto'1'.Inthismode, thebitclock(LCLK) isoutputat12 timestheinputclock,or twicetherateas inDDR mode. Depending on thestateofFALL_SDR, LCLK may be outputineitherofthetwo manners shown inFigure45.As Figure45 illustrates,onlytheLCLK rising(orfalling)edge isused tocapturethe outputdatainSDR mode. Figure45. SDR InterfaceModes The SDR mode does notwork wellbeyond 40MSPS because theLCLK frequencybecomes veryhigh. DATA OUTPUT FORMAT MODES The ADC output,by default,isinstraightoffsetbinarymode. Programming theBTC_MODE bitto'1'invertsthe MSB, and theoutputbecomes binarytwo'scomplement mode. Also by default,the firstbitof the frame (followingthe risingedge of FCLKP) isthe LSB of the ADC output. Programming the MSB_FIRST mode invertsthe bitorderinthe word,and the MSB isoutputas the firstbit followingtheFCLKP risingedge. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):AFE5805

(1.4V□to□3.6V) High-Level CS (1.4V□to□3.6V) Device□Ready□for Serial□Register□WriteDevice□Ready□for Data□Conversion Start□of□Clock AVDD1 AVDD2 DVDD AVDD 5V/c45 LVDD ADS_RESET CS FCLK t4 t7 (3.3V,□5.0V) (1.8V) VCA_PD,□ADC_PD (2) Device□Fully Powers□Down Device□Fully Powers□Up 1 s/c109 t (1) WAKE AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING 10ms < t1 < 50ms, 10ms < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns,t6 > 100ns,t7 > 10ms, and t8 > 100ms. The AVDDx and LVDD power-onsequence does notmatteras longas –10ms < t3 < 10ms. Similarconsiderationsapplywhileshuttingdown thedevice. POWER-DOWN TIMING Power-uptimeshown isbased on 1mF bypasscapacitorson thereferencepins.tWAKE isthetimeittakesforthedevicetowake up completelyfrompower-down mode. The AFE5805 has two power-down modes: completepower-down mode and partialpower-down mode. (1)tWAKE ≤ 50ms forcompletepower-down mode. tWAKE ≤ 2ms forpartialpower-down mode (providedthe clockisnot shut offduring power-down). (2)The ADS_PD pinscan be configuredforpartialpower-down mode througha registersetting.

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V/I CW□Switch□Matrix Attenuator (VCA) PGA Clamp LPF CW/IOUT OUT OUT T/R Switch VCNTL AFE5805 LVDS Serializer 12-Bit ADC AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 THEORY OF OPERATION of0V to1.2V.WhiletheLNA isdesignedtobe drivenThe AFE5805 isan 8-channel,fullyintegratedanalog from a single-endedsource,the internalTGC signalfront-enddevice controllingthe LNA, attenuator, path isdesignedto be fullydifferentialto maximizePGA, LPF, and ADC, thatimplementsa number of dynamic range while also optimizingfor low,proprietarycircuitdesign techniquesto specifically even-orderharmonicdistortion.address the performance demands of medical ultrasoundsystems.Itoffersunparalleledlow-noise CW dopplersignalprocessingisfacilitatedby routing and low-power performance at a high levelof the differentialLNA outputsto V/Iamplifierstages. integration.For the TGC signalpath,each channel The resultingsignalcurrentsof each channel then consistsof a 20dB fixed-gainlow-noiseamplifier connectto an 8×10 switchmatrixthatiscontrolled (LNA), a linear-in-dBvoltage-controlledattenuator through the serialinterfaceand a corresponding (VCA),and a programmablegainamplifier(PGA),as register.The CW outputsare typicallyroutedto a wellas a clampingand low-passfilterstage.Digitally passive delay linethat allows coherent summing controlledthroughthe logicinterface,the PGA gain (beam forming)oftheactivechannelsand additional can be set to fourdifferentsettings:20dB, 25dB, off-chipsignalprocessing,as shown inFigure46. externally-appliedcontrolvoltage(VCNTL )intherange Figure46. FunctionalBlock Diagram Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):AFE5805

A1-A8□Attenuator□Stages Control Input VB Q2 Q3 QS C -C Clipping□Amplifiers1 8 Q5 Q6 Q7 Q8 A1 A2 A3 A4 A5 A6 A7 A8 VCNTL AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com LOW-NOISE AMPLIFIER (LNA) The attenuatorisessentiallya variablevoltagedivider the input range of each clippingamplifier,theThe LNA performsa single-endedinputtodifferential amplifieroutputrisesfrom0V (FET completelyON) tooutputvoltageconversionand is configuredfora VCM – VT (FET nearlyOFF), where VCM is thefixed gain of 20dB (10V/V). The ultralow common source voltageand VT is the thresholdinput-referrednoiseofonly0.7nV/√Hz, alongwiththe voltageof the FET. As each FET approachesitsofflinearinputrange of 250mV PP , resultsin a wide stateand the controlvoltagecontinuesto rise,thedynamic range thatsupportsthe high demands of nextclippingamplifier/FETcombinationtakesoverforPW and CW ultrasoundimagingmodes. Largerinput the next portionof the piecewise-linearattenuationsignalscan be acceptedby the LNA, but distortion characteristic.performance degrades as input signal levels network.VOLTAGE-CONTROLLED ATTENUATOR (VCA) The VCA is designed to have a linear-in-dB attenuationcharacteristic;thatis,the average gain lossindB isconstantforeach equalincrementofthe controlvoltage (VCNTL). Figure 47 shows the simplifiedschematicofthisVCA stage. Figure47. Voltage-ControlledAttenuatorSimplifiedSchematic

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(+1.65V) T o□ADC Inputs AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 PROGRAMMABLE POST-GAIN AMPLIFIER (PGA) PROGRAMMABLE CLAMPINGFollowingthe VCA is a programmable post-gain amplifier(PGA). Figure 48 shows a simplified To furtheroptimizetheoverloadrecoverybehaviorof schematicofthePGA, includingtheclampingstage. a completeTGC channel,the AFE5805 integratesa The gain of thisPGA can be configuredto four programmable clamping stage, as shown in differentgainsettings:20dB, 25dB, 27dB, and 30dB, Figure 49. This clamping stage precedes the programmablethroughtheserialport;see Table10. low-passfilterinordertopreventthefiltercircuitfrom (largeinputsignals),the attenuatorand PGA noise LOW-PASS FILTERdominate. The AFE5805 integratesan anti-aliasingfilterinthe formofa programmablelow-passfilter(LPF)foreach channel.The LPF isdesignedas a differential,active, second-order filterthat approximates a Bessel characteristic,withtypically12dB per octaveroll-off. Figure49 shows thesimplifiedschematicofhalfthe differentialactive low-pass filter.Programmable through the serialinterface,the –3dB frequency cornercan be set to either10MHz or 15MHz. The filterbandwidthissetforallchannelssimultaneously. Figure48. Post-GainAmplifier (SimplifiedSchematic) Figure49. Clamping Stage and Low-Pass Filter(SimplifiedSchematic) Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com ANALOG-TO-DIGITAL CONVERSION deviceswithouthavingto externallydriveand route 12-bitlevel. The ADC outputgoes to a serializerthatoperates

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7pF0.1/c109F CIN /c179 /c1090.1 F VB (+2.4V) IN VBL T/R AFE5805 AFE5805 www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010

APPLICATION INFORMATION

The LNA closed-looparchitectureis internallyANALOG INPUT AND LNA compensated formaximum stabilitywithouttheneed of externalcompensationcomponents (inductorsorWhile the LNA is designed as a fullydifferential capacitors).At the same time, the totalinputamplifier,itis optimizedto performa single-ended capacitanceis kept to a minimum withonly 16pF.inputto differentialoutputconversion.A simplified Thisarchitectureminimizesany loadingofthesignalschematicofan LNA channelisshown inFigure50. source that may otherwise lead to aA biasvoltage(VB) of +2.4V isinternallyappliedto frequency-dependentvoltagedivider.Moreover,thetheLNA inputsthrough8kΩ resistors.Inaddition,the closed-loopdesignyieldsverylow offsetsand offsetdedicatedsignalinput(IN pin)includesa pairof drift;thisconsiderationisimportantbecause theLNAback-to-backdiodes that provide a coarse input directlydrives the subsequent voltage-controlledclampingfunctionin case the inputsignalrisesto attenuator.very large levels, exceeding 0.7VPP . This TypicalCharacteristics).The optimalnoise powerAs Figure50 also shows, the complementaryLNA matching is achieved for source impedances ofinput(VBL pin)is internallydecoupled by a small around 200Ω. Furtherdetailsof the AFE5805 inputcapacitor.Furthermore,for each inputchannel,a noise performance are shown in the Typicalseparate VBL pin is brought out for external Characteristicgraphs.bypassing.This bypassingshould be done with a small,0.1mF (typical)ceramic capacitorplaced in Table16.Noise Figureversus Source Resistancecloseproximityto each VBL pin.Attentionshouldbe (RS)at2MHzgivento providea low-noiseanalog ground forthis bypass capacitor.A noisy ground potentialmay R S (Ω) NOISE FIGURE (dB) cause noise to be pickedup and injectedintothe 50 2.6signalpath,leadingtohighernoiselevels. 200 1.0 400 1.1 1000 2.3 Figure50. LNA Channel (SimplifiedSchematic) Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):AFE5805

+5V AFE5805 3k/c87 C2 /c179 /c109 0.1 FC1 3k/c87 RTBAS40

0.1 F/c109

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com OVERLOAD RECOVERY ±0.3V can significantlyreduce the overalloverload ultrasoundreceivechannel front-endthatincludes As Figure51 shows,thefront-endcircuitryshouldbe typicalexternaloverloadprotectionelements.Here, capacitivelycoupledtotheLNA signalinput(IN).This fourhigh-voltageswitchingdiodesareconfiguredina couplingensuresthatthe LNA inputbiasvoltageof bridgeconfigurationand form the transmit/receive +2.4V ismaintainedand decoupledfrom any other (T/R)switch.Duringthetransmitperiod,highvoltage biasingvoltagebeforetheLNA. the over-voltageto small levels,Schottkydiodes (such as the BAS40 series by Infineon® ) are commonly used.For example,clampingto levelsof Figure51. TypicalInputOverload ProtectionCircuitofan UltrasoundSystem

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 VCA — GAIN CONTROL When the AFE5805 operates in CW mode, the and minimum attenuation(maximum gain)atVCNTL = 1.2V.Table17 shows thenominalgainsforeach of the fourPGA gain settings.The totalgain range is typically46dB and remainsconstant,independentof thePGA selected;theMax Gain column reflectsthe absolutegainofthefullsignalpathcomprisedofthe fixedLNA gainof20dB and theprogrammable PGA gain. Table17.Nominal Gain ControlRanges forEach oftheFour PGA Gain Settings MIN GAIN AT MAX GAIN AT PGA GAIN VCNTL = 0V VCNTL = 1.2V 20dB –4.5dB 41.5dB 25dB –0.5dB 45.5dB 27dB 1.5dB 47.5dB 30dB 3.5dB 49.5dB As previouslydiscussed,the VCA architectureuses eightattenuatorsegments thatare equallyspaced in Figure52. ExternalFilteringoftheVCNTL Inputorder to approximatethe linear-in-dBgain-control slope.This approximationresultsin a monotonic slope;gainrippleistypicallylessthan±0.5dB. CW DOPPLER PROCESSINGThe AFE5805 gain-controlinput has a –3dB The AFE5805 integratesmany of the elementsbandwidth of approximately1.5MHz. This wide necessaryto allowforthe implementationof a CWbandwidth,althoughusefulinmany applications,can dopplerprocessingcircuit,such as a V/Iconverterforallow high-frequencynoise to modulate the gain each channeland a cross-pointswitchmatrixwithancontrolinput.In practice,thismodulationcan easily 8-inputinto10-output(8×10)configuration.be avoidedby additionalexternalfiltering(RF and C F) ofthecontrolinput,as Figure52 shows.Steppingthe InordertoswitchtheAFE5805 fromthedefaultTGCcontrolvoltagefrom 0V to 1.2V, the gain control mode operationintoCW mode, bitD5 of the VCAresponse time istypicallylessthan 500ns to settle controlregistermust be updated to low ('0');seewithin10% ofthefinalsignallevelof1VPP (–6dBFS) Table5.Thissettingalsoenablesaccesstoallotheroutput. registers that determine the switch matrix configuration(seetheInputRegisterBitMap tables).The controlvoltageinput(VCNTL pin)representsa In orderto processCW signals,the LNA internallyhigh-impedanceinput.MultipleAFE5805 devicescan feeds into a differentialV/I amplifierstage. Thebe connected in parallelwithno significantloading transconductanceof the V/I amplifieris typicallyeffectsusingtheVCNTL pinofeach device.Note that 15.6mA/V witha 100mV PP inputsignal.For properwhen theVCNTL pinisleftunconnected,itfloatsup to operation,the CW outputsmust be connectedto ana potentialof about +3.7V. For any voltagelevel externalbiasvoltageof +2.5V.Each CW outputisabove 1.2V and up to 5.0V,the VCA continuesto designedto sinka smalldc currentof 0.9mA, andoperateatitsminimum attenuationlevel;however,it can delivera signalcurrentofup to2.9mAPP .isrecommended tolimitthevoltagetoapproximately 1.5Vorless. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):AFE5805

(+2.5V) Amplifier I□and□Q Channel ADC AFE5805 CW□Out 8□In□By□10□Out CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 AFE5805 CW□Out 8□In□By□10□Out CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 Passive Delay Line Clock L□=□220 H/c109 AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com The resultingsignalcurrentthenpasses throughthe Aftersumming, theCW signalpathfurtherconsistsof 8×10 switchmatrix.Depending on the programmed a highdynamic range mixerfordown-conversionto configurationof the switchmatrix,any V/Iamplifier I/Q base-band signals.The I/Q signalsare then currentoutputcan be connectedto any of 10 CW band-limited(thatis, low-frequencycontents are outputs.This design is a simple current-summing removed) in a filterstage thatprecedes a pairof circuitsuch thateach CW outputcan representthe high-resolution,lowsample rateADCs. sum of any or allof the channelcurrents.The CW outputsare typicallyroutedto a passiveLC delay line,allowingcoherentsumming ofthesignals. Figure53. Conceptual CW Doppler SignalPath Using CurrentSumming and a PassiveDelay Linefor Beamforming

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Differential□Sine-Wave, PECL,□or□LVDS□Clock□Input CMOS□Single-Ended Clock CLKP CLKM CMOS□Clock□Input www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 CLOCK INPUT The eightchannels on the device operatefrom a singleclockinput.To ensurethattheaperturedelay and jitterarethesame forallchannels,theAFE5805 uses a clock tree network to generate individual samplingclockstoeach channel.The clockpathsfor allthechannelsarematched fromthesourcepointto the samplingcircuit.This architectureensures that the performance and timingfor allchannels are identical.The use of the clock tree for matching introducesan aperturedelaythatisdefinedas the delaybetween therisingedge ofFCLK and theactual instantof sampling.The aperturedelaysforallthe channelsare matched tothebestpossibleextent.A mismatch of ±20ps (±3s) could existbetween the apertureinstantsof the eightADCs withinthe same Figure55. InternalClock Buffer chip.However, the aperturedelaysof ADCs across two differentchips can be several hundred picosecondsapart. The AFE5805 can operate either in CMOS single-endedclockmode (defaultisDIFF_CLK = 0) ordifferentialclockmode (SINE,LVPECL, orLVDS). In the single-endedclock mode, CLKM must be forcedto0VDC ,and thesingle-endedCMOS applied on theCLKP pin.Figure54 shows thisoperation. Figure56. DifferentialClock DrivingCircuit (DIFF_CLK = 1) Figure54. Single-EndedClock DrivingCircuit (DIFF_CLK = 0) When configuredfor the differentialclock mode (registerbitDIFF_CLK = 1)theAFE5805 clockinputs Figure57. Single-EndedClock DrivingCircuitcan be drivendifferentially(SINE,LVPECL, orLVDS) When DIFF_CLK = 1withlittleor no differencein performancebetween them, or with a single-ended(LVCMOS). The For best performance,the clock inputsmust becommon-mode voltageof the clockinputsisset to driven differentially,reducing susceptibilitytoVCM using internal5kΩ resistors,as shown in common-mode noise. For high input frequencyFigure 55. This method allows using sampling,itisrecommended to use a clocksourcetransformer-coupleddrivecircuitsfora sine wave withvery low jitter.Bandpass filteringof the clockclockor ac-couplingforLVPECL and LVDS clock sourcecan helpreducetheeffectofjitter.Ifthedutysources,as shown inFigure56 and Figure57.When cycledeviatesfrom50% by more than2% or3%, itisoperating in the differentialclock mode, the recommended toenabletheDCC throughregisterbitsingle-endedCMOS clockcan be ac-coupledto the EN_DCC.CLKP input,withCLKM connectedto ground witha 0.1mF capacitor,as Figure57 shows. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):AFE5805

VREFT□=□1.5V□+ VCM 1.5V VREFB□=□1.5V /c45 VCM 1.5V REFT REFB ISET 0.1 F/c109 2.2 F/c109 56.2k/c87 2.2 F/c109 0.1 F/c109 AFE5805 + + AFE5805 SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com REFERENCE CIRCUIT The device also supports the use of external matches towithin50mV ofVCM .Allbiascurrentsrequiredfortheinternaloperationof REFB in thismode are given by Equation3 andBufferingtheinternalbandgap voltagealsogenerates Equation4:the common-mode voltageVCM , which isset to the midlevelof REFT and REFB. It is meant as a referencevoltagetoderivetheinputcommon-mode if (3)the inputisdirectlycoupled.Itcan alsobe used to derivethe referencecommon-mode voltagein the externalreferencemode. Figure 58 shows the (4) suggesteddecouplingforthereferencepins. The stateof the referencevoltageinternalbuffers during various combinations of the ADS_PD, INT/EXT, and EXT_REF_VCM registerbits is describedinTable18. Figure58. Suggested Decoupling on theReferencePins

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010 Table18. StateofReferenceVoltagesforVariousCombinations ofADS_PD and INT/EXT PIN,REGISTER BIT INTERNAL BUFFER STATE ADS_PD pin 0 0 1 1 0 0 1 1 INT/EXT pin 0 1 0 1 0 1 0 1 EXT_REF_VCM 0 0 0 0 1 1 1 1 CM pin 1.5V 1.5V 1.5V 1.5V Force Do notuse Force Do notuse (1) Weakly forcedwithreducedstrength. Poor RMS jitter(> 100ps),combined withinadequate power-supplydesign (forexample, supply voltagePOWER SUPPLIES initializationsequence in order to stabilizeLVDSInTGC mode, onlytheVCA (attenuator)draws a low clocktimingand SNR performance.current(typically8mA) fromthe5V supply.Switching intotheCW mode, theinternalV/I-amplifiersarethen Table19.Address and Data inHexadecimalpowered from the 5V railsas well,raisingthe operatingcurrenton the5V rail.Atthesame time,the ADDRESS DATA post-gainamplifiers(PGA) are beingpowered down, 01 0010htherebyreducingthecurrentconsumptionon the3.3V D1 0140hrail(referto the ElectricalCharacteristicstablefor DA 0001hdetailson TGC mode and CW mode current consumption). E1 0020h 02 0080hAllanalogsupplyrailsfortheAFE5805 shouldbe low 01 0000hnoise,includingthe 3.3V digitalsupplyDVDD that connectstotheinternallogicblocksoftheVCA within Writingtotheseregistershas thefollowingadditionalthe AFE5805. Itis recommended to tiethe DVDD effects:pinstothesame 3.3V analogsupplyas theAVDD1/2 pins,ratherthan a different3.3V railthatmay also a. Total chip power increasesby approximately providepower to otherlogicdevicein the system. 8mW — thisincludesa currentincreaseof about Transientsand noisegeneratedby thosedevicescan 1.9mA on AVDD1 and about1.1mA on LVDD. coupleintotheAFE5805 and degrade overalldevice b. With referencetotheLVDS TimingDiagram andperformance. the Definitionof Setup and Hold Times, LCLKP/LCLKM shiftby about 100ps to the left CLOCK JITTER,POWER NOISE, SNR, AND relativeto CLK and OUTP/OUTM. This shift LVDS TIMING causes the data setuptimeto reduce by 100ps and thedataholdtimetoincreaseby 100ps.As explainedinapplicationnoteSLYT075 ,ADC clock c. The clockpropagationdelay(tPROP )isreducedbyjittercan degrade ADC performance.Therefore,itis approximately2ns. The typicaland minimumalwayspreferredtouse a low jitterclocktodrivethe valuesforthisspecificationare reduced by 2ns,AFE5805. To ensure the performance of the and themaximum valueisreducedby 1.5ns.AFE5805, a clockwitha jitterof1ps RMS orbetteris ensureLVDS timingstability. Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):AFE5805

SBOS421D –MARCH 2008–REVISED MARCH 2010 www.ti.com GROUNDING AND BYPASSING High-speed mixed signaldevices are sensitiveto Allbypassingand power suppliesforthe AFE5805 shouldbe referencedtothisanaloggroundplane.All BOARD LAYOUT itself. In orderto maintainproperLVDS timing,allLVDS recommended value for thisbypass capacitoris Additionaldetailson PCB layouttechniquescan be 2.2mF. All other designed referencepins can be found in the Texas InstrumentsApplicationReport bypassed with smallercapacitorvalues,typically MicroStar BGA Packaging Reference Guide 0.1mF. For best resultschoose low-inductance (SSYZ015B), which can be downloaded from the TI ceramicchipcapacitors(size402)and placethem as web site(www.ti.com). closeas possibletothedevicepinsas possible.

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www.ti.com SBOS421D –MARCH 2008–REVISED MARCH 2010

REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionC (October,2008)toRevisionD Page Changes from RevisionB (July,2008)toRevisionC Page

Changed common-mode voltageVCM toVCM and relatedreferencestoCM pin,includingEquation3 and
Added CLOCK JITTER,POWER NOISE, SNR, AND LVDS TIMING ,ClockJitter,Power Noise,SNR, and LVDS Copyright© 2008–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLink(s):AFE5805

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) AFE5805ZCF ACTIVE BGA ZCF 135 160 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Dec-2009 Addendum-Page 1

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Product Information

AFE5805ZCFT specifications and overview.

Summary

FULLY-INTEGRATED,8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/?숰z, 12-Bit, 50MSPS, 122mW/Channel

Description

FULLY-INTEGRATED,8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/?숰z, 12-Bit, 50MSPS, 122mW/Channel

Source title AFE5805ZCFT Datasheet(PDF) - Texas Instruments

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AFE5805ZCFT

Read AFE5805ZCFT online.

AFE5805_10 TI | Alldatasheet

Document overview

Technical content

APPLICATIONS

2 SubmitDocumentationFeedback Copyright© 2008–2010,Texas InstrumentsIncorporated

ELECTRICAL CHARACTERISTICS

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00 X S_RST

16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

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0 X PDN_COMPLETE

11 X X X ILVDS_FRAME <2:0>

1 X X X TERM_LCLK <2:0>

1 X X X TERM_FRAME <2:0>

1 X X X TERM_DAT <2:0>

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0 X 0 DUALCUSTOM_PAT

26 X X X X X X X X X X BITS_CUSTOM1 <9:0>

27 X X X X X X X X X X BITS_CUSTOM2 <9:0>

0 X PAT_DESKEW

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APPLICATION INFORMATION

0.1 F/c109

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REVISION HISTORY

AFE5805ZCFT specifications and overview.

More parts from the same family.