AFE5804ZCFT

Texas Instruments

FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.89nV/√Hz, 12-Bit, 40MSPS, 101mW/Channel REVISED OCTOBER 2011

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LNA8□Channels SPI IN1 IN8 . CH1 LVDS OUT CH8 VCA/PGA Clamp and LPF Logic/Controls Reference CW□Switch□Matrix□(8 10)/c180 I (10)OUT 12-Bit ADC AFE5804 AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 FULLY-INTEGRATED,8-CHANNELANALOGFRONT-ENDFORULTRASOUND 0.89nV/√Hz,12-Bit,40MSPS,101mW/Channel Check forSamples: AFE5804 1FEATURES DESCRIPTION The AFE5804 isa completeanalogfront-enddevice 23• 8-ChannelComplete Analog Front-End: specificallydesigned for ultrasoundsystems that– LNA, VCA, PGA, LPF, and ADC requirelowpower and smallsize.

Mode ControlforPower/Noise Optimization: The AFE5804 consistsofeightchannels,includinga– Low Noise (Full-Channel): low-noise amplifier (LNA), voltage-controlled0.89nV/√Hz (TGC Mode I) attenuator(VCA), programmable gain amplifier 1.23nV/√Hz (TGC Mode II) (PGA), low-pass filter(LPF), and a 12-bit 1.03nV/√Hz (PW Mode) analog-to-digitalconverter(ADC) with low voltage differentialsignaling(LVDS) dataoutputs.– Ultra-LowPower: 101mW/Channel (TGC Mode II) The LNA gainissetfor20dB gainand has excellent 65mW/Channel (CW Mode) noiseand signalhandlingcapabilities,includingfast overloadrecovery.VCA gaincan varyover a 46dB• Low-Noise Pre-Amp (LNA): rangewitha 0V to1.2V controlvoltagecommon toall– 0.75nV/√Hz channelsoftheAFE5804. – 20dB FixedGain The PGA can be programmed forgains of 20dB,– 280mV PP LinearInputRange 25dB, 27dB, and 30dB. The internallow-passfilter
Variable-GainAmplifier: can alsobe programmed to12.5MHz or17MHz. – Gain ControlRange: 46dB The LVDS outputsoftheADC reducethenumber of
PGA Gain Settings:20dB, 25dB, 27dB, 30dB interfacelinestoan ASIC orFPGA, therebyenabling the high system integrationdensitiesdesiredfor• Low-Pass Filter: portablesystems.The ADC can eitherbe operated– SelectableBW: 12.5MHz,17MHz withinternalor externalreferences.The ADC also – 2nd-Order,Bessel featuresa signal-to-noiseratio(SNR) enhancement mode thatcan be usefulathighgains.• Gain Error:±0.5dB
Channel Matching:±0.25dB The AFE5804 is availablein a 15mm × 9mm, 135-ball BGA package that is Pb-free• Clamping (RoHS-compliant)and green. It is specifiedfor• FastOverload Recovery:Two Clock Cycles operationfrom0°C to+85°C.
12-BitAnalog-to-DigitalConverter: – 10MSPS to50MSPS – 69dB SNR at10MHz – SerialLVDS Interface
IntegratedCW Switch Matrix
15mm × 9mm, 135-BGA Package: – Pb-Free(RoHS-Compliant)and Green

APPLICATIONS

MedicalImaging,Ultrasound – PortableSystems – Battery-PoweredSystems Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2Infineonisa registeredtrademarkofInfineonTechnologies. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2008–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. PACKAGING/ORDERING INFORMATION (1)(2) OPERATING PACKAGE TEMPERATURE ORDERING TRANSPORT PRODUCT PACKAGE-LEAD DESIGNATOR RANGE NUMBER MEDIA, QUANTITY ECO STATUS AFE5804ZCFR Tape and Reel,1000 AFE5804 μFBGA-135 ZCF 0°C to+85°C AFE5804ZCFT Tape and Reel,250 Pb-Free,Green AFE5804ZCF Tray,160 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. (2) These packagesconformtoLead (Pb)-freeand greenmanufacturingspecifications.Additionaldetailsincludingspecificmaterialcontent can be accessedatwww.ti.com/leadfree. GREEN: TIdefinesGreen tomean Lead (Pb)-Freeand inaddition,uses lesspackage materialsthatdo notcontainhalogens,including bromine(Br),orantimony(Sb)above 0.1%oftotalproductweight.N/A:Not yetavailableLead (Pb)-Free;forestimatedconversion dates,go towww.ti.com/leadfree.Pb-FREE: TIdefinesLead (Pb)-Freetomean RoHS compatible,includinga leadconcentrationthat does notexceed 0.1% oftotalproductweight,and,ifdesignedtobe soldered,suitableforuse inspecifiedlead-freesoldering processes. ABSOLUTE MAXIMUM RATINGS (1) Over operatingfree-airtemperaturerange,unlessotherwisenoted. AFE5804 UNIT Supplyvoltagerange,AVDD1 –0.3to+3.9 V Supplyvoltagerange,AVDD2 –0.3to+3.9 V Supplyvoltagerange,AVDD_5V –0.3to+6 V Supplyvoltagerange,DVDD –0.3to+3.9 V Supplyvoltagerange,LVDD –0.3to+2.2 V Voltagebetween AVSS1 and LVSS –0.3to+0.3 V Voltageatanaloginputs –0.3tominimum [3.6,(AVDD2 + 0.3)] V ExternalvoltageappliedtoREFT-pin –0.3to+3 V ExternalvoltageappliedtoREFB-pin –0.3to+2 V Voltageatdigitalinputs –0.3tominimum [3.9,(AVDD2 + 0.3)] V Peak soldertemperature(2) +260 °C Maximum junctiontemperature,TJ +125 °C Storagetemperaturerange –55 to+150 °C Operatingtemperaturerange 0 to+85 °C HBM 2000 V ESD ratings CDM 750 V MM 150 V (1) Stressesabove theseratingsmay cause permanentdamage. Exposuretoabsolutemaximum conditionsforextendedperiodsmay degradedevicereliability.These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thosespecifiedisnotsupported. (2) DevicecomplieswithJSTD-020D.

2 Copyright© 2008–2011,Texas InstrumentsIncorporated

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011

ELECTRICAL CHARACTERISTICS

AtAVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,TGC mode I,single-endedinputintoLNA, ac-coupled (1.0μF),VCNTL = 1.0V,fIN = 5MHz, Clock= 40MSPS, 50% dutycycle,LPF = 12.5MHz,internalreferencemode, ISET = 56kΩ, LVDS buffersetting= 3.5mA,and ambienttemperatureTA = +25°C, unlessotherwisenoted. AFE5804 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PREAMPLIFIER (LNA) Gain A SE-inputtodifferentialoutput 20 dB Inputvoltage(TGC, PW modes) VIN Linearoperation(HD2 ≤ 40dB) 280 mV PP (CW mode) Linearoperation 220 mV PP Maximum inputvoltage Limitedby internaldiodes 600 mV PP Inputvoltagenoise(TGC) en (RTI) R S = 0Ω,f= 2MHz 0.75 nV/√Hz TGC mode I 3 pA/√Hz Inputcurrentnoise In (RTI) TGC mode II 1.7 pA/√Hz Common-mode voltage,input VCMI Internallygenerated 2.4 V Bandwidth BW Small-signal,–3dB 55 MHz Inputresistance R IN At2.5MHz 8 kΩ IncludesinternalESD and clampingInputcapacitance C IN 16 pFdiodes FULL-SIGNAL CHANNEL (LNA + VCA + LPF + ADC) Inputvoltagenoise en R S = 0Ω,f= 2MHz, PGA = 30dB 0.89 nV/√Hz(TGC mode I) Inputvoltagenoise(TGC mode II) R S = 0Ω,f= 2MHz, PGA = 30dB 1.23 nV/√Hz Inputvoltagenoise(PW mode) R S = 0Ω,f= 2MHz, PGA = 30dB 1.03 nV/√Hz Noisefigure NF R S = 200Ω,f= 2MHz 1.1 dB Low-passfilterbandwidth LPF At–3dB,selectablethroughSPI 12.5,17 MHz Bandwidthtolerance ±10 % High-passfilter HPF (First-order,due tointernalac-coupling) 200 kHz Group delayvariation 1MHz to10MHz ±3 ns ≤ 6dB overloadtowithin3%,Overloadrecovery 2 ClockCyclesVCNTL = 0V to1.2V ACCURACY Gain (PGA) SelectablethroughSPI 20,25,27,30 dB Totalgain,max (1) LNA + PGA gain,VCNTL = 1.2V 47.5 49 50.5 dB VCNTL = 0V to1.2V 46 dB Gain range VCNTL = 0.1Vto1.0V 40 dB 0V < VCNTL < 0.1V ±0.5 dB 1.0V< VCNTL < 1.2V ±0.5 dB Gain matching Channel-to-channel –0.5 ±0.25 +0.5 dB Offseterror VCNTL = 1.2V,PGA = 30dB –39 +39 LSB Offseterrordrift(tempco) ±5 ppm/°C Clamp level LevelinternallyfixedbeforeLPF 2.3 VPP GAIN CONTROL (VCA) Inputvoltagerange VCNTL Gain range= 46dB 0 to1.2 V Gain slope VCNTL = 0.1Vto1.0V 44.4 dB/V Inputresistance 25 kΩ Response time VCNTL = 0V to1.2Vstep;to90% signal 0.5 μs (1) ExcludesdigitalgainwithinADC. (2) Excludeserrorofinternalreference. Copyright© 2008–2011,Texas InstrumentsIncorporated 3

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AtAVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,TGC mode I,single-endedinputintoLNA, ac-coupled (1.0μF),VCNTL = 1.0V,fIN = 5MHz, Clock= 40MSPS, 50% dutycycle,LPF = 12.5MHz,internalreferencemode, ISET = 56kΩ, LVDS buffersetting= 3.5mA,and ambienttemperatureTA = +25°C, unlessotherwisenoted. AFE5804 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE fIN = 2MHz; –1dBFS 59.7 dBFS(VCNTL = 1.0V,PGA = 30dB) Signal-to-noiseratio SNR fIN = 5MHz; –1dBFS 59.5 dBFS fIN = 10MHz; –1dBFS 59.1 dBFS fIN = 5MHz; –1dBFS –45 dBFS(VCNTL = 0.35V,PGA = 30dB) fIN = 5MHz; –1dBFSSecond-harmonicdistortion HD2 –50 –70 dBFS(VCNTL = 1V,PGA = 30dB) fIN = 5MHz; –6dBFS –61 –70 dBFS(VCNTL = 1V,PGA = 20dB) fIN = 5MHz; –1dBFS –43 dBFS(VCNTL = 0.35V,PGA = 30dB) fIN = 5MHz; –1dBFSThird-harmonicdistortion HD3 –43 –50 dBFS(VCNTL = 1V,PGA = 30dB) fIN = 5MHz; –6dBFS –61 –70 dBFS(VCNTL = 1V,PGA = 20dB) f1 = 4.99MHz at–6dBFS,Intermodulationdistortion IMD3 58 dBcf2 = 5.01MHz at–32dBFS Crosstalk fIN ≤ 5MHz, VCNTL = 0.6V,–6dBFS –67 dBc CW —SIGNAL CHANNELS Inputvoltagenoise(CW) en R S = 0Ω,f= 2MHz 1.1 nV/√Hz Outputnoisecorrelationfactor Summing ofeightchannels 0.6 % AtVIN = 100mV PP 13.8 mA/V Outputtransconductance IOUT /VIN AtVIN = 270mV PP 12.2 mA/V Dynamic CW outputcurrent,max IOUTAC 2.9 mA PP StaticCW outputcurrent(sink) IOUTDC 0.9 mA Outputcommon-mode voltage(3) VCM 2.5 V Outputimpedance 50 kΩ Outputcapacitance 10 pF INTERNAL REFERENCE VOLTAGES (ADC) Referencetop VREFT 0.5 V Referencebottom VREFB 2.5 V VREFT – VREFB 1.95 2 2.05 V Common-mode voltage(internal) VCM 1.425 1.5 1.575 V VCM outputcurrent ±2 mA (3) CW outputsrequirean externallyappliedbiasvoltageof+2.5V.

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www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 ELECTRICAL CHARACTERISTICS (continued) AtAVDD_5V = 5.0V,AVDD1 = AVDD2 = DVDD = 3.3V,LVDD = 1.8V,TGC mode I,single-endedinputintoLNA, ac-coupled (1.0μF),VCNTL = 1.0V,fIN = 5MHz, Clock= 40MSPS, 50% dutycycle,LPF = 12.5MHz,internalreferencemode, ISET = 56kΩ, LVDS buffersetting= 3.5mA,and ambienttemperatureTA = +25°C, unlessotherwisenoted. AFE5804 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EXTERNAL REFERENCE VOLTAGES (ADC) Referencetop VREFT 2.4 2.5 2.6 V Referencebottom VREFB 0.4 0.5 0.6 V VREFT – VREFB 1.9 2.1 V Switchingcurrent(4) 2.5 mA POWER SUPPLY SUPPLY VOLTAGES At40MSPS AVDD1, AVDD2, DVDD Operating 3.15 3.3 3.47 V AVDD_5V Operating 4.75 5 5.25 V LVDD 1.7 1.8 1.9 V SUPPLY CURRENTS IAVDD1 (ADC) 99 110 mA TGC mode I 123 136 mA IAVDD2 (VCA) CW mode 63 75 mA TGC mode I 7 10 mA IAVDD_5V (VCA) CW mode 54 61 mA IDVDD (VCA) 1.5 3.0 mA ILVDD (ADC) 68 80 mA Allchannels,TGC mode I,no signal 896 985 mW Allchannels,TGC mode II,no signal 808 898 mW Power dissipation,total(5) Allchannels,PW mode ,no signal 840 925 mW Allchannels,CW mode, no signal(6) 525 575 mW No clockapplied,no signal 528 mW POWER-DOWN MODES Power-down dissipation,total Completepower-down mode 52 68 mW Power-down responsetime 1.0 μs Power-upresponsetime PD tovalidoutput(90% level) 50 μs Power-down dissipation(7) Partialpower-down mode 95 mW THERMAL CHARACTERISTICS Temperaturerange 0 85 °C Thermalresistance,TJA 32 °C/W Thermalresistance,TJC 4.2 °C/W (4) Currentdrawn by theeightADC channelsfromtheexternalreferencevoltages;sourcingforVREFT, sinkingforVREFB. (5) Programmable power affectson thefront-end;ADC power consumptionremainsconstantatabout57mW/channel for40MSPS. (6) ADC powered-down duringCW mode. (7) AtVCA_PD pinpulledhigh;see alsoPower-Down Timingdiagram. Copyright© 2008–2011,Texas InstrumentsIncorporated 5

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com DIGITAL CHARACTERISTICS DC specificationsrefertotheconditionwhere thedigitaloutputsarenotswitching,butarepermanentlyata validlogiclevel '0' or'1'.AtC LOAD = 5pF(1),IOUT = 3.5mA (2),R LOAD = 100Ω(2),and no internaltermination,unlessotherwisenoted. AFE5804 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS High-levelinputvoltage 1.4 3.3 V Low-levelinputvoltage 0 0.3 V High-levelinputcurrent 10 μA Low-levelinputcurrent(3) –10 μA Inputcapacitance 3 pF LVDS OUTPUTS High-leveloutputvoltage 1375 mV Low-leveloutputvoltage 1025 mV Outputdifferentialvoltage,|VOD | 350 mV VOS outputoffsetvoltage(2) Common-mode voltageofOUTP and OUTM 1200 mV Outputcapacitanceinsidethedevice,fromeitherOutputcapacitance 2 pFoutputtoground 1x (clockFCLKP and FCLKM 10 50 MHzrate) 6x (clockLCLKP and LCLKM 60 300 MHzrate) CLOCK Clockinputrate 10 50 MSPS Clockdutycycle 50 % Clockinputamplitude,differential Sine-wave,ac-coupled 3 VPP(VCLKP – VCLKM) LVPECL, ac-coupled 1.6 VPP LVDS, ac-coupled 0.7 VPP Clockinputamplitude,single-ended (VCLKP) High-levelinputvoltage,VIH CMOS 2.2 V Low-levelinputvoltage,VIL CMOS 0.6 V (1) C LOAD istheeffectiveexternalsingle-endedloadcapacitancebetween each outputpinand ground. (2) IOUT referstotheLVDS buffercurrentsetting;R LOAD isthedifferentialloadresistancebetween theLVDS outputpair. (3) ExceptpinJ3 (INT/EXT),whichhas an internalpull-upresistor(52kΩ)to3.3V.

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1x□ADCLK 6x□ADCLK IN1 OUT1P OUT1M LCLKP LCLKM FCLKP FCLKM 12x□ADCLK 12-Bit ADC Serializer DigitalLPFPGA Digital Reference REFT INT/ EXT CW[0:9] REFB CM OUT8P OUT8M ISET Registers SDATA CS SCLK ADC Control PD Clock Buffer (ADCLK) CLKPAVSS2AVDD2 (3.3V) (AVSS) CLKMAVDD (3.3V)LVDD (1.8V) Power- Down T est□P atterns Drive□Current Output□F ormat Digital□Gain(0dB□to□12dB) /c188/c188/c188 VCALNA /c188 IN8 VCNTL LPFPGAVCA CW□Switch□Matrix (8x10) LNA /c188 /c188 /c188 /c188/c188 /c188Channels 2□to□7 ADC_ RESET /c188 /c188 T SCLK AVDD_5V DVDD(3.3V) AVSS1 20,25,27 30dB AFE5804 /c188 12.5,□17MHz AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 FUNCTIONAL BLOCK DIAGRAM Copyright© 2008–2011,Texas InstrumentsIncorporated 7

D AVSS2AVSS2AVDD2 DVDDCW9 C AVSS2AVSS2VCNTL DVDDCW8 B AVSS2AVSS2AVDD_5V AVSS2CW7 A IN8IN4IN2 VCA_PDIN3IN1 E 87 9 VBL5VBL7 VBL6 CW0AVSS2 AVDD2 CW1AVSS2 VB2 CW2VB4 AVDD_5V IN5IN7 IN6 AVSS2AVSS2AVDD2 AVSS2VCMCW5 J SCLKVCA_CSDNC RSTADS_PD H AVSS2AVSS2AVDD1 AVSS2AVSS1 G AVDD1DNCDNC AVDD1AVDD1CLKM F AVSS2AVSS2VB1 AVSS2VB5CW6 K Rows AVSS2 VB3 AVSS2 CW4VREFL AVDD2 ADS_ RESETCS SDA T A REFBAVDD1 REFT ISETAVDD1 CM CW3VREFH VB6 AVSS1AVSS1DNC AVSS1AVSS1DNC P L VDDL VSSLCLKM L VSSLCLKP N OUT5POUT1POUT3P L VDDOUT4P M OUT5MOUT1MOUT3M L VSSOUT2MOUT4M L AVSS1AVSS1AVDD1 AVSS1AVSS1CLKP R L VSS OUT2P DNC INT/EXT DNCAVSS1 DNC FCLKPL VDD FCLKM OUT8POUT6P OUT7P OUT8MOUT6M OUT7M EN_SMAVSS1 AVDD1 AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com PIN CONFIGURATION ZCF PACKAGE 135-BGA BOTTOM VIEW

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R OUT8M OUT7M OUT6M OUT5M LVSS OUT1M OUT2M OUT3M OUT4M 9 8 7 6 5 4 3 2 1 P OUT8P OUT7P OUT6P OUT5P LVDD OUT1P OUT2P OUT3P OUT4P N FCLKP FCLKM LVDD LVDD LVSS LVSS LVSS LCLKM LCLKP M DNC DNC AVSS1 AVSS1 AVSS1 AVSS1 AVSS1 DNC DNC L EN_SM AVDD1 AVSS1 AVSS1 AVSS1 AVSS1 AVSS1 AVDD1 CLKP K ISET CM AVDD1 AVDD1 AVDD1 DNC AVDD1 DNC CLKM J REFB REFT AVDD1 AVSS2 AVSS2 AVSS2 INT/ EXT AVDD1 AVSS1 H ADS_RESET SDATA CS SCLK RST VCA_ CS DNC DNC ADS_PD G CW4 AVDD2 VREFL AVSS2 AVSS2 AVSS2 VCM AVDD2 CW5 F CW3 VB6 VREFH AVSS2 AVSS2 AVSS2 VB5 VB1 CW6 E CW2 AVDD_5V VB4 AVSS2 AVSS2 AVSS2 VB3 AVDD_5V CW7 D CW1 VB2 AVSS2 AVSS2 DVDD AVSS2 AVSS2 VCNTL CW8 C CW0 AVDD2 AVSS2 AVSS2 DVDD AVSS2 AVSS2 AVDD2 CW9 B VBL5 VBL6 VBL7 VBL8 DNC VBL4 VBL3 VBL2 VBL1 A IN5 IN6 Legend: AVDD1 +3.3V;□Analog AVDD2 +3.3V;□Analog +3.3V;□Analog +1.8V;□Digital +5V;□Analog DVDD LVDD AVDD_5V Analog□Ground Analog□Ground Digital□Ground AVSS1 AVSS2 LVSS IN7 IN8 VCA_PD IN4 IN3 IN2 IN1 AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 ZCF PACKAGE 135-BGA CONFIGURATION MAP (TOP VIEW) Copyright© 2008–2011,Texas InstrumentsIncorporated 9

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com Table1. TERMINAL FUNCTIONS PIN NO. PIN NAME FUNCTION DESCRIPTION H7 CS Input Chipselectforserialinterface;activelow H1 ADS_PD Input Power-down pinforADS; activehigh H9 ADS_ RESET Input RESET inputforADS; activelow H6 SCLK Input Serialclockinputforserialinterface H8 SDATA Input Serialdatainputforserialinterface J2,L2,K7,J7, AVDD1 POWER 3.3VanalogsupplyforADSK3,L8,K5,K6 L3,M3, L4,M4, L5,M5, L6,M6, AVSS1 GND AnaloggroundforADS L7,M7, J1 P5,N6, N7 LVDD POWER 1.8VdigitalsupplyforADS N3, N4, N5, R5 LVSS GND DigitalgroundforADS C5, D5 DVDD POWER 3.3VdigitalsupplyfortheVCA; connecttothe3.3Vanalogsupply(AVDD2). C2, C8, G2, G8 AVDD2 POWER 3.3VanalogsupplyforVCA E2,E8 AVDD_5V POWER 5V supplyforVCA C3, D3, C4, D4, E4,F4,G4, E5, F5,G5, C6, D6, AVSS2 GND AnaloggroundforVCA E6,F6,G6, C7, D7, J4,J5,J6 K1 CLKM Input NegativeclockinputforADS (connecttoGround insingle-endedclockmode) L1 CLKP Input PositiveclockinputforADS K8 CM Input/Output 1.5Vcommon-mode I/OforADS. Becomes inputpininone oftheexternalreferencemodes. C9 CW0 Output CW output0 D9 CW1 Output CW output1 E9 CW2 Output CW output2 F9 CW3 Output CW output3 G9 CW4 Output CW output4 G1 CW5 Output CW output5 F1 CW6 Output CW output6 E1 CW7 Output CW output7 D1 CW8 Output CW output8 C1 CW9 Output CW output9 L9 EN_SM Input EnablesaccesstotheVCA register.Activehigh.Connectpermanentlyto3.3V(AVDD1). N8 FCLKM Output LVDS frameclock(negativeoutput) N9 FCLKP Output LVDS frameclock(positiveoutput) A1 IN1 Input LNA inputChannel1 A2 IN2 Input LNA inputChannel2 A3 IN3 Input LNA inputChannel3 A4 IN4 Input LNA inputChannel4 A9 IN5 Input LNA inputChannel5 A8 IN6 Input LNA inputChannel6 A7 IN7 Input LNA inputChannel7 A6 IN8 Input LNA inputChannel8 J3 INT/EXT Input Internal/externalreferencemode selectforADS; internal= high K9 ISET Input CurrentbiaspinforADS. Requires56kΩ toground. N2 LCLKM Output LVDS bitclock(6x);negativeoutput N1 LCLKP Output LVDS bitclock(6x);positiveoutput R4 OUT1M Output LVDS dataoutput(negative),Channel1 P4 OUT1P Output LVDS dataoutput(positive),Channel1 R3 OUT2M Output LVDS dataoutput(negative),Channel2 P3 OUT2P Output LVDS dataoutput(positive),Channel2 R2 OUT3M Output LVDS dataoutput(negative),Channel3 P2 OUT3P Output LVDS dataoutput(positive),Channel3

10 Copyright© 2008–2011,Texas InstrumentsIncorporated

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 Table1. TERMINAL FUNCTIONS (continued) PIN NO. PIN NAME FUNCTION DESCRIPTION R1 OUT4M Output LVDS dataoutput(negative),Channel4 P1 OUT4P Output LVDS dataoutput(positive),Channel4 R6 OUT5M Output LVDS dataoutput(negative),Channel5 P6 OUT5P Output LVDS dataoutput(positive),Channel5 R7 OUT6M Output LVDS dataoutput(negative),Channel6 P7 OUT6P Output LVDS dataoutput(positive),Channel6 R8 OUT7M Output LVDS dataoutput(negative),Channel7 P8 OUT7P Output LVDS dataoutput(positive),Channel7 R9 OUT8M Output LVDS dataoutput(negative),Channel8 P9 OUT8P Output LVDS dataoutput(positive),Channel8 J9 REFB Input/Output 0.5VNegativereferenceofADS. Decouplingtoground.Becomes inputinexternalrefmode. J8 REFT Input/Output 2.5VPositivereferenceofADS. Decouplingtoground.Becomes inputinexternalrefmode. H5 RST Input RESET inputforVCA. ConnecttotheVCA_ CS pin(H4). H4 VCA_ CS Output ConnecttoRST –pin(H5) F2 VB1 Output Internalbiasvoltage.Bypass togroundwith2.2μF. D8 VB2 Output Internalbiasvoltage.Bypass togroundwith0.1μF. E3 VB3 Output Internalbiasvoltage.Bypass togroundwith0.1μF. E7 VB4 Output Internalbiasvoltage.Bypass togroundwith0.1μF F3 VB5 Output Internalbiasvoltage.Bypass togroundwith0.1μF. F8 VB6 Output Internalbiasvoltage.Bypass togroundwith0.1μF. B1 VBL1 Input ComplementaryLNA inputChannel1;bypasstogroundwith0.1μF. B2 VBL2 Input ComplementaryLNA inputChannel2;bypasstogroundwith0.1μF. B3 VBL3 Input ComplementaryLNA inputChannel3;bypasstogroundwith0.1μF. B4 VBL4 Input ComplementaryLNA inputChannel4;bypasstogroundwith0.1μF. B9 VBL5 Input ComplementaryLNA inputChannel5;bypasstogroundwith0.1μF. B8 VBL6 Input ComplementaryLNA inputChannel6;bypasstogroundwith0.1μF. B7 VBL7 Input ComplementaryLNA inputChannel7;bypasstogroundwith0.1μF. B6 VBL8 Input ComplementaryLNA inputChannel8;bypasstogroundwith0.1μF. A5 VCA_PD Input Power-down pinforVCA; low= normalmode, high= power-down mode. G3 VCM Output VCA referencevoltage.Bypass togroundwith0.1μF. D2 VCNTL Input VCA controlvoltageinput F7 VREFH Output Clamp referencevoltage(2.7V).Bypass togroundwith0.1μF. G7 VREFL Output Clamp referencevoltage(2.0V).Bypass togroundwith0.1μF. B5,H2, H3, K2, K4,M1, M2, DNC Do notconnect M8, M9 Copyright© 2008–2011,Texas InstrumentsIncorporated 11

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 Sample n Sample n□+□12 tPROP t (A)D 12□clocks□latency ADC Input (1) Clock Input 6X□FCLK LCLKM LCLKP 1X□FCLK FCLKM FCLKP SERIAL DATA OUTP OUTM tSAMPLE Sample n□+□13 tH1 tSU1 tH2 tSU2 LCLKM LCLKP OUTM OUTP t =□min(t ,□t ) t =□min(t ,□t ) SU SU1 SU2 H H1 H2 AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com (1)ReferencedtoADC Input(internalnode)forillustrationpurposesonly. Figure1. LVDS Timing Diagram Figure2. DefinitionofSetup and Hold Times TIMING CHARACTERISTICS (1) AFE5804 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tD(A) ADC aperturedelay 1.5 4.5 ns AperturedelayvariationChannel-to-channelwithinthesame device(3σ) ±20 ps tJ Aperturejitter 400 fS,rms Time tovaliddataaftercoming outof 50 μsCOMPLETE POWER-DOWN mode Time tovaliddataaftercoming outofPARTIAL tWAKE Wake-up time POWER-DOWN mode (withclockcontinuingto 2 μs runduringpower-down) Time tovaliddataafterstoppingand restarting 40 μstheinputclock ClockData latency 12 cycles (1) Timingparametersareensuredby designand characterization;notproductiontested.

12 Copyright© 2008–2011,Texas InstrumentsIncorporated

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 LVDS OUTPUT TIMING CHARACTERISTICS (1)(2) Typicalvaluesareat+25°C, minimum and maximum valuesoverspecifiedtemperaturerangeofTMIN = 0°C toTMAX = +85°C, sampling frequency= as specified,C LOAD = 5pF (3),IOUT = 3.5mA,R LOAD = 100Ω(4),and no internaltermination,unlessotherwisenoted. AFE5804 40MSPS 50MSPS PARAMETER TEST CONDITIONS (5) MIN TYP MAX MIN TYP MAX UNIT tSU Data setuptime(6) Data valid(7)tozero-crossingofLCLKP 0.67 0.47 ns Zero-crossingofLCLKP todatabecomingtH Data holdtime(6) 0.85 0.65 nsinvalid(7) ADC inputclockrisingedge cross-overtotPROP Clockpropagationdelay 10 14 16.6 10 12.5 14.1 nsoutputclock(FCLKP) risingedge cross-over Dutycycleofdifferentialclock,LVDS bitclockdutycycle 45.5 50 53 45 50 53.5(LCLKP – LCLKM) Bitclockcycle-to-cyclejitter 250 250 ps,pp Frame clockcycle-to-cyclejitter 150 150 ps,pp (1) Allcharacteristicsareatthemaximum ratedspeed foreach speed grade. (2) Timingparametersareensuredby designand characterization;notproductiontested. (3) C LOAD istheeffectiveexternalsingle-endedloadcapacitancebetween each outputpinand ground. (4) IOUT referstotheLVDS buffercurrentsetting;R LOAD isthedifferentialloadresistancebetween theLVDS outputpair. (5) Measurements aredone witha transmissionlineof100Ω characteristicimpedance between thedeviceand theload. (6) Setupand holdtimespecificationstakeintoaccounttheeffectofjitteron theoutputdataand clock.These specificationsalsoassume thatdataand clockpathsareperfectlymatched withinthereceiver.Any mismatchinthesepathswithinthereceiverwouldappearas reducedtimingmargin. (7) Data validreferstoa logichighof+100mV and a logiclowof–100mV. LVDS OUTPUT TIMING CHARACTERISTICS (1)(2) Typicalvaluesareat+25°C, minimum and maximum valuesoverspecifiedtemperaturerangeofTMIN = 0°C toTMAX = +85°C, sampling frequency= as specified,C LOAD = 5pF (3),IOUT = 3.5mA,R LOAD = 100Ω(4),and no internaltermination,unlessotherwisenoted. AFE5804 30MSPS 20MSPS 10MSPS PARAMETER TEST CONDITIONS (5) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT Data valid(7)tozero-crossingoftSU Data setuptime(6) 0.8 1.5 3.7 nsLCLKP Zero-crossingofLCLKP todatatH Data holdtime(6) 1.2 1.9 3.9 nsbecoming invalid(7) ADC inputclockrisingedge risingedge cross-over Dutycycleofdifferentialclock,LVDS bitclockdutycycle 46.5 50 52 48 50 51 49 50 51(LCLKP – LCLKM) Bitclockcycle-to-cycle 250 250 750 ps,ppjitter Frame clockcycle-to-cycle 150 150 500 ps,ppjitter (1) Allcharacteristicsareatthespeeds otherthanthemaximum ratedspeed foreach speed grade. (2) Timingparametersareensuredby designand characterization;notproductiontested. (3) C LOAD istheeffectiveexternalsingle-endedloadcapacitancebetween each outputpinand ground. (4) IOUT referstotheLVDS buffercurrentsetting;R LOAD isthedifferentialloadresistancebetween theLVDS outputpair. (5) Measurements aredone witha transmissionlineof100Ω characteristicimpedance between thedeviceand theload. (6) Setupand holdtimespecificationstakeintoaccounttheeffectofjitteron theoutputdataand clock.These specificationsalsoassume thatdataand clockpathsareperfectlymatched withinthereceiver.Any mismatchinthesepathswithinthereceiverwouldappearas reducedtimingmargin. (7) Data validreferstoa logichighof+100mV and a logiclowof–100mV. Copyright© 2008–2011,Texas InstrumentsIncorporated 13

0 0.1 1.2 Gain□(dB) V (V)CNTL PGA□= 30dB PGA□= 25dB PGA□= 20dB PGA□= 27dB TGC□I□Mode Low□Noise /c45 /c45 /c45 /c45 /c45 /c45 0 3 30 Normalized□Gain□(dB) Frequency□(MHz) 6 9 12 15 18 21 24 27 /c45 /c45 /c45 /c45 /c45 /c45 1.0 5.5 30.0 Normalized□Gain□(dB) Frequency□(MHz) 300 250 200 150 100 0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL PGA□= 30dB PGA□= 20dB Frequency□=□2MHz TGC□I□Mode,□Low□Noise 300 250 200 150 100 0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL Frequency□=□5MHz TGC□I□Mode,□Low□Noise PGA□= 30dB PGA□= 20dB 350 300 250 200 150 100 0 0.1 1.2 Noise (nV/ ) /c214Hz V (V)CNTL PGA = 30dB PGA = 20dB Frequency = 2MHz TGC II Mode, Low Power AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. GAIN vs VCNTL AT 5MHz 12.5MHz FILTER RESPONSE Figure3. Figure4. 17MHz FILTER RESPONSE OUTPUT-REFERRED NOISE vs VCNTL Figure5. Figure6. OUTPUT-REFERRED NOISE vs VCNTL OUTPUT-REFERRED NOISE vs VCNTL Figure7. Figure8.

14 Copyright© 2008–2011,Texas InstrumentsIncorporated

0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL Frequency□=□2MHz PW□Mode PGA□= 30dB PGA□= 20dB 400 350 300 250 200 150 100 0 0.1 1.2 Noise (nV/ ) /c214Hz V (V)CNTL Frequency = 5MHz TGC II Mode, Low Power PGA = 30dB PGA = 20dB 300 250 200 150 100 0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL Frequency□=□5MHz PW□Mode PGA□= 30dB PGA□= 20dB 200 180 160 140 120 100 0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL Frequency□=□2MHz TGC□II□Mode,□Low□Power PGA□= 30dB PGA□= 20dB 200 180 160 140 120 100 0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL PGA□= 30dB PGA□= 20dB Frequency□=□5MHz TGC□II□Mode,□Low□Power 160 140 120 100 0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL PGA□= 30dB PGA□= 20dB Frequency□=□2MHz PW□Mode AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. OUTPUT-REFERRED NOISE vs VCNTL OUTPUT-REFERRED NOISE vs VCNTL Figure9. Figure10. OUTPUT-REFERRED NOISE vs VCNTL INPUT-REFERRED NOISE vs VCNTL Figure11. Figure12. INPUT-REFERRED NOISE vs VCNTL INPUT-REFERRED NOISE vs VCNTL Figure13. Figure14. Copyright© 2008–2011,Texas InstrumentsIncorporated 15

0 0.1 1.2 Noise□(nV/ ) /c214Hz V (V)CNTL PGA□= 30dB PGA□=□20dB Frequency□=□5MHz PW□Mode 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1 10 Noise□Figure□(dB) Frequency□(MHz) TGC□I□Mode PGA□=□30dB V =□1.2VCNTL R =S 50/c87 R =□400S /c87 R =□200S /c87 R =□1kS /c87 1 10 Input-Referred□Noise□(nV/ ) /c214Hz Frequency□(MHz) R =S 50/c87 R =□400S /c87 TGC□I□Mode PGA□=□30dB V =□1.2VCNTL R =□200S /c87 R =□1kS /c87 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 1 10 Noise□(nV/ ) /c214Hz Frequency□(MHz) TGC□I□Mode PGA□=□30dB V =□1.2VCNTL R =S 50/c87 R =□400S /c87 R =□200 /c87S R =□1kS /c87 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 1 10 Noise□(nV/ ) /c214Hz Frequency□(MHz) R =S 50/c87 R =□400S /c87 TGC□II□Mode PGA□=□30dB V =□1.2VCNTL R =□200 /c87S R =□1kS /c87 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 1 10 Noise□(nV/ ) /c214Hz Frequency□(MHz) R =S 50/c87 R =□400S /c87 PW□Mode PGA□=□30dB V =□1.2VCNTL R =□200 /c87S R =□1kS /c87 AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. INPUT-REFERRED NOISE vs VCNTL NOISE FIGURE vs FREQUENCY AND R S Figure15. Figure16. INPUT-REFERRED NOISE vs FREQUENCY AND R S OUTPUT-REFERRED NOISE vs FREQUENCY AND R S Figure17. Figure18. OUTPUT-REFERRED NOISE vs FREQUENCY AND R S OUTPUT-REFERRED NOISE vs FREQUENCY AND R S Figure19. Figure20.

16 Copyright© 2008–2011,Texas InstrumentsIncorporated

1.4 1.2 1.0 0.8 0.6 0.4 0.2 20dB Noise□(nV/ ) /c214Hz Gain□Setting□(PGA) 25dB 27dB 30dB R =□0 V =□1.2V TGC□I,□Low□Noise /c87S CNTL 2MHz5MHz10MHz 2MHz5MHz10MHz 5MHz2MHz 10MHz 2MHz5MHz10MHz 1.4 1.2 1.0 0.8 0.6 0.4 0.2 20dB Noise□(nV/ ) /c214Hz Gain□Setting□(PGA) 25dB 27dB 30dB R =□0 V =□1.2V PW□Mode /c87S CNTL 2MHz5MHz10MHz 2MHz5MHz10MHz 2MHz5MHz10MHz 2MHz 5MHz10MHz 1.4 1.2 1.0 0.8 0.6 0.4 0.2 20dB Noise□(nV/ ) /c214Hz Gain□Setting□(PGA) 25dB 27dB 30dB R =□0 ,□V =□1.2V,□TGC□II,□Low□Power/c87S CNTL 2MHz5MHz10MHz 2MHz5MHz10MHz 2MHz5MHz10MHz 2MHz5MHz10MHz 2000 1800 1600 1400 1200 1000 800 600 400 200 /c450.45 Channel Gain□(dB) 0.050.10 0.20 Channel-to-Channel AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. INPUT-REFERRED NOISE vs PGA INPUT-REFERRED NOISE vs PGA Figure21. Figure22. GAIN MATCH HISTOGRAM INPUT-REFERRED NOISE vs PGA (VCNTL = 0.1V) Figure23. Figure24. Copyright© 2008–2011,Texas InstrumentsIncorporated 17

/c450.45 Channel Gain□(dB) 0.050.10 0.20 Channel-to-Channel 2000 1800 1600 1400 1200 1000 800 600 400 200 /c450.45 Channel Gain□(dB) 0.050.10 0.20 Channel-to-Channel 900 800 700 600 500 400 300 200 100 2012 Channel Code 2016201820222014 2020 207220682064206020562052204820442040203620322024 20282026 20702066206220582054205020462042203820342030 2500 2000 1500 1000 500 12.6 Channel Transconductance□(mA/V) /c4555 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz2MHz TGC□I□Mode PGA□=□20dB, 6dBFS/c45 5MHz /c4545 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□20dB, 1dBFS/c45 AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. GAIN MATCH HISTOGRAM GAIN MATCH HISTOGRAM (VCNTL = 0.6V) (VCNTL = 1.0V) Figure25. Figure26. CW ACCURACY HISTOGRAM OUTPUT OFFSET HISTOGRAM Figure27. Figure28. SECOND HARMONIC vs VCNTL AND FREQUENCY SECOND HARMONIC vs VCNTL AND FREQUENCY Figure29. Figure30.

18 Copyright© 2008–2011,Texas InstrumentsIncorporated

/c4555 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□20dB, 6dBFS/c45 /c4535 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□20dB, 1dBFS/c45 /c4555 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□30dB, 6dBFS/c45 /c4545 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□30dB, 1dBFS/c45 /c4555 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□30dB, 6dBFS/c45 /c4535 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□30dB, 1dBFS/c45 AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. THIRD HARMONIC vs VCNTL AND FREQUENCY THIRD HARMONIC vs VCNTL AND FREQUENCY Figure31. Figure32. SECOND HARMONIC vs VCNTL AND FREQUENCY SECOND HARMONIC vs VCNTL AND FREQUENCY Figure33. Figure34. THIRD HARMONIC vs VCNTL AND FREQUENCY THIRD HARMONIC vs VCNTL AND FREQUENCY Figure35. Figure36. Copyright© 2008–2011,Texas InstrumentsIncorporated 19

/c4555 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□20dB, 6dBFS/c45 /c4545 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□20dB, 1dBFS/c45 /c4555 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□20dB, 6dBFS/c45 /c4535 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□20dB, 1dBFS/c45 /c4555 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□30dB, 6dBFS/c45 /c4545 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz2MHz 5MHz TGC□II□Mode PGA□=□30dB, 1dBFS/c45 AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. SECOND HARMONIC vs VCNTL AND FREQUENCY SECOND HARMONIC vs VCNTL AND FREQUENCY Figure37. Figure38. THIRD HARMONIC vs VCNTL AND FREQUENCY THIRD HARMONIC vs VCNTL AND FREQUENCY Figure39. Figure40. SECOND HARMONIC vs VCNTL AND FREQUENCY SECOND HARMONIC vs VCNTL AND FREQUENCY Figure41. Figure42.

20 Copyright© 2008–2011,Texas InstrumentsIncorporated

/c4555 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□30dB, 6dBFS/c45 /c4535 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□30dB, 1dBFS/c45 /c4555 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz2MHz 5MHz PW□Mode PGA□=□20dB, 6dBFS/c45 /c4545 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz2MHz 5MHz PW□Mode PGA□=□20dB, 1dBFS/c45 /c4555 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz PW□Mode PGA□=□20dB, 6dBFS/c45 /c4535 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz PW□Mode PGA□=□20dB, 1dBFS/c45 AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. THIRD HARMONIC vs VCNTL AND FREQUENCY THIRD HARMONIC vs VCNTL AND FREQUENCY Figure43. Figure44. SECOND HARMONIC vs VCNTL AND FREQUENCY SECOND HARMONIC vs VCNTL AND FREQUENCY Figure45. Figure46. THIRD HARMONIC vs VCNTL AND FREQUENCY THIRD HARMONIC vs VCNTL AND FREQUENCY Figure47. Figure48. Copyright© 2008–2011,Texas InstrumentsIncorporated 21

/c4555 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz PW□Mode PGA□=□30dB, 6dBFS/c45 /c4545 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz PW□Mode PGA□=□30dB, 1dBFS/c45 /c4555 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz PW□Mode PGA□=□30dB, 6dBFS/c45 /c4535 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Distortion□(dBFS) V (V)CNTL 10MHz 2MHz 5MHz PW□Mode PGA□=□30dB, 1dBFS/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□20dB, 6dBFS/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL 2MHz TGC□I□Mode PGA□=□20dB, 1dBFS/c45 10MHz 5MHz AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. SECOND HARMONIC vs VCNTL AND FREQUENCY SECOND HARMONIC vs VCNTL AND FREQUENCY Figure49. Figure50. THIRD HARMONIC vs VCNTL AND FREQUENCY THIRD HARMONIC vs VCNTL AND FREQUENCY Figure51. Figure52. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure53. Figure54.

22 Copyright© 2008–2011,Texas InstrumentsIncorporated

/c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□I□Mode PGA□=□25dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□25dB, 1dBFS/c45 /c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□I□Mode PGA□=□27dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL 10MHz 2MHz 5MHz TGC□I□Mode PGA□=□27dB, 1dBFS/c45 /c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□I□Mode PGA□=□30dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□I□Mode PGA□=□30dB, 1dBFS/c45 10MHz 2MHz 5MHz AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure55. Figure56. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure57. Figure58. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure59. Figure60. Copyright© 2008–2011,Texas InstrumentsIncorporated 23

/c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□II□Mode PGA□=□20dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□20dB, 1dBFS/c45 /c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL 10MHz 2MHz 5MHz TGC□II□Mode PGA□=□25dB, 6dBFS/c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□II□Mode PGA□=□25dB, 1dBFS/c45 10MHz 2MHz 5MHz /c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□II□Mode PGA□=□27dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□II□Mode PGA□=□27dB, 1dBFS/c45 10MHz 2MHz 5MHz AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure61. Figure62. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure63. Figure64. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure65. Figure66.

24 Copyright© 2008–2011,Texas InstrumentsIncorporated

/c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□II□Mode PGA□=□30dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL TGC□II□Mode PGA□=□30dB, 1dBFS/c45 10MHz 2MHz 5MHz /c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□20dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□20dB, 1dBFS/c45 10MHz 2MHz 5MHz /c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□25dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□25dB, 1dBFS/c45 10MHz 2MHz 5MHz AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure67. Figure68. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure69. Figure70. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure71. Figure72. Copyright© 2008–2011,Texas InstrumentsIncorporated 25

/c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□27dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□27dB, 1dBFS/c45 10MHz 2MHz 5MHz /c4560 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□30dB, 6dBFS/c45 10MHz 2MHz 5MHz /c45 /c45 /c45 /c45 /c45 /c45 /c45 0.6 1.2 Crosstalk□(dBc) V (V)CNTL PW□Mode PGA□=□30dB, 1dBFS/c45 10MHz 2MHz 5MHz 0.50 0.25 0.25 0.5 /c45 /c45 Time□( s)/c109 0 10 Output□Voltage□(V) 2 4 6 8 TGC□I□Mode PGA□=□30dB V =□1V V =□250mV ,□0.25mV CNTL IN PP PP 0.5 0.25 0.25 0.5 /c45 /c45 Time□( s)/c109 0 10 Output□( Full-Scale) /c177 2 4 6 8 TGC□Mode□II PGA□=□30dB V =□1.0V V =□250mV ,□0.25mV CNTL IN PP PP AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure73. Figure74. CROSSTALK vs VCNTL CROSSTALK vs VCNTL Figure75. Figure76. OVERLOAD RECOVERY OVERLOAD RECOVERY Figure77. Figure78.

26 Copyright© 2008–2011,Texas InstrumentsIncorporated

1.0 0.5 /c45 /c45 0.5 1.0 Sample□Points 0 80 Output□Voltage□(V) 302010 40 50 60 70 90 100 110 120 TGC□Mode□I V =□1V PGA□=□20dB V =□0.54V IN PP CNTL 1.0 0.5 /c45 /c45 0.5 1.0 Sample□Points 0 80 Output□Voltage□(V) 302010 40 50 60 70 90 100 110 120 TGC□Mode□I V =□0.5V PGA□=□30dB V =□1V IN PP CNTL 1.0 0.5 /c45 /c45 0.5 1.0 Time□( s)/c109 0 10 Output□Voltage□(V) TGC□I□Mode PGA□=□30dB V =□0V□to□1.2V,□40MSPSCNTL VCNTL 1.0 0.5 /c45 /c45 0.5 1.0 Time ( s)/c109 0 20 Output ( Full-Scale) /c177 TGC I Mode PGA = 30dB V = 0.4V, 40MSPSCNTL 305 15 25 PD On = 25 s Off = 15 s /c109 /c109 V (V) CNTL 0 1.2 SNR□and□SNRD□(dBFS) SNR SNRD TGC□I□Mode Input□= 44.2dBm Frequency□=□5MHz /c45 PGA□=□30dB PGA□=□20dB 100M Magnitude□( ) /c87 100 /c45 100 Phase□( ) /c176 /c45 80 /c45 20 /c45 40 /c45 60 Frequency□(Hz) 100k 1M 10M Magnitude□(Z )IN Phase AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. LNA OVERLOAD FULL-CHANNEL OVERLOAD Figure79. Figure80. VCNTL RESPONSE TIME PARTIAL POWER-DOWN/POWER-UP RESPONSE TIME Figure81. Figure82. SNR AND SNRD vs VCNTL MAGNITUDE AND PHASE vs FREQUENCY Figure83. Figure84. Copyright© 2008–2011,Texas InstrumentsIncorporated 27

ADC□Frequency□(MSPS) 10 50 Current□(mA) 403020 AVDD1 LVDD /c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 1.80 2.20 Magnitude□(dBFS) 1.951.901.85 2.00 TGC□I□Mode PGA□=□30dB V =□1VCNTL 2.05 2.10 2.15 /c4532 /c456 /c4585 /c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 4.80 5.20 Magnitude□(dBFS) 4.954.904.85 5.00 TGC□I□Mode PGA□=□30dB V =□1VCNTL 5.05 5.10 5.15 /c4532 /c456 /c4587 /c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 1.80 2.20 Magnitude□(dBFS) 1.951.901.85 2.00 TGC□II□Mode PGA□=□30dB V =□1VCNTL 2.05 2.10 2.15 /c4532 /c456 /c4587 /c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 4.80 5.20 Magnitude□(dBmFS) 4.954.904.85 5.00 TGC□II□Mode PGA□=□30dB V =□1VCNTL 5.05 5.10 5.15 /c4532 /c456 /c4590 /c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 1.80 2.20 Magnitude□(dBFS) 1.951.901.85 2.00 PW□Mode PGA□=□30dB V =□1VCNTL 2.05 2.10 2.15 /c4532 /c456 /c4585 AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. INTERMODULATION DISTORTION MSPS vs LVDD AND AVDD1 CURRENTS (1.99MHz and 2.01MHz) Figure85. Figure86. INTERMODULATION DISTORTION INTERMODULATION DISTORTION (4.99MHz and 5.01MHz) (1.99MHz and 2.01MHz) Figure87. Figure88. INTERMODULATION DISTORTION INTERMODULATION DISTORTION (4.99MHz and 5.01MHz) (1.99MHz and 2.01MHz) Figure89. Figure90.

28 Copyright© 2008–2011,Texas InstrumentsIncorporated

/c45 /c45 /c45 /c45 /c45 /c45 100 120 Frequency□(MHz) 4.80 5.20 Magnitude□(dBFS) 4.954.904.85 5.00 PW□Mode PGA□=□30dB V =□1VCNTL 5.05 5.10 5.15 /c4532 /c456 /c4587 AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 TYPICAL CHARACTERISTICS (continued) AVDD_5V = 5.0V,AVDD1 = VDD2 = DVDD = 3.3V,LVDD = 1.8V,single-endedinputintoLNA, ac-coupledwith1.0μF, VCNTL = 1.0V,fIN 5MHz, Clock= 40MSPS, 50% dutycycle,internalreferencemode, ISET = 56kΩ,LVDS buffersetting= 3.5mA,atambienttemperatureTA = +25°C, unlessotherwisenoted. INTERMODULATION DISTORTION (4.99MHz and 5.01MHz) Figure91. Copyright© 2008–2011,Texas InstrumentsIncorporated 29

(connect externally) VCA_CS RST [H4] [H9] VCA_SCLK VCA_SDATA ADS_CS ADS_SCLK ADS_SDATA ADS_RESET ADS_RESET [H8]SDATA [H7]CS [H6]SCLK [L9] EN_SM Tie to: +3.3V (AVDD1) [H5] AFE5804 SPI Interface and Register AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com SERIAL INTERFACE The AFE5804 has a setofinternalregistersthatcan be accessedthroughtheserialinterfaceformedby pinsCS (chipselect,activelow),SCLK (serialinterfaceclock),and SDATA (serialinterfacedata).When CS islow,the followingactionsoccur:

Serialshiftofbitsintothedeviceisenabled
SDATA (serialdata)islatchedateveryrisingedge ofSCLK
SDATA isloadedintotheregisteratevery24thSCLK risingedge Iftheword lengthexceeds a multipleof24 bits,theexcessbitsareignored.Data can be loadedinmultiplesof 24-bitwords withina singleactiveCS pulse.The firsteightbitsformtheregisteraddressand theremaining16 bitsformtheregisterdata.The interfacecan work withSCLK frequenciesfrom20MHz down toverylow speeds (afew hertz)and alsowitha non-50% SCLK dutycycle. RegisterInitialization Afterpower-up,the internalregistersmust be initializedto the respectivedefaultvalues.Initializationcan be done inone oftwo ways: 1. Througha hardwarereset,by applyinga low-goingpulseon theADS_ RESET pin;or 2. Through a softwarereset;usingthe serialinterface,setthe S_RST bithigh.Settingthisbitinitializesthe internalregistersto the respectivedefaultvalues and then self-resetsthe bitlow. In thiscase, the ADS_ RESET pinstayshigh(inactive). 3. The registersinTable2 must be programmed aftertheinitializationstage.The power-supplyrippleand clock jittereffectscan be minimized. Table2.RegisterData ADDRESS DATA 01 0010h D1 0140h DA 0001h E1 0020h 02 0080h 01 0000h SerialPortInterface(SPI)Information Figure92. TypicalConnection Diagram fortheSPI ControlLines

30 Copyright© 2008–2011,Texas InstrumentsIncorporated

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK SDATA Data□latched□on□rising□edge□of□SCLK Start□Sequence End□Sequence D0 D39VCA_SDA T A VCA_SCLK AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 SERIAL INTERFACE TIMING AFE5804 PARAMETER DESCRIPTION MIN TYP MAX UNIT t1 SCLK period 50 ns t2 SCLK hightime 20 ns t3 SCLK lowtime 20 ns t4 Data setuptime 5 ns t5 Data holdtime 5 ns t6 CS falltoSCLK rise 8 ns t7 Time between lastSCLK risingedge toCS risingedge 8 ns Internally-GeneratedVCA ControlSignals VCA_SCLK and VCA_SDATA signalsaregeneratedif:

Registerswithaddress16,17,or18 (hex)arewrittento,and
EN_SM pinisHIGH Copyright© 2008–2011,Texas InstrumentsIncorporated 31

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com SERIAL REGISTER MAP Table3.SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1)(2)(3)(4) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT 00 X S_RST Self-clearingsoftwareRESET. Inactive RES_03 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VCA VCA_SDATA D5 = 116 X X X X X X X X X X X X X X 1 1 See Table5 information<0:15> (TGC mode) VCA_SDATA17 X X X X X X X X X X X X X X X X See Table5 information<16:31> VCA_DATA18 X X X X X X X X See Table5 information<32:39> Channel-specificADCX X X X PDN_CH <1:4> Inactivepower-down mode. Channel-specificADCx X X X X PDN_CH <8:5> Inactivepower-down mode. Partialpower-down mode (fast0F X PDN_PARTIAL Inactiverecoveryfrompower-down). Registermode forcomplete0 X PDN_COMPLETE Inactivepower-down (slowerrecovery). ConfiguresthePD pinfor CompleteX 0 PDN_PIN_CFG partialpower-down mode. power-down LVDS currentdrive X X X ILVDS_LCLK <2:0> programmabilityforLCLKM 3.5mA drive and LCLKP pins. LVDS currentdriveILVDS_FRAME11 X X X programmabilityforFCLKM 3.5mA drive<2:0> and FCLKP pins. LVDS currentdrive X X X ILVDS_DAT <2:0> programmabilityforOUTM and 3.5mA drive OUTP pins. Enablesinternaltermination TerminationX EN_LVDS_TERM forLVDS buffers. disabled Programmable terminationfor Termination1 X X X TERM_LCLK <2:0> LCLKM and LCLKP buffers. disabled TERM_FRAME Programmable terminationfor Termination1 X X X <2:0> FCLKM and FCLKP buffers. disabled Programmable terminationfor Termination1 X X X TERM_DAT <2:0> OUTM and OUTP buffers. disabled Channel-specific, X X X X LFNS_CH <1:4> low-frequencynoise Inactive suppressionmode enable. Channel-specific, x X X X X LFNS_CH <8:5> low-frequencynoise Inactive suppressionmode enable. Enablesa repeatingfull-scaleX 0 0 EN_RAMP Inactiveramp patternon theoutputs. Enablesthemode whereintheDUALCUSTOM_0 X 0 outputtogglesbetween two InactivePAT definedcodes. Enablesthemode whereintheSINGLE_CUSTOM0 0 X outputisa constantspecified Inactive25 _PAT code. 2MSBs fora singlecustom BITS_CUSTOM1 pattern(andforthefirstcodeX X Inactive<11:10> ofthedualcustom pattern). <11> istheMSB. BITS_CUSTOM2 2MSBs forthesecond code ofX X Inactive<11:10> thedualcustom pattern. 10 lowerbitsforthesingle BITS_CUSTOM1 custom pattern(andforthe26 X X X X X X X X X X Inactive<9:0> firstcode ofthedualcustom pattern).<0> istheLSB. 10 lowerbitsforthesecondBITS_CUSTOM227 X X X X X X X X X X code ofthedualcustom Inactive<9:0> pattern. (1) The unused bitsineach register(identifiedas blanktablecells)must be programmed as '0'. (2) X = Registerbitreferencedby thecorrespondingname and description(defaultsettingislistedintable). (3) Bitsmarked as '0' shouldbe forcedto0,and bitsmarked as '1' shouldbe forcedto1 when theparticularregisterisprogrammed. (4) Multiplefunctionsina registershouldbe programmed ina singlewriteoperation.

32 Copyright© 2008–2011,Texas InstrumentsIncorporated

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 Table3.SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE (1)(2)(3)(4) (continued) ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT X X X X GAIN_CH4 <3:0> Programmable gainchannel4. 0dB gain X X X X GAIN_CH3 <3:0> Programmable gainchannel3. 0dB gain X X X X GAIN_CH2 <3:0> Programmable gainchannel2. 0dB gain X X X X GAIN_CH1 <3:0> Programmable gainchannel1. 0dB gain X X X X GAIN_CH5 <3:0> Programmable gainchannel5. 0dB gain X X X X GAIN_CH6 <3:0> Programmable gainchannel6. 0dB gain X X X X GAIN_CH7 <3:0> Programmable gainchannel7. 0dB gain X X X X GAIN_CH8 <3:0> Programmable gainchannel8. 0dB gain Single-1 1 X DIFF_CLK Differentialclockmode. ended clock Enablestheduty-cycle1 1 X EN_DCC Disabledcorrectioncircuit. External42 Drivestheexternalreference reference1 1 X EXT_REF_VCM mode throughtheVCM pin. drivesREFT and REFB Controlsthephase ofLCLK1 1 X X PHASE_DDR <1:0> 90 degreesoutputrelativetodata. 0 X PAT_DESKEW Enablesdeskew patternmode. Inactive X 0 PAT_SYNC Enablessyncpatternmode. Inactive Binarytwoscomplement Straight1 1 X BTC_MODE formatforADC output. offsetbinary SerializedADC outputcomes LSB-first1 1 X MSB_FIRST outMSB-first. output EnablesSDR outputmode DDR output1 1 X EN_SDR (LCLK becomes a 12x input46 modeclock). ControlswhethertheLCLK Risingedgerisingorfallingedge comes in ofLCLK in1 1 1 1 FALL_SDR themiddleofthedatawindow middleofwhen operatinginSDR output datawindowmode. SUMMARY OF FEATURES POWER IMPACT (RelativetoDefault) FEATURES DEFAULT SELECTION AT fS = 50MSPS ANALOG FEATURES Internalorexternalreference Internalreferencemode takesapproximately20mW moreN/A Pin(drivenon theREFT and REFB pins) power on AVDD1 Externalreferencedrivenon theCM pin Off Register42 Approximately8mW lesspower on AVDD1 Dutycyclecorrectioncircuit Off Register42 Approximately7mW more power on AVDD1 WithzeroinputtotheADC, low-frequencynoisesuppression Low-frequencynoisesuppression Off Register14 causesdigitalswitchingatfS/2,therebyincreasingLVDD power by approximately5.5mW/channel Differentialclockmode takesapproximately7mW more powerSingle-endedordifferentialclock Single-ended Register42 on AVDD1 RefertothePower-Down Modes sectionintheElectricalPower-down mode Off Pinand register0F Characteristicstable DIGITAL FEATURES Programmable digitalgain(0dB to12dB) 0dB Registers2A and 2B No difference StraightoffsetorBTC output Straightoffset Register46 No difference Swap polarityofanaloginputpins Off Register24 No difference LVDS OUTPUT PHYSICAL LAYER LVDS internaltermination Off Register12 Approximately7mW more power on AVDD LVDS currentprogrammability 3.5mA Register11 As perLVDS clockand databuffercurrentsetting LVDS OUTPUT TIMING LSB- orMSB-firstoutput LSB-first Register46 No difference SDR mode takesapproximately2mW more power on LVDDDDR orSDR output DDR Register46 (atfS = 30MSPS) LCLK phase relativetodataoutput RefertoFigure94 Register42 No difference Copyright© 2008–2011,Texas InstrumentsIncorporated 33

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com DESCRIPTION OF SERIAL REGISTERS SOFTWARE RESET ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

00 X S_RST

Softwareresetisappliedwhen theRST bitissetto'1';settingthisbitresetsallinternalregistersand self-clears to'0'. Table4.VCA RegisterInformation ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RES_V03 0 0 0 0 0 0 0 0 0 0 0 0 0 0CA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA 1(1) 1(1)

16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA VCA17 D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 VCA VCA VCA VCA VCA VCA VCA VCA18 D39 D38 D37 D36 D35 D34 D33 D32 (1) BitsD0 and D1 ofregister16 areforcedto'1'. space

VCA_SCLK and VCA_SDATA become activeonlywhen one oftheregisters16,17 or18 (addressinhex)of theAFE5804 arewritteninto.
The contentsofallthreeregisters(total40 bits)are writtenon VCA_SDATA even ifonlyone oftheabove registersiswrittento.Thisconditionisonlyvalidifthecontentoftheregisterhas changed because ofthe most recentwrite.Writingcontentsthatare the same as existingcontentsdoes not triggeractivityon VCA_SDATA.
For example,ifregister17 iswrittentoaftera RESET isapplied,thenthecontentsofregister17 as wellas thedefaultvaluesofthebitsinregisters16 and 18 arewrittentoVCA_SDATA.
Ifregister16 isthenwrittento,thenthenew contentsofregister16,thepreviouslywrittencontentsofregister 17,and thedefaultcontentsofregister18 arewrittentoVCA_SDATA. Note thatregardlessofwhat iswritten toD0 and D1 ofregister16,therespectiveoutputson VCA_SDATA arealways‘1’.
Alternatively,allthreeregisters(16,17 and 18) can alsobe writtenwithinone writecycleoftheADC serial interface.Inthatcase,therewouldbe 48 consecutiveSCLK edges withinthesame CS activewindow.
VCA_SCLK isgeneratedusingan oscillator(runningat approximately6MHz) insidethe AFE5804, but the oscillatorisgatedso thatitisactiveonlyduringthewriteoperationofthe40 VCA bits.
The externalADC SCLK frequencycan be greaterthan 6MHz. To ensure the SDATA transferreliability,≥ 1µs gap isrecommended between programmingtwo VCA registersconsecutively. VCA Reset
VCA_ CS shouldbe permanentlyconnectedtotheRST-input.
When VCA_ CS goes high(eitherbecause ofan activelow pulseon ADS_ RESET formore than10ns oras a resultorsettingbitRES_VCA), thefollowingfunctionsareperformedinsidetheAFE5804: – BitsD0 and D1 ofregister16 areforcedto‘1’ – Allotherbitsinregisters16,17 and 18 areRESET totherespectivedefaultvalues(‘0’ forallbitsexcept D5 ofregister16 whichissettoa defaultof‘1’). – No activityon signalsVCA_SCLK and VCA_SDATA.
IfbitRES_VCA has been setto‘1’,thenthestatemachine isintheRESET stateuntilRES_VCA issetto‘0’.

34 Copyright© 2008–2011,Texas InstrumentsIncorporated

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 INPUT REGISTER BIT MAPS Table5.VCA RegisterMap BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 D0:D7 D8:D11 D12:D15 D16:D19 D20:D23 D24:D27 D28:D31 D32:D35 D36:D39 Control CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 Table6.Byte 1—ControlByte RegisterMap BIT NUMBER BIT NAME DESCRIPTION D0 (LSB) 1 Startbit;thisbitispermanentlysethigh= 1 D1 WR Writebit;thisbitispermanentlysethigh= 1 D2 PWR 1= Power-down mode enabled D3 BW Low-passfilterbandwidthsetting(seeTable11) D4 M0 (seeTable12) D5 M1 (seeTable12) D6 PG0 LSB ofPGA gaincontrol(seeTable13) D7 (MSB) PG1 MSB ofPGA gaincontrol Table7.Byte 2—FirstData Byte BIT NUMBER BIT NAME DESCRIPTION D8 (LSB) DB1:1 Channel1,LSB ofmatrixcontrol D9 DB1:2 Channel1,matrixcontrol D10 DB1:3 Channel1,matrixcontrol D11 DB1:4 Channel1,MSB ofmatrixcontrol D12 DB2:1 Channel2,LSB ofmatrixcontrol D13 DB2:2 Channel2,matrixcontrol D14 DB2:3 Channel2,matrixcontrol D15 (MSB) DB2:4 Channel2,MSB ofmatrixcontrol Table8.Byte 3—Second Data Byte BIT NUMBER BIT NAME DESCRIPTION D16 (LSB) DB3:1 Channel3,LSB ofmatrixcontrol D17 DB3:2 Channel3,matrixcontrol D18 DB3:3 Channel3,matrixcontrol D19 DB3:4 Channel3,MSB ofmatrixcontrol D20 DB4:1 Channel4,LSB ofmatrixcontrol D21 DB4:2 Channel4,matrixcontrol D22 DB4:3 Channel4,matrixcontrol D23 (MSB) DB4:4 Channel4,MSB ofmatrixcontrol Copyright© 2008–2011,Texas InstrumentsIncorporated 35

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com Table9.Byte 4—ThirdData Byte BIT NUMBER BIT NAME DESCRIPTION D24 (LSB) DB5:1 Channel5,LSB ofmatrixcontrol D25 DB5:2 Channel5,matrixcontrol D26 DB5:3 Channel5,matrixcontrol D27 DB5:4 Channel5,MSB ofmatrixcontrol D28 DB6:1 Channel6,LSB ofmatrixcontrol D29 DB6:2 Channel6,matrixcontrol D30 DB6:3 Channel6,matrixcontrol D31 (MSB) DB6:4 Channel6,MSB ofmatrixcontrol Table10.Byte 5—FourthData Byte BIT NUMBER BIT NAME DESCRIPTION D32 (LSB) DB7:1 Channel7,LSB ofmatrixcontrol D33 DB7:2 Channel7,matrixcontrol D34 DB7:3 Channel7,matrixcontrol D35 DB7:4 Channel7,MSB ofmatrixcontrol D36 DB8:1 Channel8,LSB ofmatrixcontrol D37 DB8:2 Channel8,matrixcontrol D38 DB8:3 Channel8,matrixcontrol D39 (MSB) DB8:4 Channel8,MSB ofmatrixcontrol Table11.LPF Bandwidth Setting SETTING FUNCTION BW D3 = 0 Bandwidthsetto17MHz (default) BW D3 = 1 Bandwidthsetto12.5MHz Table12.Mode Setting M1 [D5] M0 [D4] FUNCTION 0 0 CW mode 0 1 TGC mode I;high-performancemode, lowestnoise 1 0 TGC mode II;lowestpower mode 1 1 PW mode Table13.PGA Gain Setting PG1 (D7) PG0 (D6) FUNCTION 0 0 SetsPGA gainto20dB (default) 0 1 SetsPGA gainto25dB 1 0 SetsPGA gainto27dB 1 1 SetsPGA gainto30dB

36 Copyright© 2008–2011,Texas InstrumentsIncorporated

Channel□1 Input V/I Converter VCA_SDATA CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 AVDD_5V VCA_SCLK Decode Logic (T o□Other□Channels) AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 Table14.CW Switch MatrixControlforEach Channel DBn:4 (MSB) DBn:3 DBn:2 DBn:1 (LSB) LNA INPUT CHANNEL n DIRECTED TO 0 0 0 0 OutputCW0 0 0 0 1 OutputCW1 0 0 1 0 OutputCW2 0 0 1 1 OutputCW3 0 1 0 0 OutputCW4 0 1 0 1 OutputCW5 0 1 1 0 OutputCW6 0 1 1 1 OutputCW7 1 0 0 0 OutputCW8 1 0 0 1 OutputCW9 1 0 1 0 ConnectedtoAVDD_5V 1 0 1 1 ConnectedtoAVDD_5V 1 1 0 0 ConnectedtoAVDD_5V 1 1 0 1 ConnectedtoAVDD_5V 1 1 1 0 ConnectedtoAVDD_5V 1 1 1 1 ConnectedtoAVDD_5V Figure93. Basic CW Cross-PointSwitch MatrixConfiguration Copyright© 2008–2011,Texas InstrumentsIncorporated 37

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com POWER-DOWN MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X PDN_CH <1:4> X X X X PDN_CH <8:5> 0F X PDN_PARTIAL

0 X PDN_COMPLETE

X 0 PDN_PIN_CFG Each oftheeightADC channelscan be individuallypowered down. PDN_CH <N > controlsthepower-down mode fortheADC channel<N >. In additionto channel-specificpower-down, the AFE5804 also has two globalpower-down modes: partial power-down mode and completepower-down mode. In additionto programming the device for eitherof these two power-down modes (througheitherthe PDN_PARTIAL or PDN_COMPLETE bits,respectively),the ADS_PD pinitselfcan be configuredas eithera partialpower-down pinora completepower-down pincontrol.Forexample,ifPDN_PIN_CFG = 0 (default),when theADS_PD pinishigh,thedeviceenterscompletepower-down mode. However,ifPDN_PIN_CFG = 1,when theADS_PD pinishigh,thedeviceenterspartialpower-down mode. The partialpower-down mode functionallowsthe AFE5804 to be rapidlyplacedina low-powerstate.In this mode, most amplifiersinthe signalpath are powered down, whilethe internalreferencesremain active.This configurationensuresthattheexternalbypass capacitorsretaintherespectivecharges,minimizingthewake-up responsetime.The wake-up responseistypicallylessthan50μs,providedthattheclockhas been runningforat least50μs beforenormaloperatingmode resumes.The power-down timeisinstantaneous(lessthan1.0μs). In partialpower-down mode, the parttypicallydissipatesonly 95mW, representinga 76% power reduction compared to the normal operatingmode. Thisfunctioniscontrolledthroughthe ADS_PD and VCA_PD pins, whicharedesignedtointerfacewith3.3V low-voltagelogic.Ifseparatecontrolofthetwo PD pinsisnotdesired, then both can be tiedtogether.In thiscase,the ADS_PD pin shouldbe configuredto operateas a partial power-down mode pin(seefurtherinformationbelow). For normaloperationthePD pinsshouldbe tiedtoa logiclow (0);a high(1)placestheAFE5804 intopartial power-down mode. To achievethe lowestpower dissipationof only52mW, the AFE5804 can be placedincompletepower-down mode. Thismode iscontrolledthroughtheserialinterfaceby settingRegister16 (bitD2) and Register0F (bit D9:D10). In complete power-down mode, all circuits(includingreferences)withinthe AFE5804 are powered-down, and the bypass capacitorsthen discharge.Consequently,the wake-up time from complete power-down mode depends largelyon thetimeneeded torechargethebypass capacitors.Anotherfactorthat affectsthewake-up timeistheelapsedtimethattheAFE5804 spends inshutdownmode.

38 Copyright© 2008–2011,Texas InstrumentsIncorporated

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 LVDS DRIVE PROGRAMMABILITY ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X ILVDS_LCLK <2:0>

11 X X X ILVDS_FRAME <2:0>

X X X ILVDS_DAT <2:0> The LVDS drivestrengthofthebitclock(LCLKP or LCLKM) and theframe clock(FCLKP or FCLKM) can be individuallyprogrammed. The LVDS drivestrengthsof allthe data outputsOUTP and OUTM can also be programmed tothesame value. Allthreedrivestrengths(bitclock,frame clock,and data)are programmed usingsetsof threebits.Table 15 shows an example ofhow thedrivestrengthofthebitclockisprogrammed (themethod issimilarfortheframe clockand datadrivestrengths). Table15.BitClock DriveStrength(1) ILVDS_LCLK <2> ILVDS_LCLK <1> ILVDS_LCLK <0> LVDS DRIVE STRENGTH FOR LCLKP AND LCLKM 0 0 0 3.5mA (default) 0 0 1 2.5mA 0 1 0 1.5mA 0 1 1 0.5mA 1 0 0 7.5mA 1 0 1 6.5mA 1 1 0 5.5mA 1 1 1 4.5mA (1) Currentsettingslowerthan1.5mA arenotrecommended. Copyright© 2008–2011,Texas InstrumentsIncorporated 39

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com LVDS INTERNAL TERMINATION PROGRAMMING ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X EN_LVDS_TERM

1 X X X TERM_LCLK <2:0>

1 X X X TERM_FRAME <2:0>

1 X X X TERM_DAT <2:0>

The LVDS buffershave high-impedancecurrentsources thatdrivethe outputs.When drivingtraceswith characteristicimpedances thatare notperfectlymatched withtheterminationimpedance on thereceiverside, theremay be reflectionsback totheLVDS outputpinsoftheAFE5804 thatcause degradedsignalintegrity.By enablingan internaltermination(betweenthe positiveand negativeoutputs)forthe LVDS buffers,the signal integritycan be significantlyimproved in such scenarios.To set the internalterminationmode, the EN_LVDS_TERM bitshouldbe setto'1'.Once thisbitisset,theinternalterminationvaluesforthebitclock, frame clock,and data bufferscan be independentlyprogrammed usingsetsof threebits.Table 16 shows an example ofhow theinternalterminationoftheLVDS bufferdrivingthebitclockisprogrammed (themethod is similarfortheframe clockand datadrivestrengths).These terminationvaluesare onlytypicalvaluesand can varyby severalpercentagesacrosstemperatureand fromdevicetodevice. Table16.BitClock InternalTermination INTERNAL TERMINATION BETWEEN TERM_LCLK <2> TERM_LCLK <1> TERM_LCLK <0> LCLKP AND LCLKM (Ω) 0 0 0 None 0 0 1 260 0 1 0 150 0 1 1 94 1 0 0 125 1 0 1 80 1 1 0 66 1 1 1 55 LOW-FREQUENCY NOISE SUPPRESSION MODE ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X LFNS_CH <1:4> X X X X LFNS_CH <8:5> The low-frequencynoisesuppressionmode isespeciallyusefulinapplicationswhere good noiseperformanceis desiredinthefrequencyband of0MHz to1MHz (arounddc).Settingthismode shiftsthelow-frequencynoiseof the AFE5804 to approximatelyfS/2,therebymoving the noise flooraround dc to a much lower value. LFNS_CH <8:1> enablesthismode individuallyforeach channel.

40 Copyright© 2008–2011,Texas InstrumentsIncorporated

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 LVDS TEST PATTERNS ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X 0 0 EN_RAMP

0 X 0 DUALCUSTOM_PAT

25 0 0 X SINGLE_CUSTOM_PAT X X BITS_CUSTOM1 <11:10> X X BITS_CUSTOM2 <11:10>

26 X X X X X X X X X X BITS_CUSTOM1 <9:0>

27 X X X X X X X X X X BITS_CUSTOM2 <9:0>

0 X PAT_DESKEW

X 0 PAT_SYNC The AFE5804 can outputa varietyoftestpatternson theLVDS outputs.These testpatternsreplacethenormal ADC dataoutput.SettingEN_RAMP to'1'causes allthechannelstooutputa repeatingfull-scaleramp pattern. The ramp incrementsfrom zero code to full-scalecode instepsof 1LSB everyclockcycle.Afterhittingthe full-scalecode,itreturnsback tozerocode and ramps again. The devicecan alsobe programmed tooutputa constantcode by settingSINGLE_CUSTOM_PAT to'1',and programmingthedesiredcode inBITS_CUSTOM1 <11:0>.Inthismode, BITS_CUSTOM <11:0> taketheplaceof the 12-bitADC data at the output,and are controlledby LSB-firstand MSB-firstmodes inthe same way as normalADC dataare. The devicemay alsobe made totogglebetween two consecutivecodes by programmingDUAL_CUSTOM_PAT to'1'.The two codes arerepresentedby thecontentsofBITS_CUSTOM1 <11:0> and BITS_CUSTOM2 <11:0>. Inadditiontocustom patterns,thedevicemay alsobe made tooutputtwo presetpatterns: 1. Deskew patten:Set usingPAT_DESKEW, thismode replacesthe 12-bitADC outputD <11:0> withthe 010101010101 word. 2. Sync pattern:SetusingPAT_SYNC, thenormalADC word isreplacedby a fixed111111000000 word. Note thatonlyone oftheabove patternsshouldbe activeatany giveninstant. Copyright© 2008–2011,Texas InstrumentsIncorporated 41

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com PROGRAMMABLE GAIN ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME X X X X GAIN_CH4 <3:0> X X X X GAIN_CH3 <3:0> X X X X GAIN_CH2 <3:0> X X X X GAIN_CH1 <3:0> X X X X GAIN_CH5 <3:0> X X X X GAIN_CH6 <3:0> X X X X GAIN_CH7 <3:0> X X X X GAIN_CH8 <3:0> The AFE5804, throughitsregisters,allowsfora digitalgain to be programmed foreach channel.This programmable gaincan be settoachievethefull-scaleoutputcode even witha loweranaloginputswing.The programmablegainnotonlyfillstheoutputcode rangeoftheADC, butalsoenhances theSNR ofthedeviceby usingquantizationinformationfrom some extrainternalbits.The programmable gainforeach channelcan be individuallysetusinga setoffourbits,indicatedas GAIN_CHN <3:0> forChannel N. The gainsettingiscoded in binaryfrom0dB to12dB,as shown inTable17. Table17.Gain SettingforChannel 1 GAIN_CH1 <3> GAIN_CH1 <2> GAIN_CH1 <1> GAIN_CH1 <0> CHANNEL 1 GAIN SETTING 0 0 0 0 0dB 0 0 0 1 1dB 0 0 1 0 2dB 0 0 1 1 3dB 0 1 0 0 4dB 0 1 0 1 5dB 0 1 1 0 6dB 0 1 1 1 7dB 1 0 0 0 8dB 1 0 0 1 9dB 1 0 1 0 10dB 1 0 1 1 11dB 1 1 0 0 12dB 1 1 0 1 Do notuse 1 1 1 0 Do notuse 1 1 1 1 Do notuse

VREFT□=□1.5V□+ VCM 1.5V VREFB□=□1.5V /c45 VCM 1.5V AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 CLOCK, REFERENCE, AND DATA OUTPUT MODES ADDRESS IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME 1 1 X DIFF_CLK 1 1 X EN_DCC 1 1 X EXT_REF_VCM 1 1 X X PHASE_DDR <1:0> 1 1 X BTC_MODE 1 1 X MSB_FIRST 1 1 X EN_SDR 1 1 1 1 FALL_SDR INPUT CLOCK The AFE5804 isconfiguredby defaulttooperatewitha single-endedinputclock;CLKP isdrivenby a CMOS clockand CLKM istiedto'0'.However,by programmingDIFF_CLK to'1',thedevicecan be made towork witha differentialinputclockon CLKP and CLKM. Operatingwitha low-jitterdifferentialclockgenerallyprovidesbetter SNR performance,especiallyatinputfrequenciesgreaterthan30MHz. Incaseswhere thedutycycleoftheinputclockfallsoutsidethe45% to55% range,itisrecommended toenable an internaldutycyclecorrectioncircuit.Enablethiscircuitby settingtheEN_DCC bitto'1'. EXTERNAL REFERENCE The AFE5804 can be made tooperateinexternalreferencemode by pullingtheINT/EXT pinto'0'.Inthismode, theREFT and REFB pinsshouldbe drivenwithvoltagelevelsof2.5V and 0.5V,respectively,and must have enough drivestrengthto drivethe switchedcapacitanceloadingof the referencevoltagesby each ADC. The advantageofusingtheexternalreferencemode isthatmultipleAFE5804 unitscan be made tooperatewiththe same externalreference,therebyimprovingparameterssuch as gain matchingacrossdevices.However, in applicationsthatdo not have an availablehighdrive,differentialexternalreference,the AFE5804 can stillbe drivenwitha singleexternalreferencevoltageon the CM pin.When EXT_REF_VCM isset as '1'(and the INT/EXT pinissetto'0'),theCM pinisconfiguredas an inputpin,and thevoltageson REFT and REFB are generatedas shown inEquation1 and Equation2. (1) (2) Copyright© 2008–2011,Texas InstrumentsIncorporated 43

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com BIT CLOCK PROGRAMMABILITY The outputinterfaceoftheAFE5804 isnormallya DDR interface,withtheLCLK risingedge and fallingedge transitionsinthemiddleofalternatedatawindows.Figure94 shows thisdefaultphase. Figure94. LCLK DefaultPhase The phase of LCLK can be programmed relativeto the output frame clock and data using bits PHASE_DDR <1:0>.Figure95 shows theLCLK phase modes. Figure95. LCLK Phase ProgrammabilityModes

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 Inadditiontoprogrammingthephase ofLCLK intheDDR mode, thedevicecan alsobe made tooperateinSDR mode by settingtheEN_SDR bitto'1'.Inthismode, thebitclock(LCLK) isoutputat12 timestheinputclock,or twicetherateas inDDR mode. Depending on thestateofFALL_SDR, LCLK may be outputineitherofthetwo manners shown inFigure96.As Figure96 illustrates,onlytheLCLK rising(orfalling)edge isused tocapturethe outputdatainSDR mode. Figure96. SDR InterfaceModes The SDR mode does notwork wellbeyond 40MSPS because theLCLK frequencybecomes veryhigh. DATA OUTPUT FORMAT MODES The ADC output,by default,isinstraightoffsetbinarymode. Programming theBTC_MODE bitto'1'invertsthe MSB, and theoutputbecomes binarytwoscomplement mode. Also by default,the firstbitof the frame (followingthe risingedge of FCLKP) isthe LSB of the ADC output. Programming the MSB_FIRST mode invertsthe bitorderinthe word,and the MSB isoutputas the firstbit followingtheFCLKP risingedge. Copyright© 2008–2011,Texas InstrumentsIncorporated 45

(1.4V□to□3.6V) High-Level CS (1.4V□to□3.6V) Device□Ready□for Serial□Register□WriteDevice□Ready□for Data□Conversion Start□of□Clock AVDD1 AVDD2 DVDD AVDD 5V/c45 LVDD ADS_RESET CS FCLK t4 t7 (3.3V,□5.0V) (1.8V) VCA_PD,□ADC_PD (2) Device□Fully Powers□Down Device□Fully Powers□Up 1 s/c109 t (1) WAKE AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING 10μs < t1 < 50ms, 10μs < t2 < 50ms, –10ms < t3 < 10ms, t4 > 10ms, t5 > 100ns,t6 > 100ns,t7 > 10ms, and t8 > 100μs. (1)The AVDDx and LVDD power-onsequence does notmatteras longas –10ms < t3 < 10ms. Similarconsiderationsapplywhileshutting down thedevice. POWER-DOWN TIMING Power-uptimeshown isbased on 1μF bypasscapacitorson thereferencepins.tWAKE isthetimeittakesforthedevicetowake up completelyfrompower-down mode. The AFE5804 has two power-down modes: completepower-down mode and partialpower-down mode. (2)tWAKE ≤ 50μs forcompletepower-down mode. tWAKE ≤ 2μs forpartialpower-down mode (providedthe clockisnot shut offduring power-down). (3)The ADS_PD pinscan be configuredforpartialpower-down mode througha registersetting.

V/I CW□Switch□Matrix Attenuator (VCA) PGA Clamp LPF CW/IOUT OUT OUT T/R Switch VCNTL AFE5804 LVDS Serializer 12-Bit ADC AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 THEORY OF OPERATION of0V to1.2V.WhiletheLNA isdesignedtobe drivenThe AFE5804 is an eight-channel,fullyintegrated from a single-endedsource,the internalTGC signalanalog front-end device. Its integratedLNA, path isdesignedto be fullydifferentialto maximizeattenuator,PGA, LPF, and ADC implementa number dynamic range while also optimizingfor low,ofproprietarycircuitdesigntechniquestospecifically even-orderharmonicdistortion.address the performance demands of medical ultrasoundsystems.Itoffersunparalleledlow-noise CW dopplersignalprocessingisfacilitatedby routing and low-power performance at a high levelof the differentialLNA outputsto V/Iamplifierstages. integration.For the TGC signalpath,each channel The resultingsignalcurrentsof each channel then consistsof a 20dB fixed-gainlow-noiseamplifier connectto an 8×10 switchmatrixthatiscontrolled (LNA), a linear-in-dBvoltage-controlledattenuator through the serialinterfaceand a corresponding (VCA),and a programmablegainamplifier(PGA),as register.The CW outputsare typicallyroutedto a well as a clamping and low-pass filterstage. passive delay linethat allows coherent summing Digitally-controlledthrough the logicinterface,the (beam forming)oftheactivechannelsand additional PGA gaincan be settofourdifferentsettings:20dB, off-chipsignalprocessing,as shown inFigure97. externally-appliedcontrolvoltage(VCNTL )intherange Figure97. FunctionalBlock Diagram Copyright© 2008–2011,Texas InstrumentsIncorporated 47

A1-A8□Attenuator□Stages Control Input VB Q2 Q3 QS C -C Clipping□Amplifiers1 8 Q5 Q6 Q7 Q8 A1 A2 A3 A4 A5 A6 A7 A8 VCNTL AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com LOW-NOISE AMPLIFIER (LNA) The attenuatorisessentiallya variablevoltagedivider As with many high-gainsystems, the front-end thatconsistsof the seriesinputresistor(RS) and amplifieris criticalto achieve a certainoverall eightidenticalshunt FETs placed in paralleland performance level. Using a proprietarynew controlledby sequentiallyactivatedclippingamplifiers architecture,the LNA of the AFE5804 delivers (A1 through A8). Each clippingamplifiercan be exceptionallow-noiseperformance,whileoperating understoodas a specializedvoltagecomparatorwith on a very low quiescent currentcompared to a soft transfercharacteristicand well-controlled CMOS-based architectureswith similar noise outputlimitvoltage.ReferencevoltagesV1 through performances. V8 are equallyspaced over the 0V to 1.2V control approximately2.4V; the signalsource should be Thus, low controlvoltageshave most of the FETs ac-coupledto the LNA inputby an adequately-sized turned on, producingmaximum signalattenuation. capacitor.Internally,theLNA directlydrivestheVCA, Similarly,high controlvoltagesturnthe FETs off, avoiding the typicaldrawbacks of ac-coupled leadingtominimalsignalattenuation.Therefore,each architectures,such as slowoverloadrecovery. FET acts to decrease the shunt resistanceof the voltagedividerformed by R S and the parallelFET network.VOLTAGE-CONTROLLED ATTENUATOR (VCA) The VCA is designed to have a linear-in-dB attenuationcharacteristic;thatis,the average gain lossindB isconstantforeach equalincrementofthe controlvoltage (VCNTL). Figure 98 shows the simplifiedschematicofthisVCA stage. Figure98. Voltage-ControlledAttenuatorSimplifiedSchematic

(+1.65V) T o□ADC Inputs CLAMP LPF AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 PROGRAMMABLE POST-GAIN AMPLIFIER CLAMPING (PGA) To furtheroptimizetheoverloadrecoverybehaviorof Followingthe VCA is a programmable post-gain a completeTGC channel,the AFE5804 integratesa amplifier(PGA). Figure 99 shows a simplified clamping stage, as shown in Figure 100. This schematicofthePGA, includingtheclampingstage. clampingstageprecedesthe low-passfilterinorder The gain of thisPGA can be configuredto four to preventthe filtercircuitfrom being driveninto differentgainsettings:20dB, 25dB, 27dB, and 30dB, overload,the resultof which would be an extended programmablethroughtheserialport;see Table11. recoverytime.The clampinglevelisfixedto clamp thesignalleveltoapproximately2.3VPP differential.The PGA structureconsists of a differential, programmable-gain voltage-to-currentconverter LOW-PASS FILTERstagefollowedby transimpedanceamplifierstobuffer each sideofthedifferentialoutput.Low inputnoiseis The AFE5804 integratesan anti-aliasingfilterinthe alsoa requirementforthePGA designas a resultof formofa programmablelow-passfilter(LPF)foreach the largeamount of signalattenuationthatcan be channel.The LPF isdesignedas a differential,active, appliedin the precedingVCA stage.At minimum second-order filterthat approximates a Bessel VCA attenuation(used forsmallinputsignals),the characteristic,withtypically12dB per octaveroll-off. LNA noisedominates;at maximum VCA attenuation Figure100 shows thesimplifiedschematicofhalfthe (largeinputsignals),the attenuatorand PGA noise differentialactive low-pass filter.Programmable dominates. through the serialinterface,the –3dB frequency cornercan be settoeither12.5MHz or 17MHz. The filterbandwidthissetforallchannelssimultaneously. Figure99. Post-GainAmplifier (SimplifiedSchematic) Figure100. Clamping Stage and Low-Pass Filter(SimplifiedSchematic) Copyright© 2008–2011,Texas InstrumentsIncorporated 49

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com ANALOG-TO-DIGITAL CONVERSION deviceswithouthavingto externallydriveand route 12-bitlevel. The ADC outputgoes to a serializerthatoperates

7pF0.1/c109F CIN /c179 /c1090.1 F VB (+2.4V) IN VBL T/R AFE5804 AFE5804 www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011

APPLICATION INFORMATION

The LNA closed-looparchitectureis internallyANALOG INPUT AND LNA compensated formaximum stabilitywithouttheneed forexternalcompensationcomponents (inductorsorWhile the LNA is designed as a fullydifferential capacitors).At the same time, the totalinputamplifier,itis optimizedto performa single-ended capacitanceis kept to a minimum withonly 16pF.inputto differentialoutputconversion.A simplified Thisarchitectureminimizesany loadingofthesignalschematicofan LNA channelisshown inFigure101. source that may otherwise lead to aA biasvoltage(VB) of +2.4V isinternallyappliedto frequency-dependentvoltagedivider.Moreover,thetheLNA inputsthrough8kΩ resistors.Inaddition,the closed-loopdesignyieldsverylow offsetsand offsetdedicatedsignalinput(IN pin)includesa pairof drift;thisconsiderationisimportantbecause theLNAback-to-backdiodes that provide a coarse input directlydrives the subsequent voltage-controlledclampingfunctionin case the inputsignalrisesto attenuator.very large levels, exceeding 0.6VPP . This Frequency Over R S in the TypicalCharacteristics).As Figure101 alsoshows, the complementaryLNA The optimalnoise power matching is achievedforinput(VBL pin)is internallydecoupled by a small sourceimpedances of around 200Ω. Furtherdetailscapacitor.Furthermore,for each inputchannel,a of the AFE5804 inputnoiseperformanceare shownseparate VBL pin is brought out for external intheTypicalCharacteristicgraphs.bypassing.This bypassingshould be done with a small,0.1μF (typical)ceramic capacitorplaced in Table18.Noise Figureversuscloseproximityto each VBL pin.Attentionshouldbe Source Resistance(RS)at2MHzgivento providea low-noiseanalog ground forthis bypass capacitor.A noisy ground potentialmay R S (Ω) NOISE FIGURE (dB) cause noise to be pickedup and injectedintothe 50 2.1signalpath,leadingtohighernoiselevels. 200 1.1 400 1.2 1000 1.9 Figure101. LNA Channel (SimplifiedSchematic) Copyright© 2008–2011,Texas InstrumentsIncorporated 51

+5V AFE5804 3k/c87 C2 /c179 /c109 0.1 FC1 3k/c87 RTBAS40

0.1 F/c109

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com OVERLOAD RECOVERY ±0.3V can significantlyreduce the overalloverload ultrasoundreceivechannel front-endthatincludes As Figure102 shows, the front-endcircuitryshould typicalexternaloverloadprotectionelements.Here, be capacitivelycoupledtotheLNA signalinput(IN). fourhigh-voltageswitchingdiodesareconfiguredina ThiscouplingensuresthattheLNA inputbiasvoltage bridgeconfigurationand form the transmit/receive of+2.4V ismaintainedand decoupledfromany other (T/R)switch.Duringthetransmitperiod,highvoltage biasingvoltagebeforetheLNA. the over-voltageto small levels,Schottkydiodes (such as the BAS40 series by Infineon®) are commonly used.For example,clampingto levelsof Figure102. TypicalInputOverload ProtectionCircuitofan UltrasoundSystem

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 VCA —GAIN CONTROL When the AFE5804 operates in CW mode, the and minimum attenuation(maximum gain)atVCNTL = 1.2V.Table19 shows thenominalgainsforeach of the fourPGA gain settings.The totalgain range is typically46dB and remainsconstantindependentof thePGA selected;theMax Gain column reflectsthe absolutegainofthefullsignalpathcomprisedofthe fixedLNA gainof20dB and theprogrammable PGA gain. Table19.Nominal Gain ControlRanges forEach oftheFour PGA Gain Settings MIN GAIN MAX GAIN AT PGA GAIN AT VCNTL = 0V VCNTL = 1.2V 20dB –5.5dB 40.5dB 25dB –1.0dB 45.0dB 27dB 1.0dB 47.0dB 30dB 3.0dB 49.0dB As previouslydiscussed,the VCA architectureuses eightattenuatorsegments thatare equallyspaced in Figure103. ExternalFilteringoftheVCNTL Inputorder to approximatethe linear-in-dBgain-control slope.This approximationresultsin a monotonic slope;gainrippleistypicallylessthan±0.5dB. CW DOPPLER PROCESSINGThe AFE5804 gain-controlinput has a –3dB The AFE5804 integratesmany of the elementsbandwidth of approximately1.5MHz. This wide necessaryto allowforthe implementationof a CWbandwidth,althoughusefulinmany applications,can dopplerprocessingcircuit,such as a V/Iconverterforallow high-frequencynoise to modulate the gain each channeland a cross-pointswitchmatrixwithancontrolinput.In practice,thismodulationcan easily 8-inputinto10-output(8×10)configuration.be avoidedby additionalexternalfiltering(RF and C F) of the controlinput,as Figure103 shows. Stepping InordertoswitchtheAFE5804 fromthedefaultTGCthecontrolvoltagefrom 0V to1.2V,thegaincontrol mode operationintoCW mode, bitD5 ofthecontrolresponse time istypicallylessthan 500ns to settle registermust be updatedtolow ('0').Thissettingalsowithin10% of the finalsignallevelof a 1VPP enablesaccess to allotherregistersthatdetermine(–6dBFS) output. theswitchmatrixconfiguration(seetheInputRegister BitMap tables).InordertoprocessCW signals,theThe controlvoltageinput(VCNTL pin)representsa LNA internallyfeeds intoa differentialV/Iamplifierhigh-impedanceinput.MultipleAFE5804 devicescan stage.The transconductanceof the V/Iamplifierisbe connected in parallelwithno significantloading typically13.5mA/V witha 100mV PP inputsignal.ForeffectsusingtheVCNTL pinofeach device.Note that properoperation,theCW outputsmust be connectedwhen theVCNTL pinisleftunconnected,itfloatsup to toan externalbiasvoltageof+2.5V.Each CW outputa potentialof about +3.7V. For any voltagelevel isdesignedtosinka smalldc currentof0.9mA, andabove 1.2V and up to 5.0V,the VCA continuesto can delivera signalcurrentup to2.9mAPP .operateatitsminimum attenuationlevel;however,it isrecommended tolimitthevoltagetoapproximately 1.5Vorless. Copyright© 2008–2011,Texas InstrumentsIncorporated 53

(+2.5V) Amplifier I□and□Q Channel ADC AFE5804 CW□Out 8□In□By□10□Out CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 AFE5804 CW□Out 8□In□By□10□Out CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 Passive Delay Line Clock L□=□220 H/c109 AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com outputsare typicallyroutedto a passiveLC delay line,allowingcoherentsumming ofthesignals. Figure104. Conceptual CW Doppler SignalPath Using CurrentSumming and a PassiveDelay Linefor Beam-Forming

Differential□Sine-Wave, PECL,□or□LVDS□Clock□Input CMOS□Single-Ended Clock CLKP CLKM CMOS□Clock□Input www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 CLOCK INPUT The eightchannels on the device operatefrom a singleclockinput.To ensurethattheaperturedelay and jitterarethesame forallchannels,theAFE5804 uses a clock tree network to generate individual samplingclockstoeach channel.The clockpathsfor allthechannelsarematched fromthesourcepointto the samplingcircuit.This architectureensures that the performance and timingfor allchannels are identical.The use of the clock tree for matching introducesan aperturedelaythatisdefinedas the delaybetween therisingedge ofFCLK and theactual instantof sampling.The aperturedelaysforallthe channelsare matched tothebestpossibleextent.A mismatch of ±20ps (±3σ) could existbetween the apertureinstantsof the eightADCs withinthe same Figure106. InternalClock Buffer chip.However, the aperturedelaysof ADCs across two differentchips can be several hundred picosecondsapart. The AFE5804 can operate either in CMOS single-endedclockmode (defaultisDIFF_CLK = 0) ordifferentialclockmode (SINE,LVPECL, orLVDS). In the single-endedclock mode, CLKM must be forcedto0VDC ,and thesingle-endedCMOS applied on theCLKP pin.Figure105 shows thisoperation. Figure107. DifferentialClock DrivingCircuit (DIFF_CLK = 1) Figure105. Single-EndedClock DrivingCircuit (DIFF_CLK = 0) When configuredfor the differentialclock mode (registerbitDIFF_CLK = 1)theAFE5804 clockinputs Figure108. Single-EndedClock DrivingCircuitcan be drivendifferentially(SINE,LVPECL, orLVDS) When DIFF_CLK = 1withlittleor no differencein performancebetween them, or with a single-ended(LVCMOS). The For best performance,the clock inputsmust becommon-mode voltageof the clockinputsisset to driven differentially,reducing susceptibilitytoVCM using internal5kΩ resistors,as shown in common-mode noise. For high input frequencyFigure 106. This method allows using sampling,itisrecommended to use a clocksourcetransformer-coupleddrivecircuitsfora sine wave withvery low jitter.Bandpass filteringof the clockclockor ac-couplingforLVPECL and LVDS clock sourcecan helpreducetheeffectofjitter.Ifthedutysources,as shown in Figure107 and Figure108. cycledeviatesfrom50% by more than2% or3%, itisWhen operatingin the differentialclockmode, the recommended toenabletheDCC throughregisterbitsingle-endedCMOS clockcan be ac-coupledto the EN_DCC.CLKP input,withCLKM connectedto ground witha 0.1μF capacitor,as Figure108 shows. Copyright© 2008–2011,Texas InstrumentsIncorporated 55

VREFT□=□1.5V□+ VCM 1.5V VREFB□=□1.5V /c45 VCM 1.5V REFT REFB ISET 0.1 F/c109 2.2 F/c109 56.2k/c87 2.2 F/c109 0.1 F/c109 AFE5804 + + AFE5804 SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com REFERENCE CIRCUIT The device also supports the use of external matches towithin50mV ofVCM .Allbiascurrentsrequiredfortheinternaloperationof REFB in thismode are given by Equation3 andBufferingtheinternalbandgap voltagealsogenerates Equation4:the common-mode voltageVCM , which isset to the midlevelof REFT and REFB. It is meant as a referencevoltagetoderivetheinputcommon-mode if (3)the inputisdirectlycoupled.Itcan alsobe used to derivethe referencecommon-mode voltagein the externalreferencemode. Figure 109 shows the (4) suggesteddecouplingforthereferencepins. The stateof the referencevoltageinternalbuffers duringvariouscombinationsofthePD, INT/EXT, and EXT_REF_VCM registerbitsisdescribedinTable20. Figure109. Suggested Decoupling on theReferencePins

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011 Table20.StateofReferenceVoltagesforVariousCombinations ofPD and INT/EXT REGISTER BIT INTERNAL BUFFER STATE PD 0 0 1 1 0 0 1 1 INT/EXT 0 1 0 1 0 1 0 1 EXT_REF_VCM 0 0 0 0 1 1 1 1 CM pin 1.5V 1.5V 1.5V 1.5V Force Do notuse Force Do notuse (1) Weakly forcedwithreducedstrength. Poor RMS jitter(greaterthan100ps),combined withPOWER SUPPLIES inadequatepower-supplydesign(forexample,supply voltagedropsand rippleincreases),can affectLVDSThe AFE5804 operateson threesupplyrails:a digital timing.As a result,occasionalglitchesmight be1.8V supply,and the3.3V and 5V analogsupplies.At observed on the AFE5804 outputs. If thisinitialpower-up,thepartisoperationalinTGC mode, phenomenon is observed,or ifthe clockjitterandwith the registersin the respective default LVDD noiseareconcernsinthesystem,theregistersconfigurations(seeTable3). inTable21 can be writtenas partoftheinitializationInTGC mode, onlytheVCA (attenuator)draws a low sequence inordertostabilizeLVDS clocktimingandcurrent(typically7mA) fromthe5V supply.Switching SNR performance.intotheCW mode, theinternalV/I-amplifiersarethen powered from the 5V railas well,raisingthe Table21.Address and Data inHexadecimaloperatingcurrenton the5V rail.Atthesame time,the ADDRESS DATApost-gainamplifiers(PGA) are beingpowered down, 01 0010htherebyreducingthecurrentconsumptionon the3.3V rail(referto the ElectricalCharacteristicstablefor D1 0140h detailson TGC mode and CW mode current DA 0001h consumption). E1 0020h AllanalogsupplyrailsfortheAFE5804 shouldbe low 02 0080h noise,includingthe 3.3V digitalsupplyDVDD that 01 0000hconnectstotheinternallogicblocksoftheVCA within b. With referencetotheLVDS TimingDiagram and Definition of Setup and Hold Times,CLOCK JITTER,POWER NOISE, SNR, AND LCLKP/LCLKM shiftby about 100ps to the leftLVDS TIMING relativeto CLK and OUTP/OUTM. This shift As explainedin ApplicationNote SLYT075 , ADC causes the data setuptimeto reduce by 100ps clockjittercan degradeADC performance.Therefore, and thedataholdtimetoincreaseby 100ps. jitter,theSNR oftheAFE5804 may be degraded as Power-supply noise can usuallybe minimized if wellas the LVDS timingstability.In addition,clean grounding,bypassing,and PCB layout are well and stablepower suppliesare always preferredto managed. Some guidelinescan be found in the maximizetheAFE5804 SNR and ensureLVDS timing Grounding and Bypassing and Board Layout stability. sections. Copyright© 2008–2011,Texas InstrumentsIncorporated 57

SBOS442C –JUNE 2008–REVISED OCTOBER 2011 www.ti.com GROUNDING AND BYPASSING High-speed mixed signaldevices are sensitiveto Allbypassingand power suppliesforthe AFE5804 shouldbe referencedtothisanaloggroundplane.All BOARD LAYOUT AFE5804 itself. In orderto maintainproperLVDS timing,allLVDS tracesshouldfollowa controlledimpedance designThe AFE5804 internallygenerates a number of (forexample,100Ω differential).Inaddition,allLVDSreferencevoltages,such as the biasvoltages(VB1 tracelengthsshouldbe equaland symmetrical;itisthroughVB6). Note thatinorderto achieveoptimal recommended to keep tracelengthvariationslesslow-noise performance, the VB1 pin must be than150mil(0.150inor3,81mm).bypassed witha capacitorvalueofatleast1μF; the recommended value for thisbypass capacitoris Additionaldetailson PCB layouttechniquescan be 2.2μF. All other designed referencepins can be found in the Texas InstrumentsApplicationReport bypassed with smallercapacitorvalues,typically MicroStar BGA Packaging Reference Guide 0.1μF. For best resultschoose low-inductance (SSYZ015B), which can be downloaded from the TI ceramicchipcapacitors(size402)and placethem as web site(www.ti.com). closeas possibletothedevicepinsas possible.

www.ti.com SBOS442C –JUNE 2008–REVISED OCTOBER 2011

REVISION HISTORY

NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionB (November 2008)toRevisionC Page Changes from RevisionA (September 2008)toRevisionB Page Copyright© 2008–2011,Texas InstrumentsIncorporated 59

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AFE5804ZCF Active Production NFBGA (ZCF) | 135 160 | JEDEC TRAY (10+1) Yes SNAGCU Level-3-260C-168 HR 0 to 70 AFE5804 AFE5804ZCF.A Active Production NFBGA (ZCF) | 135 160 | JEDEC TRAY (10+1) Yes SNAGCU Level-3-260C-168 HR 0 to 70 AFE5804 AFE5804ZCF.B Active Production NFBGA (ZCF) | 135 160 | JEDEC TRAY (10+1) Yes SNAGCU Level-3-260C-168 HR 0 to 70 AFE5804 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) AFE5804ZCF ZCF NFBGA 135 160 10 x 16 150 315 135.9 7620 19.2 13.5 10.35 Pack Materials-Page 1

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Product Information

AFE5804ZCFT specifications and overview.

Summary

FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.89nV/√Hz, 12-Bit, 40MSPS, 101mW/Channel REVISED OCTOBER 2011

Description

FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.89nV/√Hz, 12-Bit, 40MSPS, 101mW/Channel REVISED OCTOBER 2011

Source title AFE5804ZCFT Datasheet(PDF) - Texas Instruments

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00 X S_RST

16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

34 Copyright© 2008–2011,Texas InstrumentsIncorporated

36 Copyright© 2008–2011,Texas InstrumentsIncorporated

0 X PDN_COMPLETE

38 Copyright© 2008–2011,Texas InstrumentsIncorporated

11 X X X ILVDS_FRAME <2:0>

1 X X X TERM_LCLK <2:0>

1 X X X TERM_FRAME <2:0>

1 X X X TERM_DAT <2:0>

40 Copyright© 2008–2011,Texas InstrumentsIncorporated

0 X 0 DUALCUSTOM_PAT

26 X X X X X X X X X X BITS_CUSTOM1 <9:0>

27 X X X X X X X X X X BITS_CUSTOM2 <9:0>

0 X PAT_DESKEW

42 Copyright© 2008–2011,Texas InstrumentsIncorporated

44 Copyright© 2008–2011,Texas InstrumentsIncorporated

46 Copyright© 2008–2011,Texas InstrumentsIncorporated

48 Copyright© 2008–2011,Texas InstrumentsIncorporated

50 Copyright© 2008–2011,Texas InstrumentsIncorporated

APPLICATION INFORMATION

0.1 F/c109

52 Copyright© 2008–2011,Texas InstrumentsIncorporated

54 Copyright© 2008–2011,Texas InstrumentsIncorporated

56 Copyright© 2008–2011,Texas InstrumentsIncorporated

58 Copyright© 2008–2011,Texas InstrumentsIncorporated

REVISION HISTORY

AFE5804ZCFT specifications and overview.

More parts from the same family.