AFE5803ZCF.B

Texas Instruments

Fully Integrated, 8-Channel Ultrasound Analog Front End, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 158 mW/CH REVISED JANUARY 2012

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 FullyIntegrated,8-ChannelUltrasoundAnalogFrontEnd, 0.75nV/rtHz,14/12-Bit,65MSPS,158mW/CH Check forSamples: AFE5803 1FEATURES DESCRIPTION The AFE5803 isa highlyintegratedAnalogFront-End• 8-ChannelComplete Analog Front-End (AFE) solutionspecificallydesigned forultrasound– LNA, VCAT, PGA, LPF, ADC systems in which high performanceand smallsize

Programmable Gain Low-Noise Amplifier are required.The AFE5803 integratesa complete (LNA) time-gain-control(TGC) imagingpath.Italsoenables users to select one of various power/noise– 24/18/12dB Gain combinations to optimize system performance.– 0.25/0.5/1VPP LinearInputRange Therefore,the AFE5803 is a suitableultrasound – 0.63/0.7/0.9nV/rtHzInputReferredNoise analogfrontend solutionforportablesystems. – Programmable ActiveTermination The AFE5803 containseightchannels of voltage
40 dB Low Noise VoltageControlled controlledamplifier(VCA),14/12-bitAnalog-to-Digital Converter (ADC). The VCA includesLow noiseAttenuator(VCAT) Amplifier(LNA), Voltage controlledAttenuator• 24/30dB Programmable Gain Amplifier(PGA) (VCAT), Programmable Gain Amplifier(PGA), and• 3rd Order LinearPhase Low-Pass Filter(LPF) Low-Pass Filter (LPF). The LNA gain is – 10,15,20,30 MHz programmable to support250 mV PP to 1 VPP input signals.Programmable activeterminationis also• 14-bitAnalog toDigitalConverter(ADC) supportedby the LNA. The ultra-lownoise VCAT– 77 dBFS SNR at65 MSPS providesan attenuationcontrolrange of 40 dB and – LVDS Outputs improves overalllow gain SNR which benefits harmonicimagingand near fieldimaging.The PGA• Noise/Power Optimizations(FullChain) providesgainoptionsof24 dB and 30 dB. Beforethe– 158 mW/CH at0.75nV/rtHz,65 MSPS ADC, a LPF can be configuredas 10 MHz, 15 MHz, – 101 mW/CH at1.1nV/rtHz,40 MSPS 20 MHz or30 MHz tosupportultrasoundapplications with differentfrequencies.The high-performance• ExcellentDevice-to-DeviceGain Matching 14bit/65MSPS ADC in the AFE5803 achieves– ±0.5dB (Typical)and ±0.9dB (Max) 77dBFS SNR. ItensuresexcellentSNR atlow chain
Low Harmonic Distortion gain.The ADC ’s LVDS outputsenableflexiblesystem integrationdesiredforminiaturizedsystems.• Fastand ConsistentOverload Recovery
Small Package: 15 mm x 9 mm, 135-BGA The AFE5803 isavailableina 15mm × 9mm, 135-pin BGA package and itisspecifiedforoperationfrom 0°C to 85°C. Itisalsopin-to-pincompatibleto theAPPLICATIONS AFE5807, AFE5808 and AFE5808A.• MedicalUltrasoundImaging
NondestructiveEvaluationEquipments Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

24, 30dB 3rd LP Filter 10, 15, 20,

30 MHz

AFE5803 (1 of 8 Channels) 14Bit ADC LVDS ReferenceReference Differential TGC Vcntl EXT/INT REFs SPI OUT VCAT AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. Figure1. Block Diagram PACKAGING/ORDERING INFORMATION (1) TRANSPORT MEDIA,PRODUCT PACKAGE TYPE OPERATING ORDERING NUMBER QUANTITY AFE5803 ZCF 0°C to85°C AFE5803ZCF Tray,160 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com.

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) VALUE UNIT MIN MAX AVDD –0.3 3.9 V AVDD_ADC –0.3 2.2 VSupplyvoltage range AVDD_5V –0.3 6 V DVDD –0.3 2.2 V Voltagebetween AVSS and LVSS –0.3 0.3 V Voltageatanaloginputsand digitalinputs –0.3 min [3.6,AVDD+0.3] V Peak soldertemperature(2) 260 °C Maximum junctiontemperature(TJ),any condition 105 °C Storagetemperaturerange –55 150 °C Operatingtemperaturerange 0 85 °C Human Body Model (HBM) 2000 V ESD Ratings Charged DeviceModel (CDM) 500 V (1) Stressesabove thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions" isnotimpliedExposuretoabsolutemaximum ratedconditionsforextendedperiodsmay degradedevicereliability. (2) DevicecomplieswithJSTD-020D. THERMAL INFORMATION AFE5803 THERMAL METRIC (1) BGA UNITS

135 PINS

θJA Junction-to-ambientthermalresistance 34.1 θJCtop Junction-to-case(top)thermalresistance 5 θJB Junction-to-boardthermalresistance 11.5 °C/W ψJT Junction-to-topcharacterizationparameter 0.2 ψJB Junction-to-boardcharacterizationparameter 10.8 θJCbot Junction-to-case(bottom)thermalresistance n/a (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . RECOMMENDED OPERATING CONDITIONS PARAMETER MIN MAX UNIT AVDD 3.15 3.6 V AVDD_ADC 1.7 1.9 V DVDD 1.7 1.9 V AVDD_5V 4.75 5.5 V AmbientTemperature,TA 0 85 °C Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):AFE5803

SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com DEVICE INFORMATION PIN CONFIGURATION Top View ZCF (BGA-135) 1 2 3 4 5 6 7 8 9 A AVDD INP8 INP7 INP6 INP5 INP4 INP3 INP2 INP1 B CM_BYP ACT8 ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 C AVSS INM8 INM7 INM6 INM5 INM4 INM3 INM2 INM1 D AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD AVDD E CH7_TEST_OUTP CH7_TEST_OUTM AVSS AVSS AVSS AVSS AVSS AVDD AVDD F CH7_BUFFER_OUTM CH7_BUFFER_OUTP AVSS AVSS AVSS AVSS AVSS DNC DNC G AVSS AVSS AVSS AVSS AVSS AVSS AVSS DNC DNC H CH8_BUFFER_OUTM CH8_BUFFER_OUTP AVSS AVSS AVSS AVSS AVSS PDN_GLOBAL RESET J CH8_TEST_OUTP CH8_TEST_OUTM AVSS AVSS AVSS AVDD_ADC AVDD_ADC PDN_VCA SCLK K AVDD AVDD_5V VCNTLP VCNTLM VHIGH AVSS DNC AVDD_ADC SDATA L CLKP_ADC CLKM_ADC AVDD_ADC REFM DNC DNC DNC PDN_ADC SEN M AVDD_ADC AVDD_ADC VREF_IN REFP DNC DNC DNC DNC SDOUT N D8P D8M DVDD DNC DVSS DNC DVDD D1M D1P P D7M D6M D5M FCLKM DVSS DCLKM D4M D3M D2M R D7P D6P D5P FCLKP DVSS DCLKP D4P D3P D2P PIN FUNCTIONS PIN

DESCRIPTION

NO. NAME Informationsection. A1,D8, D9, E8, AVDD 3.3V AnalogsupplyforLNA, VCAT, PGA, LPF blocks. E9,K1 K2 AVDD_5V 5 V AnalogsupplyforLNA, VCAT, PGA, LPF blocks. J6,J7,K8,L3, AVDD_ADC 1.8V Analogpower supplyforADC. M1, M2 C1, D1~D7, E3~E7, F3~F7, G1~G7, AVSS Analogground. H3~H7,J3~J5, NegativeinputofdifferentialADC clock.Inthesingle-endclockmode, itcan be tiedtoGND directlyorL2 CLKM_ADC througha 0.1µF capacitor. PositiveinputofdifferentialADC clock.Inthesingle-endclockmode, itcan be tiedtoclocksignalL1 CLKP_ADC directlyorthrougha 0.1µF capacitor. Biasvoltageand bypasstoground.≥1µF isrecommended. To suppresstheultralowfrequencynoise,B1 CM_BYP 10µF can be used. E2 CH7_TEST_OUTM CH7 PGA negativeoutputwhen PGA testmode isenabled.Can be floatedifnotused. E1 CH7_TEST_OUTP CH7 PGA positiveoutputwhen PGA testmode isenabled.Can be floatedifnotused. Negativedifferentialoutputforthebufferamplifierwhen PGA testmode isenabled.Can be floatedifnotF1 CH7_BUFFER_OUTM used.See theTEST MODES intheapplicationinformationsection. Positivedifferentialoutputforthebufferamplifierwhen PGA testmode isenabled.Can be floatedifnotF2 CH7_BUFFER_OUTP used.See theTEST MODES intheapplicationinformationsection. J2 CH8_TEST_OUTM CH8 PGA negativeoutputwhen PGA testmode isenabled.Can be floatedifnotused. J1 CH8_TEST_OUTP CH8 PGA positiveoutputwhen PGA testmode isenabled.Can be floatedifnotused. Negativedifferentialoutputforthebufferamplifierwhen PGA testmode isenabled.Can be floatedifnotH1 CH8_BUFFER_OUTM used.See theTEST MODES intheapplicationinformationsection. Positivedifferentialoutputforthebufferamplifierwhen PGA testmode isenabled.Can be floatedifnotH2 CH8_BUFFER_OUTP used.See theTEST MODES intheapplicationinformationsection. N8, P9~P7, D1M~D8M ADC CH1~8 LVDS negativeoutputsP3~P1, N2 N9, R9~R7, D1P~D8P ADC CH1~8 LVDS positiveoutputsR3~R1, N1 P6 DCLKM LVDS bitclock(7x)negativeoutput

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 PIN FUNCTIONS (continued) PIN NO. NAME R6 DCLKP LVDS bitclock(7x)positiveoutput F8,F9,G8, G9, K7, DNC Do notconnect.Must leavefloatedL5~L7,M5~M8, N4, N6 N3, N7 DVDD ADC digitaland I/Opower supply,1.8V N5, P5,R5 DVSS ADC digitalground P4 FCLKM LVDS frameclock(1X)negativeoutput R4 FCLKP LVDS frameclock(1X)positiveoutput CH1~8 complimentaryanaloginputs.Bypass togroundwith≥ 0.015µF capacitors.The HPF responseC9~C2 INM1 …INM8 oftheLNA depends on thecapacitors. L8 PDN_ADC ADC partial(fast)power down controlpinwithan internalpulldown resistorof100 kΩ.ActiveHigh. J8 PDN_VCA VCA partial(fast)power down controlpinwithan internalpulldown resistorof20 kΩ.ActiveHigh. Global(complete)power-down controlpinfortheentirechipwithan internalpulldown resistorof20kΩ.H8 PDN_GLOBAL ActiveHigh. 0.5V referenceoutputintheinternalreferencemode. Must leavefloatedintheinternalreferencemode.L4 REFM Addingtestpointon PCB isrecommended formonitoringthereferenceoutput. 1.5V referenceoutputintheinternalreferencemode. Must leavefloatedintheinternalreferencemode.M4 REFP Addingtestpointon PCB isrecommended formonitoringthereferenceoutput. H9 RESET Hardware resetpinwithan internalpull-downresistorof20 kΩ.Activehigh. J9 SCLK Serialinterfaceclockinputwithan internalpull-downresistorof2 0kΩ K9 SDATA Serialinterfacedatainputwithan internalpull-downresistorof20 kΩ M9 SDOUT Serialinterfacedatareadout.Highimpedance when readoutisdisabled. L9 SEN Serialinterfaceenablewithan internalpullup resistorof20 kΩ.Activelow. K4 VCNTLM Negativedifferentialattenuationcontrolpin. K3 VCNTLP Positivedifferentialattenuationcontrolpin K5 VHIGH Biasvoltage;bypasstogroundwith≥1µF. M3 VREF_IN ADC 1.4V referenceinputintheexternalreferencemode; bypasstogroundwith0.1 µF. F8,F9,G8, G9, K7,L5~L7, DNC Do notconnect.Must leavefloatedM5~M8, N4, Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):AFE5803

u 8CH_SNR- 10N 10 1 1C = x - 1CH_SNRN + N 56 7 -C 1010 AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com

ELECTRICAL CHARACTERISTICS

AVDD_5 V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V,AC-coupledwith0.1µF atINP and bypassedtoground with15nF atINM, No activetermination,VCNTL = 0 V,fIN = 5 MHz, LNA = 18 dB,PGA = 24 dB,14Bit,sample rate= 65 MSPS, LPF Filter= 15 MHz, lownoisemode, VOUT = –1 dBFS, ADC configuredininternalreferencemode, single-ended VCNTL mode, VCNTLM = GND, atambienttemperatureTA = 25°C, unlessotherwisenoted.Min and max valuesare specifiedacrossfull-temperaturerangewithAVDD_5 V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V PARAMETER TEST CONDITION MIN TYP MAX UNITS TGC FULL SIGNAL CHANNEL (LNA+VCAT+LPF+ADC) Inputreferredcurrentnoise Low NoiseMode/Medium Power Mode/Low Power Mode 2.7/2.1/2 pA/rtHz Rs = 200 Ω,200 Ω activetermination,PGA = 24dB,LNA = 12/18/24dB 3.85/2.4/1.8 dB NF Noisefigure Rs = 100 Ω,100 Ω activetermination,PGA = 24dB,LNA = 12/18/24dB 5.3/3.1/2.3 dB VMAX Maximum LinearInputVoltage LNA gain= 24/18/12dB 250/500/1000 mV PP VCLAMP Clamp Voltage Reg52[10:9]= 0,LNA = 24/18/12dB 350/600/1150 Low noisemode 24/30 PGA Gain dB Medium/Low power mode 24/28.5 LNA = 24 dB,PGA = 30 dB,Low noisemode 54 Totalgain LNA = 2 4dB,PGA = 30 dB,Med power mode 52.5 dB LNA = 24 dB,PGA = 30 dB,Low power mode 52.5 Ch-CH NoiseCorrelationFactorwithout Summing of8 channels 0Signal(1) Fullband (VCNTL = 0/0.8) 0.15/0.17Ch-CH NoiseCorrelationFactorwith Signal(1) 1MHz band overcarrier(VCNTL= 0/0.8) 0.18/0.75 VCNTL = 0.6V(22dB totalchannelgain) 68 70 SignaltoNoiseRatio(SNR) VCNTL = 0,LNA = 18 dB,PGA =24 dB 59.3 63 dBFS VCNTL = 0,LNA = 24 dB,PGA = 24 dB 58 SNR over2 MHz band aroundcarrieratVCNTL = 0.6V (22 dB totalNarrow Band SNR 75 77 dBFSgain) InputCommon-mode Voltage AtINP and INM pins 2.4 V 8 kΩ Inputresistance Presetactiveterminationenabled 50/100/200/400 Ω Inputcapacitance 20 pF InputControlVoltage VCNTLP -VCNTLM 0 1.5 V Common-mode voltage VCNTLP and VCNTLM 0.75 V Gain Range -40 dB Gain Slope VCNTL = 0.1V to1.1V 35 dB/V InputResistance Between VCNTLP and VCNTLM 200 KΩ InputCapacitance Between VCNTLP and VCNTLM 1 pF TGC Response Time VCNT L= 0 V to1.5V stepfunction 1.5 µs 3rdorder-Low-passFilter 10,15,20,30 MHz Settlingtimeforchange inLNA gain 14 µs Settlingtimeforchange inactive 1 µsterminationsetting (1) Noisecorrelationfactorisdefinedas Nc/(Nu+Nc),where Nc isthecorrelatednoisepower insinglechannel;and Nu istheuncorrelated noisepower insinglechannel.Itsmeasurement followsthebelowequation,inwhichtheSNR ofsinglechannelsignaland theSNR of summed eightchannelsignalaremeasured.

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5 V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V,AC-coupledwith0.1µF atINP and bypassedtoground with15nF atINM, No activetermination,VCNTL = 0 V,fIN = 5 MHz, LNA = 18 dB,PGA = 24 dB,14Bit,sample rate= 65 MSPS, LPF Filter= 15 MHz, lownoisemode, VOUT = –1 dBFS, ADC configuredininternalreferencemode, single-ended VCNTL mode, VCNTLM = GND, atambienttemperatureTA = 25°C, unlessotherwisenoted.Min and max valuesare specifiedacrossfull-temperaturerangewithAVDD_5 V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V PARAMETER TEST CONDITION MIN TYP MAX UNITS AC ACCURACY LPF Bandwidthtolerance ±5% CH-CH groupdelayvariation 2 MHz to15 MHz 2 ns CH-CH Phase variation 15 MHz signal 11 Degree 0 V < VCNTL < 0.1V (Dev-to-Dev) ±0.5 Gain matching dB 1.1V < VCNTL < 1.5V(Dev-to-Dev) ±0.5 Gain matching Channel-to-Channel ±0.25 dB Outputoffset Vcntl= 0,PGA = 30 dB,LNA = 24 dB –75 75 LSB AC PERFORMANCE Fin= 2 MHz; VOUT = -1dBFS –60 Fin= 5 MHz; VOUT = -1dBFS –60 Fin= 5 MHz; VIN= 500 mVpp,HD2 Second-HarmonicDistortion dBc–55VOUT = –1dBFS, LNA = 18dB,VCNTL =0.88V Fin= 5 MHz; Vin= 250 mVpp, –55VOUT =–1 dBFS, LNA = 24dB,VCNTL = 0.88V Fin= 2 MHz; VOUT = –1dBFS –55 Fin= 5 MHz; VOUT = –1dBFS –55 Fin= 5 MHz; VIN = 500 mVpp,HD3 Third-HarmonicDistortion dBc–55VOUT = –1 dBFS, LNA = 18 dB,VCNTL = 0.88V Fin= 5 MHz; VIN = 2 50 mVpp, –55VOUT = –1 dBFS, LNA = 24 dB,VCNTL = 0.88V Fin= 2 MHz; VOUT =–1 dBFS –55 THD TotalHarmonicDistortion dBc Fin= 5 MHz; VOUT =–1 dBFS –55 f1= 5 MHz at–1dBFS,IMD3 Intermodulationdistortion –60 dBcf2= 5.01MHz at–27 dBFS XTALK Cross-talk Fin= 5 MHz; VOUT = –1 dBFS –65 dB Phase Noise 1 kHz off5 MHz (VCNTL =0V) –132 dBc/Hz LNA InputReferredVoltageNoise Rs = 0 Ω,f= 2MHz, Rin= HighZ,Gain = 24/18/12dB 0.63/0.70/0.9 nV/rtHz High-PassFilter -3dB Cut-offFrequency 50/100/150/200 KHz LNA linearoutput 4 VPP VCAT+ PGA VCAT InputNoise 0dB/-40dB Attenuation 2/10.5 nV/rtHz PGA InputNoise 24 dB/30dB 1.75 nV/rtHz -3dB HPF cut-offFrequency 80 KHz ADC SPECIFICATIONS Sample rate 10 65 MSPS SNR Signal-to-noiseratio IdlechannelSNR ofADC 14b 77 dBFS REFP 1.5 V Internalreferencemode REFM 0.5 V VREF_IN Voltage 1.4 V Externalreferencemode VREF_IN Current 50 µA ADC inputfull-scalerange 2 Vpp LVDS Rate 65MSPS at14 bit 910 Mbps Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):AFE5803

SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD_5 V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V,AC-coupledwith0.1µF atINP and bypassedtoground with15nF atINM, No activetermination,VCNTL = 0 V,fIN = 5 MHz, LNA = 18 dB,PGA = 24 dB,14Bit,sample rate= 65 MSPS, LPF Filter= 15 MHz, lownoisemode, VOUT = –1 dBFS, ADC configuredininternalreferencemode, single-ended VCNTL mode, VCNTLM = GND, atambienttemperatureTA = 25°C, unlessotherwisenoted.Min and max valuesare specifiedacrossfull-temperaturerangewithAVDD_5 V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V PARAMETER TEST CONDITION MIN TYP MAX UNITS POWER DISSIPATION AVDD Voltage 3.15 3.3 3.6 V AVDD_ADC Voltage 1.7 1.8 1.9 V AVDD_5V Voltage 4.75 5 5.5 V DVDD Voltage 1.7 1.8 1.9 V TGC lownoisemode, 65 MSPS 158 190 TGC lownoisemode, 40 MSPS 145 Totalpower dissipationperchannel mW/CH TGC medium power mode, 40 MSPS 114 TGC lowpower mode, 40 MSPS 101.5 TGC lownoisemode, no signal 202 240 TGC medium power mode, no signal 126 TGC lowpower mode, no signal 99 AVDD (3.3V)Current mA TGC lownoisemode, 500 mV PP Input,1%dutycycle 210 TGC medium power mode, 500 mV PP Input,1% dutycycle 133 TGC lowpower,500 mV PP Input,1% dutycycle 105 TGC mode no signal 25.5 35 AVDD_5V Current mA TGC mode, 500 mV PP Input,1%dutycycle 16.5 TGC lownoisemode, no signal 99 121 TGC medium power mode, no signal 68 TGC lowpower mode, no signal 55.5 VCA Power dissipation mW/CH TGC lownoisemode, 500 mV PP input,1%dutycycle 102.5 TGC medium power mode, 500 mV PP Input,1% dutycycle 71 TGC lowpower mode, 500 mV PP input,1%dutycycle 59.5 AVDD_ADC(1.8V) Current 65 MSPS 187 205 mA DVDD(1.8V) Current 65 MSPS 77 110 mA

65 MSPS 59 69

50 MSPS 51

ADC Power dissipation/CH mW/CH

40 MSPS 46

20 MSPS 35

Power dissipationinpower down mode PDN_VCA = High,PDN_ADC = High 25 mW/CH Completepower-down PDN_Global=High 0.6 Power-down responsetime Time takentoenterpower down 1 µs Power-upresponsetime VCA power down 2µs+1% ofPDN time µs ADC power down 1 Completepower down 2.5 ms fin= 5 MHz, at50 mVpp noiseat1 KHz on supply(2) –65 dBcPower supplymodulationratio,AVDD and AVDD_5V fin= 5 MHz, at50 mVpp noiseat50 KHz on supply(2) –65 dBc Power supplyrejectionratio f= 10 kHz,VCNTL = 0 V (highgain),AVDD –40 dBc f= 10 kHz,VCNTL = 0 V(highgain),AVDD_5V –55 dBc f= 10 kHz,VCNTL = 1 V (lowgain),AVDD –50 dBc (2) PSMR specificationiswithrespecttoinputsignalamplitude.

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 DIGITAL CHARACTERISTICS Typicalvaluesareat25°C, AVDD = 3.3V,AVDD_5 = 5 V and AVDD_ADC = 1.8V,DVDD = 1.8V,14 bitsample rate= 65 MSPS, unlessotherwisenoted.Minimum and maximum valuesareacrossthefulltemperaturerange:TMIN = 0°C toTMAX = +85°C PARAMETER CONDITION MIN TYP MAX UNITS (1) DIGITAL INPUTS/OUTPUTS VIH Logichighinputvoltage 2 3.3 V VIL Logiclowinputvoltage 0 0.3 V Logichighinputcurrent 200 µA Logiclowinputcurrent 200 µA Inputcapacitance 5 pF VOH Logichighoutputvoltage SDOUT pin DVDD V VOL Logiclowoutputvoltage SDOUT pin 0 V LVDS OUTPUTS with100 ohms externaldifferentialOutputdifferentialvoltage 400 mVtermination Outputoffsetvoltage Common-mode voltage 1100 mV FCLKP and FCLKM 1X clockrate 10 65 MHz DCLKP and DCLKM 7X clockrate 70 455 MHz 6X clockrate 60 390 MHz tsu Data setuptime(2) 350 ps th Data holdtime(2) 350 ps ADC INPUT CLOCK CLOCK frequency 10 65 MSPS Clockdutycycle 45% 50% 55% Sine-wave,ac-coupled 0.5 Vpp Clockinputamplitude, LVPECL, ac-coupled 1.6 Vppdifferential(VCLKP_ADC –VCLKM_ADC ) LVDS, ac-coupled 0.7 Vpp Common-mode voltage biasedinternally 1 V ClockinputamplitudeVCLKP_ADC CMOS CLOCK 1.8 Vpp(single-ended) (1) The DC specificationsrefertotheconditionwhere theLVDS outputsarenotswitching,butarepermanentlyata validlogiclevel0 or1 with100Ω externaltermination. (2) Setupand holdtimespecificationstakeintoaccounttheeffectofjitteron theoutputdataand clock.These specificationsalsoassume thatthedataand clockpathsareperfectlymatched withinthereceiver.Any mismatchinthesepathswithinthereceiverwouldappear as reducedtimingmargins Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):AFE5803

Vcntl (V) Gain (dB) Low noise Medium power Low power Vcntl (V) Gain (dB) −40 deg C 25 deg C 85 deg C −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.1 0.2 0.3 0.4 0.5 −0.9 −0.8 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.1 0.2 0.3 0.4 0.5 1000 2000 3000 4000 5000 6000 7000 8000 9000 Gain (dB) Number of Occurrences G004 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.1 0.2 0.3 0.4 0.5 0.6 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.1 0.2 0.3 0.4 0.5 0.6 1000 2000 3000 4000 5000 6000 7000 8000 9000 Gain (dB) Number of Occurrences G005 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 −0.7 −0.6 −0.5 −0.4 −0.3 −0.2 −0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.7 1000 2000 3000 4000 5000 6000 7000 8000 Gain (dB) Number of Occurrences G005 −72 −68 −64 −60 −56 −52 −48 −44 −40 −36 −32 −28 −24 −20 −16 −12−8 −40 812 −72 −68 −64 −60 −56 −52 −48 −44 −40 −36 −32 −28 −24 −20 −16 −12−8 −40 812 100 110 120 ADC Output Number of Occurrences G058 AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS AVDD_5 V = 5 V, AVDD = 3.3V, AVDD_ADC = 1.8V, DVDD = 1.8V, ac-coupledwith0.1µF caps atINP and 1 5nF caps atINM, No activetermination,VCNTL = 0 V, FIN = 5 MHz, LNA = 18 dB, PGA = 24 dB, 14 Bit,sample rate= 65 MSPS, LPF Filter= 15 MHz, low noisemode, VOUT = -1dBFS,ADC isconfiguredininternalreference mode, single-endedVCNTL mode, VCNTLM = GND, atambienttemperatureTA = 25°C, unlessotherwisenoted. Figure2.Gain vs.VCNTL, LNA = 18 dB and PGA = 24 dB Figure3.Gain Variationvs.Temperature,LNA = 18 dB and PGA = 24 dB Figure4.Gain Matching Histogram, Figure5.Gain Matching Histogram, VCNTL= 0.3V(34951channels) VCNTL = 0.6V(34951channels) Figure6.Gain Matching Histogram, Figure7.Output OffsetHistogram,VCNTL = 0V (1247 channels)VCNTL = 0.9V(34951channels)

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Impedance Magnitude Response Frequency (Hz) Impedance (Ohms) Open −90 −80 −70 −60 −50 −40 −30 −20 −10 Impedance Phase Response Frequency (Hz) Phase (Degrees) Open 100 150 200 250 300 350 400 450 500 Impedance Magnitude Response Frequency (Hz) Impedance (Ohms)

50 Ohms

100 Ohms

200 Ohms

400 Ohms

−90 −80 −70 −60 −50 −40 −30 −20 −10 Impedance Phase Response Frequency (Hz) Phase (Degrees) −30 −25 −20 −15 −10 0 10 20 30 40 50 60 Frequency (MHz) Amplitude (dB) 10MHz 15MHz 20MHz 30MHz −30 −27 −24 −21 −18 −15 −12 10 100 500 LNA INPUT HPF CHARECTERISTICS Frequency (KHz) Amplitude (dB) AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 TYPICAL CHARACTERISTICS (continued) Figure8.InputImpedance withoutActiveTermination Figure9.InputImpedance withoutActiveTermination (Magnitude) (Phase) Figure10.InputImpedance withActiveTermination Figure11.InputImpedance withActiveTermination (Magnitude) (Phase) Figure12.Low-Pass FilterResponse Figure13.LNA High-Pass FilterResponse vs.Reg59[3:2] Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):AFE5803

Vcntl (V) Input reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB −40 −35 −30 −25 −20 −15 −10 10 100 500 HPF CHARECTERISTICS (LNA+VCA+PGA+ADC) Frequency (KHz) Amplitude (dB) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Vcntl (V) Input reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB Vcntl (V) Input reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Vcntl (V) Input reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB Vcntl (V) Input reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure14.FullChannel High-Pass FilterResponse at Figure15.IRN,PGA = 24 dB and Low Noise Mode DefaultRegisterSetting Figure16.IRN,PGA = 24 dB and Low Noise Mode Figure17.IRN,PGA = 24 dB and Medium Power Mode Figure18.IRN,PGA = 24 dB and Medium Power Mode Figure19.IRN,PGA = 24 dB and Low Power Mode

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0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 Vcntl (V) Input reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB 110 130 150 170 190 210 220 Vcntl (V) Output reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB 100 120 140 160 180 200 220 240 260 280 300 Vcntl (V) Output reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB 100 120 140 160 180 200 220 240 260 280 300 320 340 Vcntl (V) Output reffered noise (nVHz) LNA 12 dB LNA 18 dB LNA 24 dB 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Frequency (MHz) Amplitude (nVHz) 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 Frequency (MHz) Amplitude (nVHz) AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 TYPICAL CHARACTERISTICS (continued) Figure20.IRN,PGA = 24 dB and Low Power Mode Figure21.ORN, PGA = 24 dB and Low Noise Mode Figure22.ORN, PGA = 24 dB and Medium Power Mode Figure23.ORN, PGA = 24 dB and Low Power Mode Figure24.IRN,PGA = 24 dB and Low Noise Mode Figure25.ORN, PGA = 24 dB and Low Noise Mode Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):AFE5803

Vcntl (V) SNR (dBFS) 24 dB PGA gain 30 dB PGA gain Vcntl (V) SNR (dBFS) 24 dB PGA gain 30 dB PGA gain 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 Gain (dB) SNR (dBFS) Low noise Low power 50 100 150 200 250 300 350 400 Source Impedence (Ω ) Noise Figure (dB) 100 ohm act term 200 ohm act term 400 ohm act term Without Termination 50 100 150 200 250 300 350 400 Source Impedence (Ω ) Noise Figure (dB) 50 ohm act term 100 ohm act term 200 ohm act term 400 ohm act term Without Termination 50 100 150 200 250 300 350 400 Source Impedence (Ω ) Noise Figure (dB) 50 ohm act term 100 ohm act term 200 ohm act term 400 ohm act term No Termination AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure26.SNR, LNA = 18 dB and Low Noise Mode Figure27.SNR, LNA = 18 dB and Low Power Mode Figure28.SNR vs.DifferentPower Modes Figure29.Noise Figure,LNA = 12 dB and Low Noise Mode Figure30.Noise Figure,LNA = 18 dB and Low Noise Mode Figure31.Noise Figure,LNA = 24 dB and Low Noise Mode

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1.5 2.5 3.5 4.5 50 100 150 200 250 300 350 400 Source Impedence (Ω ) Noise Figure (dB) Low noise Low power Medium power 50 100 150 200 250 300 350 400 Source Impedence (Ω ) Noise Figure (dB) Low noise Low power Medium power −80.0 −75.0 −70.0 −65.0 −60.0 −55.0 −50.0 1 2 3 4 5 6 7 8 9 10 Frequency (MHz) HD2 (dB) Low noise Low power Medium power −75 −70 −65 −60 −55 −50 −45 1 2 3 4 5 6 7 8 9 10 Frequency (MHz) HD3 (dBc) Low noise Low power Medium power −90 −85 −80 −75 −70 −65 −60 −55 −50 −45 −40 6 12 18 24 30 36 Gain (dB) HD2 (dBc) Low noise Low power Medium power −90 −80 −70 −60 −50 −40 6 12 18 24 30 36 Gain (dB) HD3 (dBc) Low noise Low power Medium power AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 TYPICAL CHARACTERISTICS (continued) Figure32.Noise Figurevs.Power Modes with400 Ω Figure33.Noise Figurevs.Power Modes without Termination Termination Figure34.HD2 vs.Frequency,Vin = 500 mV PP and Figure35.HD3 vs.Frequency,Vin = 500 mVpp and VOUT = -1dBFS VOUT = -1dBFS Figure36.HD2 vs.Gain,LNA = 12 dB and Figure37.HD3 vs.Gain,LNA = 12 dB and PGA = 24 dB and VOUT = -1dBFSPGA = 24 dB and VOUT = -1dBFS Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):AFE5803

−90 −80 −70 −60 −50 −40 12 18 24 30 36 42 Gain (dB) HD2 (dBc) Low noise Low power Medium power −90 −80 −70 −60 −50 −40 12 18 24 30 36 42 Gain (dB) HD3 (dBc) Low noise Low power Medium power −90 −85 −80 −75 −70 −65 −60 −55 −50 −45 −40 18 24 30 36 42 48 Gain (dB) HD2 (dBc) Low noise Low power Medium power −90 −80 −70 −60 −50 −40 18 21 24 27 30 33 36 39 42 45 48 Gain (dB) HD3 (dB) Low noise Low power Medium power −70 −66 −62 −58 −54 −50 14 18 22 26 30 34 38 42 Gain (dB) IMD3 (dBFS) Fin1=2MHz, Fin2=2.01MHz Fin1=5MHz, Fin2=5.01MHz G001 −70 −66 −62 −58 −54 −50 14 18 22 26 30 34 38 42 Gain (dB) IMD3 (dBFS) Fin1=2MHz, Fin2=2.01MHz Fin1=5MHz, Fin2=5.01MHz G001 AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure38.HD2 vs.Gain,LNA = 18 dB and PGA = 24 dB Figure39.HD3 vs.Gain,LNA = 18 dB and PGA = 24 dB and VOUT = -1dBFS and VOUT = -1dBFS Figure40.HD2 vs.Gain,LNA = 24 dB and PGA = 24 dB Figure41.HD3 vs.Gain,LNA = 24 dB and PGA = 24 dB and VOUT = -1dBFS and VOUT = -1dBFS Figure42.IMD3, Fout1 = -1dBFS and Fout2 = -21dBFS Figure43.IMD3, Fout1 = -7dBFS and Fout2 = -7dBFS

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−75 −70 −65 −60 5 10 100 1000 2000 PSMR vs SUPPLY FREQUENCY Supply frequency (kHz) PSMR (dBc) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 −80 −75 −70 −65 −60 −55 5 10 100 1000 2000 PSMR vs SUPPLY FREQUENCY Supply frequency (kHz) PSMR (dBc) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 −90 −80 −70 −60 −50 −40 −30 −20 5 10 100 1000 2000 3V PSRR vs SUPPLY FREQUENCY Supply frequency (kHz) PSRR wrt supply tone (dB) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 −90 −80 −70 −60 −50 −40 −30 −20 5 10 100 1000 2000 5V PSRR vs SUPPLY FREQUENCY Supply frequency (kHz) PSRR wrt supply tone (dB) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 0.0 2000.0 4000.0 6000.0 8000.0 10000.0 12000.0 14000.0 16000.0 18000.0 20000.0 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Time (µs) Output Code Vcntl (V) Output Code Vcntl 0.0 2000.0 4000.0 6000.0 8000.0 10000.0 12000.0 14000.0 16000.0 18000.0 20000.0 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Time (µs) Output Code Vcntl (V) Output Code Vcntl AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 TYPICAL CHARACTERISTICS (continued) Figure44.AVDD Power Supply ModulationRatio, Figure45.AVDD_5V Power Supply ModulationRatio, 100mV PP Supply Noise withDifferentFrequencies100 mV PP Supply Noise withDifferentFrequencies Figure46.AVDD Power Supply RejectionRatio,100mV PP Figure47.AVDD_5 V Power Supply RejectionRatio, Supply Noise withDifferentFrequencies 100mV PP Supply Noise withDifferentFrequencies Figure48.VCNTL Response Time,LNA = 18 dB Figure49.VCNTL Response Time,LNA = 18 dB and PGA = 24 dB and PGA = 24 dB Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):AFE5803

−1.2 −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Time (µs) Input (V) −1.2 −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Time (µs) Input (V) −10000.0 −8000.0 −6000.0 −4000.0 −2000.0 0.0 2000.0 4000.0 6000.0 8000.0 10000.0 Time (µs) Output Code Positive overload Negative overload Average −10000 −8000 −6000 −4000 −2000 2000 4000 6000 8000 10000 Time (µs) Output Code 47nF 15nF −40 −35 −30 −25 −20 −15 −10 Frequency (MHz) Gain (dB) k=2 k=3 k=4 k=5 k=6 k=7 k=8 k=9 k=10 G000 −2000 −1600 −1200 −800 −400 400 800 1200 1600 2000 1 1.5 2 2.5 3 3.5 4 4.5 5 Time (µs) Output Code 47nF 15nF AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure50.Pulse InversionAsymmetrical PositiveInput Figure51.Pulse InversionAsymmetrical NegativeInput Figure52.Pulse Inversion,VIN = 2 VPP ,PRF = 1 KHz, Gain Figure53.Overload Recovery Response vs.INM = 21 dB Capacitor,VIN = 50 mV PP /100µVPP ,Max Gain Figure54.Overload Recovery Response vs.INM Capacitor Figure55.DigitalHigh-Pass FilterResponse (Zoomed),VIN = 50 mV PP /100µVPP ,Max Gain

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 TIMING CHARACTERISTICS (1) Typicalvaluesareat25°C, AVDD_5V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V,Differentialclock,C LOAD = 5pF,R LOAD = 100 Ω,14Bit,sample rate= 65MSPS, unlessotherwisenoted.Minimum and maximum valuesareacrossthe fulltemperaturerangeTMIN = 0°C toTMAX = 85°C withAVDD_5V = 5 V,AVDD = 3.3V,AVDD_ADC = 1.8V,DVDD = 1.8V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT The delayintimebetween therisingedge oftheinputsamplingta Aperturedelay 0.7 3 nsclockand theactualtimeatwhichthesamplingoccurs Aperturedelay Acrosschannelswithinthesame device ±150 ps matching tj Aperturejitter 450 Fs rms Input ADC latency Default,afterreset,or/0 x 2 [12]= 1,LOW_LATENCY = 1 11/8 clock cycles Data and frameclock Inputclockrisingedge (zerocross)toframeclockrisingedge (zerotdelay 3 5.4 7 nsdelay cross)minus 3/7oftheinputclockperiod(T). Δtdelay Delayvariation Atfixedsupplyand 20°C T difference.Devicetodevice –1 1 ns tRISE Risetimemeasured from–100 mV to100 mV Falltimemeasured 0.14 nsData risetimeData fall from100 mV to–100 mV 10 MHz < fCLKIN < 65 MHztimetFALL 0.15 tFCLKRISE Frame clockrisetime Risetimemeasured from–100mV to100mV Falltimemeasured 0.14 ns Frame clockfalltime from100 mV to–100 mV 10 MHz < fCLKIN < 65MHztFCLKFALL 0.15 Frame clockdutycycle Zerocrossingoftherisingedge tozerocrossingofthefallingedge 48% 50% 52% tDCLKRISE Risetimemeasured from–100mV to100mV Falltimemeasured 0.13 nsBitclockrisetimeBit from100 mV to–100 mV 10 MHz < fCLKIN < 65MHzclockfalltimetDCLKFALL 0.12 Zerocrossingoftherisingedge tozerocrossingofthefallingedgeBitclockdutycycle 46% 54%10 MHz < fCLKIN < 65 MHz (1) Timingparametersareensuredby designand characterization;notproductiontested. OUTPUT INTERFACE TIMING (1)(2)(3) Setup Time (tsu),ns Hold Time (th),ns tPROG = (3/7)xT + tdelay,ns(foroutputdataand frame clock) (foroutputdataand frame clock)fCLKIN , InputClock InputClock Zero-Cross(risingedge)Data ValidtoInputClock InputClock Zero-CrossingtoDataFrequency toFrame Clock Zero-Cross(risingZero-Crossing Invalid edge) MHz MIN TYP MAX MIN TYP MAX MIN TYP MAX (1) FCLK timingisthesame as fortheoutputdatalines.Ithas thesame relationtoDCLK as thedatapins.Setupand holdarethesame forthedataand theframeclock. (2) Data validislogicHIGH = +100mV and logicLOW = -100mV (3) Timingparametersareensuredby designand characterization;notproductiontested. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):AFE5803

12-Bit 6x serialization mode 14-Bit 7x serialization mode LVDS Setup and Hold Timing tPROG Frame Clock FCLK Freq = f CLKIN Input Clock CLKIN Freq = f CLKIN SAMPLE N D13(D0) Data bit in MSB First modeData bit in LSB First mode Bit Clock DCLK Freq = 7 x f CLKIN Output Data CH nOUT Data rate = 14 x f CLKIN D11(D0) D10(D1) SAMPLE N tPROG T Input Signal ta Sample N SampleN+C d C d clock cycleslatency D0 (D13) D13(D0) D12(D1) D11(D2) D10(D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 (D10) D2 (D11) SAMPLE N d D1 (D12) Sample N+C d+1 D1 (D12) D0 (D13) D13(D0) D12(D1) D11(D2) D10(D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 (D10) D2 (D11) D1 (D12) D0 (D13) D13(D0) D12(D1) D11(D2) D10(D3) D9 (D4) D8 (D5) D7 (D6) D6 (D7) D5 (D8) D4 (D9) D3 (D10) D2 (D11) D1 (D12) D0 (D13) ta AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com Figure56. LVDS Timing Diagrams

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D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0A7 A6 A5 A4 A3 A2 A1 A0 SEN SCLK SDATA RESET Data□Latched□On□Rising□Edge□of□SCLK Start□Sequence Start□Sequence End□Sequence End□Sequence T0384-01 AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 LVDS Output InterfaceDescription AFE5803 has LVDS outputinterfacewhich supportsmultipleoutputformats.The ADC resolutionscan be configuredas 12bitor 14bitas shown intheLVDS timingdiagramsFigure56.The ADCs intheAFE5803 are runningat14bit;2 LSBs areremoved when 12-bitoutputisselected;and two 0s areadded atLSBs when 16-bit outputis selected.AppropriateADC resolutionscan be selectedforoptimizingsystem performance-cost effectiveness.When the devicesrun at 16bitmode, higherend FPGAs are requiredto processhigherrateof LVDS data.CorrespondingregistersettingsarelistedinTable1. Table1.Corresponding RegisterSettings LVDS Rate 12 bit(6X DCLK) 14 bit(7X DCLK) 16 bit(8X DCLK) Reg 3 [14:13] 11 00 01 Reg 4 [2:0] 010 000 000 Description 2 LSBs removed N/A 2 0s added atLSBs SERIAL REGISTER TIMING SerialRegisterWriteDescription Programming ofdifferentmodes can be done throughtheserialinterfaceformed by pinsSEN (serialinterface enable),SCLK (serialinterfaceclock),SDATA (serialinterfacedata)and RESET. Allthesepinshave a pull-down resistortoGND of100kΩ.Serialshiftofbitsintothedeviceisenabledwhen SEN islow.SerialdataSDATA is latchedat everyrisingedge of SCLK when SEN isactive(low).The serialdata isloadedintothe registerat every24thSCLK risingedge when SEN islow.Iftheword lengthexceeds a multipleof24 bits,theexcessbits areignored.Data can be loadedinmultipleof24-bitwords withina singleactiveSEN pulse(thereisan internal counterthatcountsgroupsof24 clocksafterthefallingedge ofSEN). The interfacecan work withtheSCLK frequencyfrom 20 MHz down tolow speeds (fewHertz)and even withnon-50% dutycycleSCLK. The datais dividedintotwo main portions:a registeraddress(8bits)and thedataitself(16bits),toloadon theaddressed register.When writingtoa registerwithunused bits,theseshouldbe setto0.Figure57 illustratesthisprocess. Figure57. SPI Timing Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):AFE5803

x x x x x x x x x x x x x x x xA7 A6 A5 A4 A3 A2 A1 A0 SEN SCLK SDATA SDOUT Start Sequence End Sequence D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com SPI Timing Characteristics Minimum valuesacrossfulltemperaturerange TMIN = 0°C to TMAX = 85°C, AVDD_5V =5.0V,AVDD=3.3V, AVDD_ADC=1.8V, DVDD=1.8V PARAMETER DESCRIPTION MIN TYP MAX UNIT t1 SCLK period 50 ns t2 SCLK hightime 20 ns t3 SCLK lowtime 20 ns t4 Data setuptime 5 ns t5 Data holdtime 5 ns t6 SEN falltoSCLK rise 8 ns t7 Time between lastSCLK risingedge toSEN risingedge 8 ns t8 SDOUT delay 12 20 28 ns RegisterReadout The deviceincludesan optionwhere thecontentsoftheinternalregisterscan be readback.Thismay be useful as a diagnostictestto verifythe serialinterfacecommunicationbetween the externalcontrollerand the AFE. First,the <REGISTER READOUT ENABLE > bit(Reg0[1])needs to be setto '1'.Then user shouldinitiatea serialinterfacecyclespecifyingtheaddressoftheregister(A7-A0)whose contenthas tobe read.The databits are "don’t care".The devicewilloutputthe contents(D15-D0) of the selectedregisteron the SDOUT pin. SDOUT has a typicaldelayt8of20nS fromthefallingedge oftheSCLK. Forlowerspeed SCLK, SDOUT can be latchedon therisingedge ofSCLK. For higherspeed SCLK,e.g.theSCLK periodlesserthan60nS, itwould be bettertolatchtheSDOUT atthenextfallingedge ofSCLK. The followingtimingdiagramshows thisoperation (thetimespecificationsfollowthe same informationprovided.In the readoutmode, usersstillcan access the <REGISTER READOUT ENABLE > through SDATA/SCLK/SEN. To enable serialregisterwrites,set the <REGISTER READOUT ENABLE > bitback to'0'. Figure58. SerialInterfaceRegisterRead The AFE5803 SDOUT bufferistri-statedand willgetenabledonlywhen 0[1](REGISTER READOUT ENABLE) isenabled.SDOUT pinsfrommultipleAFE5803s can be tiedtogetherwithoutany pull-upresistors.Levelshifter SN74AUP1T04 can be used toconvert1.8Vlogicto2.5V/3.3Vlogicsifneeded.

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Serial Register WriteDevice Ready for Data Conversion Start of Clock AVDD AVDD_5V AVDD_ADC DVDD RESET SEN CLKP_ADC t4 t7 AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 10 µs < t1< 50 ms, 10 µs < t2< 50 ms, –10 ms < t3< 10 ms, t4> 10 ms, t5> 100 ns,t6> 100 ns,t7> 10 ms, and t8> 100 µs. The AVDDx and DVDD power-onsequence does notmatteras longas –10ms < t3< 10ms. Similarconsiderations applywhileshuttingdown thedevice. Figure59. Recommended Power-up Sequencing and Reset Timing Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):AFE5803

SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com REGISTER MAP ADC RegisterMap A resetprocessisrequiredattheAFE5803 initializationstage.Initializationcan be done inone oftwo ways: 1. Througha hardwarereset,by applyinga positivepulseattheRESET pin 2. Through a softwarereset,usingtheserialinterface,by settingtheSOFTWARE RESET bittohigh.Setting thisbitinitializesthe internalregistersto the respectivedefaultvalues(allzeros)and then self-resetsthe SOFTWARE RESET bittolow.Inthiscase,theRESET pincan staylow(inactive). Afterreset,allADC and VCA registersare set to ‘0’, i.e.defaultsettings.Duringregisterprogramming,all reserved/unlistedregisterbitsneed tobe setas ‘0’.Registersettingsare maintainedwhen theAFE5803 isin eitherpartialpower down mode orcompletepower down mode. Table2.ADC RegisterMap ADDRESS ADDRESS Default FUNCTION DESCRIPTION(DEC) (HEX) Value 0[0] 0x0[0] 0 SOFTWARE_RESET 0:Normal operation; 1:Resetsthedeviceand self-clearsthebitto'0' 0[1] 0x0[1] 0 REGISTER_READOUT_ENABLE 0:Disablesreadout; 1:enablesreadoutofregisteratSDOUT Pin 1[0] 0x1[0] 0 ADC_COMPLETE_PDN 0:Normal 1:CompletePower down 1[1] 0x1[1] 0 LVDS_OUTPUT_DISABLE 0:OutputEnabled; 1:Outputdisabled 1[9:2] 0x1[9:2] 0 ADC_PDN_CH <7:0> 0:Normal operation; 1:Power down. Power down IndividualADC channels. 1[9]→CH8 …1[2]→CH1 1[10] 0x1[10] 0 PARTIAL_PDN 0:Normal Operation; 1:PartialPower Down ADC 1[11] 0x1[11] 0 LOW_FREQUENCY_ 0:No suppression; NOISE_SUPPRESSION 1:SuppressionEnabled 1[13] 0x1[13] 0 EXT_REF 0:InternalReference; 1:ExternalReference.VREF_IN isused.Both3[15]and 1[13]shouldbe set as 1 intheexternalreferencemode 1[14] 0x1[14] 0 LVDS_OUTPUT_RATE_2X 0:1x rate; 1:2x rate.Combines datafrom2 channelson 1 LVDS pair.When ADC clock rateislow,thisfeaturecan be used 1[15] 0x1[15] 0 SINGLE-ENDED_CLK_MODE 0:Differentialclockinput; 1:Single-endedclockinput 2[2:0] 0x2[2:0] 0 RESERVED Setto0 2[10:3] 0x2[10:3] 0 POWER-DOWN_LVDS 0:Normal operation; 1:PDN IndividualLVDS outputs.2[10]→CH8 …2[3]→CH1 2[11] 0x2[11] 0 AVERAGING_ENABLE 0:No averaging; 1:Average2 channelstoincreaseSNR 2[12] 0x2[12] 0 LOW_LATENCY 0:DefaultLatencywithdigitalfeaturessupported,11 cyclelatency 1:Low Latencywithdigitalfeaturesbypassed,8 cyclelatency 2[15:13] 0x2[15:3] 0 TEST_PATTERN_MODES 000:Normal operation; 001:Sync; 010:De-skew; 011:Custom; 100:All1's; 101:Toggle; 110:All0's; 111:Ramp 3[7:0] 0x3[7:0] 0 INVERT_CHANNELS 0:No inverting; 1:Invertchanneldigitaloutput.3[7]→CH8;3[0]→CH1 3[8] 0x3[8] 0 CHANNEL_OFFSET_ 0:No offsetsubtraction; SUBSTRACTION_ENABLE 1:OffsetvalueSubtractEnabled 3[9:11] 0x3[9:11] 0 RESERVED Setto0 3[12] 0x3[12] 0 DIGITAL_GAIN_ENABLE 0:No digitalgain; 1:DigitalgainEnabled

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 Table2.ADC RegisterMap (continued) ADDRESS ADDRESS Default FUNCTION DESCRIPTION(DEC) (HEX) Value 3[14:13] 0x3[14:13] 0 SERIALIZED_DATA_RATE Serializationfactor 00:14x 01:16x 10:reserved 11:12x when 4[1]=1.Inthe16x serializationrate,two 0s arefilledattwo LSBs (see Table1) 3[15] 0x3[15] 0 ENABLE_EXTERNAL_ 0:Internalreferencemode; REFERENCE_MODE 1:Settoexternalreferencemode Note:both3[15]and 1[13]shouldbe setas 1 when configuringthedevicein theexternalreferencemode 4[1] 0x4[1] 0 ADC_RESOLUTION_SELECT 0:14bit; 1:12bit 4[3] 0x4[3] 0 ADC_OUTPUT_FORMAT 0:2'scomplement; 1:Offsetbinary 4[4] 0x4[4] 0 LSB_MSB_FIRST 0:LSB first; 1:MSB first 5[13:0] 0x5[13:0] 0 CUSTOM_PATTERN Custom patterndataforLVDS output(2[15:13]=011) 10[8] 0xA[8] 0 SYNC_PATTERN 0:Testpatternoutputsof8 channelsareNOT synchronized. 1:Testpatternoutputsof8 channelsaresynchronized. 13[9:0] 0xD[9:0] 0 OFFSET_CH1 Valuetobe subtractedfromchannel1 code 13[15:11] 0xD[15:11] 0 DIGITAL_GAIN_CH1 0 dB to6 dB in0.2dB steps 15[9:0] 0xF[9:0] 0 OFFSET_CH2 valuetobe subtractedfromchannel2 code 15[15:11] 0xF[15:11] 0 DIGITAL_GAIN_CH2 0dB to6dB in0.2dB steps 17[9:0] 0x11[9:0] 0 OFFSET_CH3 valuetobe subtractedfromchannel3 code 17[15:11] 0x11[15:11] 0 DIGITAL_GAIN_CH3 0 dB to6 dB in0.2dB steps 19[9:0] 0x13[9:0] 0 OFFSET_CH4 valuetobe subtractedfromchannel4 code 19[15:11] 0x13[15:11] 0 DIGITAL_GAIN_CH4 0 dB to6 dB in0.2dB steps 21[0] 0x15[0] 0 DIGITAL_HPF_FILTER_ENABLE 0:DisablethedigitalHPF filter; _ CH1-4 1:Enablefor1-4channels 21[4:1] 0x15[4:1] 0 DIGITAL_HPF_FILTER_K_CH1-4 SetK forthehigh-passfilter(kfrom2 to10,i.e.0010B to1010B). Thisgroupoffourregisterscontrolsthecharacteristicsofa digitalhigh-pass transferfunctionappliedtotheoutputdata,followingtheformula: y(n)= 2k/(2k + 1)[x(n)– x(n– 1)+ y(n– 1)](seeTable3 and Figure55) 25[9:0] 0x19[9:0] 0 OFFSET_CH8 valuetobe subtractedfromchannel8 code 25[15:11] 0x19[15:11] 0 DIGITAL_GAIN_CH8 0 dB to6 dB in0.2dBsteps 27[9:0] 0x1B[9:0] 0 OFFSET_CH7 valuetobe subtractedfromchannel7 code 27[15:11] 0x1B[15:11] 0 DIGITAL_GAIN_CH7 0 dB to6dB in0.2dB steps 29[9:0] 0x1D[9:0] 0 OFFSET_CH6 valuetobe subtractedfromchannel6 code 29[15:11] 0x1D[15:11] 0 DIGITAL_GAIN_CH6 0 dB to6 dB in0.2dB steps 31[9:0] 0x1F[9:0] 0 OFFSET_CH5 valuetobe subtractedfromchannel5 code 31[15:11] 0x1F[15:11] 0 DIGITAL_GAIN_CH5 0 dB to6 dB in0.2dB steps 33[0] 0x21[0] 0 DIGITAL_HPF_FILTER_ENABLE 0:DisablethedigitalHPF filter; _ CH5-8 1:Enablefor5-8channels 33[4:1] 0x21[4:1] 0 DIGITAL_HPF_FILTER_K_CH5-8 SetK forthehigh-passfilter(kfrom2 to10,010B to1010B) Thisgroupoffourregisterscontrolsthecharacteristicsofa digitalhigh-pass transferfunctionappliedtotheoutputdata,followingtheformula: y(n)= 2k/(2k + 1)[x(n)– x(n– 1)+ y(n– 1)](seeTable3 and Figure55) 66[15] 0x42[15] 0 DITHER 0:Disableditherfunction. 1:Enableditherfunction.ImprovetheADC linearitywithslightnoise degradation. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):AFE5803

Default=No ADC Output 12/14b Final Digital Output12/14b Digital Gain Default=0 Channel Average Default=No Digital HPF Default = No /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 k k 2y n = x n x n 1 y n 1 /c233 /c249 /c45 /c45 /c43 /c45/c235 /c251/c43 AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com ADC Register/DigitalProcessingDescription The ADC in the AFE5803 has extensivedigitalprocessingfunctionalitieswhich can be used to enhance ultrasoundsystemperformance.The digitalprocessingblocksarearrangedas inFigure60. Figure60. ADC DigitalBlock Diagram AVERAGING_ENABLE: Address: 2[11] When setto1,two samples,correspondingtotwo consecutivechannels,areaveraged(channel1 with2,3 with 4,5 with6,and 7 with8).Ifbothchannelsreceivethesame input,theneteffectisan improvementinSNR. The averagingisperformedas:

Channel1 + channel2 comes outon channel3
Channel3 + channel4 comes outon channel4
Channel5 + channel6 comes outon channel5
Channel7 + channel8 comes outon channel6 ADC_OUTPUT_FORMAT: Address: 4[3] The ADC output,by default,isin2’s-complementmode. Programming the ADC_OUTPUT_FORMAT bitto 1 invertstheMSB, and theoutputbecomes straight-offsetbinarymode. DIGITAL_GAIN_ENABLE: Address: 3[12] Settingthisbitto1 appliestoeach channelithecorrespondinggaingivenby DIGTAL_GAIN_CHi <15:11>.The gainisgivenas 0dB + 0.2dB × DIGTAL_GAIN_CHi <15:11>.For instance,ifDIGTAL_GAIN_CH5 <15:11> = 3, channel 5 is increasedby 0.6dB gain.DIGTAL_GAIN_CHi <15:11> = 31 produces the same effectas DIGTAL_GAIN_CHi <15:11> = 30,settingthegainofchannelito6dB. DIGITAL_HPF_ENABLE
CH1-4:Address21[0]
CH5-8:Address33[0] DIGITAL_HPF_FILTER_K_CHX
CH1-4:Address21[4:1]
CH5-8:Address3[4:1] Thisgroup ofregisterscontrolsthecharacteristicsofa digitalhigh-passtransferfunctionappliedtotheoutput data,followingEquation1. (1) These digitalHPF registers(one forthe firstfourchannelsand one forthe second group of fourchannels) describethe settingof K. The digitalhigh pass filtercan be used to suppress low frequencynoise which commonly existsinultrasoundecho signals.The digitalfiltercan significantlybenefitnearfieldrecoverytimedue toT/R switchlowfrequencyresponse.Table3 shows thecut-offfrequencyvs K,alsosee Figure55.

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 Table3.DigitalHPF –1dB Corner Frequency vs K and Fs k 40 MSPS 50 MSPS 65 MSPS 2 2780 KHz 3480 KHz 4520 KHz 3 1490 KHz 1860 KHz 2420 KHz 4 770 KHz 960 KHz 1250 KHz LOW_FREQUENCY_NOISE_SUPPRESSION: Address: 1[11] The low-frequencynoisesuppressionmode isespeciallyusefulinapplicationswhere good noiseperformanceis desiredinthefrequencyband of0MHz to1MHz (arounddc).Settingthismode shiftsthelow-frequencynoiseof theAFE5803 toapproximatelyFs/2,therebymoving thenoisefloorarounddc toa much lowervalue.Registerbit 1[11]isused forenablingor disablingthisfeature.When thisfeatureisenabled,power consumptionof the devicewillbe increasedby approximate1 mW/CH. LVDS_OUTPUT_RATE_2X: Address: 1[14] The outputdataalwaysuses a DDR format,withvalid/differentbitson thepositiveas wellas thenegativeedges oftheLVDS bitclock,DCLK. The outputrateissetby defaultto1X (LVDS_OUTPUT_RATE_2X = 0),where each ADC has one LVDS streamassociatedwithit.Ifthesamplingrateislow enough,two ADCs can shareone LVDS stream,inthisway loweringthe power consumptiondevotedto the interface.The unused outputswill outputzero.To avoid consumptionfrom those outputs,no terminationshould be connected to them. The distributionon theused outputpairsisdone inthefollowingway:

Channel1 and channel2 come outon channel3.Channel1 comes outfirst.
Channel3 and channel4 come outon channel4.Channel3 comes outfirst.
Channel5 and channel6 come outon channel5.Channel5 comes outfirst.
Channel7 and channel8 come outon channel6.Channel7 comes outfirst CHANNEL_OFFSET_SUBSTRACTION_ENABLE: Address: 3[8] Settingthisbitto 1 enablesthe subtractionof the valueon the correspondingOFFSET_CHx <9:0> (offsetfor channel i) from the ADC output.The number is specifiedin 2s-complement format.For example, OFFSET_CHx <9:0> = 11 1000 0000 means subtract–128.For OFFSET_CHx <9:0> = 00 0111 1111 theeffectis tosubtract127.Ineffect,bothadditionand subtractioncan be performed.Note thattheoffsetisappliedbefore thedigitalgain(seeDIGITAL_GAIN_ENABLE). The wholedatapathis2s-complementthroughoutinternally,with digitalgain being the laststep.Only when ADC_OUTPUT_FORMAT=1 (straightbinaryoutputformat)isthe 2s-complementword translatedintooffsetbinaryattheend. SERIALIZED_DATA_RATE: Address: 3[14:13] See Table1 fordetaildescription. TEST_PATTERN_MODES: Address: 2[15:13] The AFE5803 can outputa varietyoftestpatternson theLVDS outputs.These testpatternsreplacethenormal ADC dataoutput.The devicemay alsobe made tooutput6 presetpatterns: 1. Ramp: SettingRegister2[15:13]=111causesallthechannelstooutputa repeatingfull-scaleramp pattern. The ramp incrementsfrom zerocode tofull-scalecode instepsof1LSB everyclockcycle.Afterhittingthe full-scalecode,itreturnsback tozerocode and ramps again. 2. Zeros:The devicecan be programmed tooutputallzerosby settingRegister2[15:13]=110; 3. Ones: The devicecan be programmed tooutputall1s by settingRegister2[15:13]=100; 4. Deskew Patten:When 2[15:13]=010;thismode replacesthe14-bitADC outputwiththe01010101010101 word. 5. Sync Pattern:When 2[15:13]=001,thenormalADC outputisreplacedby a fixed11111110000000 word. 6. Toggle:When 2[15:13]=101,thenormalADC outputisalternatingbetween 1'sand 0's.The startstateof ADC word can be either1'sor0's. 7. Custom Pattern:Itcan be enabledwhen 2[15:13]=011;.Users can writetherequiredVALUE intoregister bits<CUSTOM PATTERN > which isRegister5[13:0].Then the devicewilloutputVALUE at itsoutputs, about3 to4 ADC clockcyclesafterthe24thrisingedge ofSCLK. So, thetimetakentowriteone valueis24 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):AFE5803

SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com SCLK clockcycles+ 4 ADC clockcycles.To change thecustomerpatternvalue,userscan repeatwriting Register5[13:0]witha new value.Due tothespeed limitofSPI,therefreshrateofthecustom patternmay notbe high.Forexample,128 pointscustom patternwilltakeapproximately128 x (24SCLK clockcycles+ 4 ADC clockcycles). NOTE onlyone oftheabove patternscan be activeatany giveninstant. SYNC_PATTERN: Address: 10[8] By enablingthisbit,allchannels'testpatternoutputsare synchronized.When 10[8]isset as 1, the ramp patternsofall8 channelsstartsimultaneously.

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 VCA RegisterMap Table4.VCA RegisterMap ADDRESS ADDRESS Default FUNCTION DESCRIPTION(DEC) (HEX) Value 51[0] 0x33[0] 0 RESERVED 0 51[3:1] 0x33[3:1] 0 LPF_PROGRAMMABILITY 000:15MHz, 010:20MHz, 011:30MHz, 100:10MHz 51[4] 0x33[4] 0 PGA_INTEGRATOR_DISABLE 0:Enable (PGA_HPF_DISABLE) 1:DisablesoffsetintegratorforPGA. See explanationforthePGA integratorfunctioninAPPLICATION INFORMATION section 51[6:5] 0x33[6:5] 0 PGA_CURRENT_CLAMP_LEVEL 00:–2dBFS; 10:0dBFS; 01:–4dBFS when 51[7]=0 Note:thecurrentclamp circuitmakes surethatPGA outputisinlinear range.Forexample,at00 setting,PGA outputHD3 willbe worsen by 3dB at–2dBFS ADC input.Innormaloperation,thecurrentclamp functioncan be setas 00 51[7] 0x33[7] 0 PGA_CURRENT_CLAMP_DISABLE 0:EnablesthePGA currentclamp circuit; 1:DisablesthePGA currentclamp circuitbeforethePGA outputs. 51[6:5]determinesthecurrentclamp level 51[13] 0x33[13] 0 PGA_GAIN_CONTROL 0:24dB; 1:30dB. 52[4:0] 0x34[4:0] 0 ACTIVE_TERMINATION_ See Table6 Reg 52[5]shouldbe setas '1'toaccessthesebits INDIVIDUAL_RESISTOR_CNTL 52[5] 0x34[5] 0 ACTIVE_TERMINATION_ 0:Disables; INDIVIDUAL_RESISTOR_ENABLE 1:Enablesinternalactiveterminationindividualresistorcontrol 52[7:6] 0x34[7:6] 0 PRESET_ACTIVE_ TERMINATIONS 00:50ohm, 01:100ohm, 10:200ohm, 11:400ohm. (Note:thedevicewilladjustresistormapping (52[4:0])automatically. 50ohm activeterminationisNOT supportedin12dB LNA setting. Instead,'00'representshighimpedance mode when LNA gainis12dB) 52[8] 0x34[8] 0 ACTIVE TERMINATION ENABLE 0:Disables; 1:Enablesactivetermination 52[10:9] 0x34[10:9] 0 LNA_INPUT_CLAMP_SETTING 00:Autosetting, 01:1.5Vpp, 10:1.15Vppand 11:0.6Vpp 52[11] 0x34[11] 0 RESERVED Setto0 52[12] 0x34[12] 0 LNA_INTEGRATOR_DISABLE 0:Enables; (LNA_HPF_DISABLE) 1:DisablesoffsetintegratorforLNA. See theexplanationforthis functioninthefollowingsection 52[14:13] 0x34[14:13] 0 LNA_GAIN 00:18dB; 01:24dB; 10:12dB; 11:Reserved 52[15] 0x34[15] 0 LNA_INDIVIDUAL_CH_CNTL 0:Disable; 1:EnableLNA individualchannelcontrol.See Register57 fordetails 53[7:0] 0x35[7:0] 0 PDN_CH <7:0> 0:Normal operation; 1:Powers down correspondingchannels.Bit7→CH8, Bit6→CH7 …Bit0→CH1. PDN_CH willshutdown whicheverblocksare active 53[8] 0x35[8] 0 RESERVED Setto0 53[9] 0x35[9] 0 RESERVED Setto0 53[10] 0x35[10] 0 LOW_POWER 0:Low noisemode; 1:Setstolowpower mode (53[11]=0).At30dB PGA, totalchaingain may slightlychange. See typicalcharacteristics Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):AFE5803

SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com Table4.VCA RegisterMap (continued) ADDRESS ADDRESS Default FUNCTION DESCRIPTION(DEC) (HEX) Value 53[11] 0x35[11] 0 MED_POWER 0:Low noisemode; 1:Setstomedium power mode(53[10]=0).At30dB PGA, totalchain gainmay slightlychange. See typicalcharacteristics 53[12] 0x35[12] 0 PDN_VCAT_PGA 0:Normal operation; 1:Powers down VCAT (voltage-controlled-attenuator)and PGA 53[13] 0x35[13] 0 PDN_LNA 0:Normal operation; 1:Powers down LNA only 53[14] 0x35[14] 0 VCA_PARTIAL_PDN 0:Normal operation; 1:Powers down LNA, VCAT, and PGA partially(fastwake response) 53[15] 0x35[15] 0 VCA_COMPLETE_PDN 0:Normal operation; 1:Powers down LNA, VCAT, and PGA completely(slowwake response).Thisbitcan overwrite53[14]. 54[4:0] 0x36[4:0] 0 BUFFER_AMP_GAIN_CNTL SelectsFeedback resistorforthebufferamplifiersee Table7 54[7] 0x36[7] 0 RESERVED Setto0 54[8] 0x36[8] 0 RESERVED Setto0 54[9] 0x36[9] 0 RESERVED Setto0 57[1:0] 0x39[1:0] 0 CH1_LNA_GAIN_CNTL 00:18dB; CH2_LNA_GAIN_CNTL 11:Reserved REG52[15] shouldbe setas '1' 57[5:4] 0x39[5:4] 0 CH3_LNA_GAIN_CNTL 00:18dB; 01:24dB;57[7:6] 0x39[7:6] 0 CH4_LNA_GAIN_CNTL 10:12dB; 11:Reserved57[9:8] 0x39[9:8] 0 CH5_LNA_GAIN_CNTL REG52[15] shouldbe setas '1'57[11:10] 0x39[11:10] 0 CH6_LNA_GAIN_CNTL 57[13:12] 0x39[13:12] 0 CH7_LNA_GAIN_CNTL 57[15:14] 0x39[15:14] 0 CH8_LNA_GAIN_CNTL 59[3:2] 0x3B[3:2] 0 HPF_LNA 00:100kHz; 01:50kHz; 10:200kHz; 11:150kHz with0.015uFon INMx 59[6:4] 0x3B[6:4] 0 DIG_TGC_ATT_GAIN 000:0dB attenuation; 001:6dB attenuation; N: ~N ×6dB attenuationwhen 59[7]= 1 59[7] 0x3B[7] 0 DIG_TGC_ATT 0:disabledigitalTGC attenuator; 1:enabledigitalTGC attenuator 59[8] 0x3B[8] 0 BUFFER_AMP_PDN 0:Power down; 1:Normal operation 59[9] 0x3B[9] 0 PGA_TEST_MODE 0:Normal operation; 1:PGA outputsappearattestoutputs

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 AFE5803 VCA RegisterDescription LNA InputImpedances Configuration(ActiveTerminationProgrammability) DifferentLNA inputimpedances can be configuredthroughthe register52[4:0].By enablingand disablingthe feedbackresistorsbetween LNA outputsand ACTx pins,LNA inputimpedance isadjustableaccordingly.Table5 describestherelationshipbetween LNA gainand 52[4:0]settings. The AFE5803 alsohas 4 presetactiveterminationimpedances as describedin52[7:6].An internaldecoderis used toselectappropriateresistorscorrespondingtodifferentLNA gain. Table5.Register52[4:0]Description 52[4:0]/0x34[4:0] FUNCTION

00000 No feedbackresistorenabled

00001 Enables450 Ω feedbackresistor

00010 Enables900 Ω feedbackresistor

00100 Enables1800 Ω feedbackresistor

01000 Enables3600 Ω feedbackresistor

10000 Enables4500 Ω feedbackresistor

Table6.Register52[4:0]vs LNA InputImpedances 52[4:0]/0x34[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 LNA:12dB HighZ 150 Ω 300 Ω 100 Ω 600 Ω 120 Ω 200 Ω 86 Ω LNA:18dB HighZ 90 Ω 180 Ω 60 Ω 360 Ω 72 Ω 120 Ω 51 Ω LNA:24dB HighZ 50 Ω 100 Ω 33 Ω 200 Ω 40 Ω 66.67Ω 29 Ω 52[4:0]/0x34[4:0] 01000 01001 01010 01011 01100 01101 01110 01111 LNA:12dB 1200 Ω 133 Ω 240 Ω 92 Ω 400 Ω 109 Ω 171 Ω 80 Ω LNA:18dB 720 Ω 80 Ω 144 Ω 55 Ω 240 Ω 65 Ω 103 Ω 48 Ω LNA:24dB 400 Ω 44 Ω 80 Ω 31 Ω 133 Ω 36 Ω 57 Ω 27 Ω 52[4:0]/0x34[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 LNA:12dB 1500 Ω 136 Ω 250 Ω 94 Ω 429 Ω 111 Ω 176 Ω 81 Ω LNA:18dB 900 Ω 82 Ω 150 Ω 56 Ω 257 Ω 67 Ω 106 Ω 49 Ω LNA:24dB 500 Ω 45 Ω 83 Ω 31 Ω 143 Ω 37 Ω 59 Ω 27 Ω 52[4:0]/0x34[4:0] 11000 11001 11010 11011 11100 11101 11110 11111 LNA:12dB 667 Ω 122 Ω 207 Ω 87 Ω 316 Ω 102 Ω 154 Ω 76 Ω LNA:18dB 400 Ω 73 Ω 124 Ω 52 Ω 189 Ω 61 Ω 92 Ω 46 Ω LNA:24dB 222 Ω 41 Ω 69 Ω 29 Ω 105 Ω 34 Ω 51 Ω 25 Ω Programmable Feedback ResistorsforBufferAmplifierinTGC TestMode Differentfeedbackresistorscan be configuredforthebufferamplifierthroughtheregister54[4:0]when TGC test mode isenabled.Therefore,certaingaincan be appliedto the PGA testoutputsforCH7 and CH8. Table 7 describestherelationshipbetween theresistorconfigurationsand 54[4:0]settings.Note these5 resistorareput inparallel.When multiplebitsareenabled,theresistanceisreduced. Table7.Register54[4:0]Description 54[4:0] FUNCTION

00001 Enables250 Ω feedbackresistor

00010 Enables250 Ω feedbackresistor

00100 Enables500 Ω feedbackresistor

01000 Enables1000 Ω feedbackresistor

10000 Enables2000 Ω feedbackresistor

24, 30dB 3rd LP Filter 10, 15, 20, AFE5803 (1 of 8 Channels) 14Bit ADC LVDS ReferenceReference Differential TGC Vcntl EXT/INT REFs SPI OUT VCAT AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com THEORY OF OPERATION AFE5803 OVERVIEW The AFE5803 is a highlyintegratedAnalog Front-End(AFE) solutionspecificallydesigned forultrasound systems in which high performance and small size are required.The AFE5803 integratesa complete time-gain-control(TGC) imagingpath.Italsoenablesuserstoselectone ofvariouspower/noisecombinationsto optimizesystem performance.The AFE5803 containseightchannels;each channelsincludesa Low-Noise Amplifier(LNA),a VoltageControlledAttenuator(VCAT), a Programmable Gain Amplifier(PGA), a Low-pass Filter(LPF),and a 14-bitAnalog-to-DigitalConverter(ADC). Inaddition,multiplefeaturesintheAFE5803 aresuitableforultrasoundapplications,such as activetermination, individualchannel control,fastpower up/down response,programmable clamp voltagecontrol,fastand consistentoverloadrecovery,etc.Thereforethe AFE5803 bringspremium image qualityto ultra–portable, handheldsystemsalltheway up tohigh-endultrasoundsystems.Itssimplifiedfunctionblockdiagramislistedin Figure61. Figure61. FunctionalBlock Diagram LOW-NOISE AMPLIFIER (LNA) In many high-gainsystems,a low noise amplifieris criticalto achieveoverallperformance.Using a new proprietaryarchitecture,theLNA intheAFE5803 deliversexceptionallow-noiseperformance,whileoperatingon a low quiescentcurrentcompared to CMOS-based architectureswithsimilarnoise performance.The LNA performssingle-endedinputtodifferentialoutputvoltageconversion.Itisconfigurablefora programmable gain of24/18/12dBand itsinput-referrednoiseisonly0.63/0.70/0.9nV/√Hz respectively.Programmable gainsettings resultina flexiblelinearinputrange up to 1Vpp, realizinghighsignalhandlingcapabilitydemanded by new transducertechnologies.Largerinputsignalcan be acceptedby theLNA; however,thesignalcan be distorted sinceitexceeds theLNA ’s linearoperationregion.Combining thelow noiseand highinputrange,a wide input dynamic range isachievedconsequentlyforsupportingthe high demands from variousultrasoundimaging modes. The LNA inputisinternallybiasedatapproximately+2.4V; thesignalsourceshouldbe ac-coupledtotheLNA inputby an adequately-sizedcapacitor,e.g.≥0.1µF.To achievelow DC offsetdrift,theAFE5803 incorporatesa DC offsetcorrectioncircuitforeach amplifierstage.To improvethe overloadrecovery,an integratorcircuitis used toextracttheDC component oftheLNA outputand thenfedback totheLNA ’s complementaryinputforDC offsetcorrection.ThisDC offsetcorrectioncircuithas a high-passresponseand can be treatedas a high-pass filter.The effectivecornerfrequencyisdeterminedby the capacitorC BYPASS connectedat INM. With larger capacitors,thecornerfrequencyislower.For stableoperationatthehighestHP filercut-offfrequency,a ≥15 nF capacitorcan be selected.This cornerfrequencyscalesalmostlinearlywiththe valueof the C BYPASS . For example,15 nF givesa cornerfrequencyofapproximately100 kHz, while47 nF can givean effectivecorner frequencyof33 KHz. The DC offsetcorrectioncircuitcan alsobe disabled/enabledthroughregister52[12].

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 The AFE5803 can be terminatedpassivelyoractively.Activeterminationispreferredinultrasoundapplicationfor reducingreflectionfrom mismatches and achievingbetteraxialresolutionwithoutdegradingnoisefiguretoo much. Activeterminationvaluescan be presetto50,100,200,400Ω;othervaluesalsocan be programmed by users throughregister52[4:0].A feedback capacitoris requiredbetween ACTx and the signalsource as Figure62 shows.On theactiveterminationpath,a clampingcircuitisalsoused tocreatea low impedance path when overloadsignalisseen by theAFE5803. The clamp circuitlimitslargeinputsignalsattheLNA inputsand improvesthe overloadrecoveryperformanceof the AFE5803. The clamp levelcan be setto 350 mVpp, 600 mVpp, 1.15 Vpp automaticallydepending on the LNA gain settingswhen register52[10:9]=0.Other clamp voltages,such as 1.15Vpp,0.6Vpp, and 1.5Vpp, arealsoachievableby settingregister52[10:9].Thisclamping circuitisalsodesignedto obtaingood pulseinversionperformanceand reduce the impactfrom asymmetric inputs. Figure62. AFE5803 LNA withDC OffsetCorrectionCircuit VOLTAGE-CONTROLLED ATTENUATOR The voltage-controlledattenuatoris designed to have a linear-in-dBattenuationcharacteristic;thatis,the averagegainlossindB (refertoFigure2)isconstantforeach equalincrementofthecontrolvoltage(VCNTL) as shown inFigure63.A differentialcontrolstructureisused toreducecommon mode noise.A simplifiedattenuator structureisshown inthefollowingFigure63 and Figure64. The attenuatorisessentiallya variablevoltagedividerthatconsistsoftheseriesinputresistor(RS) and seven shuntFETs placedinparalleland controlledby sequentiallyactivatedclippingamplifiers(A1 throughA7).VCNTL isthe effectivedifferencebetween VCNTLP and VCNTLM. Each clippingamplifiercan be understoodas a specializedvoltagecomparator with a softtransfercharacteristicand well-controlledoutputlimitvoltage. ReferencevoltagesV1 throughV7 are equallyspaced overthe0V to1.5Vcontrolvoltagerange.As thecontrol voltageincreasesthroughthe inputrange of each clippingamplifier,the amplifieroutputrisesfrom a voltage where theFET isnearlyOFF toVHIGH where theFET iscompletelyON. As each FET approachesitsON state and the controlvoltagecontinuesto rise,the nextclippingamplifier/FETcombinationtakesover forthe next portionof the piecewise-linearattenuationcharacteristic.Thus, low controlvoltageshave most of the FETs turnedOFF, producingminimum signalattenuation.Similarly,highcontrolvoltagesturntheFETs ON, leadingto maximum signalattenuation.Therefore,each FET actstodecreasetheshuntresistanceofthevoltagedivider formedby Rs and theparallelFET network. Additionally,a digitallycontrolledTGC mode isimplementedtoachievebetterphase-noiseperformanceinthe AFE5803. The attenuatorcan be controlleddigitallyinsteadoftheanalogcontrolvoltageVCNTL .Thismode can be setby theregisterbit59[7].The variablevoltagedividerisimplementedas a fixedseriesresistanceand FET as theshuntresistance.Each FET can be turnedON by connectingtheswitchesSW1-7. Turningon each ofthe switchescan giveapproximately6dB of attenuation.Thiscan be controlledby the registerbits59[6:4].This digitalcontrolfeaturecan eliminatethenoisefromtheVCNTL circuitand ensurethebetterSNR and phase noise forTGC path. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):AFE5803

C - C Clipping Amplifiers1 8 A1 - A7 Attenuator Stages Attenuator Input RS VB Q2 Q3 Q4 Q5 Q6 Q7 VHIGH Attenuator Output Attenuator Input SW1 SW2 SW3 SW4 SW5 SW6 SW7 AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com Figure63. SimplifiedVoltageControlledAttenuator(AnalogStructure) Figure64. SimplifiedVoltageControlledAttenuator(DigitalStructure) The voltagecontrolledattenuator’s noisefollowsa monotonicrelationshiptotheattenuationcoefficient.At higher attenuation,theinput-referrednoiseishigherand vice-versa.The attenuator’s noiseisthenamplifiedby thePGA and becomes thenoiseflooratADC input.Intheattenuator’s highattenuationoperatingrange,i.e.VCNTL is high,theattenuator’s inputnoisemay exceed theLNA ’s outputnoise;theattenuatorthenbecomes thedominant noise source forthe followingPGA stage and ADC. Thereforethe attenuator’s noise should be minimized compared totheLNA outputnoise.The AFE5803 ’s attenuatorisdesignedforachievinglow noiseeven athigh attenuation(lowchannelgain)and realizingbetterSNR in near field.The inputreferrednoisefordifferent attenuationsislistedinthebelowtable: Table8.Voltage-Controlled-Attenuatornoisevs Attenuation Attenuation(dB) AttenuatorInputReferrednoise(nV/rtHz) –40 10.5 –36 10 –30 9 –24 8.5 –18 6 –12 4 –6 3 0 2 PROGRAMMABLE GAIN AMPLIFIER (PGA) Afterthevoltagecontrolledattenuator,a programmablegainamplifiercan be configuredas 24dB or30dB witha constantinputreferrednoiseof 1.75 nV/rtHz.The PGA structureconsistsof a differentialvoltage-to-current converterwithprogrammable gain,currentclamp( bias control)circuits,a transimpedanceamplifierwitha programmablelow-passfilter,and a DC offsetcorrectioncircuit.Itssimplifiedblockdiagramisshown below:

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 Figure65. SimplifiedBlock Diagram ofPGA Low inputnoiseisalwayspreferredina PGA and itsnoisecontributionshouldnotdegrade theADC SNR too much aftertheattenuator.Attheminimum attenuation(usedforsmallinputsignals),theLNA noisedominates;at the maximum attenuation(largeinputsignals),the PGA and ADC noisedominates.Thus 24 dB gainof PGA achievesbetterSNR as longas theamplifiedsignalscan exceed thenoiseflooroftheADC. The PGA currentclamp circuitcan be enabled(register51)toimprovetheoverloadrecoveryperformanceofthe AFE. Ifwe measure thestandarddeviationoftheoutputjustafteroverload,for0.5V VCNTL ,itisabout3.2LSBs in normal case,i.ethe outputisstablein about 1 clockcycleafteroverload.With the currentclamp circuit disabled,the valueapproaches4 LSBs meaning a longertimedurationbeforethe outputstabilizes;however, withthe currentclamp circuitenabled,therewillbe degradationinHD3 forPGA outputlevels> -2dBFS. For example,fora –2dBFS outputlevel,theHD3 degradesby approximately3dB. The AFE5803 integratesan anti-aliasingfilterin the form of a programmable low-passfilter(LPF) in the transimpedanceamplifier.The LPF isdesignedas a differential,active,3rd orderfilterwitha typical18dB per octaveroll-off.Programmable throughthe serialinterface,the –1dB frequencycornercan be set to one of 10MHz, 15 MHz, 20 MHz, and 30MHz. The filterbandwidthissetforallchannelssimultaneously. A selectableDC offsetcorrectioncircuitisimplementedinthePGA as well.Thiscorrectioncircuitissimilartothe one used in the LNA. Itextractsthe DC component of the PGA outputsand feeds back to the PGA ’s complimentaryinputsforDC offsetcorrection.ThisDC offsetcorrectioncircuitalsohas a high-passresponse witha cut-offfrequencyof80 KHz. ANALOG TO DIGITAL CONVERTER The analog-to-digitalconverter(ADC) oftheAFE5803 employs a pipelinedconverterarchitecturethatconsistsof a combinationofmulti-bitand single-bitinternalstages.Each stagefeedsitsdataintothedigitalerrorcorrection logic,ensuringexcellentdifferentiallinearityand no missingcodes atthe14-bitlevel.The 14 bitsgivenoutby each channelare serializedand sentout on a singlepairof pinsinLVDS format.Alleightchannelsof the AFE5803 operatefroma common inputclock(CLKP/M).The samplingclocksforeach oftheeightchannelsare generatedfrom the inputclockusinga carefullymatched clockbuffertree.The 14x clockrequiredforthe serializerisgeneratedinternallyfromtheCLKP/M pins.A 7x and a 1x clockarealsogivenoutinLVDS format, alongwiththe data,to enableeasy data capture.The AFE5803 operatesfrom internally-generatedreference voltagesthataretrimmedtoimprovethegainmatchingacrossdevices.The nominalvaluesofREFP and REFM are 1.5V and 0.5V,respectively.Alternately,thedevicealsosupportsan externalreferencemode thatcan be enabledusingtheserialinterface. UsingserializedLVDS transmissionhas multipleadvantages,such as a reducednumber ofoutputpins(saving routingspace on theboard),reducedpower consumption,and reducedeffectsofdigitalnoisecouplingtothe analogcircuitinsidetheAFE5803. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):AFE5803

(a)□INP (b)□INM (c) ACT CM CM S0493-01 ADC Input Clocks CLKP CLKM 5 kΩ 5 kΩ VCM AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com EQUIVALENT CIRCUITS Figure66. EquivalentCircuitsofLNA inputs Figure67. EquivalentCircuitsofVCNTLP/M Figure68. EquivalentCircuitsofClock Inputs

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–VdiffVcommon +Vdiff External 100- Load/c87 Switch impedance is nominally 50 ( 10%)/c87 /c177 AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 Figure69. EquivalentCircuitsofLVDS Outputs Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):AFE5803

0.1μF 0.1μF SCLK SDATA RESET SEN SOUT PDN_ADC PDN_VCA PDN_GLOBAL AVSS DVSS AVSS AVSS AVSS DVSS CVCNTL 470pF CVCNTL 470pF CH7_TEST_OUTP CH7_OUTP CH7_TEST_OUTM CH7_BUFFER_OUTM CH7_BUFFER_OUTP R (optional) Clock termination depends on clock types LVDS, PECL, or CMOS 5VA AVDD_5 V AVDD_ADC AVDD DVDD 3.3VA 1.8VA 1.8VD 10μF 1μF 1μF 1μF 1μF 1μF 1μF 1μF 1μF >1μF 0.1μF 0.1 μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 15nF 15nF 15nF 15nF 15nF 15nF 15nF 15nF 10μF 10μF 10μF 0.1μF N*0.1 Fμ N*0.1 Fμ N*0.1 Fμ CM_BYP VHIGH VCNTLP IN VCNTLP VCNTLM VREF_IN RVCNTL 200Ω RVCNTL 200Ω VCNTLM IN 1.4V >1μF R (optional) CH7_OUTM DNCs CH8_TEST_OUTP CH8_OUTP CH8_TEST_OUTM CH8_BUFFER_OUTM CH8_BUFFER_OUTP R (optional) R (optional) CH8_OUTM AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com

APPLICATION INFORMATION

Figure70. ApplicationCircuit

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DC□Offset Correction ACTx CACT CIN CBYPASS INPx INMx Input AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 A typicalapplicationcircuitdiagramislistedabove.The configurationforeach blockisdiscussedbelow. LNA CONFIGURATION LNA InputCoupling and Decoupling The LNA closed-looparchitectureisinternallycompensated formaximum stabilitywithouttheneed ofexternal compensationcomponents.The LNA inputsare biasedat 2.4 V and AC couplingisrequired.A typicalinput configurationisshown inFigure71.C IN istheinputAC couplingcapacitor.C ACT isa partoftheactivetermination feedback path.Even ifthe activeterminationis not used, the C ACT is requiredforthe clamp functionality. Recommended valuesforC ACT = 1 µF and C IN are ≥ 0.1 µF. A pairof clampingdiodesiscommonly placed between the T/R switchand the LNA input.Schottkydiodes withsuitableforwarddrop voltage(e.g.the BAT754/54 series,the BAS40 series,the MMBD7000 series,or similar)can be considereddependingon the transducerecho amplitude. Figure71. LNA InputConfigurations Thisarchitectureminimizesany loadingofthesignalsourcethatmay otherwiseleadtoa frequency-dependent voltagedivider.The closed-loopdesignyieldslow offsetsand offsetdrift.C BYPASS (≥0.015µF) isused tosetthe high-passfiltercut-offfrequencyand decouple the complimentaryinput.Itscut-offfrequencyis inversely proportionalto the C BYPASS value,The HPF cut-offfrequencycan be adjustedthroughthe register59[3:2]a Table9 lists.Low frequencysignalsatT/R switchoutput,such as signalswithslowringing,can be filteredout.In addition,theHPF can minimizesystem noisefrom DC-DC converters,pulserepetitionfrequency(PRF) trigger, and frame clock.Most ultrasoundsystems’ signalprocessingunitincludesdigitalhigh-passfiltersor band-pass filters(BPFs) inFPGAs or ASICs. Furthernoisesuppressioncan be achievedintheseblocks.In addition,a digitalHPF isavailableintheAFE5803 ADC. Iflow frequencysignaldetectionisdesiredinsome applications, theLNA HPF can be disabled. Table9.LNA HPF Settings(CBYPASS = 15 nF) Reg59[3:2](0x3B[3:2]) Frequency 00 100 KHz 01 50 KHz 10 200 KHz 11 150 KHz Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):AFE5803

total LNAnoise s LNAnoiseLNA _ Noise V R I/c61 /c43 /c180 (b) Active Termination S0499-01 LNARs (a)□No Termination (c)□Passive Termination LNARs Rf LNARs Rt AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com CM_BYP and VHIGH pins,which generateinternalreferencevoltages,need to be decoupled with ≥1uF capacitors.Biggerbypassingcapacitors(>2.2uF)may be beneficialiflowfrequencynoiseexistsinsystem. LNA Noise Contribution The noisespec iscriticalforLNA and itdeterminesthe dynamic range of entiresystem.The LNA of the AFE5803 achieveslow power and an exceptionallylow-noisevoltageof0.63nV/√Hz, and a low currentnoiseof 2.7pA/√Hz. Typicalultrasonictransducer’s impedance Rs variesfrom tensof ohms to severalhundreds of ohms. Voltage noise is the dominant noise in most cases; however, the LNA currentnoise flowingthroughthe source impedance (Rs)generatesadditionalvoltagenoise. (2) The AFE5803 achieveslow noisefigure(NF) overa wide range ofsourceresistancesas shown inFigure29, Figure30,andFigure31. ActiveTermination In ultrasoundapplications,signalreflectionexistsdue to long cablesbetween transducerand system.The reflectionresultsinextraringingadded toecho signalsinPW mode. Sincetheaxialresolutiondepends on echo signallength,such ringingeffectcan degrade the axialresolution.Hence, eitherpassiveterminationor active termination,ispreferredifgood axialresolutionisdesired.Figure72 shows threeterminationconfigurations: Figure72. TerminationConfigurations

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4500Ω 3600Ω 1800Ω 900Ω 450Ω IN LNA RZ A1 2 /c61 /c110/c43 f IN IN IN LNA RZ / /C / /RA1 2 /c61 /c110/c43 f AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 Under the no terminationconfiguration,the inputimpedance of the AFE5803 isabout 6 KΩ (8 K//20pF) at 1 MHz. PassiveterminationrequiresexternalterminationresistorR t,whichcontributestoadditionalthermalnoise. The LNA supportsactiveterminationwithprogrammablevalues,as shown inFigure73 . Figure73. ActiveTerminationImplementation The AFE5803 has fourpre-settings50,100,200 and 400 Ω which are configurablethroughtheregisters.Other terminationvaluescan be realizedby settingtheterminationswitchesshown inFigure73.Register[52]isused to enable these switches.The inputimpedance of the LNA under the activeterminationconfiguration approximatelyfollows: (3) Table 5 liststhe LNA R INs under differentLNA gains.System designerscan achievefinetuningfordifferent probes. The equivalentinputimpedance isgivenby Equation4 where R IN (8K) and C IN (20pF) aretheinputresistance and capacitanceoftheLNA. (4) ThereforetheZIN isfrequencydependentand itdecreasesas frequencyincreasesshown inFigure10.Since2 MHz~10 MHz isthemost commonly used frequencyrange inmedicalultrasound,thisrolling-offeffectdoesn’t impactsystem performancegreatly.Since each ultrasoundsystem includesmultipletransducerswithdifferent impedances,theflexibilityofimpedance configurationisa greatplus. Figure29,Figure30,and Figure31 shows theNF underdifferentterminationconfigurations.Itindicatesthatno terminationachievesthe bestnoisefigure;activeterminationadds lessnoisethan passivetermination.Thus terminationtopologyshouldbe carefullyselectedbased on each use scenarioinultrasound. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):AFE5803

(a) Single-Ended Input at VCNTLP (b) Differential Inputs at V and VCNTLP CNTLM TGC Gain V = 0VCNTLM VCNTLP 1.5V XdB X+40dB TGC Gain VCNTLM VCNTLP XdB X+40dB 1.5V 0.75V AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com LNA Gain Switch Response The LNA gainisprogrammablethroughSPI.The gainswitchingtimedepends on theSPI speed as wellas the LNA gainresponsetime.Duringtheswitching,glitchesmightoccurand theycan appearas artifactsinimages. LNA gainswitchingina singleimaginglinemay not be preferred,althoughdigitalsignalprocessingmightbe used hereforglitchsuppression. VOLTAGE-CONTROLLED-ATTENUATOR The attenuatorin the AFE5803 is controlledby a pairof differentialcontrolinputs,the VCNTLM/P pins.The differentialcontrolvoltagespans from0 V to1.5V. Thiscontrolvoltagevariestheattenuationoftheattenuator based on itslinear-in-dBcharacteristic.Itsmaximum attenuation(minimum channelgain)appears at VCNTLP - VCNTLM = 1.5V, and minimum attenuation(maximum channelgain)occursatVCNTLP - VCNTLM = 0.The typical gainrangeis40 dB and remainsconstant,independentofthePGA setting. When onlysingle-endedVCNTL signalisavailable,this1.5VPP signalcan be appliedon theVCNTLP pinwiththe VCNTLM pinconnectedtoground.As shown inFigure74,TGC gaincurveisinverselyproportionaltotheVCNTLP - VCNTLM . Figure74. VCNTLP and VCNTLM Configurations

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www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 As discussedinthe theoryof operation,the attenuatorarchitectureuses seven attenuatorsegments thatare equallyspaced in orderto approximatethe linear-in-dBgain-controlslope.This approximationresultsin a monotonicslope;thegainrippleistypicallylessthan±0.5dB. The controlvoltageinput(VCNTLM/P pins)representsa high-impedanceinput.The VCNTLM/P pins of multiple AFE5803 devicescan be connectedinparallelwithno significantloadingeffects.When thevoltagelevel(VCNTLP - VCNTLM ) isabove 1.5V or below 0 V, theattenuatorcontinuestooperateatitsmaximum attenuationlevelor minimum attenuationlevelrespectively.Itisrecommended tolimitthevoltagefrom-0.3V to2 V. The AFE5803 gain-controlinputhas a –3 dB bandwidthofapproximately800KHz. Thiswidebandwidth,although usefulinmany applications(e.g.fastVCNTL response),can alsoallowhigh-frequencynoisetomodulatethegain controlinputand finallyaffecttheDopplerperformance.Inpractice,thismodulationcan be avoidedby additional externalfiltering(RVCNTL and CV CNTL ) atVCNTLM/P pinsas Figure69 shows. However, theexternalfilter'scutoff frequencycannotbe kepttoolow as thisresultsinlow gainresponsetime.Withoutexternalfiltering,thegain controlresponsetimeistypicallylessthan1 μs tosettlewithin10% ofthefinalsignallevelof1VPP (–6 dBFS) outputas indicatedinFigure48 and Figure49. TypicalVCNTLM/P signalsare generatedby an 8bitto 12bit10MSPS digitalto analogconverter(DAC) and a differentialoperationamplifier.TI’s DACs, such as TLV5626 and DAC7821/11 (10MSPS/12bit),couldbe used to generate TGC controlwaveforms. Differentialamplifierswith outputcommon mode voltagecontrol(e.g. THS4130 and OPA1632) can connecttheDAC totheVCNTLM/P pins.The bufferamplifiercan alsobe configured as an activefiltertosuppresslow frequencynoise.More informationcan be foundinthedocuments SLOS318 and SBAA150 .The VCNTL vs Gain curvescan be foundinFigure2.The below tablealsoshows theabsolute gainvs.VCNTL ,whichmay helpprogramDAC correspondingly. InPW Dopplerand colorDopplermodes, VCNTL noiseshouldbe minimizedtoachievethebestclose-inphase noiseand SNR. DigitalVCNTL featureisimplementedtoaddressthisneed intheAFE5803. InthedigitalVCNTL mode, no externalVCNTL isneeded. Table10.VCNTLP –VCNTLM vs Gain Under DifferentLNA and PGA Gain Settings(Low Noise Mode) Gain (dB) Gain (dB) Gain (dB) Gain (dB) Gain (dB) Gain (dB)VCNTLP –VCNTLM LNA = 12 dB LNA = 18 dB LNA = 24 dB LNA = 12 dB LNA = 18 dB LNA = 24 dB(V) PGA = 24 dB PGA = 24 dB PGA = 24 dB PGA = 30 dB PGA = 30 dB PGA = 30 dB 1.5 –4 2 8 1.8 7.8 13.8 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):AFE5803

Noisy□Clock n×(20~65)MHz TI□Jitter□Cleaner CDCE72010/ CDCM7005 CDCLVP1208 1-to-8 CLK□Buffer 20~65□MHz ADC□CLK8 Synchronized ADC□CLKs CDCE72010□has□10 outputs□thus□the□buffer may□not□be□needed□for 64CH□systems AFE AFE AFE AFE AFE AFE AFE AFE B0437-01 AFE5803 SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com ADC OPERATION ADC Clock Distribution To ensure thatthe aperturedelayand jitterare the same forallchannels,the AFE5803 uses a clocktree networktogenerateindividualsamplingclocksforeach channel.The clock,forallthechannels,are matched from thesourcepointtothesamplingcircuitofeach oftheeightinternalADCs. The variationon thisdelayis describedintheaperturedelayparameteroftheoutputinterfacetiming.Itsvariationisgivenby theaperturejitter number ofthesame table. Figure75. ADC Clock DistributionNetwork In the single-endcase,itisrecommended thatthe use of low jittersquare signals(LVCMOS levels,1.8 V amplitude).See TIdocument SLYT075 forfurtherdetailson thetheory. The jittercleanerCDCM7005 or CDCE72010 issuitabletogeneratetheAFE5803 ’s ADC clockand ensurethe performanceforthe14bitADC with77 dBFS SNR. A clockdistributionnetworkisshown inFigure75. The AFE5803 can acceptdifferentialLVDS, LVPECL, and otherdifferentialclockinputsas wellas single-ended clock.AC couplingisrequiredbetween clockdriversand theAFE5803 clockinputs.When single-endedclockis used,CLKM shouldbe tiedto ground.Common clockconfigurationsare illustratedinFigure76. Appropriate terminationisrecommended toachievegood signalintegrity.

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(a) LVPECL Configuration (c) Transformer Based Configuration (d) CMOS Configuration (b) LVDS Configuration CMOS CLK Driver AFE CMOS CLK CMOS AFE CLOCKs CLOCK SOURCE 50 Ω 0.1 Fμ 0.1 Fμ 0.1 Fμ 0.1 Fμ CDCE72010 AFE CLOCKs100 Ω LVDS 0.1 Fμ 0.1 Fμ CDCM7005 CDCE72010 AFE CLOCKs 130 Ω LVPECL 0.1 Fμ 0.1 Fμ 83 Ω 3.3 V 3.3 V 130 Ω AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 Figure76. Clock Configurations Specialconsiderationsshould be appliedin such a clockdistributionnetwork design.In typicalultrasound systems,itispreferredthatallclocksaregeneratedfroma same clocksource,such as CW clocks,audioADC clocks,RF ADC clock,pulserepetitionfrequencysignal,frameclockand etc.By doingthis,interferencedue to clockasynchronizationcan be minimized. ADC ReferenceCircuit The ADC ’s voltagereferencecan be generatedinternallyor providedexternally.When the internalreference mode isselected,the REFP/M becomes outputpinsand shouldbe floated.When 3[15]=1 and 1[13]=1,the deviceisconfiguredtooperateintheexternalreferencemode inwhichtheVREF_IN pinshouldbe drivenwitha 1.4V referencevoltageand REFP/M must be leftopen.Sincetheinputimpedance oftheVREF_IN ishigh,no specialdrivecapabilityisrequiredforthe1.4Vvoltagereference Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):AFE5803

SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com The digitalbeam-formingalgorithminan ultrasoundsystem relieson gainmatchingacrossallreceiverchannels. A typicalsystem would have about12 octalAFEs on theboard.Insuch a case,itiscriticaltoensurethatthe gainismatched,essentiallyrequiringthe referencevoltagesseen by allthe AFEs to be the same. Matching referenceswithinthe eightchannelsof a chip is done by using a singleinternalreferencevoltagebuffer. Trimming the referencevoltageson each chip duringproductionensures thatthe referencevoltagesare well-matchedacrossdifferentchips.When the externalreferencemode isused,a solidreferenceplaneon a printedcircuitboardcan ensureminimalvoltagevariationacrossdevices.More informationon voltagereference designcan be foundinthedocument SLYT339 .The dominantgainvariationintheAFE5803 comes from the VCA gainvariation.The gainvariationcontributedby theADC referencecircuitismuch smallerthantheVCA gainvariation.Hence,inmost systems,usingtheADC internalreferencemode issufficienttomaintaingood gain matchingamong multipleAFE5803s. Inaddition,theinternalreferencecircuitwithoutany externalcomponents achievessatisfactorythermalnoiseand phase noiseperformance. POWER MANAGEMENT Power/Performance Optimization The AFE5803 has optionsto adjustpower consumptionand meet differentnoiseperformances.Thisfeature would be usefulforportablesystems operatedby batterieswhen low power ismore desired.See theelectrical characteristicstableas wellas thetypicalcharacteristicplots. Power Management Priority Power management playsa criticalroletoextendbatterylifeand ensurelongoperationtime.The AFE5803 has fastand flexiblepower down/up controlwhichcan maximizebatterylife.The AFE5803 can be powered down/up throughexternalpinsor internalregisters.The followingtableindicatestheaffectedcircuitblocksand priorities when thepower management isinvoked.The higherprioritycontrolscan overwritethelowerpriorityones.Inthe device,allthepower down controlsare logicallyORed togeneratefinalpower down fordifferentblocks.Thus, thehigherprioritycontrolscan coverthelowerpriorityones.The AFE5803 registersettingsaremaintainedwhen theAFE5803 isineitherpartialpower down mode orcompletepower down mode. Table11.Power Management Priority Name Blocks Priority Pin PDN_GLOBAL All High Pin PDN_VCA LNA + VCAT+ PGA Medium Register VCA_PARTIAL_PDN LNA + VCAT+ PGA Low Register VCA_COMPLETE_PDN LNA + VCAT+ PGA Medium Pin PDN_ADC ADC Medium Register ADC_PARTIAL_PDN ADC Low Register ADC_COMPLETE_PDN ADC Medium Register PDN_VCAT_PGA VCAT + PGA Lowest Register PDN_LNA LNA Lowest PartialPower-Up/Down Mode The partialpower up/down mode isalsocalledas fastpower up/down mode. Inthismode, most amplifiersinthe signalpath are powered down, whilethe internalreferencecircuitsremain activeas wellas the LVDS clock circuit,i.e.theLVDS circuitstillgeneratesitsframeand bitclocks. The partialpower down functionallowsthe AFE5803 to be wake up from a low-powerstatequickly.This configurationensures thatthe externalcapacitorsare dischargedslowly;thus a minimum wake-up time is needed as longas thechargeson thosecapacitorsarerestored.The VCA wake-up responseistypicallyabout2 μs or1% ofthepower down durationwhicheverislarger.The longestwake-up timedepends on thecapacitors connectedat INP and INM, as the wake-up time isthe time requiredto rechargethe caps to the desired operatingvoltages.For 0.1μF atINP and 15nF atINM can givea wake-up timeof2.5ms.For largercapacitors thistime willbe longer.The ADC wake-up time is about 1 μs. Thus the AFE5803 wake-up time is more dependenton theVCA wake-up time.Thisalsoassumes thattheADC clockhas been runningforatleast50 µs beforenormaloperatingmode resumes.The power-down timeisinstantaneous,lessthan1.0µs.

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R int/R ext CH7/8_BUFFER _O UTM CH7/8_BUFFER _O UTP CH7/8_TEST_O UTM CH7/8_TEST_O UTP PG A C H7/8P PG A C H7/8M 5 k/c87 5 k/c87 AFE5803 www.ti.com SLOS763A –JANUARY 2012–REVISED JANUARY 2012 Thisfastwake-up responseisdesiredforportableultrasoundapplicationsinwhich thepower savingiscritical. The pulserepetitionfrequencyofa ultrasoundsystem couldvaryfrom50KHz to500Hz, whiletheimagingdepth (i.e.,theactiveperiodfora receivepath)variesfrom 10 μs tohundredsofus.The power savingcan be pretty significantwhen a system’s PRF islow.Insome cases,onlytheVCA would be powered down whiletheADC keeps runningnormallytoensureminimalimpacttoFPGAs. In the partialpower-down mode, the AFE5803 typicallydissipatesonly26mW/ch, representingan 80% power reductioncompared to the normal operatingmode. This mode can be set usingeitherpins(PDN_VCA and PDN_ADC) orregisterbits(VCA_PARTIAL_PDN and ADC_PARTIAL_PDN). Complete Power-Down Mode To achievethelowestpower dissipationof0.7mW/CH, theAFE5803 can be placedintoa completepower-down mode. This mode is controlledthrough the registersADC_COMPLETE_PDN, VCA_COMPLETE_PDN or PDN_GLOBAL pin.In the complete power-down mode, allcircuitsincludingreferencecircuitswithinthe AFE5803 are powered down; and thecapacitorsconnectedtotheAFE5803 are discharged.The wake-up time depends on the timeneeded to rechargethesecapacitors.The wake-up timedepends on the timethatthe AFE5803 spends inshutdownmode. 0.1μF atINP and 15 nF atINM can givea wake-up timecloseto2.5ms. VCA TEST MODES The AFE5803 includesmultipletestmodes toacceleratesystem development.The ADC testmodes have been discussedintheregisterdescriptionsection. The VCA has a testmode inwhich theCH7 and CH8 PGA outputscan be brought.By monitoringthesePGA outputs,thefunctionalityofVCA operationcan be verified.Some registersare relatedtothistestmode. PGA Test Mode Enable: Reg59[9];BufferAmplifierPower Down Reg59[8];and BufferAmplifierGain Control Reg54[4:0]. The PGA outputsareconnectedtothevirtualgroundpinsofthebufferamplifierthrough5 kΩ resistors.The PGA outputscan be monitoredat the bufferamplifieroutputswhen the bufferampliferisenabled.Note thatthe signalsat the bufferamplifieroutputsare attenuateddue to the 5KΩ resistors.The attenuationcoefficientis R INT/EXT/5kΩ.See Table7 fortheR INT configuration. An alternativeway istomeasure thePGA outputsdirectlyattheCH8_TEST_OUTM/P and CH7_TEST_OUTM/P when thebufferamplifierispowered down. Based on thebufferamplifierconfiguration,theregisterscan be setindifferentways: Configuration1: Inthisconfiguration,thetestoutputscan be monitoredatCH7/8_TEST_OUTP/M Reg59[9]=1;Testmode enabled Reg59[8]=0;Bufferamplifierpowered down Configuration2: Inthisconfiguration,thetestoutputscan be monitoredatCH7/8_BUFFER_OUTP/M Reg59[9]=1;Testmode enabled Reg59[8]=1;Bufferamplifierpowered on Reg54[4:0]=10H;Internalfeedback2K resistorenabled.Differentvaluescan be used as well Figure77. AFE5803 PGA TestMode Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):AFE5803

SLOS763A –JANUARY 2012–REVISED JANUARY 2012 www.ti.com POWER SUPPLY, GROUNDING AND BYPASSING In a mixed-signalsystem design,power supplyand groundingdesignplaysa significantrole.The AFE5803 distinguishesbetween two differentgrounds:AVSS(Analog Ground)and DVSS(digitalground).Inmost cases,it shouldbe adequate to layout the printedcircuitboard (PCB) to use a singleground planeforthe AFE5803. Care shouldbe takenthatthisgroundplaneisproperlypartitionedbetween varioussectionswithinthesystem to minimizeinteractionsbetween analogand digitalcircuitry.Alternatively,thedigital(DVDD) supplysetconsisting oftheDVDD and DVSS pinscan be placedon separatepower and ground planes.For thisconfiguration,the AVSS and DVSS grounds shouldbe tiedtogetherat the power connectorina starlayout.In addition,optical isolatorordigitalisolators,such as ISO7240,can separatetheanalogportionfromthedigitalportioncompletely. Consequentlytheypreventdigitalnoisetocontaminatetheanalogportion.Table11 liststherelatedcircuitblocks foreach power supply. Table12.Supply vs CircuitBlocks POWER SUPPLY GROUND CIRCUIT BLOCKS LNA, attenuator,PGA withcurrentclamp AVDD (3.3VA) AVSS and BPF, referencecircuits,PGA testmode buffer,VCA SPI AVDD_5V (5VA) AVSS LNA, referencecircuits AVDD_ADC (1.8VA) AVSS ADC analogand referencecircuits DVDD (1.8VD) DVSS LVDS and ADC SPI AllBypassingand power suppliesfortheAFE5803 shouldbe referencedtotheircorrespondingground planes. Allsupplypinsshouldbe bypassed with0.1 µF ceramicchipcapacitors(size0603 or smaller).In orderto minimizetheleadand traceinductance,thecapacitorsshouldbe locatedas closetothesupplypinsas possible. Where double-sidedcomponent mounting is allowed,these capacitorsare best placed directlyunder the package.Inaddition,largerbipolardecouplingcapacitors2.2µF to10 µF, effectiveatlowerfrequencies)may alsobe used on themain supplypins.These components can be placedon thePCB inproximity(< 0.5inor 12.7mm) totheAFE5803 itself. The AFE5803 has a number of referencesuppliesneeded to be bypassed,such CM_BYP, VHIGH, and VREF_IN. These pinsshouldbe bypassed withat least1µF; highervaluecapacitorscan be used forbetter low-frequencynoisesuppression.For bestresults,choose low-inductanceceramicchipcapacitors(size0402,> 1 µF)and placethem as closeas possibletothedevicepins. High-speedmixed signaldevicesaresensitivetovarioustypesofnoisecoupling.One primarysourceofnoiseis theswitchingnoisefrom theserializerand theoutputbuffer/drivers.For theAFE5803, carehas been takento ensurethattheinteractionbetween theanalogand digitalsupplieswithinthedeviceiskepttoa minimalamount. The extentof noisecoupledand transmittedfrom the digitaland analog sectionsdepends on the effective inductancesof each of the supplyand ground connections.Smallereffectiveinductanceof the supplyand groundpinsleadstoimprovednoisesuppression.For thisreason,multiplepinsareused toconnecteach supply and groundsets.ItisimportanttomaintainlowinductancepropertiesthroughoutthedesignofthePCB layoutby use ofproperplanesand layerthickness. BOARD LAYOUT Proper groundingand bypassing,shortlead length,and the use of ground and power-supplyplanes are particularlyimportantforhigh-frequencydesigns.Achievingoptimum performancewith a high-performance devicesuch as the AFE5803 requirescarefulattentionto the PCB layoutto minimizethe effectsof board parasiticsand optimizecomponent placement.A multilayerPCB usuallyensures best resultsand allows convenientcomponent placement.In orderto maintainproperLVDS timing,allLVDS tracesshouldfollowa controlledimpedance design.In addition,allLVDS tracelengthsshould be equal and symmetrical;itis recommended tokeep tracelengthvariationslessthan150mil(0.150inor3.81mm). Additionaldetailson BGA PCB layouttechniquescan be found inthe Texas InstrumentsApplicationReport MicroStarBGA PackagingReferenceGuide (SSYZ015B ),whichcan be downloadedfromwww.ti.com.

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REVISION HISTORY

www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) AFE5803ZCF Active Production NFBGA (ZCF) | 135 160 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR 0 to 85 AFE5803 AFE5803ZCF.A Active Production NFBGA (ZCF) | 135 160 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR 0 to 85 AFE5803 AFE5803ZCF.B Active Production NFBGA (ZCF) | 135 160 | JEDEC TRAY (5+1) Yes SNAGCU Level-3-260C-168 HR 0 to 85 AFE5803 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TRAY L - Outer tray length without tabs KO - Outer tray height W - Outer tray width P1 - Tray unit pocket pitch CW - Measurement for tray edge (Y direction) to corner pocket center CL - Measurement for tray edge (X direction) to corner pocket center Text Chamfer on Tray corner indicates Pin 1 orientation of packed units. *All dimensions are nominal Device Package Name Package Type Pins SPQ Unit array matrix Max temperature (°C) L (mm) W (mm) (µm) (mm) CL (mm) CW (mm) AFE5803ZCF ZCF NFBGA 135 160 10 x 16 150 315 135.9 7620 19.2 13.5 10.35 Pack Materials-Page 1

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Product Information

AFE5803ZCF.B specifications and overview.

Summary

Fully Integrated, 8-Channel Ultrasound Analog Front End, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 158 mW/CH REVISED JANUARY 2012

Description

Fully Integrated, 8-Channel Ultrasound Analog Front End, 0.75 nV/rtHz, 14/12-Bit, 65 MSPS, 158 mW/CH REVISED JANUARY 2012

Source title AFE5803ZCF.B Datasheet(PDF) - Texas Instruments

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Technical content

30 MHz

2 SubmitDocumentationFeedback Copyright© 2012,Texas InstrumentsIncorporated

135 PINS

DESCRIPTION

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ELECTRICAL CHARACTERISTICS

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65 MSPS 59 69

50 MSPS 51

40 MSPS 46

20 MSPS 35

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50 Ohms

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200 Ohms

400 Ohms

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00000 No feedbackresistorenabled

00001 Enables450 Ω feedbackresistor

00010 Enables900 Ω feedbackresistor

00100 Enables1800 Ω feedbackresistor

01000 Enables3600 Ω feedbackresistor

10000 Enables4500 Ω feedbackresistor

00001 Enables250 Ω feedbackresistor

00010 Enables250 Ω feedbackresistor

00100 Enables500 Ω feedbackresistor

01000 Enables1000 Ω feedbackresistor

10000 Enables2000 Ω feedbackresistor

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APPLICATION INFORMATION

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AFE5803ZCF.B specifications and overview.

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