Microcontroller

AFE4110

Texas Instruments

MIXED SIGNAL MICROCONTROLLER

Manufacturer: Texas Instruments

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www.ti.com SLLSE48 –JANUARY 2012 MIXEDSIGNALMICROCONTROLLER Check forSamples: AFE4110 1FEATURES

UltraLow Supply-Voltage(ULV) Range – Extended InputMultiplexerforHigh Accuracy RC DischargeMeasurement– 1.1V-1.55VUnregulatedSingleCellBattery Operation(CPU, System Core,and Timers) • ULV Analog Pool – 3mA 1.85VInternalCharge Pump for – 8-BitAnalog-to-DigitalConverter(ADC) ExternalEEPROM (R/W),VDDIO, and – 8-BitDigital-to-AnalogConverter(DAC) InternalLCD Controller – Programmable Comparator (COMP)
FamilyMembers Include:SelectionsBetween 1MHz and 5.4MHz – AFE4110B :– 20kHz Internallow Frequency Clock Oscillator – 512B RAM Memory – ExternalClock Input(Upto8MHz) – 16KB ROM (TIPSUC, Custom) AFE4110A:– 32kHz CrystalOscillator – 14KB RAM + 512B RAM• InternalHigh Frequency OscillatorFrequency Correction – 16KB ROM (TIDSUC,TI Bootloader) – FacilitatesGenerationand Measurement of • 55-Bonding Pads Availableas Tested Wafers, Real Time IntervalsWithouta Clock Crystal See theOrderingInformationforOther Options– UtilizesFactoryCalibration(E-Fuse),S/W, and a SingleExternal1M Ω Resistor APPLICATIONS• IntegratedLCD Controller
For any applicationrequiringa fullanalog– Drives4-Mux,3-Mux,2-Mux,or StaticMode signalchainand an LCD displaydriversuchLCDs as digitalthermometers,pedometers,– Up to48 (4x12)LCD Segments thermostats,and otherportablesinglealkaline• Two 16-BitTimer0_A3 withThree batterydevices.Capture/Compare Registers Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

Timer0_A3 3 CC Registers Analog-Pool ULV-Ref, 8-bit ADC, 8-Bit DAC, Comparator SVS HF-OSC Timer1_A3 3 CC Registers P3.0 CLKIN, XTIN LF-OSC ULV Brownout LCD Segments Reset Int-Logic 16KB ROM I/O Port VCC I/O Port Vcc/1.8V/ 3.3V JTAG, SPI, BUZZER P3.6,P3.7 P2.0-P2.3 P4.0-P4.3 GND/Vss VBAT Power Activation, CPU & Working Registers 4W-JTAG Debug Support CORE TMS, TCK, TDI, TDO Vref RST/NMI/SVMOUT VDDIOACTIV 32XTL P3.1 XTOUT 4COM X 12SEG LDO, 1.8V Charge Pump 1.8V 1.0V AFE4110 SLLSE48 –JANUARY 2012 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

DESCRIPTION

The Texas InstrumentsMSP430 familyof low-powermixed signalASSPs consistsof many devicesfeaturing differentsetsofperipheralstargetedforvariousconsumer medicalapplications.The AFE4110 CPU architecture isbased on thepopularultralowpower Texas InstrumentsMSP430 RISC processor. The AFE4110 configurationwithtwo 16-bittimers,integrated48-segment LCD driver,programmable Analog Pool,supplyvoltagemonitorand internalreferencevoltagesourceisparticularlywellsuitedforimplementationof low costdigitalthermometersoperatingfroma singlecellSR60 battery.The capabilitytocorrecttheon chiphigh frequencyoscillatoroutputfacilitatesthe generationand measurement of realtime intervals.For many applications,thiscapabilityallowssystemdesignerstoeliminatea clockcrystalfromthesystemBOM. ORDERING INFORMATION (1) TA ORDERABLE PART 0ºC to70ºC AFE4110B000YS (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTIweb siteatwww.ti.com. FUNCTIONAL BLOCK DIAGRAM, AFE4110

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www.ti.com SLLSE48 –JANUARY 2012 ABSOLUTE MAXIMUM RATINGS (1) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) VALUE UNIT MIN MAX VoltageappliedatVDD referencedtoVSS (VAMR ) –0.3 1.8 V –0.3 VDD + 0.3 V Voltageappliedtoany pin(referencestoVSS ) –0.3 1.8 V Diodecurrentatany devicepin(2) ± 2.5 mA Storagetemparaturerange(3) –55 150 °C ESD toleranceHBM 2000 V (1) Stressesbeyond thoselistedunder"absolutemaximum ratings" may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions" isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagesreferencedtoVSS . (3) Highertemperaturemay be appliedduringboardsolderingaccordingtothecurrentJEDEC J-STD-020specificationwithpeak reflow temperaturesnothigherthanclassifiedon thedevicelabelon theshippingboxes orreels. RECOMMENDED OPERATING CONDITIONS overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) MIN TYP MAX UNIT VDD Supplyvoltageduringprogramexecution 1.1 1.55 V VSS Supplyvoltage(GND reference) 0 V TA Operatingfree-airtemperature 0 70 °C CV DD Capacitoron VDD 470 nF VDD > 1.1V 1 fSYSTEM (1)(2) MHz VDD > 1.5V 4 (1) The AFE4110 CPU isclockeddirectlywithMCLK. Boththehighand lowphase ofMCLK must notexceed thepulsewidthofthe specifiedmaximum frequency. (2) Modules may have a differentmaximum inputclockspecification.Seethespecificationoftherespectivemodule inthisdatasheet. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com ActiveMode Supply Current(IntoVCC ) (1)(2) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VDD TA MIN TYP MAX UNIT fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz, 1.3V 72 Program executesinRAM, 30°C µA 1.55V 86CPUOFF = 0,SCG0 = 0,SCG1 = 0,OSCOFF = 0 IAM,1MHz fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHz, 1.3V 74 Program executesinRAM, 70°C µA 1.55V 88CPUOFF = 0,SCG0 = 0,SCG1 = 0,OSCOFF = 0 fMCLK = fSMCLK = 125 kHz,fACLK = 20 kHz 1.3V 33 Program executesinRAM 30°C µA 1.55V 37CPUOFF = 0,SCG0 = 0,SCG1 = 0,OSCOFF = 0 IAM,125kHz fMCLK = fSMCLK = 125 kHz,fACLK = 20 kHz, 1.3V 35 Program executesinRAM, 70°C µA 1.55V 40CPUOFF = 0,SCG0 = 0,SCG1 = 0,OSCOFF = 0 fMCLK = fSMCLK :1 to5 MHz, fACLK = 20 kHz IAM /MHz Program executesinRAM, CPUOFF = 0,SCG0 = 0, 1.3V 30°C 45 µA/MHz SCG1 = 0,OSCOFF = 0 (1) Allinputsaretiedto0 V ortoVDD .Outputsdo notsourceorsinkany current. (2) Characterizedwithprogramexecutingtypicaldataprocessing"Type2". Low-Power Mode Supply Current(IntoVCC ) (1)(2) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VDD TA MIN TYP MAX UNIT 1.3V 8.3 11 30°C 1.55V 9.5 12fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHzILPM0 µACPUOFF = 1,SCG0 = 0,SCG1 = 0,OSCOFF = 0 1.3V 11 14 70°C 1.55V 12 17 1.3V 8.3 11 30°C 1.55V 9.5 12fMCLK = fSMCLK = 1 MHz, fACLK = 20 kHzILPM1 µACPUOFF = 1,SCG0 = 1,SCG1 = 0,OSCOFF = 0 1.3V 11 14 70°C 1.55V 12 17 1.3V 28 32 30°C 1.55V 29 33fMCLK = fSMCLK = 1MHz, fACLK = 1MHzILPM2,1MHz µACPUOFF = 1,SCG0 = 0,SCG1 = 1,OSCOFF = 0 1.3V 30 35 70°C 1.55V 32 38 1.3V 8.3 12 30°C 1.55V 9.5 13fMCLK = fSMCLK = fACLK = 20 kHzILPM2,20kHz µACPUOFF = 1,SCG0 = 0,SCG1 = 1,OSCOFF = 0 1.3V 11 15 70°C 1.55V 12 17 1.3V 8.3 11 30°C 1.55V 9.5 12fMCLK = fSMCLK = fACLK = 20 kHzILPM3 µACPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 0 1.3V 11 14 70°C 1.55V 12 17 1.3V 6 7.9 30°C 1.55V 7.8 10fMCLK = fSMCLK = fACLK = 20 kHzILPM4 µACPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 1 1.3V 8.6 12 70°C 1.55V 11 16 (1) CurrentforWDT clockedby ACLK included. (2) CurrentforBrownoutincluded.

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www.ti.com SLLSE48 –JANUARY 2012 PortsP1,P3 (exceptforP3.6,P3.7),RST, NMI, SVMOUT overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VDD = 1.1V,IOH = –1 mA (1)forportsP1,P3 VDD -0.25 VOH VDD = 1.55V,IOH = –1 mA (1)forportsP1,P3 VDD -0.15 V VDD = 1.1V,IOH = –300 µA (1)forportsP1,P3 VDD -0.15 VDD = 1.1V,IOL = 2.5mA (2)forportsP1,P3 0.2 VOL VDD = 1.55V,IOL = 2.5mA (2)forportsP1,P3 0.15 V VDD = 1.1V,IOL = 300 µA (2)forportsP1,P3 0.07 VDD = 1.55V 0.3x VDD V VIL VDD = 1.1V 0.25x VDD V VDD = 1.55V 0.7x VDD V VIH VDD = 1.55V 0.75x VDD V VHYS IntrinsicHysteresis 150 mV VDD = 1.1V,C L = 15 pF ||R L = 750Ω toVss on VOH forportsP1,P3 75 VDD = 1.1V,C L = 15 pF ||R L = 320Ω toVcc on VOL forportsP1,P3 75 Δt/Δv ns/V VDD = 1.55V,C L = 25 pF ||R L= 1600Ω toVss on VOH forportsP1,P3 75 VDD = 1.55V,C L = 25 pF ||R L= 600Ω toVss on VOL forportsP1,P3 75 IOH VDD = 1.1V – 1.55V forportsP1,P3 –1 mA IOL VDD = 1.1V – 1.55V forportsP1,P3 2.5 mA ILKG VDD = 1.1V – 1.55V ±100 nA tINT P0.x;VDD = 1.1V – 1.55V 200 ns R PULL Forpullup:VIN = VSS ;Forpulldown:VIN = VDD forportsP1,P3 30 35 40 kΩ R RST Pullupon RST, NMI, SVMOUT 30 35 40 kΩ R EXT Externalpullup resistoron RST terminal(optional) 680 kΩ C I VIN = VSS orVDD 7 pF (1) The maximum totalcurrentIOH ,foralloutputscombined shouldnotexceed 5mA toholdthemaximum voltagedropspecified (2) The maximum totalcurrentIOL ,foralloutputscombined shouldnotexceed 15mA toholdthemaximum voltagedropspecified Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com PortsP2,P4 and Port3.7,Port3.6 1.1V< VDDIO < 3.3Voverrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT VDDIO = 1.1V,IOH = –1 mA (1) VDDIO -0.25 VOH VDDIO = 3.3V,IOH = –1 mA (1) VDDIO -0.15 V VDDIO = 1.1V,IOH = –300 µA (1) VDDIO -0.15 VDDIO = 1.1V,IOL = 2.5mA (2) 0.2 VOL VDDIO = 3.3V,IOL = 2.5mA (2) 0.15 V VDDIO = 1.1V,IOL = 300 µA (2) 0.07 VDDIO = 3.3V 0.3x VDDIO V VIL VDDIO = 1.1V 0.25x V VDDIO VDDIO = 3.3V 0.7x VDDIO V VIH VDDIO = 1.1V 0.75x VDDIO V VIT+ VDDIO = 1.1V – 3.3V (positivegoinginputthreshold) VILmax+VHYS VIHmin V VIT– VDDIO = 1.1V – 3.3V (negativegoinginputthreshold) VILmax VIHmin-VHYS V VHYS IntrinsicHysteresis 150 mV VDDIO = 1.1V,C L = 15 pF ||R L = 750Ω toVSS on VOH forportsP1,P2,P3 75 VDDIO = 1.1V,C L = 15 pF ||R L = 320Ω toVDD on VOL forportsP1,P2,P3 75 Δt/Δv ns/V VDDIO = 3.3V,C L = 25 pF ||R L= 1600Ω toVSS on VOH forportsP1,P2,P3 75 VDDIO = 3.3V,C L = 25 pF ||R L= 600Ω toVSS on VOL forportsP1,P2,P3 75 IOH VDDIO = 1.1V – 3.3V forportsP1,P2,P3 –1 mA IOL VDDIO = 1.1V – 3.3V forportsP1,P2,P3 2.5 mA ILKG VDDIO = 1.1V – 3.3V ±100 nA tINT P0.x;VDD = 1.1V – 3.3V 200 ns R PULL Forpullup:VIN = VSS ;Forpulldown:VIN = VDDIO forportsP1,P2,P3 30 35 40 kΩ R RST Pullupon RST/NMI/SVMOUT 30 35 40 kΩ C I VIN = VSS orVDDIO 7 pF (1) The maximum totalcurrentIOH ,foralloutputscombined shouldnotexceed 5mA toholdthemaximum voltagedropspecified (2) The maximum totalcurrentIOL ,foralloutputscombined shouldnotexceed 15mA toholdthemaximum voltagedropspecified PortsP3.6,P3.7(HighCurrentBuzzer) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VDDIO = 1.1V,IOH = –10 mA VDDIO-0.15 VOH V VDDIO = 3.3V,IOH = –10 mA VDDIO-0.15 VDDIO = 1.1V,IOL = 10 mA 0.2 VOL V VDDIO = 3.3V,IOL = 10 mA 0.15 VDDIO = 1.1V,C L = 15 pF ||R L = 750Ω toVSS on VOH 75 VDDIO = 1.1V,C L = 15 pF ||R L = 320Ω toVDD on VOL 75 Δt/Δv ns/V VDDIO = 1.55V,C L = 25 pF ||R L= 1600Ω toVSS on 75 VDDIO = 1.55V,C L = 25 pF ||R L= 600Ω toVSS on 75 IOH VDDIO = 1.1V – 3.3V –10 mA IOL VDDIO = 1.1V – 3.3V 10 mA ILKG VDDIO = 1.1V – 3.3V ±100 nA tINT P0.x;VDD = 1.1V – 3.3V 200 ns R PULL Onlypulldownimplemented:VIN = VDDIO 30 35 40 kΩ C I VIN = VSS orVDD 7 pF

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www.ti.com SLLSE48 –JANUARY 2012 High Frequency – OSCILLATOR overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT fHFOSC VDD = 1.1V – 1.55V (untrimmed) 4 5 7 MHz DutyCycle VDD = 1.1V – 1.55V 45% 50% 55% tSTART VDDC = 1.1V – 1.55V 20 µs ΔfDCO /ΔT VDD = 1.1V – 1.55V;fDCO = 4 MHz ±0.07 %/°C ΔfDCO /VDD VDD = 1.1V – 1.55V;fDCO = 4 MHz ±1 %/V ΔfDCO /CALSTEP VDD = 1.1V – 1.55V;fDCO = 4 MHz; ±64 calibrationsteps 0.1 1 4 %/Step IOP VDD = 1.1V – 1.55V;fDCO = 4 MHz 25 µA IOP VDD = 1.1V – 1.55V;fDCO = 1 MHz 22 µA Low Frequency – OSCILLATOR overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT fLFO VDD = 1.1V – 1.55V 6 20 45 kHz DutyCycle VDD = 1.1V – 1.55V 45% 50% 55% tSTART VDD = 1.1V – 1.55V 500 µs IOP VDDC = 1.1V – 1.55V;fLFO = 20 kHz 600 nA 32 kHz Crystal– OSCILLATOR overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT fLFO VDD = 1.1V – 1.55V 32 kHz DutyCycle VDD = 1.1V – 1.55V 45% 50% 55% tSTART VDDC = 1.1V – 1.55V 200 mS IOP VDD = 1.1V – 1.55V 2 µA CP_1P8 Specifications overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Start-uptime 5mS Supplyvoltagebatteryinput 1.1 1.55 V Outputvoltage,VO 1.8x VBAT No loadvoltage VBAT = 1.55V 3 V Max loadvoltage VBAT = 1.2V 1.85 V Max load CP18 = 10 nF 0.01 3 mA Charge pump efficiency 70% Clockingfrequency 4 MHz Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com Brown-Out Reset (BOR) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VBOR(Start) 490 mV V(BOR_IT+) VDD rising;dVDD /dt< 3V/s 1095 1150 mV V(BOR_IT–) VDD falling;dVDD /dt< 3V/s 860 900 mV Vhys(BOR) 200 mV VMARGIN VMARGIN = V(BOR-IT-)– VCRIT;T = 0-70°C 40 mV tdBOR 3000(1) µs IOP VDD = 1.1V – 1.55V 500 nA (1) Depends on thevoltageramp inthesystem(actuallya maximum typicalvalue). A-POOL, ExternalReferenceSource overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VREF VDD = 1.1V – 1.55V forADC /DAC operation 100 475 mV VDD = 1.1V – 1.55V ADC /DAC notoperational 0 VDD V IREF VDD = 1.1V – 1.55V 3 µA C REF REFON = 0 20 50 pF A-POOL, Built-InReferenceSource overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VREF VDD = 1.1V – 1.55V (±1.5%;overall3%) 256 ±3% mV IREF VDD = 1.1V – 1.55V 10 µA C REF REFON = 1 20 50 pF TREF VDD = 1.1V – 1.55V (ΔV/ΔT×VREF referencedto25°C) ±250 ppm/°C tsettle VDD = 1.1V – 1.55V;REFON = 1;C REF = C REF (max) 900 µs IOP VDD = 1.1V – 1.55V;REFON = 1;C REF = C REF (max) 50 µA A-POOL, Temperature Sensor overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT ISENSOR VCC = 1.1V – 1.55V 2 µA TC SENSOR VCC = 1.1V – 1.55V;0-70°C (ΔV/ΔT referencedto30°C) 464 µV/°C VOFFSET25 VCC = 1.1V – 1.55V atTA = 30°C 179 mV tSETTLE VCC = 1.1V – 1.55V (beforestartofconversion) 15 µs VSENSOR (1) VCC = 1.1V – 1.55V;0-70°C 179 mV (1) The followingformulacan be used tocalculatethetemperaturesensoroutputvoltage VSENSOR = VOFFSET25 + TC SENSOR × (TA = 30°C)

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www.ti.com SLLSE48 –JANUARY 2012 A-POOL, InputVoltageDividers overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT any Rx individers ±1.5% ΔRx/Rx any Rx acrossswitchesand internalsupplyvoltagedivider(by4,by 8) ±2% on A0/A1 ;VA0/VA1 = 0.5V;ADIV0/ADIV1 = 1 (500mV range) 120 200 300 R IN on A2/A3 ;VA2/VA3 = 0.5V;ADIV2/ADIV4 = 1 (1V range) 80 133 190 kΩ on A2/A3 ;VA2/VA3 = 0.5V;ADIV2 + ADIV3/ADIV4 + ADIV5 = 1 (2V range) 70 114 150 ΔIVDD ADIV7 = 1 (supplyvoltagedivideron) 2 µA A-POOL, DAC-8 overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VREFEXT VDD = 1.1V – 1.55V 256 mV tSETTLE On ±1 LSB steps(6τ);VDD = 1.1V – 1.55V;VREFEXT (typ);C VREF (min) 2 µs Between allcodes >20 on AOUT (6τ);VDD = 1.1V – 1.55V;VREFEXT (typ); 14 µsC VREF (min) EI ±3 LSBVDD = 1.1V – 1.55V;VREFEXT (typ);C VREF (min);(add±7 mV forVOUT offset(1))ED ±1 LSB (1) Thisoffsetcan be compensated usingpropersoftware. A-POOL, Comparator overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VIN VDD = 1.1V – 1.55V 0 275 mV Overdrive= 20 mV 0.5 tpd Overdrive= 5 mV 0.5 µs Overdrive= 1 mV 1 A-POOL, AOUT Pin overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT |ILOAD | VDD = 1.1V – 1.55V;C LOAD = 25 pF;VOUT >50mV 5 µA |ILOAD | VDD = 1.1V – 1.55V;C LOAD = 25 pF;VOUT >20mV 2 µA tSETTLE VDD = 1.1V – 1.55V;C LOAD = 25 pF;±1% (6τ)(forAOUT 20-256mV) 4 µs A-POOL, ADC-8 Counter overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fCNT VDD = 1.1V – 1.55V 1 MHz tCONV Fullconversion(allcodes)atfCNT = 1MHz 256 µs RAM overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER CONDITIONS MIN TYP MAX UNIT VOP Operatingtemperature0-70°C, fCPU = 1MHz 1.1 V VRET Operatingtemperature0-70°C (tracksBOL level) 700 mV Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com PIN DESIGNATION, AFE4110 PAD# PAD X [µ] PAD Y [µ] PAD# PAD X [µ] PAD Y [µ] 1 2108.3 987.3 28 96.0 23.6 2 1994.6 987.3 29 171.0 23.6 3 1908.6 987.3 30 246.0 23.6 4 1824.2 987.3 31 321.0 23.6 5 1749.2 987.3 32 396.0 23.6 6 1674.2 987.3 33 471.0 23.6 7 1599.2 987.3 34 546.0 23.6 8 1521.8 987.3 35 621.0 23.6 9 1446.8 987.3 36 696.0 23.6 10 1371.8 987.3 37 771.0 23.6 11 1296.8 987.3 38 846.0 23.6 12 1221.8 987.3 39 921.0 23.6 13 1146.8 987.3 40 996.0 23.6 14 1071.8 987.3 41 1071.0 23.6 15 996.8 987.3 42 1146.0 23.6 16 921.8 987.3 43 1221.0 23.6 17 846.8 987.3 44 1296.0 23.6 18 771.8 987.3 45 1371.0 23.6 19 696.8 987.3 46 1446.0 23.6 20 621.8 987.3 47 1521.0 23.6 21 546.8 987.3 48 1596.0 23.6 22 471.8 987.3 49 1671.0 23.6 23 396.8 987.3 50 1746.0 23.6 24 321.8 987.3 51 1821.0 23.6 25 246.8 987.3 52 1896.0 23.6 26 171.8 987.3 53 1971.0 23.6 27 96.8 987.3 54 2046.0 23.6 55 2121.0 23.6

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www.ti.com SLLSE48 –JANUARY 2012 PIN FUNCTIONS PIN I/O(1) DESCRIPTION NAME NO. P3.0/XTI/EXCLK/TA1.CCI1A1 1 I/O General-purposedigitalI/O 32 kHz CrystalInput ExternalClockInput Timer1_A3 CCR1A1 capture:CCI1A1 input,compare P3.1/XTO/TSCLK/TA1.CCI1A2/ 2 I/O General-purposedigitalI/O ACTSEN/CMP 32 kHz CrystalOut TestClockInput Timer1_A3 CCR1A2 capture:CCI1A2 input,compare ActivationSense Output ComparatorOut VSS/GND 3 Power Analogand DigitalPower SupplyGround Reference Timer0_A3 Out1 output Timer1_A3 Out1 output Timer1_A3 Out0 output Timer1_A3 CCR2A2 capture:CCI2A2 input,compare Timer0_A3 Out1 output Timer1_A3 Out1 output Timer1_A3 Out0 output Timer1_A3 CCR2A3 capture:CCI2A3 input,compare RST/NMI/SVMOUT 6 I/O Resetinputactivelow Non-maskableinterruptinput SVM Output P3.6/ 7 I/O 10mA General-purposedigitalI/O TA1.CCI1A3/ Timer0_A3 Out1 output TA1.1/BOR/ACTSEN/LFOSC/CP18OK Timer0_A3 Out2 output Timer0_A3 Out0# output Timer0_A3 Out1# output Timer0_A3 Out2# output Timer1_A3 CCR1A3 capture:CCI1A3 input,compare Timer1_A3 Out1 output BOR Out ActivationSense Output LFOSC Out CP 1.8VOK Out P3.7/ 8 I/O 10mA General-purposedigitalI/O TA1.CCI2A1/HFOSC/LCDCPCLK/ Timer0_A3 Out1 output LCDFCLK/ 1KCLK/LCDCMP Timer0_A3 Out2 output Timer0_A3 Out0# output Timer0_A3 Out1# output Timer0_A3 Out2# output Timer1_A3 CCR2A1 capture:CCI2A1 input,compare LCD Charge Pump ClockOut LCD Frame ClockOut 1 kHz ActivationClockOut LCD VoltageComparatorOut TCK/P2.0/TA1.2/TA1.1/CxOUT 10 I/O JTAG Testclock General-purposedigitalI/O Timer1_A3 Out2 output Timer1_A3 Out1 output CxOUT digitaloutfromA-Pool (1) I= input,O = output,N/A = notavailableon thispackage offering. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com PIN FUNCTIONS (continued) PIN I/O(1) DESCRIPTION NAME NO. TMS/P2.1/EXT_CLK/TA0.1/TA0.2 11 I/O JTAG Testmode selec1 General-purposedigitalI/O Timer0_A3 Out2 output Timer0_A3 Out1 output XTAL_CLK orEXT_CLK monitorout TDI/P2.2/HF_CLK/CxOUT/TA1.0/ 12 I/O JTAG Testdatainput General-purposedigitalI/O Timer1_A3 Out0 output CxOUT digitaloutfromA-Pool HF_CLK out TDO/P2.3/LF_CLK/TA0.2 13 I/O JTAG Testdataoutput General-purposedigitalI/O Timer0_A3 Out2 output LF_CLK Out P4.0/TA0.2/TA1.2/ACLK/ATEST/SPI_CS 14 I/O General-purposedigitalI/O Timer0_A3 Out2 output Timer1_A3 Out2 output ACLK output AnalogTestMultiplexerOut SPI ChipSelect P4.1/TA0.2/TA1.2/SMCLK/SPI_MOSI 15 I/O General-purposedigitalI/O Timer0_A3 Out2 output Timer1_A3 Out2 output SMCLK output SPI SerialIN P4.2/TA0.2/TA1.2/MCLK/SPI_CLK 16 I/O General-purposedigitalI/O Timer0_A3 Out2 output Timer1_A3 Out2 output MCLK output SPI ClockOut P4.3/TA0.2/TA1.2/1KOSC//SPI_MISO 17 I/O General-purposedigitalI/O Timer0_A3 Out2 output Timer1_A3 Out2 output 1 kHz ActivationOscillatorOut SPI SerialOut GNDIO 18 Power PX.X GND LCD_ECOM.0 19 Analog LCD_E Common-0 ,0V – 3.4V LCD_ECOM.1 20 Analog LCD_E Common-1 ,0V – 3.4V LCD_ECOM.2 21 Analog LCD_E Common-2 ,0V – 3.4V LCD_ECOM.3 22 Analog LCD_E Common-3 ,0V – 3.4V LCD_ESEG.0 23 Analog LCD_E Segment-0 ,0V – 3.4V LCD_ESEG.1 24 Analog LCD_E Segment-1 ,0V – 3.4V LCD_ESEG.2 25 Analog LCD_E Segment-2 ,0V – 3.4V LCD_ESEG.3 26 Analog LCD_E Segment-3 ,0V – 3.4V LCD_ESEG.4 27 Analog LCD_E Segment-4 ,0V – 3.4V VSS/GND 28 Power Analogand DigitalPower SupplyGround Reference LCD_ESEG.5 29 Analog LCD_E Segment-5 ,0V – 3.4V LCD_ESEG.6 30 Analog LCD_E Segment-6 ,0V – 3.4V LCD_ESEG.7 31 Analog LCD_E Segment-7 ,0V – 3.4V LCD_ESEG.8 32 Analog LCD_E Segment-8 ,0V – 3.4V LCD_ESEG.9 33 Analog LCD_E Segment-9 ,0V – 3.4V LCD_ESEG.10 34 Analog LCD_E Segment-10 ,0V – 3.4V LCD_ESEG.11 35 Analog LCD_E Segment-11 ,0V – 3.4V

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www.ti.com SLLSE48 –JANUARY 2012 PIN FUNCTIONS (continued) PIN I/O(1) DESCRIPTION NAME NO. LCD_EHVCAP 36 Analog LCD_E HV Charge Pump ExtCapacitortoGND, 3.4V CP18CAP 37 Analog Minimum 1.8VCharge pump ExtcapacitorC toVSS CP1P8_C2_IN 38 Analog 1.8VCharge pump ExtcapacitorB for2mA drive CP1P8_C2_OUT 39 Analog 1.8VCharge pump ExtcapacitorB for2mA drive CP1P8_C1_IN 40 Analog 1.8VCharge pump ExtcapacitorA for2mA drive CP1P8_C1_OUT 41 Analog 1.8VCharge pump ExtcapacitorA for2mA drive VPP 42 Power Factoryprogrammingvoltage.VPP must be tiedtoVDD innormaluse mode. TA0.CCI2B0/A2 Timer0_A3 Out2 output Timer0_A3 Out1 output Timer1_A3 Out2 output LDO 1V Out Timer0_A3 CCR1B0 capture:CCI1B0 input,compare Timer0_A3 CCR2B0 capture:CCI2B0 input,compare AnaloginputA2 – A-Pool TA0.CCI2A1/A1 Timer0_A3 Out2 output Timer0_A3 Out1 output Timer1_A3 Out2 output LDO 1V Out Timer0_A3 CCR1A1 capture:CCI1A1 input,compare Timer0_A3 CCR2A1 capture:CCI2A1 input,compare AnaloginputA1 – A-Pool P1.2/TA0.2/TA0.1/TA1.2/AOUT/ 45 I/O General-purposedigitalI/O TA0.CCI1A2/TA0.CCI2A2/A3 Timer0_A3 Out2 output Timer0_A3 Out1 output Timer1_A3 Out2 output AnalogOut -A-Pool Timer0_A3 CCR1A2 capture:CCI1A2 input,compare Timer0_A3 CCR2A2 capture:CCI2A2 input,compare AnaloginputA3 – A-Pool P1.3/TA0.2/TA0.1/TA1.2/REFOUT/ 46 I/O General-purposedigitalI/O TA0.CCI1A3/TA0.CCI2A3/A3 Timer0_A3 Out2 output Timer0_A3 Out1 output Timer1_A3 Out2 output VrefOut – A-Pool Timer0_A3 CCR1A3 capture:CCI1A3 input,compare Timer0_A3 CCR2A3 capture:CCI2A3 input,compare AnaloginputA3 – A-Pool P1.4/TA0.2/TA0.1/TA1.2/LDO1/ 47 I/O General-purposedigitalI/O TA0.CCI1B1/TA0.CCI2B1/A0 Timer0_A3 Out2 output Timer0_A3 Out1 output Timer1_A3 Out2 output LDO 1V Out Timer0_A3 CCR1B1 capture:CCI1B1 input,compare Timer0_A3 CCR2B1 capture:CCI2B1 input,compare AnaloginputA0 – A-Pool TA0.CCI2B2 Timer0_A3 Out2 output Timer0_A3 Out1 output Timer1_A3 Out2 output Timer0_A3 CCR1B2 capture:CCI1B2 input,compare Timer0_A3 CCR2B2 capture:CCI2B2 input,compare Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com PIN FUNCTIONS (continued) PIN I/O(1) DESCRIPTION NAME NO. TA1.CCI2B0 Timer0_A3 Out2 output Timer0_A3 Out1 output Timer1_A3 Out2 output Timer1_A3 CCR1B0 capture:CCI1B0 input,compare Timer1_A3 CCR2B0 capture:CCI2B0 input,compare P3.3/TA0.1/TA1.1/TA1.0/A0/LDO1 50 I/O General-purposedigitalI/O Timer0_A3 Out1 output Timer1_A3 Out1 output Timer1_A3 Out0 output LDO 1V Out AnaloginputA0 – A-Pool P3.2/TA0.1/TA1.1/TA1.0 51 I/O General-purposedigitalI/O Timer0_A3 Out1 output Timer1_A3 Out1 output Timer1_A3 Out0 output ACTIVE 52 I SleepMode (LPM5) activationpin VBAT 53 Power BatteryPower,SwitchedfromVDD VSS/GND 54 Power Analogand DigitalPower SupplyGround Reference VDD 55 Power Analogand DigitalPower Supply

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(DSUC + APIs) 2KBTI Loader AFE41 10 B IVECS TI ROM (PSUC + APIs) 32B 2KB 14KB Cal-RAM 128B 128B Peripherals Custom ROM 0xFFFF 0xFFDF 0xC800 0xC000 0x0 0x1000 0x1C00 0x1C80 App LRAM 0x1D00 App RAM 256B 0x1DFF 14KB AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Memory Organization

AFE4110 manufacturedin2 memory configurations
AFE4110A – ApplicationDevelopmentDevice – 14KB DevelopmentRAM – 512B ApplicationRAM – 2KB DevelopmentStartUp Code ROM – 14KB BootLoaderROM
AFE4110B – Custom Masked ROM Device – 512B ApplicationRAM – 2KB ProductionStartUp Code ROM – 14KB Custom Masked ROM Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com INSTRUCTION SETSHORT-FORM DESCRIPTION The instructionset consistsof the original51CPU instructionswith threeformatsand seven address modes and additionalinstructionsforthe expandedThe AFE4110 isbased on an MSP430 CPU corewith addressrange.Each instructioncan operateon worda 16-bitRISC architecturethatishighlytransparentto and bytedata.Table1 shows examples ofthethreethe application.All operations, other than typesof instructionformats;the addressmodes areprogram-flowinstructions,are performedas register listedinTable2.operationsin conjunctionwith seven addressing modes for source operand and four addressing modes fordestinationoperand. The CPU isintegratedwith16 registersthatprovide reduced instruction execution time. The register-to-registeroperationexecutiontime is one cycleoftheCPU clock. Four of the registers,R0 to R3, are dedicatedas program counter,stackpointer,statusregister,and constant generator respectively.The remaining registersaregeneral-purposeregisters. Peripheralsare connected to the CPU using data, address,and controlbuses,and can be handledwith allinstructions. Table1.InstructionWord Formats Dualoperands,source-destination e.g.ADD R4, R5 R4 + R5 → R5 Singleoperands,destinationonly e.g.CALL R8 PC → (TOS),R8 → PC Relativejump,un/conditional Jump-on-equalbit= 0 Table2.Address Mode Descriptions ADDRESS MODE S (1) D (2) SYNTAX EXAMPLE OPERATION Register ● ● MOV Rs,Rd MOV R10, R11 R10 → R11 Indexed ● ● MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6) Symbolic(PC relative) ● ● MOV EDE, TONI M(EDE) → M(TONI) Absolute ● ● MOV & MEM, and TCDAT M(MEM) → M(TCDAT) Indirect ● MOV atRn, Y(Rm) MOV atR10,Tab(R6) M(R10) → M(Tab+R6) M(R10) → R11Indirectautoincrement ● MOV atRn+,Rm MOV atR10+, R11 R10 + 2 → R10 Immediate ● MOV at45,TONI MOV #45,TONI #45 → M(TONI) (1) S = source (2) D = destination

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www.ti.com SLLSE48 –JANUARY 2012 OperationModes The AFE4110 has one activemode and sixsoftwareselectablelow-powermodes of operation.An interrupt eventcan wake up thedevicefromany ofthefivelow-powermodes, servicetherequestand restoreback tothe low-powermode on returnfromtheinterruptprogram. The followingseven operatingmodes can be configuredby software:

Activemode AM; – Allclocksareactive
Low-power mode 0 (LPM0); – CPU isdisabled – ACLK and SMCLK remainactiveforallsources – MCLK isdisabled
Low-power mode 1 (LPM1); – CPU isdisabled – ACLK and SMCLK remain active(forLF-Osc and CLKIN as source;HF-Osc ismapped to LF-Osc as source) – MCLK isdisabled
Low-power mode 2 (LPM2); – CPU isdisabled – MCLK isdisabled – SMCLK isdisabled – ACLK remainsactiveforallsources
Low-power mode 3 (LPM3); – CPU isdisabled – MCLK isdisabled – SMCLK isdisabled – ACLK remainsactive(forLF-Osc and CLKIN as source;HF-Osc ismapped toLF-Osc as source)
Low-power mode 4 (LPM4); – CPU isdisabled – ACLK isdisabled – MCLK isdisabled – Oscillatorsarestopped(excludeActivationBlock1kHz localoscillator)
Low-power mode 5 (LPM5); – CPU coreand peripherialsarepowered off(Applicationand CalibrationRAM contentsarenotretained.) – ActivationBlock,1kHz localoscillator,and 8 bytesRAM remainactive Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com InterruptVectorAddresses The interruptvectorsand thepower-upstartaddressare locatedintheaddressrange 0FFFFh – 0FFE0h. The vectorcontainsthe16-bitaddressoftheappropriateinterrupt-handlerinstructionsequence. Table3.InterruptSources,Flags,and Vectors INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY System Reset WDTIFG(1) Reset 0x0FFFE 14,highest Power-Up ExternalReset Watchdog System NMI SVMIFG, VMAIFG (1) (Non)maskable 0x0FFFC 13 Vacantmemory access User NMI NMIIFG (1)(2) (Non)maskable 0x0FFFA 12 NMI Timer1_A3 TA1CCR0 CCIFG (3) Maskable 0x0FFF8 11 Timer1_A3 TA1CCR1 CCIFG Maskable 0x0FFF6 10 TA1CCR2 CCIFG TA1IFG (1)(3) Watchdog Timer_A IntervalTimerMode WDTIFG Maskable 0x0FFF4 9 A-Pool CxIFG Maskable 0x0FFF2 8 I/OPortP1 P1IFG.0toP1IFG.6(1)(3) Maskable 0x0FFF0 7 Timer0_A3 TA0CCR0 CCIFG (3) Maskable 0x0FFEE 6 Timer0_A3 TA0CCR1 CCIFG Maskable 0x0FFEC 5 TA0CCR1 CCIFG TA0IFG (1)(3) I/OPortP2 P2IFG.0toP2IFG.3(1)(3) Maskable 0x0FFEA 4 I/OPortP3 P3IFG.0toP3IFG.7(1)(3) Maskable 0x0FFE8 3 I/OPortP4 P4IFG.0toP4IFG.3(1)(3) Maskable 0x0FFE6 2 LCD Controller LCDFRMIFG, Maskable 0x0FFE4 1 LCDBLKOFFIFG, LCDBLKONIFG, LCDNOCAPIFG The FollowingInterruptsaremultiplexedon I/OPortP3 interrupts ActivationSense (4)(5) Muxed withP3.6 Maskable 0x0FFE8 3 CP 1p8 Valid(4)(5) Muxed withP3.7 Maskable 0x0FFE8 3 Activationsleepcountertimeout(4)(5) Muxed withP3.4 Maskable 0x0FFE8 3 CP 1p8 comparatorout(4)(5) Muxed withP3.5 Maskable 0x0FFE8 3 LCD CP comparatorout(4)(5) Muxed withP3.2 Maskable 0x0FFE8 3 APOOL comparatorout(4) Muxed withP3.3 Maskable 0x0FFE8 3 (1) Multiplesourceflags (2) A resetisgeneratediftheCPU triestofetchinstructionsfromwithinperipheralspace orvacantmemory space.(Non)maskable:the individualinterrupt-enablebitcan disablean interruptevent,butthegeneral-interruptenablecannotdisableit. (3) Interruptflagsarelocatedinthemodule. (4) No additionalsynchronizationmechanisms beyond standardMSP430 interruptsynchronization (5) InterruptSignalisdirectlyconnotedwithouta de-glitchermechanism.

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www.ti.com SLLSE48 –JANUARY 2012 SpecialFunctionRegisters(SFRs) The AFE4110 SFRs are locatedinthe lowestaddressspace and can be accessed viaword or byteformats. Other SFR registersdocumented inTexas InstrumentsMSP430x5xx "Compact SYS Module User's Guide" (SLAU321 ). Legend rw: Bitcan be readand written. rw-0,1: Bitcan be readand written.Itisresetorsetby PUC rw-(0,1): Bitcan be readand written.Itisresetorsetby POR. rw-[0,1]: Bitcan be readand written.Itisresetorsetby BOR. SFR bitisnotpresentindevice SFRIE1, SFRIE1_L, SFRIE1_H, InterruptEnable Register 15 14 13 12 11 10 9 8 r0 r0 r0 r0 r0 r0 r0 rw-0 7 6 5 4 3 2 1 0 JMBOUTIE JMBINIE – NMIIE VMAIE – OFIE WDTIE rw-0 rw-0 r0 rw-0 rw-0 r0 rw-0 rw-0 Reserved Bits15 – 9 Reserved.Read back as 0 SVMIE Bit8 SVM interruptenableflag. 0 interruptsdisabled 1 interruptsenabled JMBOUTIE Bit7 JTAG mailboxoutputinterruptenableflag. 0 interruptsdisabled 1 interruptsenabled JMBINIE Bit6 JTAG mailboxinputinterruptenableflag. 0 interruptsdisabled 1 interruptsenabled Reserved Bit5 Reserved.Reads back as 0 NMIIE Bit4 NMI pininterruptenableflag. 0 interruptsdisabled 1 interruptsenabled VMAIE Bit3 Vacantmemory accessinterruptenableflag. 0 interruptsdisabled 1 interruptsenabled Reserved Bit2 Reserved.Reads back as 0 OFIE Bit1 Oscillatorfaultinterruptenableflag.0 interruptsdisabled1 interruptsenabled WDTIE Bit0 Watchdog timerinterruptenable.ThisbitenablestheWDTIFG interruptforintervaltimermode. Itis notnecessarytosetthisbitforwatchdogmode. Because otherbitsin~IE1 may be used forother modules,itisrecommended tosetorclearthisbitusingBIS.BorBIC.Binstructions,ratherthan MOV.B orCLR.B instruction 0 interruptsdisabled 1 interruptsenabled Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com SFRIFG1, SFRIFG1_L, SFRIFG1_H, InterruptFlagRegister 15 14 13 12 11 10 9 8 r0 r0 r0 r0 r0 r0 r0 rw-0 7 6 5 4 3 2 1 0 JMBOUTIFG JMBINIFG – NMIIFG VMAIFG – OFIFG WDTIFG rw-0 rw-0 r0 rw-0 rw-0 r0 rw-0 rw-0 Reserved Bits15 – 9 Reserved.Read back as 0 SVMIFG Bit8 SVM interruptflag.ThisbitsignalsthattheA-POOL comparatorsignaledan SVM eventeither lowvoltageorhighvoltagedependingon setup 0 no interruptpending 1 interruptpending JMBOUTIFG Bit7 JTAG mailboxoutputinterruptflag 0 no interruptpending.When in16-bitmode (JMBMODE = 0),thisbitisclearedautomatically when JMBO0 has been writtenby theCPU. When in32-bitmode (JMBMODE = 1),thisbitis clearedautomaticallywhen bothJMBO0 and JMBO1 have been writtenby theCPU. Thisbitis alsoclearedwhen theassociatedvectorinSYSSNIV has been read 1 interruptpending,JMBO registersarereadyfornew messages.In16-bitmode (JMBMODE=0) JMBO0 has been receivedby JTAG. In32-bitmode (JMBMODE=1) ,JMBO0 and JMBO1 have been receivedby JTAG JMBINIFG Bit6 JTAG mailboxinputinterruptflag 0 no interruptpending.When in16-bitmode (JMBMODE = 0),thisbitisclearedautomatically when JMBI0 isreadby theCPU. When in32-bitmode (JMBMODE = 1),thisbitiscleared automaticallywhen bothJMBI0 and JMBI1 have been readby theCPU. Thisbitisalsocleared when theassociatedvectorinSYSSNIV has been read 1 interruptpending,a message iswaitingintheJMBIN registers.In16-bitmode (JMBMODE = 0)when JMBI0 has been writtenby JTAG. In32 bitmode (JMBMODE = 1)when JMBI0 and JMBI1 have been writtenby JTAG Reserved Bit5 Reserved.Reads back as 0 NMIIFG Bit4 NMI pininterruptflag 0 no interruptpending 1 interruptpending VMAIFG Bit3 Vacantmemory accessinterruptflag 0 no interruptpending 1 interruptpending Reserved Bit2 Reserved.Reads back as 0 OFIFG Oscillatorfaultinterruptflag 0 no interruptpending 1 interruptpending WDTIFG Bit0 Watchdog timerinterruptflag.Inwatchdogmode, WDTIFG remainssetuntilresetby software. Inintervalmode, WDTIFG isresetautomaticallyby servicingtheinterrupt,orcan be resetby software. Because otherbitsin~IFG1 may be used forothermodules,itisrecommended toclear 0 no interruptpending 1 interruptpending

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www.ti.com SLLSE48 –JANUARY 2012 SFRRPCR, SFRRPCR_H, SFRRPCR_L, Reset Pin ControlRegister 15 14 13 12 11 10 9 8 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 – – – – SYSRSTRE SYSRSTUP SYSNMIES SYSNMI r0 r0 r0 r0 r1 r1 r1 rw-0 Reserved Bits15–9 Reserved.Read back as 0 SYSRSTRE Bit3 ResetPinresistorenable

0 Pullup/pulldownresistorattheRST/NMI pinisdisabled

1 Pullup/pulldownresistorattheRST/NMI pinisenabled

SYSRSTUP Bit2 Resetresistorpinpullup/pulldown

0 Pulldownisselected

1 Pullupisselected

SYSNMIES Bit1 NMI edge select.Thisbitselectstheinterruptedge fortheNMI interruptwhen SYSNMI = 1. Modifyingthisbitcan triggeran NMI. Modifythisbitwhen SYSNMI = 0 toavoidtriggeringan accidentalNMI

0 NMI on risingedge

1 NMI on fallingedge

SYSNMI Bit0 NMI select.ThisbitselectsthefunctionfortheRST/NMI pin

0 Resetfunction

1 NMI function

Table4.Memory Organization TYPE AFE4110A (Dev RAM) Type AFE4110B (Custom ROM) InterruptVectors RAM 32 B ROM 32 B 0xFFE0 (1)– 0xFFFF 0xFFE0 (1)– 0xFFFF DevelopmentRAM RAM 14KB — — 0xC800 – 0xFFFF ApplicationROM — — ROM 14KB 0xC800 – 0xFFFF TIStartUp Code (DSUC/PSUC) ROM 2KB ROM 2KB 0xC000 – 0xC7FF 0xC000 – 0xC7FF TIBootLoaderCode ROM 14KB — — 0x1E0 – 0x55FF ApplicationRAM RAM 256B RAM 256B 0x1D00 – 0x1DFF 0x1D00 – 0x1DFF ApplicationLRAM (lockable) RAM 128B RAM 128B 0x1C80 – 0x1CFF 0x1C80 – 0x1CFF CalibrationRAM (lockable) RAM 128B RAM 128B 0x1C00 – 0x1C7F 0x1C00 – 0x1C7F Peripherals Registers 4 kB Registers 4 kB 0x0000 – 0x0FFF 0x0000 – 0x0FFF (1) notthewholeinterruptvectorrangeofCSYS isused on AFE4110 devices Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com Start-UpCode (SUC) The AFE4110A Development Start-UpCode (DSUC) supportssystem debug viaa JTAG connectionto an externalemulator.Afterthe releaseof RST/NMI, the DSUC checks forthe presenceof a JTAG emulatorby readingthecontentsoftheJTAG MailboxRegister.Iftheemulationpassword ispresentintheJTAG Mailbox, theDSUC unlocksfullaccesstotheon chipemulationfeatures,thenentersLPM4 whilewaitingfortoenterthe debug session.Iftheemulationpassword isnotpresentintheJTAG Mailbox,theDSUC initiatesexecutionof theLoaderCode. The AFE4110B ProductionStart-UpCode (PSUC) alsosupportssystem debug viaa JTAG connectionto an externalemulator.The differenceisthatthePSUC checks forthecontentsoftheJTAG MailboxRegisterfora confidentialpassword.Iftheconfidentialpassword ispresentintheJTAG Mailbox,thePSUC unlocksfullaccess to the on chip emulationfeatures,then entersLPM4 whilewaitingforto enterthe debug session.Ifthe confidentialpassword is not presentin the JTAG Mailboxwhen RST/NMI is released,the PSUC initates executionofthecustom ROM code. Loader Code (Loader) The AFE4110A Loaderchecksforthepresenceofan externalSPI memory devicecontaininga validdata/code package.The Loader transfersa validateddata/codepackage intoDevelopment RAM. Duringvalidationand transfer,the on chip1.85V charge pump isenabledto supplypower to VDDIO and the externalSPI memory device.(PCB levelconnectionsare required.)Once the transferof the data/codepackage iscomplete,the chargepump isdisabled,theAFE4110 registersarereturnedtotheirdefaultcontents,and executionofthecode loadedinDevelopmentRAM isinitiated. RAM Memory The RAM memory issplitintothreeranges fordifferentpurposes:Applicationmemory, lockableapplication memory and calibrationmemory. Lockableapplicationmemory and calibrationmemory can be protectedagainstaccidentalerasureby settinga dedicatedlockbitinthespecialfunctionsregister(SystemMaintenanceRegister). Note:The lockablememory islockedby defaultafterreleaseofRST/NMI orexitfromLPM5. The usercode must clearthelockbitsintheSpecialFunctionRegisterafterreleaseofRST/NMI orexitfromLPM5 toenablewriting lockablememory. Peripherals Peripheralsare connectedtotheCPU throughdata,address,and controlbusses and can be handledusingall instructions.For completemodule descriptions,see theMSP430x5xx FamilyUser'sGuide (SLAU208) and the MSP430x09x FamilyUser'sGuide (SLAU321). DigitalI/O Thereare4 I/Oportsimplemented:P1 (7I/Olines),P2 (4I/Olines),P3 (6I/Olines)and P4 (4I/Olines)

AllindividualI/Obitsareindependentlyprogrammable.
Any combinationofinput,output,and interruptconditionsispossible.
Programmable pulluporpulldownon P1 and P3(0-5)ports.
Programmable pullupon P2,P4 and P3(6,7)ports.
ExternalVDD (VDDIO) supply(1.1-3.3Vrange)toP2,P4 and P3(6,7)ports.
Edge-selectableinterruptinputcapabilityforallports.
Read/writeaccesstoport-controlregistersissupportedby allinstructions.
Portscan be accessedbyte-wise(P1,P2,P3 and P4) orword-wiseinpairs(P1/P2combo).

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disable_p3_1 MCLK CPUOFF Divider /1/2/4/8/16/32 DIVMx ACLK OSCOFF Divider /1/2/4/8/16/32 DIVAx SMCLK SCG1 Divider /1/2/4/8/16/32 DIVSx SELAx HF – OSC SCG0 SELMx LF-OSC/ VLOCLK SELSx 1100 CLKIN/XIN/P3.0 ACLK enable logic MCLK enable logic SMCLK enable logic VLOCLK DIVCLK 32KHz XTALXOUT/P3.1 xt_byp P3IN.4 P3OUT.1 P3REN.1 P3OUT.0 P3REN.0 xt_byp EN EN# EN EN PORT_3.0 + PORT_3.1 AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Oscillatorand System Clock The clocksystem intheAFE4110 familyofdevicesissupportedby theCompact ClockSystem (CCS) module thatincludesan internal20kHz currentcontrolledlow frequencyoscillator(LF-OSC),an internaladjustable (1-5.4MHz)currentcontrolledhigh frequencyoscillator(HF-OSC), a 1KHz ultralow power oscillatorforthe activationblock,an externalclockinputfromCLKIN, and a 32kHz crystaloscillator.The CCS module isdesigned tomeet therequirementsofbothlow system costand low-powerconsumption.The CCS providesa fastturn-on oftheoscillatorsinlessthan1 ms. The CCS module providesthefollowingclocksignals:

Auxiliaryclock(ACLK) issoftwareselectableforindividualperipheralmodules.ACLK issourcedfrom the internalLF-OSC, theinternalHF-OSC, an externalsourceviaCLKIN, orthecrystaloscillator.
Main clock(MCLK) isthe system clockused by the CPU. MCLK can be sourcedby same sourcesmade availabletoACLK.
Sub-Main clock(SMCLK), the subsystem master clockissoftwareselectableby the peripheralmodules. SMCLK can be sourcedby same sourcesmade availabletoACLK.
VLOCLK thisisa lowfrequencyclocksourcedby LF-OSC thatisconstantlyavailable. Figure1. Block Diagram ofCompact Clock System (CCS) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):AFE4110

& Delay RSTNMI clr Reset Logic SWBOR BOR POR PUCReset- signals and violations Interrupt signals maskable/ unmaskable Interrupt Logic nmi CPUirq SVMOE from□SVM□logic SVMPD PortsOn SVMPO set SVSEN SWPOR AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Watchdog Timer (WDT_A) The primaryfunctionof the watchdog timer(WDT_A) module isto performa controlledsystem restartaftera softwareproblem occurs.Ifthe selectedtime intervalexpires,a system resetisgenerated.Ifthe watchdog functionisnot needed inan application,the module can be configuredas an intervaltimerand can generate interruptsatselectedtimeintervals.For a completedescriptionofWDT_A, see theWatchdog Timer (WDT_A) sectionoftheMSP430x09x FamilyUsersGuide (SLAU321). Table5.WDT_A SignalConnections DEVICE CLOCK SIGNAL MODULE CLOCK SIGNAL ACLK ACLK SMCLK SMCLK LF-OSC-CLK VLOCLK HF-OSC-CLK X-CLK Compact System Module (C-SYS) The Compact SYS module handlesmany of the system functionswithinthe device.These includepower on resetand power up clearhandling,NMI sourceselectionand management, resetinterruptvectorgenerators,as wellas, configurationmanagement. Italsoincludesa data exchange mechanism viaJTAG calleda JTAG mailboxthatcan be used inthe application.For a completedescriptionof C-SYS, see the Compact System chapteroftheMSP430x09x FamilyUsersGuide (SLAU321 ). Reset/NMI/SVMOUT System The Reset system oftheMSP430x09x familyfeaturesthefunctionReset input,Reset output,NMI input,SVM outputand SVS input. Figure2. Block Diagram ofReset/NMI/SVM and PortsOn logic

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www.ti.com SLLSE48 –JANUARY 2012 Table6.System Module InterruptVectorRegisters INTERRUPT VECTOR WORDINTERRUPT VECTOR OFFSET PRIORITYREGISTER ADDRESS No interruptpending 00h Brownout(BOR) 02h Highest SVMBOR (BOR) 04h RST/NMI (BOR) 06h DoBOR (BOR) 08h Securityviolation(BOR) 0Ah SYSRSTIV, System Reset DoPOR(POR) 019Eh 0Ch WDT timeout(PUC) 0Eh WDT key violation(PUC) 10h CCS key violation 12h PMM key violation 14h Peripheralareafetch(PUC) 16h Reserved 18h-3Eh Lowest No interruptpending 00h SVMIFG 02h Highest VMAIFG 04h SYSSNIV, System NMI 019Ch JMBINIFG 06h JMBOUTIFG 08h Reserved 0Ah-3Eh Lowest No interruptpending 00h NMIFG 02h Highest SYSUNIV, User NMI OFIFG 019Ah 04h BERR 06h Reserved 08h-3Eh Lowest No interruptpending 00h SYSBERRIV, Bus Error 0198h Reserved 02h-3Eh Lowest Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):AFE4110

On time – 3 bits 0.5ms to 4ms Off time – 13 bits (1mS to 64s) RAM 50K 450K Digital interface Isolation 1.1v – 1.55v VBAT ACTIVE Res_sel In_mod_sel 1Khz Always sample Q Q SET CLR D Q Q SET CLR D Inv_mode Switch_sample_mode_SW Sense_sample_mode D Q Q DFF 16 bit compare 16 bits up counter D Q Q DFF Sleep_start Sleep_mode_sel Timer_mode Sense_interrupt DISCHRG_VCC DISCHRG_Vbat 29 bits shelf up counter C PD_sel C Sleep_start Sleep_mode_sel D Q Q DFF C POR 600 1200 CCLK acknowledge 1KHz 1KHz 1KHz CPOR VCC Core VCC BAT POR

3 Ohm

In_mod_sel POR Clk Period Clk Width AFE4110 SLLSE48 –JANUARY 2012 www.ti.com ActivationBlock The AFE4110 ActivationBlockcontrolsentryand exitfrom "deep-sleep"(LPM5) mode. When thedeviceisin LPM5, power isdisconnectedfrom AFE4110 CPU and allperipherals(includingRAM, LCD and I/O)otherthan the Activationblock.When exitingLPM5, power is reappliedto the CPU core and peripherals.Exiting "deep-sleep"(LPM5) mode istermed "wake up".The Activationblockwakes up theCPU coreand peripherals based on how itwas configuredpriortoenteringLPM5. Wake up takesplacebased eitheron a transitionon the ActivationSense (ACTIVE) inputoraftera number ofActivationClockcycleshave been counted.The ACTIVE inputcan be configuredto respond to eitherLOW-to-HIGH or HIGH-to-LOW transitions.The number of Activationclockcyclestobe countedpriortoexitingLPM5 isconfigurable.

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www.ti.com SLLSE48 –JANUARY 2012 ActivationBlock Hardware Statusand ControlRegisters: The ActivationBlockhardware registerscontrolthe method of entryand exitfrom deep sleep(LPM5) mode. AdditionalfeaturesoftheActivationBlockregistersincludethefollowing:

VBAT Power On Reset (POR) Circuit– The VBAT POR isdesignedtoresettheActivationblockduringinitial systempower up thatistypicalofinstallationofa batteryintothefinalproduct.
4-16bitwords (8B)RAM – ThisRAM isimplementedinhardwareregisters.The contentsoftheseregistersis clearedatinitalsystem power up by VBAT POR. The factthattheseregistersare clearedatinitialsystem power up allowthem tobe used todeterminewhethertheCPU isbeingpowered up by batteryinsertionor exitfromLPM5.
16bitSleep Counter– The Activationblockcan be configuredto exitLPM5 afterthe number of Activation clockcyclesthatare selected.The countercan alsobe used as a generalpurpose down counterwithout enteringLPM5.
28bitShelfCounter– ThiscounterstartsincrementingafterthefirsttimethedeviceentersLPM5. Afterthe firstexitfromLPM5 thiscounterstopsand itsoutputsremainstaticuntilVBAT power isremoved.The intent isforthiscountertorecordnumber ofActivationclockperiodsbetween initialinsertionofa batteryintothe finalproductand thefirstusage ofthefinalproduct.Inotherwords,thiscounterindicatesthelengthoftime thatthefinalproductison theshelfpriortobeingused by a consumer.
ACTIVE Sample Clock– To minimizethepower requiredfordeterminingtransitionson theACTIVE pad,the stateoftheACTIVE pad issampled onlyatintervalswhicharesetby thedutycycleoftheACTIVE Sample Clock.The periodbetween samplesand thedurationofthesample intervalareconfigurable. The ActivationBlock'strobe'registersarenotmemory mapped and requirea multi-stepprocedureforReads and Writesof theircontentsfrom the CPU. The Activationregisterstroberefersto the hardware signalused to capturedata intothe bank of hardware registers.The strobenumber (strobeaddress)indicatesthe bank of 16-hardwareregisterstobe accessed.Only16-bit(word)accessesaresupported. ActivationStrobeRegisterRead Procedure: The stepstoRead a particularActivationstroberegisterfollows: 1. WritethestrobeaddressoftheActivationregistertobe Read totheACTIVATION_RD_ADDR register 2. Wait10-MCLK clockcyclesforthetransferofselecteddatatotheACTIVATION_DATAIN register 3. Read tocontentsoftheACTIVATION_DATAIN register ActivationStrobeRegisterWriteProcedure: The stepstoWriteActivationstroberegistersfollows: 1. Writeto data valueto be transferredto the Activationhardware registerto the ACTIVATION_DATAOUT register 2. Wait10-MCLK clockcyclesfordatatotransfertotheActivationblock 3. Write a '1'to the bit correspondingto the Activationhardware registerto be writteninto the ACTIVATION_STROBES register. Note: Ifmultiplebitsare writtenin the ACTIVATION_STROBES register,multipleActivationhardware registerswillbe written Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com The tablebelowdescribesthefunctionoftheActivationstroberegisters. Table7.ActivationStrobeRegisterFunctionTable datain# strobe0 strobe1 strobe2 strobe3 strobe4 strobe5 strobe6 strobe7 datain0 RAM RAM RAM RAM sleep ACTIVE Res_sel counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain1 RAM RAM RAM RAM sleep ACTIVE PD_sel ACTCLK_Freq_Sel <2:0>counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain2 RAM RAM RAM RAM sleep ACTIVE Always_sample counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain3 RAM RAM RAM RAM sleep ACTIVE Inv_mode Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain4 RAM RAM RAM RAM sleep ACTIVE Switch_sample_mode_SW Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain5 RAM RAM RAM RAM sleep ACTIVE Switch_sample_mode Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain6 RAM RAM RAM RAM sleep ACTIVE In_mod_sel Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain7 RAM RAM RAM RAM sleep ACTIVE Sleep_mode_sel Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain8 RAM RAM RAM RAM sleep ACTIVE Reserved Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain9 RAM RAM RAM RAM sleep ACTIVE Sleep_start Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain10 RAM RAM RAM RAM sleep ACTIVE Timer_mode Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain11 RAM RAM RAM RAM sleep ACTIVE Reserved Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain12 RAM RAM RAM RAM sleep ACTIVE Reserved Reserved counterreg0 reg1 reg2 reg3 Sample ClkPeriod datain13 RAM RAM RAM RAM sleep ACTIVE DISCHRG_Vbat Reserved counterreg0 reg1 reg2 reg3 Sample ClkWidth datain14 RAM RAM RAM RAM sleep ACTIVE DISCHRG_VCC Reserved counterreg0 reg1 reg2 reg3 Sample ClkWidth datain15 RAM RAM RAM RAM sleep ACTIVE Reserved Reserved counterreg0 reg1 reg2 reg3 Sample ClkWidth Strobe0-Strobe3:ActivationBlockRAM Registers RAM Reg0 -RAM Reg3 -Bits15 -0 -Constantlypowered registersforused as RAM (Clearedby assertionof VBAT POR) Strobe4:SleepCounterRegister Sleep_counter-Bits15 -0 -Sleepcounteroutputvalue Strobe5:ACTIVE Sample ClockConfigurationRegister ACTIVE_Sample_Clock_Period - Bits12 - 0 - Number of ACTCLK cyclesper periodof the ACTIVE sample clock 0x0000 setsthesamplingperiodto~8192ms 0x0001 setsthesamplingperiodto~1ms... 0x0009 setsthesamplingperiodto~9ms ... 0x1FFF setsthesamplingfrequencyto~8192ms ACTIVE_Sample_Clock_Width - Bits15 - 13 - Number of ACTCLK half-cyclesper sample intervalof the ACTIVE sample clock Strobe6:LPM5 ConfigurationRegister Res_sel -Bit0 -PU/PD ResistorSelect 1 -500KΩ resisterselected 0 -50KΩ resisterselected

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www.ti.com SLLSE48 –JANUARY 2012 PD_sel -Bit1 -PullDown Select 1 -PMOS sensing-internalPU isconnected 0 -NMOS sensing– internalPD isconnected Always_sample -Bit1 ACTIVE SamplingSelect 1 -ContinuousACTIVE inputsensing 0 -ACTIVE inputsensingatsampled intervals Inv_mode -Bit3 -InvertedMode 1 -Low tohightransitionsensing 0 -Hightolowtransitionsensing Switch_sample_mode_SW -Bit4 -SwitchSample Mode Switch 1 -Edge sensingforexternalswitchclosureselected 0 -Levelsensingforexternalswitchclosureselected Switch_sample_mode -Bit5 -SwitchSample Mode 1 -Edge sensingforthesense_interrupt 0 -Levelsensingforthesense_interrupt In_mod_sel -Bit6 -InputMode Select 1 -Low currenthysteresissense inverterselected 0 -Standardinputselected Sleep_mode_sel -Bit7 -Sense Mode Select 1 -highselectspower down withcounter; 0 -lowselectspower down withoutcounter Sleep_start-Bit9 -SleepStart 1 -Startpower down 0 -Normal operatingmode (Thisbitmust be clearedby TIstartup code.) Timer_mode -Bit10 -TimerMode 1-StartsleepcounterwithoutenteringLPM5 0 -Sleepcounterisstartingwhen enteringLPM5 ifsleepcountermode isselected DISCHRG_Vbat -Bit13 -DischanrgeVBAT Power 1 -DischargeVbatvoltagethrough600 Ω resister 0 -No VBAT discharingselected DISCHRG_VCC -Bit14 -DischargeVCC Core 1-DischargeVcc voltagethrough1200 Ω resister 0 -No dischargeofVCC Core voltageselect Strobe7:ActivationClockFrequencySelectRegister ACTCLK_Freq_Sel -Bits2 -0 -TrimstheACT oscillatortosetthefrequency Table8.ACTIVE Sample Clock Width SETTING ACTIVE Sample Clock Interval 000 0.5ACTCLK Period 001 1 ACTCLK Period 010 1.5ClockPeriod 011 2 ClockPeriod 100 2.5ClockPeriod 101 3 ClockPeriod 110 3.5ClockPeriod 111 4 ClockPeriod Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com Table9.ActivationClock Frequency Selections SETTING CAP SETTING FREQUENCY 000 60 fF 1 kHz 001 120 fF 0.75kHz 010 180 fF 0.35kHz 011 240 fF 250 Hz 100 150 fF 400 kHz 101 210 fF 280 Hz 110 270 fF 220 Hz ActivationRegisters SHELF_CNT_LO: Shelfcounterlow 15 14 13 12 11 10 9 8 s_cnt_low(cont.) r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 s_cnt_low r0 r0 r0 r0 r0 r0 r0 r0 s_cnt_low Bits0-15 Lower 16 bitsofShelfcounter Thisisa readonlyRegister SHELF_CNT_HI: Shelfcounterhigh 15 14 13 12 11 10 9 8 r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 s_cnt_high r0 r0 r0 r0 r0 r0 r0 r0 s_cnt_high Bits0-12 Upper 13 bitsofShelfcounter Thisisa readonlyRegister ACTIVATION_DATAIN: Activationdatain 15 14 13 12 11 10 9 8 act_d_in(cont.) 7 6 5 4 3 2 1 0 act_d_in act_d_in Bits0-15 ActivationData In-Valueofthe Strobe7-0registerwhichis selectedby the ACTIVATION_RD_ADDR register

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www.ti.com SLLSE48 –JANUARY 2012 Thisisa readonlyRegister ACTIVATION_DATAOUT: Activationdataout 15 14 13 12 11 10 9 8 act_d_out(cont.) rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 act_d_out rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 act_d_out Bits0-15 ActivationData Out -The datavaluetobe writtenintotheStrob1-0registerwhichis selectedby theACTIVATION_STROBES register ACTIVATION_STROBES: Activationstrobes 15 14 13 12 11 10 9 8 Password rw-1 rw-0 rw-0 rw-1 rw-0 rw-1 rw-1 rw-0 7 6 5 4 3 2 1 0 strb7 strb6 strb5 strb4 strb3 strb2 strb1 strb0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 strbx Bits0-15 ActivationStrobe-These bitsare'one-hot'coded toselecttheStrob7-0registertobe writtenwiththecontentsoftheACTIVATION_DATAOUT register strb0 Bit0 Activationstrobe0 strb1 Bit1 Activationstrobe1 strb2 Bit2 Activationstrobe2 strb3 Bit3 Activationstrobe3 strb4 Bit4 Activationstrobe4 strb5 Bit5 Activationstrobe5 strb6 Bit6 Activationstrobe6 strb7 Bit7 Activationstrobe7 Password Bits8-15 Write0xA5 toinitiateStrobexregisterWrite-Alwaysreadsback 0x96 Strb0-7areselfclearingbits ACTIVATION_RD_ADDR: Activationread address 15 14 13 12 11 10 9 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 r-0 r-0 r-0 r-0 rw-0 rw-0 rw-0 rw-0 read_add Bits0-2 RegisterRead Address-Decimalcoded indexofStrobe7-0registertobe readback in ACTIVATION_DATAIN register ACTIVATION_STATUS: ActivationStatus 15 14 13 12 11 10 9 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com Thisisa readonlyregister. act_sense Bit0 Logichighsignalindicatesense buttonchanged state(pushed) act_sleep Bit1 SleepComparatorOUT. Can be configuredlikeMSP Timer_0out(INT_rise,INT fall,LevelLatchHigh,Levellatch Low) act_test Bit2 Counteroutfortesting ACTIVATION_SENSE: ActivationSense 15 14 13 12 11 10 9 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 Thisisa selfclearingregister activation_sense_cirBit0 Acknowledgeforclearingthesense_interruptsignal(shouldbe a highpulsethatcan comes fromSW or HW) Timer0_A3 Timer0_A3 is a 16-bittimer/counterwiththreecapture/compareregisters.Timer0_A3 can supportmultiple capture/compares,PWM outputs,and intervaltiming.Timer0_A3 also has extensiveinterruptcapabilities. Interruptsmay be generatedfrom the counteron overflowconditionsand from each of the capture/compare registers.AFE4110 Timer-0has differentClocksSources and CCx inputmultiplexing,compared toMSP430x5 documentation.Timer-0Clocksourcesand theCCx inputsignalsdescribedinthisdocument.

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CxOUT (Apool) P2.1 CCI0A CCI0B ACTIV A TION _CLK ACLK SMCLK LCD_CP_CLK TIMER_0 CCR0 OUT0 Signal Set T A 0CCR0 CCIFG Comparator 0 T A0CCR0 EQU0 Set T A 0CTL T AIFG AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Timer0_A3 SignalConnections and Block Diagrams Figure3. Timer0_CCR0 Block Diagram Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):AFE4110

sel_timer0_cci1 1 1 1 1 CxOUT (Apool) P1.1 P1.0 ACTIV A TION _CLK CCI1A CCI1B ACTIV A TION _CLK ACLK SMCLK LCD_CP_CLK TIMER_0 CCR1 OUT1 Signal Set T A 0CCR1 CCIFG Comparator 1 T A 0CCR1 EQU1 Set T A 0CTL T AIFG P1.2 P1.3 P1.4 P1.5 AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Figure4. Timer0_CCR1 Block Diagram

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sel_timer0_cci2 1 1 1 1 CxOUT (Apool) P1_DIR.1 P1_DIR.0 SMCLK CCI2A CCI2B ACTIV A TION _CLK ACLK SMCLK LCD_CP_CLK TIMER_0 CCR2 OUT2 Signal Set T A 0CCR2 CCIFG Comparator 2 T A 0CCR2 EQU2 Set T A 0CTL T AIFG P1_DIR.2 P1_DIR.3 P1_DIR.4 P1_DIR.5 AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Figure5. Timer0_CCR2 Block Diagram Timer1_A3 Timer1_A3 is a 16-bittimer/counterwiththreecapture/compareregisters.Timer1_A3 can supportmultiple capture/compares,PWM outputs,and intervaltiming.Timer1_A3 also has extensiveinterruptcapabilities. Interruptsmay be generatedfrom the counteron overflowconditionsand from each of the capture/compare registers.AFE4110 Timer-1has differentClocksSources and CCx inputmultiplexing,compared toMSP430x5 documentation.Timer-1Clocksourcesand theCCx inputsignalsdescribedinthisdocument. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):AFE4110

CxOUT (Apool) P2.0 CCI0A CCI0B LFCLK ACLK SMCLK P2.3 TIMER_1 CCR0 OUT0 Signal Set T A 1CCR0 CCIFG Comparator 0 T A 1CCR0 EQU0 Set T A 1CTL T AIFG AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Timer1_A3 SignalConnections and Block Diagrams Figure6. Timer1_CCR0 Block Diagram

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sel_timer1_cci1 1 1 1 1 CxOUT (Apool) P3.0 P3.1 P3.6 P1.6 ACTIV A TION _CLK ACLK SMCLK CCI1A CCI1B LFCLK ACLK SMCLK P2.3 TIMER_1 CCR1 OUT1 Signal Set T A 1CCR1 CCIFG Comparator 1 T A 1CCR1 EQU1 Set T A 1CTL T AIFG AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Figure7. Timer1_CCR1 Block Diagram Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):AFE4110

sel_timer1_cci2 1 1 1 1 CxOUT (Apool) P3.7 P3.4 P3.5 P1_DIR.6 ACTIV A TION _CLK ACLK SMCLK CCI2A CCI2B LFCLK ACLK SMCLK P2.3 TIMER_1 CCR2 OUT2 Signal Set T A 1CCR2 CCIFG Comparator 2 T A 1CCR2 EQU2 Set T A 1CTL T AIFG AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Figure8. Timer1_CCR2 Block Diagram LCD_E The LCD_E isequivalenttoTILCD-B (MSP430x4 family)driverthatgeneratesthesegment and common signals requiredto drivean LCD display.The LCD_E controllerhas dedicateddata memory to hold segment drive information.Common and segment signalsare generatedas definedby themode. Static,2-MUX, 3-MUX, and 4-MUX LCDs aresupportedby thisperipheral.The module can providea LCD voltageindependentofthesupply voltagewithitsintegratedchargepump. FurthermoreitispossibletocontroltheleveloftheLCD voltageand,thus,contrastby software. The LCD_E operatingvoltageisminimum 2V,thereforetheusermust verifya 2V voltageisavailableon pin 37 eitherby activatingtheCP_1P8 orusingexternalpower supply. The LCD_CP isusingtheCP_OSC as thereferenceoscillatorforboostingthe2V toLCD operatingvoltage.The CP_OSC isworkingfrom batteryvoltage(minimum 1.1V)and isshared withCP_1P8 which alsousingitfor generatingthe2V fromthebatteryvoltageinternally.

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CxIFG□logic CxOUT Reference 256mV REFON CMPON MDB□and□buffer□register CONVONAPVDIV□Register Vcc 0000 ADC-DAC-SAR-REG Up-Dn□Counter Run/ Stop set clr TA0EN TA0.0 CBSTP OSWP Aout OSEL CLKSELA0 VREF SMCLK SLOPE ODEN D/A-8 DBON TBSTP TA0.1 TA1EN TA1.0 De- Glitching DFSETx SBSTP VREFEN SLOPE EOCIFG□logic sEOC 0001 0010 0011 0100 0101 0110 0111 1000 PSELx 0000 0001 0010 0011 0100 0101 0110 0111 Pre-Scaler by 1/2/4/8/16/32 CLKDIVx SAREN xCLK xCLK from AZ-logic AZ ENCT Start□Stop□Logic Clock Logic MCLK VLOCLK 1001 /c74 SVMIFG□logic R R Vcc AFE4110 www.ti.com SLLSE48 –JANUARY 2012 A-Pool The analogfunctionspool(A-Pool)providesa seriesof functionthatcan be configuredto a Digitalto Analog converter(DAC), multichannel Analog to Digitalconverter(ADC), Supply voltagesupervisorSVS and Comparator,inputvoltagedividersand an internalreferencesource allowwide range of combined analog functions.For a completedescriptionofA-Pool,see theAnalogPoolchapteroftheMSP430x09x FamilyUsers Guide (SLAU321 ) Figure9. Block Diagram ofA-Pool Table10.A-Pool Analog inputsConnection Table A-POOL ANALOG INPUT PAD PSEL NSEL A3PSEL A0_port_sel A3a P1.2 0011 0011 0 X A3b P1.3 0011 0011 1 X A2 P1.0 0010 0010 X X A1 P1.1 0001 0001 X X A0a P1.4 0000 0000 X 0 A0b P3.3 0000 0000 X 1 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com VersatileI/OPortP1,P2,P3,P4 The versatileI/O portsP1, P2, P3 and P4 featuredevicedependent resetvalues.The resetvaluesforthe AFE4110 devicesareshown inbelow. Table11.VersatilePortReset Values PORT I/OPOWERPxOUT PxDIR PxREN PxSEL0 PxSEL1 RESET PortsON COMMENTNUMBER DOMAIN P1.0 0 0 0 0 0 PUC yes P1.0,input VDD P1.1 0 0 0 0 0 PUC yes P1.1,input VDD P1.2 0 0 0 0 0 PUC yes P1.2,input VDD P1.3 0 0 0 0 0 PUC yes P1.3,input VDD P1.4 0 0 0 0 0 PUC yes P1.4,input VDD P1.5 0 0 0 0 0 PUC yes P1.5,input VDD P1.6 0 0 0 0 0 PUC yes P1.6,input VDD P2.0 1 0 1 1 1 BOR no JTAG TCK VDDIO P2.1 1 0 1 1 1 BOR no JTAG TMS VDDIO P2.2 1 0 1 1 1 BOR no JTAG TDI VDDIO P2.3 0 1 0 1 1 BOR no JTAG TDO VDDIO P3.0 0 0 0 0 0 PUC yes P3.0,input VDD P3.1 0 0 0 0 0 PUC yes P3.1,input VDD P3.2 0 0 0 0 0 PUC yes P3.2,input VDD P3.3 0 0 0 0 0 PUC yes P3.3,input VDD P3.4 0 0 0 0 0 PUC yes P3.4,input VDD P3.5 0 0 0 0 0 PUC yes P3.5,input VDD P3.6 0 0 0 0 0 PUC yes P3.6,input VDDIO P3.7 0 0 0 0 0 PUC yes P3.7,input VDDIO P4.0 0 0 0 0 0 PUC Yes P4.0,input VDDIO P4.1 0 0 0 0 0 PUC Yes P4.1,input VDDIO P4.2 0 0 0 0 0 PUC Yes P4.2,input VDDIO P4.3 0 1 0 0 0 PUC yes P4.3,input VDDIO

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www.ti.com SLLSE48 –JANUARY 2012 Table12.Peripherals MODULE NAME REGISTER DESCRIPTION REGISTER BASE ADDRESS OFFSET AREGS Analoge-fuse ANALOG_FUSETRIM 04A0h 16h Analogtimercontrol ANALOG_TIMERCTL 14h Analogportcontrol2 ANALOG_PORTCTL2 12h Analogportcontrol1 ANALOG_PORTCTL1 10h Analogana control ANALOG_ANACTL 0Eh Analogbiascurrentcontrol ANALOG_IBIASCTL 0Ch AnalogLDO control ANALOG_LDOCTL 0Ah AnalogLDO configuration ANALOG_LDOCFG 08h AnalogLCDP control ANALOG_LCDPCTL 06h AnalogLCD chargepump control ANALOG_LCDCPCFG 04h Analogchargepump 1.8Vcontrol ANALOG_CP1P8CTL 02h Analogchargepump 1.8Vconfiguration ANALOG_CP1P8CFG 00h Activation ActivationSense ACTIVATION_SENSE 0480h 0Eh ActivationStatus ACTIVATION_STATUS 0Ch Activationreadaddress ACTIVATION_RD_ADDR 0Ah Activationstrobes ACTIVATION_STROBES 08h Activationdataout ACTIVATION_DATAOUT 06h Activationdatain ACTIVATION_DATAIN 04h Shelfcounterhigh SHELF_CNT_HI 02h Shelfcounterlow SHELF_CNT_LO 00h LCD Reserved 0400h 46h-5Fh LCD Blinking1–6(1) LCDB1-6 40h-45h Reserved 26h-3Fh LCD memory 1–6(1) LCDM1-6 20h-25h LCD_B interruptvector LCDBIV 1Eh Reserved 14h-1Ch LCD_B chargepump control LCDBCPCTL 12h Reserved 0Ah-11h LCD_B voltagecontrolregister LCDBVCTL 08h LCD_B memory controlregister LCDBMEMCTL 06h LCD_B blinkingcontrolregister LCDBBLKCTL 04h LCD B controlregister1 LCDBCTL1 02h LCD B controlregister0 LCDBCTL0 00h Timer1_A3 Timer1_A interruptvector TA1IV 0380h 2Eh Capture/compareregister2 TA1CCR2 16h Capture/compareregister1 TA1CCR1 14h Capture/compareregister0 TA1CCR0 12h Timer1_A register TA1R 10h Capture/comparecontrol2 TA1CCTL2 06h Capture/comparecontrol1 TA1CCTL1 04h Capture/comparecontrol0 TA1CCTL0 02h Timer1_A control TA1CTL 00h (1) Six8 bitregisters,buttheLCD blinkingand memory registerscan alsobe accessedas word Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com Table12.Peripherals(continued) MODULE NAME REGISTER DESCRIPTION REGISTER BASE ADDRESS OFFSET Timer0_A3 Timer0_A interruptvector TA0IV 0340h 2Eh Capture/compareregister2 TA0CCR2 16h Capture/compareregister1 TA0CCR1 14h Capture/compareregister0 TA0CCR0 12h Timer1_A register TA0R 10h Capture/comparecontrol2 TA0CCTL2 06h Capture/comparecontrol1 TA0CCTL1 04h Capture/comparecontrol0 TA0CCTL0 02h Timer1_A control TA0CTL 00h PortP4 PortP4 interruptFlag P4IFG 0220h 1Dh PortP4 interruptenable P4IE 1Bh PortP4 interruptedge select P4IES 19h PortP4 interruptvectorword P4IV 1Eh PortP4 selection1 P4SEL1 0Dh PortP4 selection0 P4SEL0 0Bh PortP4 pullup/pulldownenable P4REN 07h PortP4 direction P4DIR 05h PortP4 outout P4OUT 03h PortP4 input P4IN 01h PortP3 PortP3 interruptFlag P3IFG 0220h 1Ch PortP3 interruptenable P3IE 1Ah PortP3 interruptedge select P3IES 18h PortP3 interruptvectorword P3IV 0Eh PortP3 selection1 P3SEL1 0Ch PortP3 selection0 P3SEL0 0Ah PortP3 pullup/pulldownenable P3REN 06h PortP3 direction P3DIR 04h PortP3 outout P3OUT 02h PortP3 input P3IN 00h PortP2 PortP2 interruptFlag P2IFG 0200h 1Dh PortP2 interruptenable P2IE 1Bh PortP2 interruptedge select P2IES 19h PortP2 interruptvectorword P2IV 0Eh PortP2 selection1 P2SEL1 0Dh PortP2 selection0 P2SEL0 0Bh PortP2 pullup/pulldownenable P2REN 07h PortP2 direction P2DIR 05h PortP2 outout P2OUT 03h PortP2 input P2IN 01h PortP1 PortP1 interruptFlag P1IFG 0200h 1Ch PortP1 interruptenable P1IE 1Ah PortP1 interruptedge select P1IES 18h PortP1 interruptvectorword P1IV 0Eh PortP1 selection1 P1SEL1 0Ch PortP1 selection0 P1SEL0 0Ah PortP1 pullup/pulldownenable P1REN 06h PortP1 direction P1DIR 04h

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www.ti.com SLLSE48 –JANUARY 2012 Table12.Peripherals(continued) MODULE NAME REGISTER DESCRIPTION REGISTER BASE ADDRESS OFFSET PortP1 outout P1OUT 02h PortP1 input P1IN 00h A-POOL Analogpoolinterruptvectorregister APIV 01A0h 1Eh Analogpoolinterruptenableregisterregister APIE 1Ch Analogpoolinterruptflagregister APIFG 1Ah Analogpoolfractionalvaluebuffer APFRACTB 16h Analogpoolfractionalvalueregister APFRACT 14h Analogpoolintegervaluebuffer APINTB 12h Analogpoolintegervalueregister APINT 10h Analogpoolvoltagedividerregister APVDIV 06h Analogpooloperationmode register APOMR 04h Analogpoolcontrolregister APCTL 02h Analogpoolconfigurationregister APCNF 00h CSYS Resetvectorgenerator SYSRSTIV 0180h 1Eh System NMI vectorgenerator SYSSNIV 1Ch User NMI vectorgenerator SYSUNIV 1Ah Bus errorvectorgenerator SYSBERRIV 18h System Configurationregister SYSCNF 10h JTAG mailboxoutputregister#1 SYSJMBO1 0Eh JTAG mailboxoutputregister#0 SYSJMBO0 0Ch JTAG mailboxinputregister#1 SYSJMBI1 0Ah JTAG mailboxinputregister#0 SYSJMBI0 08h JTAG mailboxcontrolregister SYSJMBC 06h System controlregister SYSCTL 00h CCS CCS control8 register CCSCTL8 0160h 10h CCS control7 register CCSCTL7 0Eh CCS control6 register CCSCTL6 0Ch CCS control5 register CCSCTL5 0Ah CCS control4 register CCSCTL4 08h CCS control2 register CCSCTL2 04h CCS control1 register CCSCTL1 02h CCS control0 register CCSCTL0 00h WDT_A WDT_A Watchdog timercontrol WDTCTL 0150h 0Ch PMM PMM PMM control0 PMMCTL0 0120h 00h ET-WRAPPER ET-Wrapper ET Key and select ETKEYSEL 0110h 00h Special SpecialFunctionsSFR Resetpincontrolregister SFRRPCR 0100h 04h Functions SFR interruptflagregister SFRIFG1 02h SFR interruptenableregister SFRIE1 00h Legend rw: Bitcan be readand written. rw-0,1:Bitcan be readand written.Itisresetorsetby PUC. (1) rw-(0,1):Bitcan be readand written.Itisresetorsetby POR (2) rw-[0,1]:Bitcan be readand written.Itisresetorsetby BOR. (3) – bitisnotpresentindevice (1) PUC isfor"normal" registerswhichshouldbe resetatalltime (2) POR isused forregisters,whichshouldnotbe resetby a WDT event(likestatusinformation) (3) BOR isused forregisters,whichareconfiguredduringbootcode executionand shouldnotbe resetduringnormalresetevents Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com Analog ControlRegisters ANALOG_CP1P8CFG: Analog charge pump 1.8Vconfiguration 15 14 13 12 11 10 9 8 – – – 1p8_valid clk_sel force_clk mode_sel cp_1p8_pd r-0 r-0 r-0 r-0 rw-0 rw-0 rw-0 rw-1 7 6 5 4 3 2 1 0 cp_1p8_hyst_set cp_1p8_out_level cp_1p8_clk_div rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 cp_1p8_clk_div Bits2-0 Selecttheclockdivider(seetablebelow) cp_1p8_out_level Bits5-3 SettheCP validthresholdvoltage(seetablebelow) cp_1p8_hyst_set Bits7-6 Setthecomparatorhysteresis(insidetheCP loop)– 000 means closehysteresis,and 111 means widehysteresis.When usingfastclock(highcurrent)theusermust use close hysteresis000. cp_1p8_pd Bit8 Powers Down thechargepump circuitries cp_1p8_clk_mode_sel Bit9 Testmode oftheCP loop,breakthelooptocontrolby thesignalfram_force_clk cp_1p8_force_clk Bit10 Forcea continuousclocktotheCharge Pump (intestmode) cp_1p8_clk_sel Bit11 Selectwhichclocktouse (internalorexternal) cp_1p8_valid Bit12 Valid1.8vindicationoutput ANALOG_CP1P8CTL: Analog charge pump 1.8Vcontrol 15 14 13 12 11 10 9 8 Reserved rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 cp_1p8_valid_level clk_refresh_freq ext_cap_en clamp clamp_en quiet_mode rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 rw-0 cp_1p8_quiet_mode Bit0 Inhibitschargepump clocking cp_1p8_force_out_clamp_en Bit1 Controlstheoutputclamp switchtoAVDD_BAT (0-clamp accordingtocontrol;1- clamp accordingtoPD control) cp_1p8_force_out_clamp Bit2 Forcetheoutputclamp toAVDD_BAT cp_1p8_ext_cap_en Bit3 Settohighwhen highcurrentisrequired cp_1p8_clk_refresh_freq Bits4-5 Setthefrequencyforrefreshingtherdivcap (seetablebelow) cp_1p8_valid_level Bits6-7 SettheCP validthresholdvoltage(seetablebelow) Reserved Bits8 -15 cp_1p8_out_level cp_1p8_clk_divtable: Setting Freq Setting Freq 000 2.075V 000 FS (4MHz) 001 2.05V 001 001 FS/2 010 2.025V 010 FS/4 011 2 V 011 FS/8 100 1.975V 100 FS/16 101 1.95V 101 FS/32 110 1.925V 110 FS/64 111 1.9V 111 FS/128

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www.ti.com SLLSE48 –JANUARY 2012 cp_1p8_clk_refresh_freqtable: cp_1p8_clk_valid_leveltable: Setting Freq Setting Freq 00 156.25Hz 00 1.75V 01 312.5Hz 01 1.8V 10 312.5Hz 10 1.85V 11 625 Hz 11 1.9V The clockoutputisa single50 µs pulse ANALOG_LCDCPCFG: Analog LCD charge pump controlR 15 14 13 12 11 10 9 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 r-0 r-0 r-0 rw-0 r-0 r-0 r-0 rw-0 lcd_cp_clk_sel Bit0 NC (Notconnected) lcd_cp_force_clk Bit4 NC ANALOG_LCDPCTL: Analog LCDP control 15 14 13 12 11 10 9 8 seg11_en seg10_en seg9_en seg8_en seg7_en seg6_en seg5_en seg4_en rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 7 6 5 4 3 2 1 0 seg3_en seg2_en seg1_en seg0_en com3_en com2_en com1_en com0_en rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 com0_en Bit0 EnableLCD pincommon 0."1"– enable,"0"– disable com1_en Bit1 EnableLCD pincommon 1."1"– enable,"0"– disable com2_en Bit2 EnableLCD pincommon 2."1"– enable,"0"– disable com3_en Bit3 EnableLCD pincommon 3."1"– enable,"0"– disable seg0_en Bit4 EnableLCD pinsegment 0."1"– enable,"0"– disable seg1_en Bit5 EnableLCD pinsegment 1."1"– enable,"0"– disable seg2_en Bit6 EnableLCD pinsegment 2."1"– enable,"0"– disable seg3_en Bit7 EnableLCD pinsegment 3."1"– enable,"0"– disable seg4_en Bit8 EnableLCD pinsegment 4."1"– enable,"0"– disable seg5_en Bit9 EnableLCD pinsegment 5."1"– enable,"0"– disable seg6_en Bit10 EnableLCD pinsegment 6."1"– enable,"0"– disable seg7_en Bit11 EnableLCD pinsegment 7."1"– enable,"0"– disable seg8_en Bit12 EnableLCD pinsegment 8."1"– enable,"0"– disable seg9_en Bit13 EnableLCD pinsegment 9."1"– enable,"0"– disable seg10_en Bit14 EnableLCD pinsegment 10."1"– enable,"0"– disable seg11_en Bit15 EnableLCD pinsegment 11."1"– enable,"0"– disable To enablethe LCD both the relevantANALOG_LCDPCTL bitshouldbe setto 1 and the LCDON bitinLCD registerLCDBCTL0 shouldbe setto1. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com ANALOG_LDOCFG: Analog LDO configuration 15 14 13 12 11 10 9 8 r-0 r-0 rw-0 rw-0 r-0 r-0 rw-0 rw-0 7 6 5 4 3 2 1 0 high_cap_sw low_cap_sw ldo_bypass ldo_pd – ldo_trim_bits rw-0 rw-0 rw-0 rw-1 r-0 rw-0 rw-0 rw-0 ldo_trim_bits Bits0-2 LDO voltagetrimming(seetablebelow) ldo_pd Bit4 "1"LDO Shutdown. Vout=open ldo_bypass Bits5 "1"Bypass theLDO, shortsLDO VouttoVDD low_cap_sw Bit6 "1"Connectthelowcalibrationcapacitor(20pF) high_cap_sw Bit7 "1"Connectthehighcalibrationcapacitor(40pF) cap_sw_general Bit8-9 NC ldo_out_mux Bit12-13 "00"settheLDO outputswitchto"off"."11"setLDO outputswitchto"on" ldo_trim_bitstable: Setting Vout[V] 000 1.045 001 10.72 010 1.1 011 1.125 100 0.96 101 0.98 110 1 111 1.02 ANALOG_LDOCTL Analog LDO control 15 14 13 12 11 10 9 8 ldo_ctl(cont.) rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 ldo_ctl a0_port_sel LDO_IO_sel rw-0 rw-0 rw-0 rw-1 r-0 rw-0 rw-0 rw-0 LDO_IO_sel Bit0-3 Used tomux theLDO toIOs inthefollowingorder: <0> – port1.0; <1> – port1.1; <2> – port1.4; <3> – port3.3; a0_port_sel Bit4 SelectwhichIO goes toA0 inputoftheA-Pool– ,0.selectsport1.4 ldo_ctl Bits5-15 NC

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www.ti.com SLLSE48 –JANUARY 2012 ANALOG_IBIASCTL: Analog biascurrentcontrol 15 14 13 12 11 10 9 8 spare lf_force_mode hfos_current osc_6m current ctl_ref_current rw-0 rw-0 rw-0 rw-1 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 ibias_pd rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Ibias_pd Bits0-7 Poweringdown thebiascurrentsNot used ctl_ref_current Bits8-9 Selectmain referencecurrent: 00 – 10nA (Deafult) 01 – 6nA 10 – 12nA 11 – 8nA osc_6m current Bits10-11 ControlstheHF_OSC currentsetting: 00 – 1 µA 01 – 3 µA 10 – 2 µA 11 – 4 µA hfos_current Bit12 1 – SettingtheHF_OSC tolowfrequency/lowcurrentmode (1MHz/10µA) lf_mode_force Bit13 0 – lf_modeisforcedon hf_osc; 1 – lf_modeisworkingonlyofI_trimis00 spare Bits14-15 Not Used HF_OSC LF Mode -TypicalfrequencyafterHF-OSC calibratedto4.4MHz hfos_current<12> lf_mode_force<13> osc_6m current<11,10> HF-OSC Frq [MHz] 0 x 00 1.87 01 4.44 10 3.27 11 5.4 1 0 00 1 1 1 00 1 01 3.9 10 2.6 11 5 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com ANALOG_ANACTL: Analog ana control 15 14 13 12 11 10 9 8 ana_ctl(notused) lpm5_en_lcd_ana_shell Cp_osc_trim rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 rw-0 rw-0 7 6 5 4 3 2 1 0 Reserved rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Reserved Bits0-7 Ana_ctl_cp_osc_trim Bits8-9 Course trimmingofthe2 charge pumps oscillator(current trimming) lpm5_lcd_ana_shell Bit10 "1"powers down (~40nA)the max_detectblockinsidetheLCD Block ana_ctl Bits11-15 Not used ANALOG_PORTCTL1: Analog Analog portcontrol1 15 14 13 12 11 10 9 8 rw-0 r-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 r-0 r-0 rw-0 rw-0 r-0 r-0 rw-0 rw-0 sel_port3_6,sel_port3_7:PORT3.6 and PORT3.7 Inputmultiplexercontrol sel_port3_6 Bits1,0 0,0 0,1 1,0 1,1 P3SEL1/0 = 01 TA0.0 TA0.1 TA0.2 TA1.1 P3SEL1/0 = 10 NEG(TA0.0) NEG(TA0.1) NEG(TA0.2) NEG(TA1.1) P3SEL1/0 = 11 BROWNOUT ACTIVATION_SENSE LFCLK CP_1P8_COMP sel_port3_7 Bits5,4 0,0 0,1 1,0 1,1 P3SEL1/0 = 01 TA0.0 TA0.1 TA0.2 LCD_COMP P3SEL1/0 = 10 NEG(TA0.0) NEG(TA0.1) NEG(TA0.2) NEG(LCD_COMP) P3SEL1/0 = 11 LCD_CP_CLK LCD_FCLK HFCLK ACTIVATION_OSC_1KHZ sel_irq_on_p3_2 Bit8 force'0'when test_atpg_en_i= '1' sel_irq_on_p3_3 Bit9 sel_irq_on_p3_4 Bit10 sel_irq_on_p3_5 Bit11 sel_irq_on_p3_6 Bit12 sel_irq_on_p3_7 Bit13 bypass_dir_sync Bit15 "1"EnablePortx.ydirectDIR signalconnectiontoTiIMERx CCx (No Dithering)."0"Enable Portx.yDIR signal(synctoLFCLK) connectiontoTiIMERx CCx .Ditheringenabledwhen HF-CLK orEXCLK selectedas TimerClocksource.(1) (1) force'1' when test_atpg_en_i= '1'

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www.ti.com SLLSE48 –JANUARY 2012 ANALOG_PORTCTL2: Analog Analog portcontrol2 15 14 13 12 11 10 9 8 r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 dp1_6 dp1_5 dp3_5 dp3_4 dp3_3 dp3_2 dp3_1 dp3_0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 disable_p3_0 Bit0 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) disable_p3_1 Bit1 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) disable_p3_2 Bit2 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) disable_p3_3 Bit3 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) disable_p3_4 Bit4 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) disable_p3_5 Bit5 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) disable_p1_5 Bit6 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) disable_p1_6 Bit7 "1"disablesinputdriver.Use toenableconnectionanalogvoltageinputw/o feedthroughcurrentatPORTx.y inputdriverstage(1) (1) force'0' when test_atpg_en_i= '1' ANALOG_TIMERCTL: Analog timerCCx inputmux control 15 14 13 12 11 10 9 8 r-0 r-0 rw-0 rw-0 r-0 r-0 rw-0 rw-0 7 6 5 4 3 2 1 0 r-0 r-0 rw-0 rw-0 r-0 r-0 rw-0 rw-0 sel_port3_6,sel_port3_7:PORT3.6 and PORT3.7 Inputmultiplexercontrol sel_timer0_cci1 Bits1,0 0,0 0,1 1,0 1,1 Timer0CCI1A CxOUT from PortP1.1 PortP1.2 PortP1.3 InputSelect APOOL Timer0CCI1B PortP1.0 PortP1.4 PortP1.5 ACTIVATION_OSC_1KHZ InputSelect sel_timer0_cci2 Bits5,4 0,0 0,1 1,0 1,1 Timer0CCI2A CxOUT from PortP1.1DIR PortP1.2DIR PortP1.3DIR InputSelect APOOL Timer0CCI2B PortP1.0DIR PortP1.4DIR PortP1.5DIR SMCLK InputSelect sel_timer1_cci1 Bits9,8 0,0 0,1 1,0 1,1 Timer1CCI1A CxOUT from PortP3.0 PortP3.1 PortP3.6 InputSelect APOOL Timer1CCI1B PortP1.6 ACTIVATION_OSC_1KHZ ACLK SMCLK InputSelect sel_timer1_cci2 Bits13,12 0,0 0,1 1,0 1,1 Timer1CCI2A CxOUT from PortP3.7 PortP3.4 PortP3.5 InputSelect APOOL Timer1CCI2B PortP1.6DIR ACTIVATION_OSC_1KHZ ACLK SMCLK InputSelect Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com ANALOG_FUSETRIM: Analog e-fuse 15 14 13 12 11 10 9 8 – – – cal-fact(cont.) r-0 r-0 r-0 r-f* r-f* r-f* r-f* r-f* 7 6 5 4 3 2 1 0 cal-fact HF-Osc_trim HF-Osc_trim Bits2-0 HF-Oscillatortrimming.Bits7-9ofeffusemodule. cal_fact Bits12-3 Dischargecalibrationfactor.Bits10-19ofe-fusemodule.

Bits6-0ofe-fusemodule can be readviabits0-6ofAPOOL APTRIM register.
Some e-fusebitscan alsobe readviatoplevelregisterETTOPCTL0
Thisisa readonlyregister. AdditionalLCD Registers LCD registersare describedin the LCD_B chapterof the CC430 FamilyUsers Guide (slau259b).The only exceptions: 1. Bit15 ofregisterLCDBCPCTL (LCDCPCLKEXT bit)has a new functionalityas describedbelow. 2. Bit10 ofregisterANALOG_ANACTL (lpm5_lcd_ana_shellbit)has a new functionalityas describedbelow. 1.LCDBCPCTL, LCD_B Charge Pump ControlRegister LCDCPCLKEXT Bit15 Selectsbetween internaland externalclocksourcefortheLCD '0'– internalclocksource Charge Pump '1'– externalclocksource Defaultvalueofthisbitisrw-0 2.ANALOG_ANACTL lpm5_lcd_ana_shell Bit10 "1"powers down (~40nA)themax_detectblockinsidetheLCD Block Defaultvalueofthisbitisrw-1 AdditionalTimer Registers TimerregistersaredescribedinTimer_A chapteroftheMSP430x09x FamilyUsersGuide (SLAU321 ). AdditionalPortsRegisters PortregistersaredescribedinVersatileI/OPortchapteroftheMSP430x09x FamilyUsersGuide (SLAU321 ) AdditionalAPOOL Registers AnalogFunctionsPoolModule chapteroftheMSP430x09x FamilyUsersGuide (SLAU321 ). AdditionalCSYS Registers Compact System ControlModule chapterof the MSP430x09x Family Users Guide (SLAU321 ).The only exceptionsare: MEMSWP BIT 11 1 -SelectstheEMU/Loader memory configuration 0 -Selectsthecustom ROM memory configuration

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www.ti.com SLLSE48 –JANUARY 2012 CCS Registers Compact Clock System chapterof the MSP430x09x FamilyUsers Guide (SLAU321 ).The onlyexceptionis differentfunctionalityofregisterCCSCTL6 as describedbelow: CCSCTL6: CCS control6 15 14 13 12 11 10 9 8 – – – Reserved xt_off r-0 r-0 r-0 rw-0 rw-0 rw-0 rw-0 rw-1 7 6 5 4 3 2 1 0 – xt_sw xt_byp xt_clken2 xt_clken1 r-0 rw-1 r-0 rw-1 rw-1 rw-1 r-0 r-0 xt_clken1 Bit0 Enable1 of32Khz XTAL clocksynchronizationsequence xt_clken2 Bit1 Enable2 of32Khz XTAL clocksynchronizationsequence xt_byp Bit2 32Khz XTAL Bypass xt_sw Bits3-6 32Khz XTAL switchSee tablebelowforrecommended switchvalues xt_off Bit8 32Khz XTAL off Reserved Bits9-12 Recommended controlswitchsettings: XTL OscillatorPerformance SW4 SW3 SW2 SW1 Leastcurrent 1 0 0 0 Faststartup 1 0 1 1 CCS CTL6 enablestheexternalclock/XTALclock: xt_clken1,bit0 and xt_clken2,bit1 1. EnableEXT/XTL Clockby settingthext_clken2and xt_clken1bits. 2. AftersufficientdelayforXTAL orexternalclocksourcetobecome stable,theusercan switchtheCCS clock sourcetoEXT/XTL Clock 3. To stoptheclock,clearthetwo bitsinthefollowingsequence: (a) SwitchtheCCS clocksourcetootherclocksource (b) Clearbitxt_clken2 (c) Waitforatleast3 periodofXTAL (orexternalclock) (d) Clearbitxt_clken1 CCSCTL2, Compact Clock System Control2 Register 15 14 13 12 11 10 9 8 Reserved r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 Reserved FSELx r-0 rw-0 rw-1 rw-0 rw-1 rw-0 rw-0 rw-0 Reserved Bits15 – 7 Reserved.Read back as 0. FSELx Bits6 – 0 FrequencytrimmingoftheHF-OSC ValueHF-OSC 0000000 highestadjustablefrequency … … 0101000 centerfrequency … … 1111111 lowestadjustablefrequency Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLink(s):AFE4110

EN Ldo_1v_pd _i 900 mV 20pF 20pF20pF ldo_low_cap_sw 200 ldo_out_mux LDO1V ldo_high_cap_sw AFE4110 SLLSE48 –JANUARY 2012 www.ti.com WDT_A Registers WDT_A registersare describedinthe Watch Dog Timer (WDT_A) chapterof the MSP430x09x FamilyUsers Guide (SLAU321 ). PMM Registers Compact System ControlchapteroftheMSP430x09x FamilyUsersGuide (SLAU321 ). PeripheralsContinued LDO1V The Low Droop Out (LDO) is1Volt(200µA max) voltageregulatorthatcapableto drive4 GPIO ports.The regulated1V outputisrecommended touse forexternalRC charge,inordertominimizetheeffectofbattery voltagechanges between consecutiveRC charges,durringTermistorand referenceResistordischargetime measurement. Figure10. LDO1V Block Diagram CP_1P8 The CP_1P8 isan internalchargepump module whichisused toboostthebatteryvoltageto~2V. The voltage boost ismandatory fortheLCD operation. The CP_1P8 issharingtheCP_OSC withtheLCD_CP as thereferenceclockfortheboostingand alsousingthe LF_clkforvoltagefeedbacksensing. The CP_1P8 requires3 externalcapacitorsforoperationwhichareconnectedas following:
1nF capacitorconnectedbetween pads 41 (C1_out)and 40 (C1_in)
1nF capacitorconnectedbetween pads 39 (C2_out)and 38 (C2_in)
4.7nFcapacitorconnectedbetween pads 37 and ground– loadcapacitor.

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2:1 Mux 2:1 DFF 20KHzForce clk High□current□load valid Vref 0.9V Vref 0.9V Test□mode DFF 20KHz Refresh pulse CLK divider Force□quiet□mod Charge pump CLK□non overlap External□cap

285 Kohm

Cp_out_level <2:0>

315 Kohm

Cp_valid_level <1:0> 10pF 20KHz Switch control AVDD□BAT reset□/□PD□/□manual□control Clk_div <2:0> Clk_refersh_pulse<1:0> Cp1p8_cap Cp1p8_ comp_out Ibias□20nA Ibias□20nA Hyst_set<1:0> Mux 2:1 Clk in Ext Clk Clk_sel_i Rdiv_cap_force Rdiv_cap_mod_selRdiv_current_force Rdiv_current_mod_ Mux 2:1 Mux 2:1 DFF 20KHzForce clk High□current□load valid Vref 0.9V Vref 0.9V Test□mode DFF 20KHz Refresh pulse CLK divider Force□quiet□mod Charge pump CLK□non overlap External□cap Cp_out_level <2:0> Cp_valid_level <1:0> 10pF 20KHz Switch control AVDD□BAT reset□/□PD□/□manual□control Clk_div <2:0> Clk_refersh_pulse<1:0> Cp1p8_cap Cp1p8_ comp_out Ibias□20nA Ibias□20nA Hyst_set<1:0> Mux 2:1 Clk in Ext Clk Clk_sel_i Rdiv_cap_force Rdiv_cap_mod_selRdiv_current_force Rdiv_current_mod_ sel CP18□M vs AXIMUM□CHARGE□PUMP□CURRENT CHARGE□CAPACITORS V =□1.3□V, V =□1.8□V, f□=□4□MHz bat load 1.E-04 1.E-03 1.E-02 1.E-01 ext_cap_size□-□F BAT_Current Current□- A Load_Current AFE4110 www.ti.com SLLSE48 –JANUARY 2012 The CP_1P8 has a validsignalwhich indicateswhen the voltageof the CP_1P8 has reached a 1.8V (Configurable)toallowoperationoftheLCD_CP orofotherperipherals. Figure11. CP_1P8 Block Diagram Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLink(s):AFE4110

P1REN .x P1OUT .x from□Module P1SEL0.x P1SEL 1 .x 1Vcc Vss P1IN.x DModule□X□IN from LDO1V Pad□Logic to A -Pool From Apool□Register PortsOn P1IRQ . x P1IE .x P1IES .x Set Q P1IFG .x bypass_dir_sync P1DIR.x LFCLK D Q D Q (to□CCRx.y) EN1EN2 30K P1DIR.x from LDO_IO_sel from□Module from□Module P1.x AFE4110 SLLSE48 –JANUARY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION Figure12. PortP1,P1.0,P1.1,P1.4Input/Output Table13.PortP1 (P1.0,P1.1,P1.4)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION LDO_IO_selP1DIR.x P1SEL1.x P1SEL0.x NSELx/PSELx <3-0> P1.0/TA0.2/TA0.1/TA1.2/LDO1/T 0 General-purposedigitalI/O In:0;Out:1 0 0 0 XXX0 A0.CCI1B0/TA0.CCI2B0/A2 Timer0_A3 Out2 output 1 0 1 0 XXX0 Timer1_A3 Out2 output 1 1 0 0 XXX0 Timer0_A3 Out1 output 1 1 1 0 XXX0 AnaloginA2 or X X X 2 XXXX Atest1Out – A Pool LDO 1V Out 1 X X X XXX1 P1.1/TA0.2/TA0.1/TA1.2/LDO1/T 1 General-purposedigitalI/O In:0;Out:1 0 0 0 XX0X A0.CCI1A1/TA0.CCI2A1/A1 Timer0_A3 Out2 output 1 0 1 0 XX0X Timer1_A3 Out2 output 1 1 0 0 XX0X Timer0_A3 Out1 output 1 1 1 0 XX0X AnaloginA1 – A-Pool X X X 1 XXXX LDO 1V Out 1 X X X XX1X P1.4/TA0.2/TA0.1/TA1.2/LDO1/T 4 General-purposedigitalI/O In:0;Out:1 0 0 0 X0XX A0.CCI1B1/TA0.CCI2B1/A0 Timer0_A3 Out2 output 1 0 1 0 X0XX Timer1_A3 Out2 output 1 1 0 0 X0XX Timer0_A3 Out1 output 1 1 1 0 X0XX AnaloginA0 – A-Pool X X X 0 XXXX LDO 1V Out 1 X X X X1XX (1) X = Don 'tcare

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P1REN.x P1OUT.x from Module P1SEL 0 .x P1SEL1.x 1Vcc Vss P1IN. x DModule X IN from A-Pool Aout Pad Logic to A-Pool A3a NSEL.x=y or PSEL.x=y PortsOn P1IRQ.x P1IE.x P1IES.x Set Q P1 IFG.x P1DIR.x EN 1 EN 2 30K ODEN P1.xfrom Module from Module AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Figure13. PortP1,P1.2Input/Output Table14.PortP1 (P1.2)Functions CONTROL BITS/SIGNAL (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL1.x P1SEL0.x NSELx/PSELx ODEN A3PSEL P1.2/TA0.2/TA0.1/TA1.2/ 2 General-purposedigital In:0;Out:1 0 0 ≠3 0 X AOUT/TA0.CCI1A2/TA0. I/O CCI2A2/A3 Timer0_A3 Out2 1 0 1 ≠3 0 X Timer1_A3 Out2 1 1 0 ≠3 0 X Timer0_A3 Out1 1 1 1 ≠3 0 X AnalogInput-A3a X X X 3 0 0 A-poolAout 1 X X X 1 0 (1) X = Don 'tcare Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLink(s):AFE4110

P1REN.x P1OUT.x from Module P1 SEL 0.x P1 SEL1.x 1Vcc Vss P1IN. x DModule X IN from A-Pool Aout Pad Logic to A-Pool A3b NSEL.x=y or PSEL.x=y PortsOn P1 IRQ . x P1IE.x P1 IES .x Set Q P1 IFG .x P1DIR.x EN 1 EN 2 30K ODEN P1.xfrom Module from Module AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Figure14. PortP1,P1.3Input/Output Table15.PortP1 (P1.3)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL1.x P1SEL0.x NSELx/PSELx VREFEN A3PSEL P1.3/TA0.2/TA0.1/TA1.2/ 3 General-purposedigital In:0;Out:1 0 0 ≠2 0 X REFOUT/TA0.CCI1A3/T I/O A0.CCI2A3/A3 Timer0_A3 Out2 1 0 1 ≠2 0 X Timer1_A3 Out1 1 1 0 ≠2 0 X Timer0_A3 Out2 1 1 1 ≠2 0 X Timer0_A3 CCR1A3 Timer0_A3 CCR2A3 A-PoolAnalogInput- X X X 2 0 0 A3b A-PoolVref X X X X 1 X (1) X = Don 'tcare

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P1 REN. x P1 OUT.x Module□X□OUT P1 SEL0.x P1 SEL1.x 1Vcc Vss P1IN.x EN1 EN2 DModule□X□IN Pad□Logic PortsOn P1 IRQ.x P1IE.x P1IES.x Set Q P1IFG.x P1DIR.x Module□X□OUT Module□X□OUT PAD□P1.x AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Figure15. PortP1,P1.5toP1.6Input/Output Table16. PortP1 (P1.5toP1.6)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL1.x P1SEL0.x P1.5/TA0.2/TA1.2/TA0.1 5 General-purposedigitalI/O I:0;O:1 0 0 Timer0_A3 Out2 1 0 1 Timer1_A3 Out2 1 1 0 Timer0_A3 Out1 1 1 1 Timer0_A3 CCR1A3 0 ≠0 ≠0 P1.6/TA0.2/TA1.2/TA0.1 6 General-purposedigitalI/O I:0;O:1 0 0 Timer0_A3 Out2 1 0 1 Timer1_A3 Out2 1 1 0 Timer1_A3 Out1 1 1 1 Timer1_A2 CCR1B0 0 ≠0 ≠0 (1) X = Don 'tcare Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLink(s):AFE4110

P2 REN. x P2OUT.x Module□X□OUT P2 SEL0.x P2 SEL1.x VCC P2IN.x EN1 EN2 DModule□X□IN VDDIO PortsOn P2 IRQ.x P2IE.x P2IES.x Set Q P2IFG.x P 2DIR .x P2.x 10K Module□X□OUT Module□X□OUT AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Table17.PortP2 (P2.0toP2.2)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL1.x P2SEL0.x JTAG Mode TCK/P2.0/TA1.2/TA1.1/CxOUT 0 General-purposedigitalI/O I:0;O:1 0 0 0 Timer1_A3 Out1 1 0 1 0 Timer1_A3 Out2 1 1 0 0 CxOUT fromApool 1 1 1 0 JTAG-TCK (2)(3)(4) x x x 1 (1) X = Don 'tcare (2) JTAG signalsTMS,TCK and TDI readas "1" when notconfiguredas explicitJTAG terminals. (3) JTAG overridesdigitaloutputcontrolwhen configuredas explicitJTAG terminals. (4) JTAG functionwithenabledpullup resistorsisdefaultafterpower up.

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www.ti.com SLLSE48 –JANUARY 2012 Table17.PortP2 (P2.0toP2.2)Functions(continued) CONTROL BITS/SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL1.x P2SEL0.x JTAG Mode TMS/P2.1/EXT_CLK/TA0.1/TA0.2 1 General-purposedigitalI/O I:0;O:1 0 0 0 EXT_CLK Out 1 0 1 0 Timer0_A3 Out1 1 1 0 0 Timer0_A3 Out2 1 1 1 0 JTAG-TMS (2)(3)(4) x x x 1 TDI/P2.2/HF_CLK/CxOUT/TA1.0 2 General-purposedigitalI/O I:0;O:1 0 0 0 HF_CLK Out 1 0 1 0 Timer1_A3 Out0 1 1 0 0 CxOUT fromApool 1 1 1 0 JTAG-TDI (2)(3)(4) X X X 1 PortP2,P2.3,Input/Output Table18. PortP2 (P2.3)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL1.x P2SEL0.x TDO/P2.3/LFCLK/TA0.2 3 General-purposedigitalI/O I:0;O:1 0 0 LFCLK Out 1 0 1 Timer0_A3 Out2 1 1 0 JTAG-TDO (2)(3) 1 1 1 (1) X = Don 'tcare (2) ConfiguringP2.3toJTAG-TDO turnsP2.0toP2.3alsointoJTAG functions (3) JTAG functionwithdisabledpullup resistorsisdefaultafterpower up. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLink(s):AFE4110

disable_p3_1 CLKIN/XIN/P3.032KHz XT AL XOUT/P3.1 xt_byp P3IN.1 P3REN.1 P3IN.0 P3OUT.0 P3REN.0 xt_byp EN EN# EN EN P3OUT.1 35K 35K AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Figure17. PortP3,P3.0,P3.1Input/Output

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P1 REN. x P 1 OUT.x Module X OUT P 1 SEL0. x P 1 SEL1. x 1Vcc Vss P 1 IN. x EN1 #EN2 DModule X IN Pad Logic PortsOn P 1IRQ. x P 1 IE. x P1 IES. x Set Q P1 IFG. x P 1DIR. x Module X OUT Module X OUT P1.x disable_p3_2 AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Figure18. PortP3,P3.2,P3.4Input/Output Table19.PortP3 (P3.2,P3.4,P3.5)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL1.x P3SEL0.x disable_p3_x General-purposedigitalI/O I:0;O:1 0 0 I:0;O:X Timer0_A3 Out1 output 1 0 1 X P3.2/TA0.1/TA1.1/TA1.0 2 Timer1_A3 Out1 output 1 1 0 X Timer1_A3 Out0 output 1 1 1 X General-purposedigitalI/O I:0;O:1 0 0 In:0;Out:X Timer0_A3 Out1 output 1 0 1 X Timer1_A3 CCR2A2 capture:CCI2A2 input X X X 0compare (1) Don 'tCare Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 61 ProductFolderLink(s):AFE4110

SLLSE48 –JANUARY 2012 www.ti.com Table19.PortP3 (P3.2,P3.4,P3.5)Functions(continued) CONTROL BITS/SIGNALS (1) PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL1.x P3SEL0.x disable_p3_x General-purposedigitalI/O I:0;O:1 0 0 In:0;Out:X Timer0_A3 Out1 output 1 0 1 X Timer1_A3 CCR2A3 capture:CCI2A3 input, X X X 0compare Table20.PortP3 (P3.6)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL1.x P3SEL0.x Sel_port3_6<1:0> 10mA General-purposedigitalI/O In:0;Out:1 0 0 XX Timer0_A3 Out0 output 1 0 1 00 Timer0_A3 Out1 output 1 0 1 01 Timer0_A3 Out2 output 1 0 1 10 Timer1_A3 Out1 output 1 0 1 11 Timer0_A3 Out1# output 1 1 0 01N/ TA0.1N/TA0.2N/TA1.CCI1A3/ 6 Timer0_A3 Out2# output 1 1 0 10 TA1.1/BOR/ACTSEN/LFOSC/C Timer1_A3 Out1# output 1 1 0 11P18OK BOR Out 1 1 1 00 ActivationSense Output 1 1 1 01 LFCLK Out 1 1 1 10 CP 1.8VOK Out 1 1 1 11 Timer1_A3 CCR1A3 capture:CCI1A3 input, X X X XXcompare (1) Don 'tCare Table21.PortP3 (P3.7)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P3.x) x FUNCTION P3DIR.x P3SEL1.x P3SEL0.x Sel_port3_7<1:0> 10mA General-purposedigitalI/O In:0;Out:1 0 0 XX Timer0_A3 Out0 output 1 0 1 00 Timer0_A3 Out1 output 1 0 1 01 Timer0_A3 Out2 output 1 0 1 10 LCD VoltageComparatorOut 1 0 1 11 Timer0_A3 Out1# output 1 1 0 01N/TA0.1N/ TA0.2N/TA1.CCI2A1/HFOSC/L 7 Timer0_A3 Out2# output 1 1 0 10 CDCPCLK/ LCD VoltageComparatorOut# 1 1 0 11LCDFCLK/1KCLK/LCDCMP LCD Charge Pump ClockOut 1 1 1 00 LCD Frame ClockOut 1 1 1 01 HFCLK Out 1 1 1 10 1Khz ActivationClockOut 1 1 1 11 Timer1_A3 CCR2A1 capture:CCI2A1 input, compare (1) Don 'tCare

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P 3REN .x P3OUT.x from□Module P3SEL0.x P3SEL 1 .x 1Vcc Vss P3IN.x DModule□X□IN from LDO1V Pad□Logic to A -Pool From Apool□Register PortsOn P3IRQ . x P3IE .x P3IES .x Set Q P3IFG .x P3DIR.x EN1EN2 30K from LDO_IO_sel P3.xfrom□Module from□Module AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Figure19. PortP3,P3.3,Input/Output Table22.PortP3 (P3.3)Functions CONTROL BITS/SIGNALS (1) PIN NAME (P3.x) x FUNCTION LDO_IO_selP1DIR.x P1SEL1.x P1SEL0.x NSELx/PSELx <3-0> P3.3/TA0.1/TA1.1/TA1.0/A0/LDO1 3 General-purposedigitalI/O In:0;Out:1 0 0 0 0XXX Timer0_A3 Out1 output 1 0 1 0 0XXX Timer1_A3 Out1 output 1 1 0 0 0XXX Timer1_A3 Out0 output 1 1 1 0 0XXX AnaloginputA0 – A-Pool X X X 0 XXXX LDO 1V Out 1 X X X 1XXX (1) X = Don 'tcare Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 63 ProductFolderLink(s):AFE4110

P3 REN. 6 P3OUT. 6 P3 SEL0.6 P3 SEL1.6 VCC P3IN.6 EN1 EN2 DModule□X□IN VDDIO PortsOn P3 IRQ .6 P3IE.6 P3 IES.6 Set Q P3IFG.6 P 3DIR 6 PAD3.6 10K 10mA Sel_port3_6<0> TA0.0 TA0.1 TA0.2 TA1.1 BROWNOUT LFCLK CP_1P8_COMP Sel_port3_6<1> TA0.0 TA0.1 TA0.2 TA1.1 ACTIVATION _SENSE P3 REN. 7 P3OUT. 7 P3 SEL0.7 P3 SEL1.7 VCC P3IN.7 EN1 EN2 DModule□X□IN VDDIO PortsOn P3 IRQ.7 P3IE.7 P3IES.7 Set Q P3IFG.7 P 3DIR 7 PAD3.7 10K 10mA Sel_port3_7<4> LCD_CP_CLK LCD_FCLK HFCLK ACTIVATION _OSC_1KHZ Sel_port3_7<5> TA0.0 TA0.1 TA0.2 LCD_COMP TA0.0 TA0.1 TA0.2 LCD_COMP AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Figure20. PortP3,P3.6,Input/Output Figure21. PortP3,P3.7,Input/Output

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P4REN.x P4OUT.x from Module P4SEL0.x P4SEL 1 .x 1Vcc Vss P4IN.x DModule X IN from Ana_test_mux Pad Logic PortsOn P4IRQ . x P4IE .x P4IES .x Set Q P4IFG . x EN1EN2 30K from Ana_test_mux_sel P4.xfrom Module from Module P4DIR.x AFE4110 www.ti.com SLLSE48 –JANUARY 2012 Figure22. PortP4 (P4.0)Pin Input/Output Table23.PortP4 (P4.0)Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P4.x) x FUNCTION P4DIR.x P4SEL1.x P4SEL0.x Ana_test_mux <3:0> General-purposedigitalI/O I:0;O:1 0 0 0 Timer0_A3 Out2 output 1 0 1 0 Timer1_A3 Out2 output 1 1 0 0P4.0/TA0.2/TA1.2/ACLK/ATEST/SPI_ 0CS ACLK Out 1 1 1 0 AnalogTestMultiplexerOut /=0 SPI ChipSelect 1 0 0 0 (1) Don 'tCare Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 65 ProductFolderLink(s):AFE4110

P1 REN. x P1 OUT.x Module X OUT P1 SEL0.x P1 SEL1.x 1Vcc Vss P1IN.x EN1 EN2 DModule X IN Pad Logic PortsOn P1 IRQ .x P1IE.x P1 IES.x Set Q P1IFG.x P1DIR.x Module X OUT Module X OUT PAD P1.x AFE4110 SLLSE48 –JANUARY 2012 www.ti.com Figure23. PortP4 (P4.1,P4.2,P4.3)Pin Input/Output Table24.PortP4 (P4.1,P4.2,P4.3)Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P4.x) x FUNCTION P4DIR.x P4SEL1.x P4SEL0.x General-purposedigitalI/O I:0;O:1 0 0 Timer0_A3 Out2 output 1 0 1 P4.1/TA0.2/TA1.2/SMCLK/ 1 Timer1_A3 Out2 output 1 1 0SPI_MOSI SMCLK Out 0 1 1 SPI SerialIn 0 0 0 General-purposedigitalI/O I:0;O:1 0 0 Timer0_A3 Out2 output 1 0 1 P4.2/TA0.2/TA1.2/MCLK/ 2 Timer1_A3 Out2 output 1 1 0SPI_CLK MCLK Out 0 1 1 SPI ClockOut 1 0 0 General-purposedigitalI/O I:0;O:1 0 0 Timer0_A3 Out2 output 1 0 1 P4.3/TA0.2/TA1.2/1KOSC/ 3 Timer1_A3 Out2 output 1 1 0SPI_MISO 1Khz ActivationOscillatorOut 0 1 1 SPI SerialOut 1 0 0 (1) Don 'tCare

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www.ti.com 11-Jan-2012 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) AFE4110B000YS ACTIVE WAFERSALE YS 0 1 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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AFE4110 specifications and overview.

Summary

MIXED SIGNAL MICROCONTROLLER

Description

MIXED SIGNAL MICROCONTROLLER

Source title AFE4110 Datasheet(PDF) - Texas Instruments

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10 SubmitDocumentationFeedback Copyright© 2012,Texas InstrumentsIncorporated

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0 Pullup/pulldownresistorattheRST/NMI pinisdisabled

1 Pullup/pulldownresistorattheRST/NMI pinisenabled

0 Pulldownisselected

1 Pullupisselected

0 NMI on risingedge

1 NMI on fallingedge

0 Resetfunction

1 NMI function

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3 Ohm

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48 SubmitDocumentationFeedback Copyright© 2012,Texas InstrumentsIncorporated

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285 Kohm

315 Kohm

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60 SubmitDocumentationFeedback Copyright© 2012,Texas InstrumentsIncorporated

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66 SubmitDocumentationFeedback Copyright© 2012,Texas InstrumentsIncorporated

AFE4110 specifications and overview.

More parts from the same family.