AFE2126 BURR-BROWN | Alldatasheet
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Technical content
Dual HDSL/SDSL ANALOG FRONT END
FEATURES
l SERIAL DIGITAL INTERFACE l 48-LEAD SSOP PACKAGE l E1, T1 AND SDSL OPERATION l 64kbps TO 1168kbps OPERATION l SCALEABLE DATA RATE l 280mW POWER DISSIPATION PER CHANNEL l TWO COMPLETE HDSL ANALOG INTER- FACES l +5V POWER (5V or 3.3V Digital) l WIDE Rx GAIN RANGE: 0dB TO 18dB
DESCRIPTION
Burr-Brown’s dual Analog Front End chip greatly re- duces the size and cost of a DSL (Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect two digital signal processors to external compromise hybrids and line transformers. The AFE2126 is optimized for HDSL (High bit rate DSL) and for SDSL (symmetrical DSL) applications. The AFE2126 is particularly suitable for multiple rate DSL systems because the transmit and receive filter responses automatically change with clock frequency. The device operates over a wide range of data rates from 64kbps to 1168kbps. Functionally, each half of this unit consists of a transmit and a receive section. The transmit section generates analog signals from 2-bit digital symbol data, and filters the analog signals to create 2B1Q symbols. The on- board differential line driver provides a 13.5dBm signal to the telephone line. The receive section filters and digitizes the symbol data received on the telephone line. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. It is housed in a 48-lead SSOP package. © 1999 Burr-Brown Corporation PDS-1561A Printed in U.S.A. December, 1999 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 For most current data sheet and other product information, visit www.burr-brown.com ΔΣ Modulator Pulse Former Programmable Gain Amp Difference Amplifier Patents Pending1/2 of AFE2126 Line Driver txLINE+ txLINE– rxHYB+ rxHYB– rxLINE+ rxLINE– tx and rx Control Registers tx and rx Interface Lines Decimation Filter AFE2126
Specifications at 25°C, AVDD = +5V, DVDD = +3.3V, and txBaudCLK = 584kHz (E1 rate), unless otherwise noted. Specifications apply to each channel of the AFE2126. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. AFE2126E PARAMETER COMMENTS MIN TYP MAX UNITS RESOLUTION 14 Bits RECEIVE CHANNEL Number of Inputs Differential 2 Input Voltage Range Balanced Differential (1) ±3.0 V Common-Mode Voltage AV DD /2 V Input Impedance All Inputs See Typical Performance Curves Input Capacitance 10 pF Input Gain Matching Line Input vs Hybrid Input ±2% Programmable Gain 0dB, 3dB, 6dB, 9dB, 12dB, 15dB, and 18dB 0 +18 dB Settling Time For Any Change in Gain or txBaud CLK 6 Symbol Periods Gain + Offset Error Tested at Each Gain Range 5 %FSR (2) Output Data Coding Two’s Complement Output Word Rate (3) 32 584 kHz Output Bit Rate(3) 64 1168 kbits/sec TRANSMIT CHANNEL Transmit Clock Rate, txBaudCLK Symbol Rate 32 584 kHz T1 Transmit –3dB Point T1/E1 4/99-002R4 Draft Compliant 196 kHz T1 Rate Power (4, 5) 13 14 dBm E1 Transmit –3dB Point ETSI Compliant 292 kHz E1 Transmit Power (4, 5) 13 14 dBm Common-Mode Voltage, VCM AV DD /2 V Output Resistance(6) DC to 1MHz 1 Ω TRANSCEIVER PERFORMANCE Uncancelled Echo(5) rxGAIN = 0dB, Loopback Enabled –71 –68.5 dB rxGAIN = 0dB, Loopback Disabled –71 –68.5 dB rxGAIN = 3dB, Loopback Disabled –74 –71 dB rxGAIN = 6dB, Loopback Disabled –76 –73.5 dB rxGAIN = 9dB, Loopback Disabled –78 –75.5 dB rxGAIN = 12dB, Loopback Disabled –80 –77.5 dB rxGAIN = 15dB, Loopback Disabled –82 –79.5 dB rxGAIN = 18dB, Loopback Disabled –84 –81.5 dB DIGITAL INTERFACE (6) Logic Levels VIH |IIH| < 10µAD V DD – 1 DV DD + 0.3 V VIL |IIL| < 10µA –0.3 +0.8 V VOH IOH = –20µAD V DD – 0.5 V VOL IOL = 20µA +0.4 V trx1 Interface 91 4 n s POWER Analog Power Supply Voltage Specification 5 V Analog Power Supply Voltage Operating Range 4.75 5.25 V Digital Power Supply Voltage Specification 3.3 V Digital Power Supply Voltage Operating Range 3.15 5.25 V Power Dissipation (4, 5) AV DD = 5V, DVDD = 3.3V, 275 mW Power Dissipation(4, 5) AV DD = DVDD = 5V 325 mW Power Supply Rejection Ratio (PSRR) 55 dB TEMPERATURE RANGE Operating(6) –40 +85 °C NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore, the actual voltage swing about the common- mode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP and txLINEN). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Functionality only is guaranteed over temperature range.
±10mA, Continuous Junction Temperature (T ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA AFE2126E SSOP-48 333 –40 °C to +85°C AFE2126E AFE2126E/500 Tape and Reel "" " " " AFE2126E/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “AFE2126E/1K” will get a single 1000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION BLOCK DIAGRAM Pulse Former Filter txbaudCLK tx48xCLK Data In rxbaudCLK rx48xCLK Data Out Output Buffer Voltage Reference ΔΣ Modulator Transmit Control Receive Control Decimation Filter txLINE– txLINE+ REF P VCM REF N rxLINE+ rxLINE– rxHYB+ rxHYB– AFE2126
PIN # TYPE NAME DESCRIPTION CHANNEL A
1 Output Data OutA Output Data Word
2 Input rx48xCLKA Receive Clock at 48x Baud Clock
(23.032MHz for E1)
3 Input rxbaudCLKA Receive Baud Clock (584kHz for E1)
4 Input Data InA Input Data Word
5 Input tx48xCLKA Transmit Clock (584kHz for E1)
6 Input txbaudCLKA Transmit Baud Clock at 48x Baud Clock
(584kHz for E1)
7 Power DV
DD Digital Supply (+3.3V to +5V)
8 Ground DGND Digital Ground
9 Ground AGND Analog Ground
10 Output txLINE+A Transmit Line Driver Output, Positive
11 Power AV
DD Analog Supply (+5V)
12 Output txLINE–A Transmit Line Driver Output, Negative
13 Ground AGND Analog Ground
14 Power AV
DD Analog Supply (+5V)
15 Output REF N A Negative Reference Output
16 Output V CM A Common-Mode Voltage (buffered)
17 Output REF PA Positive Reference Output
18 Ground AGND Analog Ground
19 Ground AGND Analog Ground
20 Input rxLINE+A Positive Line Input
21 Input rxLINE–A Negative Line Input
22 Input rxHYB+A Positive Input from Hybrid Network
23 Input rxHYB–A Negative Input from Hybrid Network
24 Power AV
DD Analog Supply (+5V)
25 Power AV DD Analog Supply (+5V)
26 Input rxHYB–B Negative Input from Hybrid Network
27 Input rxHYB+B Positive Input from Hybrid Network
28 Input rxLINE–B Negative Line Input
29 Input rxLINE+B Postiive Line Input
30 Ground AGND Analog Ground
31 Ground AGND Analog Ground
32 Output REF
PB Positive Reference Output
33 Output V CM B Common-Mode Voltage (buffered)
34 Output REF N B Negative Reference Output
35 Power AV DD Analog Supply (+5V)
36 Ground AGND Analog Ground
37 Output txLINE–B Transmit LIne Driver Output, Negative
38 Power AV
DD Analog Supply (+5V)
39 Output txLINE+B Transmit Line Driver Output, Positive
40 Ground AGND Analog Ground
41 Ground DGND Digital Ground
42 Power DV
DD Digital Supply (+3.3V to +5V)
43 Input txbaudCLKB Transmit Baud Clock (584kHz for E1)
44 Input tx48xCLKB Transmit Clock at 48x Baud Clock
(28.032MHz for E1)
45 Input Data InB Input Data Word
46 Input rxbaudCLKB Receive Baud Clock (584kHz for E1)
47 Input rx48xCLKB Receive Clock at 48x Baud Clock
(28.032MHz for E1)
48 Output Data OutB Output Data Word
txLINE–A AGND AV DD REF N A VCM A REF PA AGND AGND rxLINE+A rxLINE–A rxHYB+A rxHYB–A AV DD Data OutB rx48xCLKB rxbaudCLKB Data InB tx48xCLKB txbaudCLKB DV DD DGND AGND txLINE+B AV DD txLINE–B AGND AV DD REF N B VCM B REF PB AGND AGND rxLINE+B rxLINE–B rxHYB+B rxHYB–B AV DD AFE2126 Channel A Channel B
TYPICAL PERFORMANCE CURVES At Output of HDSL Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD + = +5V, DVDD + = +3.3V, txBaudCLK = 392kHz (T1), unless otherwise specified. CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. CURVE 2. Input Impedance of rxLINE and rxHYB. 100 120 300 500 INPUT IMPEDANCE vs BIT RATE Input Impedance (kΩ ) Bit Rate (kbps) 700 900 1300 1100 T1 = 784kbps, 16kΩ E1 = 1168kbps, 10.5kΩ POWER SPECTRAL DENSITY LIMIT - T1 RATE Frequency (kHz) 500 1000 1500 2000 25000 Power Spectral Density (dBm/Hz) –20 –40 –60 –80 –100 –120
1 AFE Transmits HDSL Symbol
9 Loopback Control 1 Loopback Mode
0 Normal Operation
channel programmable gain amplifier. rxLINE+ and rxLINE– inputs are connected. (bits 15-2). The spare bits (1 and 0) will be always be low. Eight additional (interdata) bits follow and are always high. The data is clocked out on the falling edge of rx48xCLK. may be used for more flexible post-processing. FIGURE 5. Data Out Word. mise hybrid (– to + and + to –) as shown in Figure 6. frequencies just by changing the clock speed.
output provide some smoothing for the output transmission. At lower bit rates, the amount of smoothing will be less. loss with the input impedance of the AFE2126. rate of 320k bits per second. FIGURE 6. Basic Connection Diagram for Each Channel of the AFE2126.
similar to the one shown in Figure 7. applied both to the AFE and to the input of an adaptive filter. FIGURE 7. Uncancelled Echo Test Diagram. TABLE III. Typical Power Dissipation (per channel). remain in the range 4.75V to 5.25V). specifications includes all power dissipated in the AFE2126. various conditions is shown in Table III.
The analog front end of an HDSL system has two conflicting requirements. It must accept and deliver moderately high rate digital signals and it must generate, drive, and convert precision analog signals. To achieve optimal system perfor- mance with the AFE2126, both the digital and the analog sections must be treated carefully in board layout design. The power supply for the digital section of the AFE2126 can range from 3.3V to 5V. This supply should be decoupled to digital ground with ceramic 0.1µF capacitors placed as close to DGND and DV DD as possible. One capacitor should be placed between pins 7 and 8, and the second capacitor, between pins 41 and 42. Ideally, both a digital power supply plane and a digital ground plane should run up to, and underneath the digital pins of the AFE2126 (pins 1 through 6, and pins 43 through 48). However, DV DD may be supplied by a wide printed circuit board (PCB) trace. A digital ground plane underneath all digital pins is strongly recommended. The remaining portion of the AFE2126 should be considered analog. All AGND pins should be connected directly to a common analog ground plane and all AV DD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. The analog power supply pins should be decoupled to analog ground with ceramic 0.1µF capacitors placed as close to the AFE2126 as possible. One 10µF tantalum capacitor should also be used with each AFE2126 between the analog supply and analog ground. Ideally, all ground planes and traces, and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE2126 by a small trace.