AFE1302 TI | Alldatasheet
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Copyright © 2000, Texas Instruments Incorporated SBWS014 Printed in U.S.A. December, 2000 ADSL ANALOG FRONT-END
FEATURES
G NOISE FLOOR: –144dBm/Hz G MULTIRATE COMPATIBLE G VCXO CIRCUITRY AND DAC AFE1302
DESCRIPTION
Burr-Brown’s Analog Front-End from Texas Instru- ments reduces the size and cost of an ADSL-compliant system by providing the active analog circuitry needed to connect an ADSL Digital Signal Processor (DSP) to an external line driver, receiver, TX/RX filters, hy- brid, transformer, and POTS filter. The AFE1302 is designed for downstream data rates of 4Mbps and higher, and operation at a clock rate of 35.328MHz, with an output word rate of up to 8.832MWords/s. Functionally, this unit consists of a transmit (TX) chan- nel, a receive (RX) channel, a VCXO (Voltage Con- trolled Crystal Oscillator) control Digital-to-Analog Converter (DAC), and VCXO active circuitry. The TX section converts, filters, and buffers outgoing Discrete Multi Tone (DMT) data from the ADSL DSP. The receive section amplifies, filters, and digitizes the DMT data received on the twisted pair line. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply voltage ranging from 3.3V to 5V. The chip uses only 570mW. The AFE1302 is designed to be used with external amplifiers and filters for noise reduction and dynamic- range improvement. The RX channel consists of a low-noise PGA, a switched capacitor low-pass filter, and fourth-order delta-sigma Analog-to-Digital Converter (ADC). The delta-sigma modulator operating at a 32X oversampling ratio pro- duces a 16-bit output at word rates up to 8832kHz. The TX channel consists of a fourth-order delta-sigma DAC, switched-capacitor low-pass filter, program- mable attenuator, and buffer. The buffer drives off- chip into a low-noise line driver configured as a 3-pole active filter to produce an overall low-noise high-drive TX output signal on a twisted pair line. G 8.8M TO 1.1MWords/s WORD RATE G FIVE GENERAL-PURPOSE OUTPUTS G 570mW POWER DISSIPATION G TQFP-48 PACKAGE 16-Bit DAC 16-Bit ADC VCXO DAC Atten PGA Interpolation Filter Decimation Filter Analog Loop Back General Purpose Digital Output VCXO Active Ckts BufferLP Filter LP Filter Digital InterfaceFrom DSP TX Output RX Input AFE1302 Digital Loopback Patents Pending www.ti.com AFE1302
Typical at 25°C, AVDD = +5V, DVDD = +3.3V, fCLK = 35.328MHz, TX output and RX input measured differentially, unless otherwise specified. AFE1302Y PARAMETER CONDITIONS MIN TYP MAX UNITS RECEIVE CHANNEL Input Signal (CMV = AVDD /2) Differential, G = –6dB 9.0 9.6 Vp-p Common-Mode Voltage AV DD /2 V Input Impedance Pin-to-AV DD 2.8 k Ω Input Capacitance 30 pF Programmable Amplifier Range –6 40 dB Gain Step Size Monotonicity Guaranteed 1 dB Input Noise PGA = +40dB (1) –148 –144 dBm/Hz Output Word Rate 1.104 8.832 MWords/s Output Word Resolution (15 Bits + 1 Sign Bit) or (14 Bits + 2 Sign Bits) 16 Bits ADC Sampling Rate 35.328 MSamples/s Low-Pass Frequency Corner One Pole Analog Filter 1.1 MHz Passband Droop At 550kHz 1 dB SINAD PGA Gain = 40dB, Input Referred 100 dB PGA Gain = 0dB 68 dB THD Single Tone, PGA = 0dB 75 84 dB MTPR (MultiTone Power Ratio) 75 dB TRANSMIT CHANNEL Input Word Rate 1.104 8.832 MWords/s Input Word Resolution (15 Bits + 1 Sign Bit) or (14 Bits + 2 Sign Bits) 16 Bits Peak Signal Amplitude Differential, G = 0dB 4.4 4.8 Vp-p Common-Mode Voltage AV DD /2 Load Resistance Differential 400 Ω Load Capacitance Differential 10 pF Programmable Attenuator Range –31 0 dB Attenuator Step Size Monotonicity Guaranteed 1.0 dB Attenuator Step Accuracy 0.5 dB Low-Pass Filter Corner Frequency Fourth-Order, 0.1dB Programmable 127 kHz Passband Ripple –0.1 dB Group Delay Variation 10 µs Output Noise Measured at 50kHz –110 dBm/Hz Measured at 200kHz –116 dBm/Hz THD Distortion FS Output 0dB 65 dBc FS Output –6dB 73 dBc SFDR in RX Band (20 Tone Test) See Note (2) –98 dBVrms MTPR 70 dB VCXO WITH EXTERNAL CIRCUITRY Sensitive to PCB Layout Frequency 35.328 MHz Tuning Range ±100 ppm DAC Resolution Monotonicity Guaranteed 10 Bits DIGITAL INTERFACE Logic Levels V IH |IIH| < 10µAD V DD – 1 DV DD DV DD + 0.3 V VIL |IIL| < 10µA –0.3 0 0.8 V VOH IOH = –20µAD V DD – 0.5 V VOL IOL = 20µA 0.4 V CONTROL INTERFACE (GC0, GC1, GP0, GP1, GP2) Logic Levels VOH IOH = 1mA DV DD – 0.5 V VOL IOL = 1mA 0.4 V POWER Analog Power Supply Voltage AV DD 4.75 5 5.25 V Analog Dissipated Power 470 mW Digital Power Supply Voltage DV DD 3.0 3.3 5.5 V Digital Dissipated Power V DD = 3.3V 100 mW TEMPERATURE RANGE Operation 07 0 °C Thermal Resistance, θJA 56.5 °C/W NOTES: (1) With TX in operation, no RX data, referred to 100Ω . (2) With TX reverb multitone signal (25.875kHz to 138kHz at a 4.3125kHz step), measured signal level beyond 150kHz at TXP, TXN.
ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. AV SS 4 TXP AV DD 4 TXN AV SS 6 CMI CMO VREF1 VRNTX VRPTX VRNRX VRPRX CLKM CLKNIB DV SS 2 AV SS 1 XTALO XTALI AV DD 1 VCXO VREF2 AV DD 2 AV SS 2 AV SS 5 CLIP PDOWN RESETN GP2 GP1 GP0 RXN RXP AV DD 3 AV SS 3 GC1 GC0 CLWD CTRLIN DV DD 1 DV SS 1 TX3 TX2 TX1 TX0 RX3 RX2 RX1 RX0 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 AFE1302 PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER (1) MEDIA AFE1302Y TQFP-48 355 0 °C to +70°C AFE1302Y AFE1302Y/250 Tape and Reel "" " " " AFE1302Y/2K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “AFE1302Y/2K ” will get a single 2000-piece Tape and Reel. PACKAGE/ORDERING INFORMATION ±10mA, Continuous
Number Type Pin Name Description External Connection Analog Interface
23 Output GC0 External Gain Control Output LSB Optional Swap Amp
24 Output GC1 External Gain Control Output MSB Optional Swap Amp
19 Input RXN Analog Receive Negative Input Line Interface
20 Input RXP Analog Receive Positive Input Line Interface
25 Output VRPRX RX Reference Positive Output 0.1uF,1 µF to AV SS 3 26 Output VRNRX RX Reference Negative Output 0.1uF,1 µF to AVSS 3 30 Output CMO Output Common-Mode voltage 0.1uF,1 µF to AVSS 3 27 Output VRPTX TX Reference Positive Output 0.1uF,1 µF to AVSS 3 28 Output VRNTX TX Reference Negative Output 0.1uF,1 µF to AVSS 3 29 Output VREF1 Unbuffered Bandgap Reference 0.1uF,1 µF to AVSS 3 31 Output CMI Unbuffered Common-Mode Voltage 0.1uF,1 µF to AVSS 3
35 Output TXP TX Positive Output Line Interface
33 Output TXN TX Negative Output Line Interface
40 Output VREF2 DAC Reference Voltage XTAL Interface
41 Output VCXO VXCO Control Voltage DAC Output XTAL Interface
43 — XTALI XTAL Oscillator Input XTAL 44 — XTALO XTAL Oscillator Output XTAL Digital Interface 48 Output CLKM Master Clock Output, f = 35.328MHz DSP
47 Output CLKNIB Nibble Clock Output DSP
1 Output CLWD Word Clock Output DSP
2 Input CTRLIN Serial Data Input DSP
5 Input TX3 Digital Transmit Input DSP
6 Input TX2 Digital Transmit Input DSP
7 Input TX1 Digital Transmit Input DSP
8 Input TX0 Digital Transmit Input DSP
9 Output RX3 Digital Receive Output DSP
10 Output RX2 Digital Receive Output DSP
11 Output RX1 Digital Receive Output DSP
12 Output RX0 Digital Receive Output DSP
13 Output CLIP Clipping Detection Output DSP
14 Input PDOWN Power-Down Select, “1” = Power Down DSP
15 Input RESETN Reset Pin (Active LOW) DSP
16 Output GP2 General-Purpose Output 2 —
17 Output GP1 General-Purpose Output 1 —
18 Output GP0 General-Purpose Output 0 —
46 — DV SS 2 Digital Ground 2 DGND Plane 3 3V or 5V DV DD 1 Digital Power 0.1uF,1 µF to DVSS 1 4 — DV SS 1 Digital Ground 1 DGND Plane 21 5V AV DD 3 Analog Power (Main) 0.1uF,1 µF to AVSS 3 22 — AV SS 3 Analog Ground (Main) AGND Plane 32 — AV SS 6 Analog Ground for TX Output AGND Plane 34 5V AV DD 4 Analog Power for TX Output 0.1uF,1 µF to AVSS 4 36 — AV SS 4 Analog Ground for TX Output AGND Plane 37 — AV SS 5 Analog Clock Ground AGND Plane 38 — AV SS 2 Analog Clock Ground AGND Plane 39 5V AV DD 2 Analog Clock Power 0.1uF,1 µF to AVSS 2 42 5V AV DD 1 XTAL Power 0.1uF,1 µF to AVSS 1 45 — AV SS 1 XTAL Ground AGND Plane
FIGURE 2. AFE1302 Transmit/Receive Timing Diagram. NOTE: CLKM = 35.328; For N = 1, CLKNIB = 35.328MHz, CLWD = 8.832MHz; tS: Setup Time, min tS = 5ns; tH : Hold Time, min tH = 5ns. is one sign bit. Please refer to Tables I and II. TABLE I. AFE1302 TX Data Format, Address 001, Bit 9 = 0. TABLE II. AFE1302 TX Data Format, Address 001, Bit 9 = 1. TABLE IV. AFE1302 RX Data Format, Address 001, Bit 9 = 1.
data is greater than 7FFF, it will be clipped to 7FFF.
- For the two sign-bit case, if AFEG_RX data is greater
bit 3 in AFE1302 control register. FIGURE 3. AFE1302 Program Timing.
12 Data Bits ≥ 16 HIGH Stop BitsData ID
3 Bit
NOTE: CLWD = 8.832MHz/N; tS: Setup Time, min tS = 10ns; tH : Hold Time, min tH = 10ns. the AFE control register on the CTRLIN pin in 16-bit blocks. data ID code 6 and 7 are reserved for future use.
1 5 1 4 1 3 1 2 1 1 1 0 9876543210 R X REGISTER
0 X 0 0 0 External Gain Control GC1 (1 Bit)
0 X 0 0 0 External Gain Control GC0 (1 Bit)
0 0 0 0 0 0 0 0 0 0 AGC RX Gain Setting –6dB (6 Bits) 0 0 0 0 0 0 1 0 0 0 AGC RX Gain Setting –5dB (6 Bits)
0 X X X X X X 0 0 0 AGC RX Gain Setting X dB (6 Bits)
0 1 0 1 1 1 0 0 0 0 AGC RX Gain Setting 40dB (6 Bits) 0 X 0 0 0 X = 1, Filter Setting 1.1MWords/s; X = 0, Filter Setting 8.8MWords/s 0 0 0 0 0 0 0 Reserved, Must Be Set As Shown 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 T X REGISTER 0 0 0 0 0 0 0 0 1 Transmit Attenuator Setting = 0dB (5 Bits) 0 0 0 0 0 1 0 0 1 Transmit Attenuator Setting = –1dB (5 Bits)
0 X X X X X 0 0 1 Transmit Attenuator Setting = X dB (5 Bits)
0 1 1 1 1 1 0 0 1 Transmit Attenuator Setting = –31dB (5 Bits)
0 X 0 0 1 GP2 (General-Purpose Output 2)
0 X 0 0 1 GP1 (General-Purpose Output 1)
0 X 0 0 1 GP0 (General-Purpose Output 0)
0 X 0 0 1 X = 1, RX and TX Data Format Has 1 Sign Bit and 15 Data Bits
X = 0, RX and TX Data Format Has 2 Sign Bits and 14 Data Bits 0 0 0 1 0 0 1 Reserved, Must Be Set As Shown 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 AFE REGISTER
0 X 0 1 0 Digital Loopback TX to RX Through Digital Section (1 Bit)
X = 1, Loopback Mode; X = 0, Normal Operation Mode
0 X 0 1 0 Analog Loopback TX to RX Through Analog Section (1 Bit)
X = 1, Loopback Mode; X = 0, Normal Operation Mode
0 X 0 1 0 X = 1, RX Enable Mode
0 X X 0 1 0 Data Word Clock Divider (2 Bits)
0 0 0 0 1 0 Data Word Clock = 8.832MHz (2 Bits) 0 0 1 0 1 0 Data Word Clock = 4.416MHz (2 Bits) 0 1 0 0 1 0 Data Word Clock = 2.208MHz (2 Bits) 0 1 1 0 1 0 Data Word Clock = 1.104MHz (2 Bits)
0 X 0 1 0 Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared
0 0 0 1 0 0 1 0 1 0 Reserved, Must Be Set As Shown 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 VCXO DAC VALUE REGISTER
0 X X X X X X X X X X 0 1 1 VCXO DAC Input Word (10 Bits)
0 0 0 0 0 0 0 0 0 0 0 0 1 1 VCXO DAC Input Word = 0 (10 Bits) 0 1 1 1 1 1 1 1 1 1 1 0 1 1 VCXO DAC Input Word = +FS (10 Bits) 0 0 0 0 1 1 Reserved, Must Be Set As Shown 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 INTERFACE REGISTER
0 X X X X X X X X 1 0 0 Reserved
0 X 1 0 0 X = 0, TX[3:0] Should Be Latched On Falling CLKNIB
X = 1, TX[3:0] Should Be Latched On Rising CLKNIB
0 X 1 0 0 X = 0, RX[3:0] Should Be Latched On Falling CLKNIB
X = 1, RX[3:0] Should Be Latched On Rising CLKNIB
0 X 1 0 0 Digital Loopback RX Into TX:
X = 1 Loopback Mode; X = 0 Normal Mode 0 0 1 0 0 Reserved, Must Be Set As Shown 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 RESERVED 0 1 111 101 1 1111 1 01 Reserved, Must Be Set As Shown
0 X XXX XXX X XXXX 110 Reserved, Data ID 6
0 X XXX XXX X XXXX 111 Reserved, Data ID 7
NOTE: All registers are initially set to zero. TABLE V. AFE1302 Control Register. START BIT DATA BITS DATA ID
coded in two’s complement, as shown in Table VI. The AFE1302 scales operation with the clock frequency. changed for different frequency requirements. underneath all digital pins is strongly recommended. FIGURE 4. VCXO Circuit Layout, Approximately Two Times Actual Size.
ADSL FRONT-END SYSTEM PERFORMANCE PARAMETER CONDITIONS VALUE UNITS TX PATH Peak Signal Amplitude to Telephone Line 12 Vp-p Load Impedance 100 Ω Output Power To Line (100 Ω Match) 13 dBm Low-Pass Filter Corner Frequency 127 kHz Passband Ripple 3d B Group Delay Variation 15 ms Output Noise, Out of Band See Note (2) –142 dBm/Hz RX PATH RX Input 12.5 Vp-p MTPR 70 dB Noise Floor PGA = 40dB –142 dBm/Hz External High-Pass Filter Corner Frequency 157 kHz Anti-Alias Filter Corner Frequency 1.1 MHz Passband Ripple 3d B NOTE: (1) dBm referenced from average tone power and spread over 4kHz receive tone bins. (2) Measured at 200kHz with typical ADSL multitone transmission signal. TABLE VIII. ADSL Front-End System Performance when using the AFE1302 in a Texas Instruments Reference Design Evaluation Board. Typical at 25°C, AVDD = +5V, DVDD = +3.3V, fCLK = 35.328MHz, TX output and RX input measured at line side. The specifications for the complete system solution are given in Table VIII. The numbers include the effects of both the AFE1302 and the surrounding external components, includ- ing a Burr-Brown TX line driver from Texas Instruments. RECEIVE Receive channel external components include a hybrid, receive amplifier, fifth-order high-pass passive filter, and first-order, low-pass, anti-alias filter. The ADSL system is frequency division multiplexed on a single twisted pair. Filters are used to separate the transmit and receive signals. When the AFE1302 drives long twisted-pair loops, the transmit signal is much larger than the receive signal. The hybrid will ideally eliminate all of the transmit signal at the receive input. However, for poorly matched lines, the actual reduction may be quite small. Without external filtering between the transmit output and the receive input, the transmit signal will clip the receive input before the on-chip receive filter can reduce the transmit signal. Therefore, external receive filters are required to eliminate transmit noise. Refer to Figure 6 for an external circuit and contact the factory for a detailed reference design document.
ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY AFE1302Y/250 ACTIVE TQFP PFB 48 250 AFE1302Y/2K ACTIVE TQFP PFB 48 2000 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 3-Oct-2003
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