AFE1230E

AFE1230 BURR-BROWN | Alldatasheet

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G.SHDSL ANALOG FRONT-END

FEATURES

G E1, T1, AND SUBRATE OPERATION G COMPLIES WITH G.SHDSL AND HDSL2 G 16-BIT, DELTA-SIGMA CONVERTERS G ON-CHIP DRIVER AND PGA G PROGRAMMABLE tx AND rx FILTERS G SERIAL DIGITAL INTERFACE G 750mW POWER DISSIPATION AT E1 G +5V POWER (5V OR 3.3V DIGITAL) G SSOP-28 PACKAGE G –40°C TO +85°C TEMPERATURE RANGE

DESCRIPTION

Texas Instrument’s analog front-end chip, the AFE1230, is designed to greatly reduce the size and cost of G.SHDSL and HDSL2 application designs. It provides a transceiver as the line interface between the Digital Signal Processor (DSP) and the local loop. The AFE1230 is designed to handle upstream and downstream data transmission over a wide range of data rates from 64kbps to 2.5Mbps. Function- ally, this unit consists of a transmitter and receiver section. The transmitter section consists of a digital interpolation filter, a 16-bit, delta-sigma Digital-to-Analog (D/A) con- verter, a digitally programmable fifth-order or seventh-order SC (Switched Capacitor) low-pass filter, and a differential output line driver. The receiver section includes an input Programmable Gain Amplifier (PGA), a 16-bit, delta-sigma Analog-to-Digital (A/D) converter, and a programmable decimation filter. The AFE1230 receives a 16-bit data word plus an 8-bit control byte via the serial interface to facilitate the D/A conversion and control functions. The subsequent analog signal is sent to the on-chip line driver that provides 14.5dBm power into a 135Ω line for G.SHDSL operation. In addition, the on-chip line driver can be used as an output buffer with an external line driver, such as the OPA2677, to generate over 17dBm power into a 135Ω line for HDSL2 operation. With an appropriate DSP, the transmitted Power Spectral Density (PSD) complies with either the G.SHDSL standard or with the HDSL2 stan- dard (via an OPA2677 used as an external driver). In the receive path, the input amplifier sums the signals from the line and hybrid path to perform first-order analog echo cancellation. The resultant signal is then digitized by the rest of the receive section into a 16-bit digital word that is sent to the external DSP. This IC operates on a single 5V supply, while the digital supply can be from 3.3V to 5V. It is housed in a SSOP-28 package. The typical power consumption is 750mW at E1 rates with G.SHDSL (560mW for HDSL2 operation) and an operation temperature range of –40°C to +85°C. AFE1230 ∆Σ 16-Bit A/D Converter PGA Input Amplifier Patents PendingAFE1230 Driver/ Buffer txLINE txLINE hybINPUT hybINPUT rxINPUT rxINPUT tx and rx Digital Interface Registers Programmable Digital LPF Digital Interpolation LPF Programmable SC LPF ∆Σ 16-Bit D/A Converter MCLK txBaud txData rxBaud rxData AFE1230 SBWS015A – AUGUST 2001 www.ti.com PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1D V DD Power Digital Supply

2 GNDD Ground Digital Ground

3 txBaud Input Transmit Baud Clock 4 txData Input Digital Input of Transmit Section

5 MCLK Input Master Clock 48x Clock

6 rxBaud Input Recieve Baud Clock 7 rxData Output Digital Output of Recieve Section 8D V DD Power Digital Supply

9 GNDD Ground Digital Ground

10 GNDA Ground Analog Ground

11 HybP Input Positive Hybrid Input

12 HybM Input Negative Hybrid Input

13 LineP Input Positive Line Input

14 LineM Input Negative Line Input

15 GNDA Ground Analog Ground—Recieve

16 GNDA Ground Analog Ground—Reference

REF P Output Positive Reference Voltage, rx/tx

18 V CM Output Common-Mode Voltage, rx/tx

19 V REF M Output Negative Reference Input, rx/tx

20 AV DD Power Analog Supply—Reference

21 AV DD Power Analog Supply—Recieve

22 AV DD Power Analog Supply—Transmit

23 GNDA Ground Analog Ground/Driver

24 txOutM Output Line Driver Output Negative 25 AV DD Power Analog Supply/Driver 26 txOutP Output Line Driver Output Positive

27 GNDA Ground Analog Ground/Driver

28 GNDA Ground Analog Ground Transmit

This integrated circuit can be damaged by ESD. Texas Instru- ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE SPECIFIED DRAWING PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER DESIGNATOR RANGE MARKING NUMBER (1) MEDIA AFE1230E SSOP-28 324 DBQ –40 °C to +85°C AFE1230E AFE1230E Rail AFE1230E/1K "" "" " AFE1230E/1K Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “AFE1230E/1K” will get a single 1000-piece Tape and Reel. The AFE1230E/1K can only be ordered in 1000-unit increments. PACKAGE/ORDERING INFORMATION DV DD GNDD txBaud txData MCLK rxBaud rxData DV DD GNDD GNDA HybP HybM LineP LineM GNDA GNDA txOutP AV DD txOutM GNDA AV DD AV DD AV DD VREF M VCM VREF P GNDA GNDA AFE1230

PARAMETER CONDITIONS MIN TYP MAX UNITS RECEIVE CHANNEL Number of Inputs Differential 2 Input Voltage Range Balanced Differential (1) ±3.1 V Common-Mode Voltage AV DD /2 V A/D Converter Code ∆Σ A/D Converter 16 Bits Programmable Gain Range 3dB Steps 0 +21 dB Gain Absolute Accuracy R IN = 10kΩ± 20% % Gain Step Accuracy 3dB Steps, Accuracy Relative to Gain = 1 ±0.5 dB Settling Time for Gain Change 6 Symbol Periods Output Data Coding Binary Two's Complement 16 Bits MCLK Master Clock 1.28 40.8 MHz System Bit Rate 80k 2.55M bps Symbol Rate Three Bits/Symbol 26.7 850 kHz Output Word Rate (OWR) Two rx Words/Symbol Period (2) 53.4 1700 kHz Filter Cutoff Frequency(3) Programmable 5th-Order LPF, 0.25 0.5 OWR 0.25x and 0.5x OWR TRANSMIT CHANNEL D/A Converter Code ∆Σ D/A Converter 16 Bits Output Line Power(4) Internal Line Driver, PAR = 3, 14.5 dBm Provides 14.5dBm at 135Ω Line with 1:3.7 Transformer Output Power(5) Internal Line Buffer, PAR = 4, 10 dBm Load is External Driver OPA2677 Output Voltage Balanced Differential ±3.1 V Common-Mode Voltage, VCM AV DD /2 V Output Resistance DC to 1MHz 0.2 Ω Input Data Coding Binary Two's Complement 16 Bits MCLK Master Clock 1.28 40.8 MHz System Bit Rate Three Bits/Symbol 80k 2.55M bps Input Symbol Rate Three Bits/Symbol 26.7 850 kHz Input Word Rate (IWR) Two Words/Symbol Period 53.4 1700 kHz Filter Cutoff Frequency TRASNSCEIVER PERFORMANCE Uncancelled Echo(7) rxGAIN = 12dB –80 dB DIGITAL INTERFACE Logic Levels: VIH |IIH| < 10µAD V DD – 1D V DD + 0.3 V VIL |IIL| < 10µA –0.3 +0.8 V VOH IOH = –20µAD V DD – 0.5 V VOL IOL = 20µA +0.4 V POWER Analog Power-Supply Voltage Specification 5 V Analog Power-Supply Voltage Operating Range 4.75 5.25 V Digital Power-Supply Voltage Specification 3.3 V Digital Power-Supply Voltage Operating Range 3.15 5.25 V Power Dissipation (8) AV DD = 5V, DVDD = 3.3V, 750 mW 14.5dBm at 135Ω Line, E1 Power Dissipation(9) AV DD = 5V, DVDD = 3.3V 560 mW PSRR 60 dB TEMPERATURE RANGE Operating(10) –40 +85 °C

ELECTRICAL CHARACTERISTICS

All specifications are typical at 25°C, AVDD = +5V, DVDD = +3.3V, MCLK = 37.1MHz (E1 rate), unless otherwise noted. NOTES: (1) With a balanced differential signal, the positive input is 180° out-of-phase with the negative input, therefore, the actual voltage swing about the common- mode voltage on each pin is ±1.55V to achieve a total input range of ±3.1V or 6.2Vp-p. (2) The A/D converter oversamples the receive signal and outputs data words at twice the symbol rate; the A/D converter conversion rate is called the Output Word Rate (OWR). (3) The digital low-pass filter that is part of the A/D converter can be programmed by the user for a 3dB frequency of 1/2 of the OWR or 1/4 of the OWR. (4) The internal line driver is designed for G.SHDSL. (5) An external driver (OPA2677) should be used for HDSL2 application. (6) The cutoff frequencies are user programmable. (7) Uncancelled echo is the sum of all noise and distortion errors for both the transmit and receive channels. (8) For a random sequence of the symbol, using an internal driver providing 14.5dBm power to the line for G.SHDSL. (9) For a random sequence while driving an external line driver (OPA2677) for HDSL2. (10) Functionality only guaranteed over temperature range.

FIGURE 1. Functional Block Diagram of the AFE1230. interface for processing by the DSP. lation filter and a programmable SC low-pass filter (SCLPF). The interpolation filter is an anti-imaging low-pass filter.

APPLICATION INFORMATION

The AFE1230 consists of a transmitter and receiver section, as shown in Figure 1; the transmitter section consists of a digital interpolation filter, a 16-bit, delta-sigma D/A converter, a programmable fifth-order or seventh-order SC low-pass filter, and a differential output line driver. The receiver section includes a digitally programmable gain amplifier, a 16-bit, delta-sigma A/D converter, and a decimation filter. The AFE1230 receives a 16-bit word plus an 8-bit control byte via the serial interface to facilitate the D/A conversion and control functions. The received 16-bit word is up sampled by two through the digital interpolation filter, then oversampled by the delta-sigma modulator by a factor of 12x where it is then processed by the multilevel D/A converter section before being filtered by the fifth-order or seventh-order Butterworth low- pass SC filter section. The subsequent analog signal is sent to the on-chip line driver where the analog signal can be driven into an appropriate transformer to provide up to 14.5dBm power into a 135Ω line for G.SHDSL. In addition, the on-chip line driver can be used as an output buffer to generate 17dBm into a 135Ω line via an external line driver (such as the OPA2677) for HDSL2. With an appropriate DSP, the transmitted PSD complies with either the G.SHDSL standard or, with an OPA2677 used as an external driver, the HDSL2 standard. In the receive path, the input amplifier sums the signals from the line and hybrid paths to perform first-order analog echo cancel- lation. The resultant signal is then digitized by a fourth-order cascaded delta-sigma A/D c onverter with an OSR (OverSampling Ratio) of 24x. The subsequent oversampledTABLE I. tx Filter Cutoff Frequency Setting. tx CUTOFF (txData Bits 29, 28) RATIO (Corner Frequency) 00 0.25 MCLK/24 01 0.38 MCLK/24 10 0.5 MCLK/24 ∆Σ 16-Bit A/D Converter PGA Input Amplifier Patents PendingAFE1230 Driver/ Buffer txLINE txLINE hybINPUT hybINPUT rxINPUT rxINPUT OPA2677 tx and rx Digital Interface Registers Programmable Digital LPF Digital Interpolation LPF Programmable SC LPF ∆Σ 16-Bit D/A Converter MCLK txBaud txData rxBaud rxData VrRef External Driver for HDSL2

FIGURE 4. Internal Receive Amplifier. latched internally to the AFE at the rising edge of MCLK. proper timings required to operate the AFE1230. (37.12MHz for E1). MCLK must use a 50/50 duty cycle. the txBaud should not be smaller than one MCLK period. falling edge of txBaud can occur at any time of the tF period. remain stable at least 2.5ns after the rising edge of MCLK. rxBaud: The receive data baud clock, generated by the DSP. rxBaud is 517.33kHz for T1 and 773.33kHz for E1 (2.3Mbps). should be no shorter than one period of MCLK. stable at least 2.5ns after the rising edge of MCLK.

TABLE IV. tx Data Structure. TABLE V. tx Data Format. BIT DESCRIPTION BIT STATE OUTPUT STATE 47-32 tx D/A Converter Word 1 XXXX 16-Bit Binary Two's Complement Word to tx D/A Converter (MSB First)

31 Power Control 0 Normal Power, Any Speed

1 Low Power, Low Speed (< 1/2 Full Word Rate)

30 Reserved (1) 0 Reserved for Future Use

29-28 tx Cutoff Frequency Control 00 0.25x Word Rate 01 0.38x Word Rate 10 0.5x Word Rate

11 Not Used

27 tx Filter Order 0 Fifth-Order Butterworth

1 Seventh-Order Butterworth

26-25 tx Power Backoff 00 Normal Transient Power

01 Normal Transient Power –6dB

10 Normal Transient Power –12dB

11 Normal Transient Power –18dB

24 rx Cutoff Frequency Control 0 0.25x Word Rate 1 0.5x Word Rate 23-8 tx D/A Converter Word 2 XXXX 16-Bit Binary Two's Complement Word to tx D/A Converter (MSB First) 7-6 Reserved (1) 00 Reserved for Future Use 5-3 rx Gain Settings 000 rx Gain = 0dB 001 rx Gain = 3dB 010 rx Gain = 6dB 011 rx Gain = 9dB 100 rx Gain = 12dB 101 rx Gain = 15dB 110 rx Gain = 18dB 111 rx Gain = 21dB 2-1 Loop-Back Control 00 Normal Operation

01 Loop-Back Mode Digital, tx Data to rx Data

10 Hybrid Mode, Line Input Connected to V

11 Line Mode, Hybrid Input Connected to V CM

0 Reserved (1) 0 Reserved

NOTE: (1) Reserved Bits must be set to 0. MSB 112 1 1 2 tx Power Backoff rx Cutoff Frequency tx Filter Order tx Cutoff Frequency Spare Loopback Spare rx Gain Spare tx DAC Word 2 Low Power tx DAC Word 1 16 2 3 2 1

The digital input and output data is coded in Binary Two’s complement with 16 bits; the scale is shown in Table VIII. or txBaud symbol clocks move one MCLK period forward or backward, resulting in 49 or 47 MCLK cycles per rxBaud), the receive data will be invalid for six symbol periods while the data settles to the final value. Loop Back The AFE1230 includes digital and analog loop-back options, as shown in Table IX. Echo Cancellation in the AFE1230 The rxHYB input is designed to be subtracted from the rxLINE input for first-order echo cancellation. To accom- plish this, note that the rxLINE input is connected to the same polarity signal at the transformer (+ to + and – to –), while the rxHYB input is connected to opposite polarity through the compromise hybrid (– to + and + to –). TABLE VI. rx Data Structure. TABLE VII. rx Data Format. BIT DESCRIPTION BIT STATE OUTPUT STATE 47-32 rx A/D Converter Word 1 XXXX 16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First) 31-24 Reserved Set All Bits Always to 0 Reserved for Future Use 23-8 rx A/D Converter Word 2 XXXX 16-Bit Binary Two's Complement Word from rx A/D Converter (MSB First) 7-0 Reserved Set All Bits Always to 0 Reserved for Future Use TABLE VIII. Digital Input/Output Data Scale. ANALOG INPUT A/D CONVERTER DATA MSB LSB Positive Full Scale 0111111111111111 Mid Scale 0000000000000000 Negative Full Scale 1000000000000000 TABLE IX. Loopback Table. LOOPBACK OPERATION Loopback = 00 Normal Operation Loopback = 01 Digital Loopback: Data In is Shortened to Data Out. Loopback = 10 Analog Loopback: The rxLINE inputs are shortened to V CM , while the transmit and rxHYB inputs are connected normally. Loopback = 11 Analog Loopback: The rxHYB inputs are shortened to V CM , while the transmit and rxLINE inputs are connected normally. MSB rx Data Word 2 Spare Spare rx Data Word 1 816 Sampling Phase The DSP will determine the sampling phase used for the AFE1230. In the case of a phase jump (i.e.: when the rxBaud

neath the AFE1230 by a small trace. FIGURE 10. AFE1230 Line Interface with OPA2677 for HDSL2. filter with 1MHz cutoff frequency on the front end of the receiver, as well as oversampling by the A/D converter.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) AFE1230E ACTIVE SSOP DB 28 48 None CU SNPB Level-3-220C-168 HR AFE1230E/1K ACTIVE SSOP DB 28 1000 None CU SNPB Level-3-220C-168 HR AFE1230E/1KG4 ACTIVE SSOP DB 28 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 10-Mar-2005 Addendum-Page 1

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