AFE1224

AFE1224 BURR-BROWN | Alldatasheet

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Technical content

2Mbps, Single Pair ANALOG FRONT END

FEATURES

l PROGRAMMABLE POWER DISSIPATION l 28-LEAD SSOP l 64kbps TO 2320kbps OPERATION

DESCRIPTION

Burr-Brown’s Analog Front End minimizes the size and cost of a single pair High bit rate Digital Sub- scriber Line (HDSL) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and an HDSL line transformer. The transmit and receive filter responses automatically change with clock frequency, allowing the AFE1224 to operate over a wide range of data rates. The power dissipation of the device can be reduced under digital control for operation at lower speeds. The AFE1224 will operate at bit rates from 64kbps to 2.320Mbps. © 1999 Burr-Brown Corporation PDS-1548A Printed in U.S.A. June, 1999 For most current data sheet and other product information, visit www.burr-brown.com International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 l SCALEABLE DATA RATE l PIN COMPATIBLE WITH AFE1124 l COMPLETE ANALOG INTERFACE l –40°C TO +85°C OPERATION Functionally, this unit consists of a transmit and a receive section. The transmit section generates analog signals from 2-bit digital symbol data and filters the analog signals to create 2B1Q symbols. The on-board differential line driver provides a 13.5dBm signal to the telephone line. The receive section filters and digitizes the symbol data received on the telephone line. The AFE1224 operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. The chip uses only 355mW for full-speed operation. It is housed in a 28-lead SSOP package. DS Modulator Pulse Former PGA Difference Amplifier Patents PendingAFE1224 Line Driver txLINE txLINE rxHYB rxHYB rxLINE rxLINE tx and rx Control Registers tx and rx Interface Lines Decimation Filter AFE1224

All specifications at 25°C, AVDD = +5V, DVDD = +3.3V, fTX = 1168kHz (E1 rate) and normal power mode, unless otherwise noted. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. AFE1224E PARAMETER COMMENTS MIN TYP MAX UNITS RECEIVE CHANNEL Number of Inputs Differential 2 Input Voltage Range Balanced Differential (1) –3.0 V Common-Mode Voltage AV DD /2 V Input Impedance, All Inputs 78kbps 32 k W 1168kbps 21 k W 2320kbps 10 k W Input Capacitance 10 pF Input Gain Matching Line Input vs Hybrid Input –2% Resolution 14 Bits Programmable Gain 0dB, 3dB, 6dB, 9dB and 12dB 0 +12 dB Settling Time for Gain Change 6 Symbol Periods Gain + Offset Error Tested at Each Gain Range 5 %FSR (2) Output Data Coding Binary Two’s Complement Data Rate Normal Power 64 2320 kbps Medium Power 64 1168 kbps Low Power 64 320 kbps Output Word Rate Normal Power (3) 32 1168 kHz TRANSMIT CHANNEL Transmit Clock Rate, fTX Symbol Rate, Normal Power 196 1168 kHz Symbol Rate, Medium Power 96 584 kHz Symbol Rate, Low Power 80 160 kHz Transmit –3dB Point 2320kbps 485 kHz 1168kbps 292 kHz 784kbps 196 kHz Transmit Power(5) 13 13.5 14 dBm Pulse Output See Typical Performance Curves Common-Mode Voltage (VCM ) AV DD /2 V Output Resistance DC to 1MHz 1 W TRANSCEIVER PERFORMANCE Uncancelled Echo(5) rxGAIN = 0dB, Loopback Enabled –71 –68.5 dB rxGAIN = 0dB, Loopback Disabled –71 –68.5 dB rxGAIN = 3dB, Loopback Disabled –74 –71 dB rxGAIN = 6dB, Loopback Disabled –76 –73.5 dB rxGAIN = 9dB, Loopback Disabled –78 –75.5 dB rxGAIN = 12dB, Loopback Disabled –80 –77.5 dB DIGITAL INTERFACE Logic Levels VIH |IIH| < 10mAD V DD –1 DV DD +0.3 V VIL |IIL| < 10mA –0.3 +0.8 V VOH IOH = –20mAD V DD –0.5 V VOL IOL = 20mA +0.4 V trx1 Interface 3 4.6 ns POWER Analog Power Supply Voltage Specification 5 V Operating Range 4.75 5.25 V Digital Power Supply Voltage Specification 3.3 V Operating Range 3.15 5.25 V Power Dissipation(4, 5) Normal Power 385 mW Medium Power 300 mW Low Power 240 mW Power Dissipation(4, 5) Normal Power, DVDD = 5V 415 mW Power Supply Rejection Ratio 55 dB TEMPERATURE RANGE Operating(6) –40 +85 °C NOTES: (1) With a balanced differential signal, the positive input is 180° out-of-phase with the negative input, therefore the actual voltage swing about the common- mode voltage on each pin is –1.5V to achieve a total input range of –3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINE+ and txLINE–). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Functionality only guaranteed over temperature range.

–10mA, Continuous ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER (1) RANGE MARKING NUMBER (2) MEDIA AFE1224E SSOP-28 324 –40 °C to +85°C AFE1224E AFE1224E Rails "" " " " AFE1224E/1K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “AFE1224E/1K” will get a single 1000- piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION Top View SSOP-28 PIN # TYPE NAME DESCRIPTION 1 — NC No Connection 2 — NC No Connection 3 Power DV DD Digital Supply (+3.3 to +5V)

4 Ground DGND Digital Ground

5 Input txbaudCLK Transmit Baud Clock

6 Input tx48xCLK Transmit Clock at 48x Baud Clock

7 Input Data In Input Data Word

8 Input rxbaudCLK Receive Baud Clock

9 Input rx48xCLK Receive Clock at 48x Baud Clock

10 Output Data Out Output Data Word

11 Power DV

DD Digital Supply (+3.3V to +5V)

12 Ground DGND Digital Ground

13 Power AV

DD Analog Supply (+5V)

14 Input rxHYB– Negative Input from Hybrid Network

15 Input rxHYB+ Positive Input from Hybrid Network

16 Input rxLINE– Negative Line Input

17 Input rxLINE+ Positive Line Input

18 Ground AGND Analog Ground

19 Output vrREF+ Positive Reference Output

20 Output V

CM Common-Mode Voltage (buffered)

21 Output vrREF– Negative Reference Output

22 Power AV DD Analog Supply (+5V)

23 Ground AGND Analog Ground

24 Output txLINE– Negative Line Output

25 Power AV

DD Output Buffer Supply (+5V)

26 Output txLINE+ Positive Line Output

27 Ground AGND Output Buffer Ground

28 — NC No Connection PIN DESCRIPTIONS NC NC DV DD DGND txbaudCLK tx48xCLK Data In rxbaudCLK rx48xCLK Data Out DV DD DGND AV DD rxHYB– NC AGND txLINE+ AV DD txLINE– AGND AV DD vrREF– V CM vrREF+ AGND rxLINE+ rxLINE– rxHYB+ AFE1224

txLINE– txLINE+ REF+ VCM REF– rxLINE+ rxLINE– rxHYB+ rxHYB–

TYPICAL PERFORMANCE CURVES At Output of HDSL Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD + = +5V, DVDD + = +3.3V, and fTX = 1168kHz, unless otherwise specified. CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. CURVE 3. Input Impedance of rxLINE and rxHYB. CURVE 2. Transmitted Pulse Template Measured at HDSL Transformer Output. 0.4T 0.4T –0.6T –1.2T 14T 50T 0.5T 1.25T –20 –40 –60 –80 –100 –120 –140 10k 100k 100M AVERAGE POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) Frequency (Hz) 1M 10M E1-SP –80dB/decade E1-SP 200 100 600 1000 INPUT IMPEDANCE vs BIT RATE Input Impedance (kW ) Bit Rate (kbps) 1400 1800 2600 2200 Two Pair T1 = 784kbps, 32kW Two Pair E1 = 1168kbps, 21kW Single Pair E1 = 2320kbps, 10kW E1, Single Pair

rxLINE+ and rxLINE– inputs are connected. and the maximum speed of the AFE1224.

1 AFE transmits HDSL Symbol

9 Loopback Control 1 Go to loopback mode

0 Normal Operation

8 Not Used N/A

01 Medium Speed, power

10 Normal Speed, power

11 Normal Speed, power

(bits 15-2). The spare bits (1 and 0) will be always be LOW. FIGURE 5. Data Out Word. frequencies just by changing the clock speed. passive anti-alias filter should be used. TABLE II. Data Output Format.

more output filtering may be needed. be used for a single line bit rate of 320k bits per second. FIGURE 6. Basic Connection Diagram.

A key measure of transceiver performance is uncancelled echo. Uncancelled echo is the summation of all of the errors in the transmit and receive paths of the AFE1224. It includes effects of linearity, distortion and noise. Uncancelled echo is tested in production by Burr-Brown with a circuit that is similar to the one shown in Figure 7, Uncancelled Echo Test Diagram. The measurement of uncancelled echo is made as follows: The AFE is connected to an output circuit including a typical 1:2 line transformer. The line is simulated by a 135W resistor. Symbol sequences are generated by the tester and applied both to the AFE and to the input of an adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the uncancelled echo signal. Once the filter taps have converged, the rms value of the uncancelled echo is calculated. Since there is no far-end signal source or additive line noise, the uncancelled echo contains only noise and linearity errors generated in the transmit and receive sections of the AFE1224. The data sheet value for uncancelled echo is the ratio of the rms uncancelled echo (referred to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135W , or 1.74Vrms). This echo value is measured under a variety of conditions: with loopback enabled (line input disconnected); with loopback disabled under all receiver gain ranges; and with the line shorted (S closed, see Figure 7). POWER DISSIPATION The power dissipation of the AFE1224 is digitally program- mable by the user to three levels: normal, medium and low. The maximum bit rate of the AFE1205 is 2.3Mbps with normal power dissipation. At lower power dissipation lev- els, the maximum bit rate is lower. The power dissipation listed in the Specifications Table applies under these normal operating conditions: 5V analog power supply, 3.3V digital power supply, standard 13.5dBm delivered to the line, and a pseudo-random equiprobable sequence of HDSL output pulses. The power dissipation specifications includes all power dissipated in the AFE1224, but it does not include power dissipated in the external load. MAXIMUM MINIMUM TYPICAL POWER POWER LEVEL SPEED SPEED DISSIPATION Normal 2.3Mbps 64kbps 385mW Medium 1.168Mbps 64kbps 300mW Low 320kbps 64kbps 240mW TABLE III. Typical Power Dissipation. The external power is 16.5dBm: 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissi- pation in the AFE1224 under various conditions is shown in Table III. LAYOUT The analog front end of an HDSL system has two conflicting requirements. It must accept and deliver moderately high rate digital signals and it must generate, drive, and convert precision analog signals. To achieve optimal system perfor- mance with the AFE1224, both the digital and the analog sections must be treated carefully in board layout design. The power supply for the digital section of the AFE1224 can range from 3.3V to 5V. This supply should be decoupled to digital ground with ceramic 0.1mF capacitors placed as close to DGND and DV DD as possible. One capacitor should be placed between pins 3 and 4 and the second capacitor between pins 11 and 12. Ideally, both a digital power supply plane and a digital ground plane should run up to and underneath the digital pins of the AFE1224 (pins 5 through 10). However, DV DD may be supplied by a wide printed circuit board (PCB) trace. A digital ground plane underneath all digital pins is strongly recommended. The remaining portion of the AFE1224 should be considered analog. All AGND pins should be connected directly to a common analog ground plane and all AV DD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. The analog power supply pins should be decoupled to analog ground with ceramic 0.1mF capacitors placed as close to the AFE1224 as possible. One 10mF tantalum capacitor should also be used with each AFE1224 between the analog supply and analog ground. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1224 by a small trace.

FIGURE 7. Uncancelled Echo Test Diagram.