AFE1203

AFE1203 BURR-BROWN | Alldatasheet

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© 1998 Burr-Brown Corporation PDS-1460A Printed in U.S.A. October, 1998 2Mbps, Single Pair HDSL ANALOG FRONT END

FEATURES

l E1/T1 SINGLE PAIR 2B1Q OPERATION l COMPLETE ANALOG INTERFACE l 385mW POWER DISSIPATION l PROGRAMMABLE POWER AFE1203 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

DESCRIPTION

Burr-Brown’s Analog Front End greatly reduces the size and cost of a single pair HDSL (High bit rate Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and an HDSL line transformer. The transmit and receive filter responses automatically change with clock frequency, allowing the AFE1203 to operate over a wide range of data rates. The power dissipation of the device can be reduced under digital control for operation at lower speeds. The AFE1203 will operate at bit rates from 160kbps to 2.3Mbps. It meets ETSI PSD specifications for single pair E1, as well as ETSI and ANSI PSD specifications for two pair E1 and T1. Functionally, this unit consists of a transmit and a receive section. The transmit section generates, filters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line. This IC operates l 48-LEAD SSOP PACKAGE l SCALEABLE DATA RATE l OPERATION FROM 2.3Mbps TO 160kbps l +5V ONLY (5V OR 3.3V DIGITAL) l –40°C TO +85°C OPERATION on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. The chip uses only 385mW for full-speed operation. It is housed in a small 48-lead SSOP package. The receive channel is designed around a fourth-order delta- sigma analog-to-digital converter. It includes a difference am- plifier designed to be used with an external compromise hybrid for first-order analog echo cancellation. A programmable gain amplifier with gains 0dB to +9dB is also included. The delta- sigma modulator, operating at a 24X oversampling ratio, pro- duces a 14-bit output at symbol rates up to 1168kHz (for 2.3Mbps operation). The transmit channel consists of a digital-to-analog converter and switched-capacitor pulse forming network followed by a differ- ential line driver. The pulse forming network receives symbol data and generates a standard 2B1Q output waveform. The differential line driver uses a composite output stage combining class B operation (for high efficiency driving large signals) with class AB operation (to minimize crossover distortion). Pulse Former PLLOUT PLLIN txDAT txCLK rxSYNC rxLOOP rxGAIN rxD13 - rxD0 Line Driver Voltage Reference Delta-Sigma Modulator Transmit Control Receive Control Decimation Filter txLINEN txLINEP REF P VCM REF N rxLINEP rxLINEN rxHYBP rxHYBN Patents Pending D/A Converter AFE1203

Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 1168kHz (E1 single pair rate) and Normal Power mode, unless otherwise specified. AFE1203E PARAMETER COMMENTS MIN TYP MAX UNITS RECEIVE CHANNEL Number of Inputs Differential 2 Input Voltage Range Balanced Differential (1) ±3.0 V Common-Mode Voltage 1.5V CMV Recommended +1.5 V Input Impedance All Inputs See Typical Performance Curves Input Capacitance 10 pF Input Gain Matching Line Input vs Hybrid Input ±2% Resolution 14 Bits Programmable Gain Four Gains: 0dB, 3.25dB, 6dB, and 9dB Settling Time Gain, rxSYNC, or Power Mode Change (8) 6 Symbol Periods Gain + Offset Error Tested at Each Gain Range 5 %FSR (2) Output Data Coding Binary Two’s Complement Data Rate Normal Power 384 2320 kbps Medium Power 192 1168 kbps Low Power 160 320 kbps Output Word Rate Normal Power, rxSYNC (3) 196 1168 kHz TRANSMIT CHANNEL Transmit Clock Rate, fTX Symbol Rate, Normal Power 196 1168 kHz Symbol Rate, Medium Power 96 584 kHz Symbol Rate, Low Power 80 160 kHz Transmit –3dB Point 2320kbps 485 kHz 1168kbps 292 kHz 784kbps 196 kHz Transmit Power(4) 13 13.5 14 dBm Pulse Output See Typical Performance Curves Common-Mode Voltage, VCM AV DD /2 V Output Resistance(5) DC to 1MHz 1 Ω TRANSCEIVER PERFORMANCE Uncancelled Echo(6) rxGAIN = 0dB, Loopback Enabled –67 dB rxGAIN = 0dB, Loopback Disabled –67 dB rxGAIN = 3.25dB, Loopback Disabled –69 dB rxGAIN = 6dB, Loopback Disabled –71 dB rxGAIN = 9dB, Loopback Disabled –73 dB DIGITAL INTERFACE (5) Logic Levels VIH |IIH| < 10µAD V DD – 1 DV DD + 0.3 V VIL |IIL| < 10µA –0.3 +0.8 V VOH IOH = –20µAD V DD – 0.5 V VOL IOL = 20µA +0.4 V POWER Analog Power Supply Voltage Specification 5 V Operating Range 4.75 5.25 V Digital Power Supply Voltage Specification 3.3 V Operating Range 3.15 5.25 V Power Dissipation(4, 7) Normal Power 385 mW Medium Power 300 mW Low Power 240 mW Power Dissipation(7) Normal Power, DVDD = 5V 415 mW PSRR 55 dB TEMPERATURE RANGE Operating(5) –40 +85 °C NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common mode voltage on each pin is ±1.5V to achieve a differential input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from txLINEP and txLINEN ). (5) Guaranteed by design and characterization. (6) Uncancelled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications section of this data sheet for more information. (7) Power dissipation includes only the power dissipated within the component and does not include power dissipated in the external loads. The AFE1203 is tested with a 1:2 line transformer. (8) This is the settling time required for any gain change, change of rxSYNC or any change of power mode.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PIN DESCRIPTIONS PIN # TYPE NAME DESCRIPTION

1 Ground AGND Analog Ground for PLL

2 Power AV DD Analog Supply (+5V) for PLL

3 Input txCLK Symbol Clock

4 Input txDAT

5 Input txDAT P XMIT Line

6 Output rxD0 ADC Output Bit-0

7 Output rxD1 ADC Output Bit-1

8 Output rxD2 ADC Output Bit-2

9 Output rxD3 ADC Output Bit-3

10 Output rxD4 ADC Output Bit-4

11 Output rxD5 ADC Output Bit-5

12 Ground DGND Digital Ground

13 Power DV

DD Digital Supply (+3.3V to +5V)

14 Output rxD6 ADC Output Bit-6

15 Output rxD7 ADC Output Bit-7

16 Output rxD8 ADC Output Bit-8

17 Output rxD9 ADC Output Bit-9

18 Output rxD10 ADC Output Bit-10

19 Output rxD11 ADC Output Bit-11

20 Output rxD12 ADC Output Bit-12

21 Output rxD13 ADC Output Bit-13

22 Input PWSEL Power Control

23 Input rxSYNC ADC Sync Signal

24 Input rxGAIN0 Receive Gain Control Bit-0

25 Input rxGAIN1 Receive Gain Control Bit-1

26 Input rxLOOP Loopback Control Signal (loopback is enabled by positive signal)

27 Power AV

DD Analog Supply (+5V)

28 Input rxHYB N Negative Input from Hybrid Network

29 Input rxHYB P Positive Input from Hybrid Network

30 Input rxLINE N Negative Line Input

31 Input rxLINE P Positive Line Input

32 Ground AGND Analog Ground

33 Ground AGND Analog Ground

34 Output REF

P Positive Reference Output, Nominally 3.5V 35 Output V CM Common-Mode Voltage (buffered), Nominally 2.5V 36 Output REF N Negative Reference Output, Nominally 1.5V

37 Power AV DD Analog Supply (+5V)

38 Ground AGND Analog Ground

39 Output txLINE

N Transmit Line Output Negative

40 Power AV DD Analog Supply (+5V)

41 Output txLINE P Transmit Line Output Positive

42 Ground AGND Analog Ground

43 NC NC Connection to Ground Recommended

44 NC NC Connection to Ground Recommended

45 NC NC Connection to Ground Recommended

46 NC NC Connection to Ground Recommended

47 Output PLL

48 Input PLL IN PLL Filter Input

±10mA, Continuous Junction Temperature (T ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER (1) RANGE AFE1203E 48-Lead SSOP 333 –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION AGND AV DD txCLK txDATN txDATP rxD0 rxD1 rxD2 rxD3 rxD4 rxD5 DGND DV DD rxD6 rxD7 rxD8 rxD9 rxD10 rxD11 rxD12 rxD13 PWSEL rxSYNC rxGAIN0 PLL IN PLLOUT NC NC NC NC AGND txLINE P AV DD txLINEN AGND AV DD REF N VCM REF P AGND AGND rxLINE P rxLINEN rxHYBP rxHYBN AV DD rxLOOP rxGAIN1 AFE1203E

TYPICAL PERFORMANCE CURVES At Output of Pulse Transformer Typical at 25°C, AVDD = +5V, and DVDD = +3.3V, unless otherwise specified. CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output. CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output. CURVE 3. Input Impedance of rxLINE and rxHYB. LOWER BREAK UPPER SPEED LIMIT FREQUENCY SLOPE LIMIT T1, Two Pair –38dBm/Hz 196kHz –80dB/decade –118dBm/Hz E1, Two Pair –40dBm/Hz 292kHz –80dB/decade –120dBm/Hz E1, Single Pair (E1-SP) –42.5dBm/Hz 485kHz –80dB/decade –122dBm/Hz TWO PAIR T1 AND E1 SINGLE PAIR E1 NORMALIZED NORMALIZED LIMITS LEVELS QUATENARY SYMBOLS (V) LEVELS QUATENARY SYMBOLS (V) 0.4T 0.4T –0.6T –1.2T 14T 50T 0.5T 1.25T 200 100 600 1000 INPUT IMPEDANCE vs BIT RATE Input Impedance (kΩ ) Bit Rate (kbps) 1400 1800 2600 2200 Two Pair T1 = 784kbps, 45kΩ Two Pair E1 = 1168kbps, 30kΩ Single Pair E1 = 2320kbps, 15kΩ E1, Single Pair –20 –40 –60 –80 –100 –120 –140 10k 100k 100M AVERAGE POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) Frequency (Hz) 1M 10M E1-SP –80dB/decade E1-SP

single pair bit rate of 500kbps. inputs are centered at midscale, 2.5V. FIGURE 2. Basic Connection Diagram.

FIGURE 3. Timing Diagram. filter downsamples the modulator output by a factor of 12. more flexible post-processing. txCLK. (3) Maximum allowable error for any txDAT edge is –ttx1/12 (–72ns for single pair E1 rate). (4) txDATN is the inverse of txDATP.

The analog front end of an HDSL system has a number of conflicting requirements. It must accept and deliver digital outputs at fairly high rates of speed, phase-lock to a high- speed digital clock, and convert the line input to a high- precision (14-bit) digital output. Thus, there are really three sections of the AFE1203: the digital section, the phase- locked loop, and the analog section. A combined analog and digital ground plane is recommended. The ground plane should pass under all of the AFE1203 and its pins. The power supply for the digital section of the AFE1203 can range from 3.3V to 5V. This supply should be decoupled to ground with a ceramic 0.1µF capacitor placed as close to DGND (pin 12) and DV DD (pin 13) as possible. Ideally, both a digital power supply plane and a ground plane should run up to and underneath the digital pins of the AFE1203 (pins 3 through 26). However, DV DD may be supplied by a wide printed circuit board (PCB) trace. A ground plane under- neath all digital pins is strongly recommended. The Phase Locked Loop (PLL) analog supply, pin 2, must be derived from AV DD , the general analog supply. The power supply to the PLL must be in the range of 4.75V to 5.25V. The PLL section of the AFE1203 should be decoupled with both a 10µF tantalum capacitor and a 0.1µF ceramic capaci- tor. Both capacitors should be placed between pins 1 and 2. The ceramic capacitor should be placed as close to the AFE1203 as possible. The placement of the tantalum capaci- tor is not as critical, but should be close. A 5Ω to 10Ω resistor should be used to connect the PLL supply (pin 2) to the analog supply. This resistor, in combination with the 10µF tantalum capacitor, form a low pass filter to keep glitches that occur on the general analog supply, AV DD , from affecting the PLL supply. The PLL ground (pin 1) should connect directly to the ground plane. The ground plane should also extend underneath PLL OUT and PLL IN (pins 47 and 48, respectively). The remaining portion of the AFE1203 should be considered analog. All AGND pins should be connected directly to the common ground plane and all AV DD pins should be con- nected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power trace pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm).