AFE1124

AFE1124 BURR-BROWN | Alldatasheet

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© 1997 Burr-Brown Corporation PDS-1425A Printed in U.S.A. October, 1997 HDSL/MDSL ANALOG FRONT END International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 l 64kbps TO 1168kbps OPERATION l SCALEABLE DATA RATE l 250mW POWER DISSIPATION l COMPLETE HDSL ANALOG INTERFACE l +5V POWER (5V or 3.3V Digital)

FEATURES

l SERIAL DIGITAL INTERFACE l 28-PIN SSOP l E1, T1 AND MDSL OPERATION Functionally, this unit consists of a transmit and a receive section. The transmit section generates analog signals from 2-bit digital symbol data and filters the analog signals to create 2B1Q symbols. The on board differential line driver provides a 13.5dBm signal to the telephone line. The receive section filters and digitizes the symbol data received on the telephone line. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. It is housed in a 28-pin SSOP package.

DESCRIPTION

Burr-Brown’s Analog Front End chip greatly reduces the size and cost of an xDSL (Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect a digital signal processor to an external compromise hybrid and line transformer. The AFE1124 is optimized for HDSL (High bit rate DSL) and for lower speed MDSL (Medium speed DSL) and RADSL (Rate Adaptive DSL) applications. Because the transmit and receive filter responses automatically change with clock frequency, the AFE1124 is particu- larly suitable for RADSL and multiple rate DSL sys- tems. The device operates over a wide range of data rates from 64kbps to 1168kbps. ΔΣ Modulator Pulse Former Programmable Gain Amp Difference Amplifier Patents PendingAFE1124 Line Driver txLINE txLINE rxHYB rxHYB rxLINE rxLINE tx and rx Control Registers tx and rx Interface Lines Decimation Filter

Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 584kHz (E1 rate), unless otherwise noted. AFE1124E PARAMETER COMMENTS MIN TYP MAX UNITS RECEIVE CHANNEL Number of Inputs Differential 2 Input Voltage Range Balanced Differential (1) ±3.0 V Common-Mode Voltage AV DD /2 V Input Impedance All Inputs See Typical Performance Curves Input Capacitance 10 pF Input Gain Matching Line Input vs Hybrid Input ±2% Resolution 14 Bits Programmable Gain 0dB, 3dB, 6dB, 9dB and 12dB 0 +12 dB Settling Time for Gain Change 6 Symbol Periods Gain + Offset Error Tested at Each Gain Range 5 %FSR (2) Output Data Coding Two’s Complement Output Symbol Rate, rxSYNC(3) 32 584 kHz Output Bit Rate, rxSYNC(3) 64 1168 kbits/sec TRANSMIT CHANNEL Transmit Clock Rate, ftx Symbol Rate 32 584 kHz T1 Transmit –3dB Point ETSI RTR/TM – Compliant 196 kHz T1 Rate Power (4, 5) See Test Method Section, txBoost = 0 13 14 dBm E1 Transmit –3dB Point ETSI RTR/TM – Compliant 292 kHz E1 Transmit Power(4, 5) See Test Method Section, txBoost = 0 13 14 dBm Pulse Output See Typical Performance Curves Common-Mode Voltage, VCM AV DD /2 V Output Resistance(6) DC to 1MHz 1 Ω TRANSCEIVER PERFORMANCE Uncancelled Echo(5) rxGAIN = 0dB, Loopback Enabled –71 –68.5 dB rxGAIN = 0dB, Loopback Disabled –71 –68.5 dB rxGAIN = 3dB, Loopback Disabled –74 –71 dB rxGAIN = 6dB, Loopback Disabled –76 –73.5 dB rxGAIN = 9dB, Loopback Disabled –78 –75.5 dB rxGAIN = 12dB, Loopback Disabled –80 –77.5 dB DIGITAL INTERFACE (6) Logic Levels VIH |IIH| < 10µAD V DD –1 DV DD +0.3 V VIL |IIL| < 10µA –0.3 +0.8 V VOH IOH = –20µAD V DD –0.5 V VOL IOL = 20µA +0.4 V trx1 Interface 91 4 n s POWER Analog Power Supply Voltage Specification 5 V Analog Power Supply Voltage Operating Range 4.75 5.25 V Digital Power Supply Voltage Specification 3.3 V Digital Power Supply Voltage Operating Range 3.15 5.25 V Power Dissipation (4, 5) AV DD = 5V, DVDD = 3.3V, 250 mW Power Dissipation(4, 5) AV DD = DVDD = 5V 300 mW PSRR 55 dB TEMPERATURE RANGE Operating(6) –40 +85 °C NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common- mode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP and txLINEN). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization.

PRODUCT PACKAGE NUMBER (1) RANGE AFE1124E 28-Pin SSOP 324 –40 to +85 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. NC NC DV DD DGND txbaudCLK tx48xCLK Data In rxbaudCLK rx48xCLK Data Out DV DD DGND AV DD rxHYB– NC AGND txLINE+ AV DD txLIKNE– AGND AV DD vrREFN VCM vrREFP AGND rxLINE+ rxLINE– rxHYB+ AFE1124 ±10mA, Continuous ABSOLUTE MAXIMUM RATINGS ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PIN # TYPE NAME DESCRIPTION

1 No Connection NC

2 No Connection NC

3 Power DV

DD Digital Supply (+3.3 to +5V)

4 Ground DGND Digital Ground

5 Input txbaudCLK Transmit Baud Clock (584kHz for E1)

6 Input tx48xCLK Transmit Clock at 48x baud clock (28.032MHz for E1)

7 Input Data In Input Data Word

8 Input rxbaudCLK Receive baud clock (584kHz for E1)

9 Input rx48xCLK Receive clock at 48x baud clock (28.032MHz for E1)

10 Output Data Out Output Data Word

11 Power DV

DD Digital Supply (+3.3 to +5V)

12 Ground DGND Digital Ground

13 Power AV DD Analog Supply (+5V)

14 Input rxHYB– Negative input from hybrid network

15 Input rxHYB+ Positive input from hybrid network

16 Input rxLINE– Negative line input

17 Input rxLINE+ Positive line input

18 Ground AGND Analog Ground

19 Output vrREFP Positive reference output

20 Output VCM Common-mode voltage (buffered)

21 Output vrREFN Negative reference output

22 Power AVDD Analog Supply (+5V)

23 Ground AGND Analog Ground

24 Output txLINE– Negative line output

25 Power AV

DD Output buffer supply (+5V)

26 Output txLINE+ Positive line output

27 Ground AGND Output buffer ground

28 No Connection NC

ΔΣ Modulator Transmit Control Receive Control Decimation Filter txLINE– txLINE+ REF P VCM REF N rxLINE+ rxLINE– rxHYB+ rxHYB–

TYPICAL PERFORMANCE CURVES At Output of HDSL Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD + = +5V, DVDD + = +3.3V, fTX = 1168kHz, unless otherwise specified. CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. –20 –40 –60 –80 –100 –120 10K 100K POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) Frequency (Hz) 1M 10M –38dBm/Hz for T1 –40dBm/Hz for E1 196kHz 292kHz –80dB/decade –120dBm/Hz for E1 –118dBm/Hz for T1 CURVE 3. Input Impedance of rxLINE and rxHYB. 0.4T B = 1.07 C = 1.00 D = 0.93 0.4T –0.6T –1.2T A = 0.01 E = 0.03 G = –0.16 14T H = –0.05 50T F = –0.01 A = 0.01 F = –0.01 0.5T 1.25T CURVE 2. Transmitted Pulse Template Measured at HDSL Transformer Output. 100 200 150 100 300 500 INPUT IMPEDANCE vs BIT RATE Input Impedance (kΩ ) Bit Rate (kbps) 700 900 1300 1100 T1 = 784kbps, 32kΩ E1 = 1168kbps, 21kΩ

rxLINE+ and rxLINE– inputs are connected. power to the output line driver.

1 AFE Transmits HDSL Symbol

9 Loopback Control 1 Loopback Mode

0 Normal Operation

(bits 15-2). The spare bits (1 and 0) will be always be low. high. The data is clocked out on the falling edge of rx48xCLK. of the A/D converter is one conversion per symbol period. used for more flexible post-processing. FIGURE 5. Data Out Word. frequencies just by changing the clock speed. passive anti-alias filter should be used.

lower bit rates, the amount of smoothing will be less. rate of 320k bits per second. FIGURE 6. Basic Connection Diagram.

A key measure of transceiver performance is uncancelled echo. Uncancelled echo is the summation of all of the errors in the transmit and receive paths of the AFE1124. It includes effects of linearity, distortion and noise. Uncancelled echo is tested in production by Burr-Brown with a circuit that is similar to the one shown in Figure 7, Uncancelled Echo Test Diagram. The measurement of uncancelled echo is made as follows. The AFE is connected to an output circuit including a typical 1:2 line transformer. The line is simulated by a 135Ω resistor. Symbol sequences are generated by the tester and applied both to the AFE and to the input of an adaptive filter. The output of the adaptive filter is subtracted from the AFE output to form the uncanceled echo signal. Once the filter taps have converged, the RMS value of the uncancelled echo is calculated. Since there is no far-end signal source or additive line noise, the uncanceled echo contains only noise and linearity errors generated in the transmit and receive sections of the AFE1124. The data sheet value for uncancelled echo is the ratio of the RMS uncanceled echo (referred to the receiver input through the receiver gain) to the nominal transmitted signal (13.5dBm into 135Ω , or 1.74Vrms). This echo value is measured under a variety of conditions: with loopback enabled (line input disconnected); with loopback disabled under all receiver gain ranges; and with the line shorted (S1 closed in Figure 7). POWER DISSIPATION Approximately 80% of the power dissipation in the AFE1124 is in the analog circuitry, and this component does not change with clock frequency. However, the power dissipa- tion in the digital circuitry does decrease with lower clock frequency. In addition, the power dissipation in the digital section is decreased when operating from a smaller supply voltage, such as 3.3V. (The analog supply, AVDD , must remain in the range 4.75V to 5.25V). The power dissipation listed in the specifications section applies under these normal operating conditions: 5V Analog Power Supply; 3.3V Digital Power Supply; standard 13.5dBm delivered to the line; and a pseudo-random equiprobable sequence of HDSL output pulses. The power dissipation specifications includes all power dissipated in the AFE1124, it does not include power dissipated in the external load. The external power is 16.5dBm: 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissi- pation in the AFE1124 under various conditions is shown in Table II. The T1 and E1 power measurements in the Specifications are made with the output circuit shown in Figure 7. This TYPICAL POWER BIT RATE DISSIPATION PER AFE1124 DVDD IN THE AFE1124 (Symbols/sec) (V) (mW) 584 (E1) 3.3 250 584 (E1) 5 300 392 (T1) 3.3 240 392 (T1) 5 270 146 (E1/4) 3.3 230 146 (E1/4) 5 245 TABLE II. Typical Power Dissipation. circuit uses a 1:2 transformer. The power measurements shown in Table II use an equivalent resistive load instead of the transformer to eliminate frequency dependent imped- ances of the transformer. LAYOUT The analog front end of an HDSL system has two conflicting requirements. It must accept and deliver moderately high rate digital signals and it must generate, drive, and convert precision analog signals. To achieve optimal system perfor- mance with the AFE1124, both the digital and the analog sections must be treated carefully in board layout design. The power supply for the digital section of the AFE1124 can range from 3.3V to 5V. This supply should be decoupled to digital ground with ceramic 0.1µF capacitors placed as close to DGND and DV DD as possible. One capacitor should be placed between pins 3 and 4 and the second capacitor between pins 11 and 12. Ideally, both a digital power supply plane and a digital ground plane should run up to and underneath the digital pins of the AFE1124 (pins 5 through 10). However, DVDD may be supplied by a wide printed circuit board (PCB) trace. A digital ground plane underneath all digital pins is strongly recommended. The remaining portion of the AFE1124 should be considered analog. All AGND pins should be connected directly to a common analog ground plane and all AVDD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. The analog power supply pins should be decoupled to analog ground with ceramic 0.1µF capacitors placed as close to the AFE1124 as possible. One 10µF tantalum capacitor should also be used with each AFE1124 between the analog supply and analog ground. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1104 by a small trace.

FIGURE 7. Uncancelled Echo Test Diagram.