AFE1115

AFE1115 BURR-BROWN | Alldatasheet

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© 1997 Burr-Brown Corporation PDS-1384 Printed in U.S.A. July, 1997 HDSL/MDSL ANALOG FRONT END WITH VCXO

DESCRIPTION

Burr-Brown’s Analog Front End greatly reduces the size and cost of an HDSL (High bit rate Digital Subscriber Line) system by providing all of the active analog circuitry needed to connect an HDSL digital signal processor to an external compromise hybrid and a HDSL line transformer. The transmit and receive filter responses automatically change with clock fre- quency—allowing the AFE1115 to operate over a range of data rates from 196kbps to 1.168Mbps. Functionally, this unit consists of a transmit and a receive section with a VCXO (Voltage Controlled Crystal Oscillator) control DAC and VCXO circuitry. The transmit section generates, filters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line. Data to the VCXO and symbol data are sent to the AFE1115 via two serial interfaces; the receive data is available as a 14-bit parallel word. This IC operates on a single 5V supply. The digital circuitry in the unit can be connected to a supply from 3.3V to 5V. It is housed in a small 56-pin SSOP package. Pulse Former Filter PLLOUT PLLIN txDATA+ txSCLK txCLK rxSYNC rxLOOP rxGAIN rxDATA Output Buffer Voltage Reference Delta-Sigma Modulator Transmit Control Receive Control Decimation Filter vcDATA vcSCLK vcLE VCXO DAC txLINE– txLINE+ vcDAC REF P VCM REF N Oscillator VCXO Output VCXO Input VCXO Output Clock rxLINE+ rxLINE– rxHYB+ rxHYB– ®AFE1115 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 l +5V ONLY (5V or 3.3V Digital) l SCALEABLE DATA RATE l 300mW POWER DISSIPATION l 56-PIN SSOP

FEATURES

l COMPLETE HDSL ANALOG INTERFACE l E1, T1 AND MDSL OPERATION l VCXO AND VCXO CONTROL CIRCUITRY

Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 584kHz (E1 rate), unless otherwise specified. AFE1115E PARAMETER COMMENTS MIN TYP MAX UNITS RECEIVE CHANNEL Number of Inputs Differential 2 Input Voltage Range Balanced Differential (1) ±3.0 V Common-Mode Voltage +2.5 V Input Impedance All Inputs See Typical Performance Curves Input Capacitance 10 pF Input Gain Matching Line Input vs Hybrid Input ±2% Resolution 14 Bits Programmable Gain Three Gains: –3dB, 3dB, and 9dB –3 +9 dB Settling Time for Gain Change 6 Symbol Periods Gain + Offset Error Tested at Each Gain Range 5 %FSR (2) Output Data Coding Two’s Complement Output Data Rate, rxSYNC(3) 98 584 kHz TRANSMIT CHANNEL Transmit Clock Rate, ftx Symbol Rate 98 584 kHz T1 Transmit –3dB Point Bellcore TA-NWT-3017 Compliant 196 kHz T1 Rate Power (4, 5) See Test Method Section 13 14 dBm E1 Transmit –3dB Point ETSI RTR/TM-03036 Compliant 292 kHz E1 Transmit Power (4, 5) See Test Method Section 13 14 dBm Pulse Output See Typical Performance Curves Common-Mode Voltage, VCM AV DD /2 V Output Resistance(6) DC to 1MHz 1 Ω TRANSCEIVER PERFORMANCE Uncancelled Echo(7) rxGAIN = –3dB, Loopback Enabled –67 dB rxGAIN = –3dB, Loopback Disabled –67 dB rxGAIN = 3dB, Loopback Disabled –71 dB rxGAIN = 9dB, Loopback Disabled –73 dB VCXO PERFORMANCE VCXO Control DAC Resolution 8 Bits VCXO Control DAC Output Positive Full Scale Output 4.5 V VCXO Control DAC Output Negative Full Scale Output 0.5 V VCXO Performance See VCXO Circuit and Layout Section DIGITAL INTERFACE (6) Logic Levels VIH |IIH| < 10µAD V DD –1 DV DD +0.3 V VIL |IIL| < 10µA –0.3 +0.8 V VOH IOH = –20µAD V DD –0.5 V VOL IOL = 20µA +0.4 V POWER Analog Power Supply Voltage Specification 5 V Analog Power Supply Voltage Operating Range 4.75 5.25 V Digital Power Supply Voltage Specification 3.3 V Digital Power Supply Voltage Operating Range 3.15 5.25 V Power Dissipation (4, 5, 8) AV DD = 5V, DVDD = 3.3V, 300 mW Power Dissipation(4, 5, 8) AV DD = DVDD = 5V 350 mW PSRR 60 dB TEMPERATURE RANGE Operating(6) –40 +85 °C NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common- mode voltage on each pin is ±1.5V to achieve a total input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (16.5dBm output from txLINEP and txLINEN). (5) See the Test Method section of this data sheet for more information. (6) Guaranteed by design and characterization. (7) Uncancelled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications sections of this data sheet for more information. (8) Power dissipation includes only the power dissipated with in the component and does not include power dissipated in the external loads. See the Discussion of Specifications section for more information.

PRODUCT PACKAGE NUMBER (1) RANGE AFE1115E 56-Pin Plastic SSOP 346 –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. vcOUT vcINP vcCLK DVDD Unused Pin Unused Pin txCLK txSCLK txDATA rxDATA0 rxDATA1 rxDATA2 rxDATA3 rxDATA4 rxDATA5 GNDD DV DD rxDATA6 rxDATA7 rxDATA8 rxDATA9 rxDATA10 rxDATA11 rxDATA12 rxDATA13 Unused Pin rxSYNC rxGAIN0 DGND vcSCLK vcDATA vcLATCH PLL IN PLLOUT AV DD AGND AGND vcDAC AGND txLINE+ AV DD txLINE– AGND AV DD vrREF V CM vrREF AGND AGND rxLINE+ rxLINE– rxHYB+ rxHYB– AV DD rxLOOP rxGAIN1 AFE1115E

PIN # TYPE NAME DESCRIPTION

1 Output vcOUT VCXO Output

2 Input vcINP VCXO Input

3 Output vcCLK VCXO Output Clock

4 Power DVDD Digital Supply (+3.3 to +5V)

5 NC Unused Pin

6 NC Unused Pin

7 Input txCLK Transmit Baud Clock (XMTLE signal) (1168kHz for E1)

8 Input txSCLK Transmit Serial Clock

9 Input txDATA Transmit Data Input

10 Output rxDATA0 ADC Output Bit-0

11 Output rxDATA1 ADC Output Bit-1

12 Output rxDATA2 ADC Output Bit-2

13 Output rxDATA3 ADC Output Bit-3

14 Output rxDATA4 ADC Output Bit-4

15 Output rxDATA5 ADC Output Bit-5

16 Ground GNDD Digital Ground

17 Power DV

DD Digital Supply (+3.3 to +5V)

18 Output rxDATA6 ADC Output Bit-6

19 Output rxDATA7 ADC Output Bit-7

20 Output rxDATA8 ADC Output Bit-8

21 Output rxDATA9 ADC Output Bit-9

22 Output rxDATA10 ADC Output Bit-10

23 Output rxDATA11 ADC Output Bit-11

24 Output rxDATA12 ADC Output Bit-12

25 Output rxDATA13 ADC Output Bit-13

26 NC Unused Pin (DV

DD may be connected for pinout compatibility with AFE1105)

27 Input rxSYNC ADC Sync Signal (392kHz for T1, 584kHz for E1)

28 Input rxGAIN0 Receive Gain Control Bit-0

29 Input rxGAIN1 Receive Gain Control Bit-1

30 Input rxLOOP Loopback Control Signal (loopback is enabled by positive signal)

31 Power AV DD Analog Supply (+5V)

32 Input rxHYB– Negative Input from Hybrid Network

33 Input rxHYB+ Positive Input from Hybrid Network

34 Input rxLINE– Negative Line Input

35 Input rxLINE+ Positive Line Input

36 Ground AGND Analog Ground

37 Ground AGND Analog Ground

38 Output vrREFP Positive Reference Output

39 Output V

CM Common-mode Voltage (buffered)

40 Output vrREFN Negative Reference Output

41 Power AV DD Analog Supply (+5V)

42 Ground AGND Analog Ground

43 Output txLINE– Negative Line Output

44 Power AV DD Analog Supply (+5V)

45 Output txLINE+ Positive Line Output

46 Ground AGND Analog Ground

47 Output vcDAC VCXO Control

48 Ground AGND Analog Ground

49 Ground AGND PLL Ground

50 Power AV

51 Output PLL OUT PLL Filter Output

52 Input PLL IN PLL Filter Input

53 Input vcLATCH VCXO Control Latch Enable

54 Input vcDATA VCXO Control Data

55 Input vcSCLK VCXO Control Serial Clock

56 Ground DGND Digital Ground

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PIN DESCRIPTIONS

INPUT IMPEDANCE vs BIT RATE Input Impedance (kΩ ) Bit Rate (kbps) 700 900 1300 1100 T1 = 784kbps, 45kΩ E1 = 1168kbps, 30kΩ –20 –40 –60 –80 –100 –120 10K 100K POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) Frequency (Hz) 1M 10M –38dBm/Hz for T1 –40dBm/Hz for E1 196kHz 292kHz –80dB/decade –120dBm/Hz for E1 –118dBm/Hz for T1 TYPICAL PERFORMANCE CURVES At Output of Pulse Transformer The curves shown below are measured at the line output of the HDSL transformer. Typical at 25°C, AVDD = +5V, DVDD = +3.3V, unless otherwise specified. CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at Transformer Output. CURVE 1. Upper Bound of Power Spectral Density Measured at Output of HDSL Transformer. CURVE 3. Input Impedance of rxLINE and rxHYB. 0.4T B = 1.07 C = 1.00 D = 0.93 0.4T –0.6T –1.2T A = 0.01 E = 0.03 G = –0.16 A B C D E F G H 0.01 1.07 1.00 0.93 0.03 –0.01 –0.16 –0.05 0.0264 2.8248 2.6400 2.4552 0.0792 –0.0264 –0.4224 –0.1320 –0.0264 –2.8248 –2.6400 –2.4552 –0.0792 0.0264 0.4224 0.1320 0.0088 0.9416 0.8800 0.8184 0.0264 –0.0088 –0.1408 –0.0440 –0.0088 –0.9416 –0.8800 –0.8184 –0.0264 0.0088 0.1408 0.0440 NORMALIZED LEVEL QUATERNARY SYMBOLS DON'T DELETE TABLE UNTIL KNOWN IF TEEPLE IS LEAVING IT IN? +3 –3 +1 –1 14T H = –0.05 50T F = –0.01 A = 0.01 F = –0.01 0.5T 1.25T

FIGURE 2. Basic Connection Diagram. resulting gain between –3dB and +9dB is shown below. frequencies just by changing the clock speed.

the AFE1115 in serial format through the txDATA input pin. 13 bits of the 16 bit word are ignored. The most significant bit (MSB) is the transmit enable bit. transmitted as shown in the table below. determine the output of the VCXO control D/A converter. the remaining eight bits of the 16 bit word are ignored. TABLE I. Transmit Symbol Data (txDATA). X = Don’t Care. TABLE II. VCXO Control DAC Output. X = Don’t Care. rxSYNC. (4) Data 1a is an interpolated value between Data 1 and Data 2. FIGURE 5. Receive Timing Diagram. TABLE III. Receive Timing (n = Delay Increments from txCLK).

13.5dBm delivered to the line; and a pseudo-random equiprobable sequence of HDSL pulses. The power dissipa- tion specifications includes all power dissipated in the AFE1115, it does not include power dissipated in the exter- nal load. The external power is 16.5dBm, 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissi- pation in the AFE1115 under various conditions is shown in TYPICAL POWER BIT RATE DISSIPATION PER AFE1115 DVDD IN THE AFE1115 (Symbols/sec) (V) (mW) 1168 (E1) 3.3 300 1168 (E1) 5 350 784 (T1) 3.3 290 784 (T1) 5 330 292 (1/4 E1) 3.3 280 292 (1/4 E1) 5 300 TABLE IV. Typical Power Dissipation. Table IV. LAYOUT The analog front end of an HDSL system has a number of conflicting requirements. It must accept and deliver digital outputs at fairly high rates of speed, generate a VCXO clock, phase-lock to a high-speed digital clock, and convert the line input to a high-precision (14-bit) digital output. Thus, there are really four sections of the AFE1115: the digital section, the phase-locked loop, the VCXO and the analog section. DIGITAL LAYOUT The power supply for the digital section of the AFE1115 can range from 3.3V to 5V. This supply should be decoupled to digital ground with a ceramic 0.1µF capacitor placed as close as possible to digital ground (DGND, pin 16) and digital power (DVDD , pin 17). Ideally, both a digital power supply plane and a digital ground plane should run to and underneath the digital pins of the AFE1115 (pins 7 through 30). However, DVDD may be supplied by a wide printed circuit board trance. A digital ground plane underneath all digital pins is strongly recommended. The VCXO circuit needs special attention for layout. There is a portion of the external VCXO circuitry which needs to be as far away as possible from a ground or power plane or other traces. See the discussion below in the section titled VCXO Circuit and Layout. ANALOG LAYOUT The phase-locked loop is powered from AV DD (pin 50) and its ground is referenced to AGND (pin 49). Note that AVDD must be in the 4.75V to 5.25V range. This portion of the AFE1115 should be decoupled with both 10µF Tantalum capacitor and a 0.1µF ceramic capacitor. The ceramic ca- pacitor should be placed as close to the AFE1115 as pos- sible. The placement of the Tantalum capacitor is not as critical, but should be close to the pin. In each case, the capacitor should be connected between AV DD and AGND (pins 49 and 50). The capacitors should be placed in quiet analog areas rather than noisy digital areas. In most systems, it will be natural to derive AVDD for the phase-locked loop (PLL) from the AVDD supply. A 5Ω to 10Ω resistor should be used to connect PLL AVDD (pin 49) to the analog supply. This resistor in combination with the 10µF capacitor form a lowpass filter—keeping glitches on the analog supply from affecting the phase locked loop. Ideally, the phase-locked loop power supply would originate from the analog supply (via the 5Ω to 10Ω resistor) near the power connector for the printed circuit board. Likewise, the PLL ground should connect to a large PCB trace or small ground plane which returns to the power supply connector underneath the PLL AVDD supply path. The PLL “ground plane” should also extend underneath PLLIN and PLLOUT (pins 51 and 52). The remaining portion of the AFE1115 should be considered analog. The four non-PLL AGND pins (pins 36, 37, 42, and 46) should be connected directly to a common analog ground plane and all non-PLL AVDD pins should be con- nected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1115 by a small trace. VCXO CIRCUIT AND LAYOUT The VCXO circuitry is shown in Figure 7. The basic VCXO circuit consists of on-chip control DAC, amplifiers, Schmidt triggers, and clock buffer along with an external crystal and varactor diodes. The control DAC output (vcDAC) varies the capacitance of the varactor diodes (D1 and D2), which controls the frequency at which the crystal circuit oscillates. The buffered clock output is available at pin 3, VCXO Clock Output. Important Note: To achieve specified analog performance when using VCXO, the crystal frequency of the VCXO must be 48x the baud rate. In addition, the txCLK and the rxSYNC control signals must be derived from the VCXO clock so that the edges of the control signal are synchronized with the 48x crystal frequency. If these recommendations are followed, the key internal analog decisions are made at the time of minimum noise. As an example, for an E1 rate of 1168kbps, the symbol rate is 584k symbols per second. In this case the VCXO crystal frequency should be 48 x 584k = 28.032MHz. Likewise, for T1, the crystal frequency should be 18.816MHz.