AFE1104E BURR-BROWN | Alldatasheet
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Technical content
HDSL/MDSL ANALOG FRONT END
FEATURES
l COMPLETE ANALOG INTERFACE l T1, E1, AND MDSL OPERATION l CLOCK SCALEABLE SPEED l SINGLE CHIP SOLUTION l +5V ONLY (5V OR 3.3V DIGITAL) l 250mW POWER DISSIPATION l 48-PIN SSOP l –40°C TO +85°C OPERATION
DESCRIPTION
Burr-Brown’s Analog Front End greatly reduces the size and cost of an HDSL or MDSL system by provid- ing all of the active analog circuitry needed to connect PairGain Technologies SPAROW HDSL digital sig- nal processor to an external compromise hybrid and a 1:2 HDSL line transformer. All internal filter re- sponses as well as the pulse former output scale with clock frequency—allowing the AFE1104 to operate over a range of bit rates from 196kbps to 1.168Mbps. Functionally, this unit is separated into a transmit and a receive section. The transmit section generates, fil- ters, and buffers outgoing 2B1Q data. The receive section filters and digitizes the symbol data received on the telephone line and passes it to the SPAROW. The HDSL Analog Interface is a monolithic device fabricated on 0.6µCMOS. It operates on a single +5V supply. It is housed in a 48-pin SSOP package. © 1996 Burr-Brown Corporation PDS-1331A Printed in U.S.A. August, 1996 International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111 Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 AFE1104 Pulse Former PLLOUT PLLIN txDAT txCLK rxGAIN rxD13 - rxD0 Line Driver Voltage Reference Delta-Sigma Modulator Transmit Control rxSYNC rxCLK rxLOOP Receive Control Decimation Filter txLINEN txLINEP REF P VCM REF N rxLINEP rxLINEN rxHYBP rxHYBN Patents Pending
Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 584kHz (E1 rate), unless otherwise specified. AFE1104E PARAMETER COMMENTS MIN TYP MAX UNITS RECEIVE CHANNEL Number of Inputs Differential 2 Input Voltage Range Balanced Differential (1) ±3.0 V Common-Mode Voltage 1.5V CMV Recommended +1.5 V Input Impedance All Inputs See Typical Performance Curves Input Capacitance 10 pF Input Gain Matching Line Input vs Hybrid Input ±2% Resolution 14 Bits Programmable Gain Four Gains: 0dB, 3.25dB, 6dB, and 9dB 0 9 dB Settling Time for Gain Change 6 Symbol Periods Gain + Offset Error Tested at Each Gain Range 5 %FSR (2) Output Data Coding Two’s Complement Output Data Rate, rxSYNC(3) 98 584 kHz TRANSMIT CHANNEL Transmit Symbol Rate, ftx 98 584 kHz T1 Transmit –3dB Point Bellcore TA-NWT-3017 Compliant 196 kHz T1 Rate Power Spectral Density (4) See Typical Performance Curves E1 Transmit –3dB Point ETSI RTR/TM-03036 Compliant 292 kHz E1 Rate Power Spectral Density(4) See Typical Performance Curves Transmit Power(4, 5) 13 14 dBm Pulse Output See Typical Performance Curves Common-Mode Voltage, VCM AV DD /2 V Output Resistance(6) DC to 1MHz 1 Ω TRANSCEIVER PERFORMANCE Uncanceled Echo(7) rxGAIN = 0dB, Loopback Enabled –67 dB rxGAIN = 0dB, Loopback Disabled –67 dB rxGAIN = 3.25dB, Loopback Disabled –69 dB rxGAIN = 6dB, Loopback Disabled –71 dB rxGAIN = 9dB, Loopback Disabled –73 dB DIGITAL INTERFACE (6) Logic Levels VIH |IIH| < 10µAD V DD –1 DV DD +0.3 V VIL |IIL| < 10µA –0.3 +0.8 V VOH IOH = –20µAD V DD –0.5 V VOL IOL = 20µA +0.4 V Receive Channel Interface trx1 rxCLK Period 35 215 ns rxCLK Duty Cycle 45 55 % trx2 rxSYNC to rxCLK Setup Time 10 ns trx3 rxCLK to rxSYNC Hold Time 10 ns trx4 rxCLK to rxD13 - rxD0 Delay 50 ns Transmit Channel Interface ttx1 txCLK Period 1.7 10.2 µs ttx2 txCLK Pulse Width 50 ns ttx3 Basic txDAT Pulse Unit t tx1/96 ns POWER Analog Power Supply Voltage Specification 5 V Analog Power Supply Voltage Operating Range 4.75 5.25 V Digital Power Supply Voltage Specification 3.3 V Digital Power Supply Voltage Operating Range 3.15 5.25 V Power Dissipation (4, 5, 8) DV DD = 3.3V 250 mW Power Dissipation(4, 5, 8) DV DD = 5V 300 mW PSRR 60 dB TEMPERATURE RANGE Operating(6) –40 +85 °C NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common mode voltage on each pin is ±1.5V to achieve a differential input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the symbol rate with interpolated values. (4) With a pseudo-random equiprobable sequence of HDSL pulses; 13.5dBm applied to the transformer (27dBm output from txLINE P and txLINEN ). (5) See the Discussion of Specifications section of this data sheet for more information. (6) Guaranteed by design and characterization. (7) Uncanceled Echo is a measure of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications section of this data sheet for more information. (8) Power dissipation includes only the power dissipated within the component and does not include power dissipated in the external loads. See the Discussion of Specifications section for more information.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. PIN DESCRIPTIONS PIN # TYPE NAME DESCRIPTION
1 Ground PGND Analog Ground for PLL
2 Power PV DD Analog Supply (+5V) for PLL
3 Input txCLK Transmit Symbol Clock (392kHz for T1, 584kHz for E1)
4 Ground DGND Digital Ground
5 Input txDAT DAC+ Line from SPAROW
6 Output rxD0 ADC Output Bit-0
7 Output rxD1 ADC Output Bit-1
8 Output rxD2 ADC Output Bit-2
9 Output rxD3 ADC Output Bit-3
10 Output rxD4 ADC Output Bit-4
11 Output rxD5 ADC Output Bit-5
12 Ground DGND Digital Ground
13 Power DV
DD Digital Supply (+3.3V to +5V)
14 Output rxD6 ADC Output Bit-6
15 Output rxD7 ADC Output Bit-7
16 Output rxD8 ADC Output Bit-8
17 Output rxD9 ADC Output Bit-9
18 Output rxD10 ADC Output Bit-10
19 Output rxD11 ADC Output Bit-11
20 Output rxD12 ADC Output Bit-12
21 Output rxD13 ADC Output Bit-13
22 Input rxCLK A/D Clock (18.816MHz for T1, 28.03MHz for E1)
23 Input rxSYNC ADC Sync Signal (392kHz for T1, 584kHz for E1)
24 Input rxGAIN0 Receive Gain Control Bit-0
25 Input rxGAIN1 Receive Gain Control Bit-1
26 Input rxLOOP Loopback Control Signal (loopback is enabled by positive signal)
27 Power AV
DD Analog Supply (+5V)
28 Input rxHYB N Negative Input from Hybrid Network
29 Input rxHYB P Positive Input from Hybrid Network
30 Input rxLINE N Negative Line Input
31 Input rxLINE P Positive Line Input
32 Ground AGND Analog Ground
33 Ground AGND Analog Ground
34 Output REF P Positive Reference Output, Nominally 3.5V 35 Output V CM Common-Mode Voltage (buffered), Nominally 2.5V 36 Output REF N Negative Reference Output, Nominally 1.5V
37 Power AV DD Analog Supply (+5V)
38 Ground AGND Analog Ground
39 Output txLINE N Transmit Line Output Negative
40 Power AV DD Analog Supply (+5V)
41 Output txLINE P Transmit Line Output Positive
42 Ground AGND Analog Ground
43 NC NC Connection to Ground Recommended
44 NC NC Connection to Ground Recommended
45 NC NC Connection to Ground Recommended
46 NC NC Connection to Ground Recommended
47 Output PLL
48 Input PLL IN PLL Filter Input
±10mA, Continuous ABSOLUTE MAXIMUM RATINGS PGND PV DD txCLK DGND txDAT rxD0 rxD1 rxD2 rxD3 rxD4 rxD5 DGND DV DD rxD6 rxD7 rxD8 rxD9 rxD10 rxD11 rxD12 rxD13 rxCLK rxSYNC rxGAIN0 PLL IN PLLOUT NC NC NC NC AGND txLINE P AV DD txLINEN AGND AV DD REF N VCM REF P AGND AGND rxLINE P rxLINEN rxHYBP rxHYBN AV DD rxLOOP rxGAIN1 AFE1104E PACKAGE DRAWING TEMPERATURE PRODUCT PACKAGE NUMBER (1) RANGE AFE1104E 48-Pin Plastic SSOP 333 –40 °C to +85°C NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL PERFORMANCE CURVES At Output of Pulse Transformer Typical at 25°C, AVDD = +5V, DVDD = +3.3V, unless otherwise specified. CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output. CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output. 0.4T B = 1.07 C = 1.00 D = 0.93 0.4T –0.6T –1.2T A = 0.01 E = 0.03 G = –0.16 A B C D E F G H 0.01 1.07 1.00 0.93 0.03 –0.01 –0.16 –0.05 0.0264 2.8248 2.6400 2.4552 0.0792 –0.0264 –0.4224 –0.1320 –0.0264 –2.8248 –2.6400 –2.4552 –0.0792 0.0264 0.4224 0.1320 0.0088 0.9416 0.8800 0.8184 0.0264 –0.0088 –0.1408 –0.0440 –0.0088 –0.9416 –0.8800 –0.8184 –0.0264 0.0088 0.1408 0.0440 NORMALIZED LEVEL QUATERNARY SYMBOLS +3 –3 +1 –1 14T H = –0.05 50T F = –0.01 A = 0.01 F = –0.01 0.5T 1.25T CURVE 3. Input Impedance of rxLINE and rxHYB. 100 200 150 100 300 500 INPUT IMPEDANCE vs BIT RATE Input Impedance (kΩ ) Bit Rate (kbps) 700 900 1300 1100 T1 = 78kbps, 45kΩ E1 = 1168kbps, 30kΩ –20 –40 –60 –80 –100 –120 10K 100K POWER SPECTRAL DENSITY LIMIT Power Spectral Density (dBm/Hz) Frequency (Hz) 1M 10M –38dBm/Hz for T1 –40dBm/Hz for E1 196kHz 292kHz –80dB/decade –120dBm/Hz for E1 –118dBm/Hz
FIGURE 2. Basic Connection Diagram. input impedance of the AFE1104. single pair bit rate of 500kbps. 1.5V in the circuit shown in Figure 2 above. the rxHYB inputs is centered at 1.5V.
The power dissipation listed in the specifications section applies under these normal operating conditions: 5V Analog Power Supply; 3.3V Digital Power Supply; standard 13.5dBm delivered to the line; and a pseudo-random equiprobable sequence of HDSL output pulses. The power dissipation specifications includes all power dissipated in the AFE1104, it does not include power dissipated in the external load. The external power is 16.5dBm, 13.5dBm to the line and 13.5dBm to the impedance matching resistors. The external load power of 16.5dBm is 45mW. The typical power dissi- pation in the AFE1104 under various conditions is shown in Table I. pins of the AFE11104 (pins 3 through 26). However, DV DD may be supplied by a wide printed circuit board (PCB) trace. A digital ground plane underneath all digital pins is strongly recommended. The phase-locked loop is powered from PV DD (pin 2) and its ground is referenced to PGND (pin 1). Note that PVDD must be in the 4.75V to 5.25V range. This portion of the AFE1104 should be decoupled with both a 10µF Tantalum capacitor and a 0.1µF ceramic capacitor. The ceramic capacitor should be placed as close to the AFE1104 as possible. The place- ment of the Tantalum capacitor is not as critical, but should be close. In each case, the capacitor should be connected between PV DD and PGND. In most systems, it will be natural to derive PVDD from the AV DD supply. A 5Ω to 10Ω resistor should be used to connect PVDD to the analog supply. This resistor in combi- nation with the 10µF capacitor form a lowpass filter— keeping glitches on AVDD from affecting PVDD . Ideally, PV DD would originate from the analog supply (via the resistor) near the power connector for the printed circuit board. Likewise, PGND should connect to a large PCB trace or small ground plane which returns to the power supply connector underneath the PV DD supply path. The PGND “ground plane” should also extend underneath PLLIN and PLL OUT (pins 47 and 48). The remaining portion of the AFE1104 should be considered analog. All AGND pins should be connected directly to a common analog ground plane and all AV DD pins should be connected to an analog 5V power plane. Both of these planes should have a low impedance path to the power supply. Ideally, all ground planes and traces and all power planes and traces should return to the power supply connector before being connected together (if necessary). Each ground and power pair should be routed over each other, should not overlap any portion of another pair, and the pairs should be separated by a distance of at least 0.25 inch (6mm). One exception is that the digital and analog ground planes should be connected together underneath the AFE1104 by a small trace. TYPICAL POWER BIT RATE DISSIPATION PER AFE1104 DVDD IN THE AFE1104 (Symbols/sec) (V) (mW) 584 (E1) 3.3 250 584 (E1) 5 300 392 (T1) 3.3 240 392 (T1) 5 270 146 (E1/4) 3.3 230 146 (E1/4) 5 245 TABLE I. Typical Power Dissipation. LAYOUT The analog front end of an HDSL system has a number of conflicting requirements. It must accept and deliver digital outputs at fairly high rates of speed, phase-lock to a high- speed digital clock, and convert the line input to a high- precision (14-bit) digital output. Thus, there are really three sections of the AFE1104: the digital section, the phase- locked loop, and the analog section. The power supply for the digital section of the AFE1104 can range from 3.3V to 5V. This supply should be decoupled to digital ground with a ceramic 0.1µF capacitor placed as close to DGND (pin 12) and DV DD (pin 13) as possible. Ideally, both a digital power supply plane and a digital ground plane should run up to and underneath the digital