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Technical content

Features

100 Watts Peak Pulse Power per Line (tp=8/20μs)

Protects one birectional I/O line Low clamping voltage Working voltages :12V Low leakage current ESD/AESD12EB IEC Compatibility IEC61000-4-2 (ESD) ±30kV (air), ±30kV (contact) IEC61000-4-4 (EFT) 40A (5/50ηs) Mechanical Characteristics Molding Compound Flammability Rating:L 94V-O Quantity Per Reel:8000pcs Reel Size:7 inch Lead Finish:Lead Free

Applications

Cell Phone Handsets and Accessories Microprocessor based equipment Personal Digital Assistants(PDA's) Notebooks,Desktops,and Servers Portable Instrumentation Peripherals Pagers SOD-523 Pin Configuration REV 2017 07 24 AEC-Q101

Maximum Ratings(@25 Unless Otherwise Specified)℃ Parameter Symbol Value Units Peak Pulse Power(tp=8/20μs waveform) Lead Soldering Temperature Operating Temperature Range Storage Temperature Range P PP T L T J T STG 100 260(10 sec.) -55~150 -55~150 Watts Maximum Ratings (T =25 unless otherwise noted ) A

Electrical Characteristics

(Ta=25 unless otherwise specified)℃ Ratings and Characteristic Curves /UNI77ac/UNI96f7/UNI7535/UNI5b50 SPSEMI www.spsemi.cn Page 2 of 3 Parameter Symbol Conditions UnitsMin. Typ. Max. AESD12EB(Marking: DC ) Reverse Stand-off Voltage Breakdown Voltage Clamping Voltage Clamping Voltage Reverse Leakage Current Junction Capacitance V RWM V BR C V C V R I C I/O I= 1 m A T I =1A,tp=8/20μs PP I =3A,tp=8/20μs PP RWM 13.3 V V V V μA F p 0Vdc,f=1MHz Between I/O Pins and GND 10 Fig.1 Pulse Waveform 501 0 3 0 150 Time( ) μs Fig.2 Non-Repetitive Peak Pulse Power vs.Pulse Time 00.01 1 10 100 1000 0.1 Pulse Duration-tp(μs) Peak Pulse Power-Ppk(KW) 20 25 100 110 Percent of I PP t= I / 2 d PP Waveform Parameters: tr=8μs t =20μs d e ESD/AESD12EB .. . REV 2017 07 24

/UNI77ac/UNI96f7/UNI7535/UNI5b50 SPSEMI www.spsemi.cn Page 3 of 3 Dimensions(SOD-523) SOD-523 Recommended Mounting Pad Layout 1.40 0.0547 0.40 0.0157 0.40 0.0157 Dimensions in ( )millimeters inches J S K C A 1 2 B D DIM A B C D J K S Millimeters Min 1.10 0.70 0.50 0.25 0.07 0.15 1.50 Max 1.30 0.90 0.70 0.35 0.20 0.25 1.70 Min 0.043 0.028 0.020 0.010 0.0028 0.006 0.059 Max 0.051 0.035 0.028 0.014 0.0079 0.010 0.067 Inches ESD/AESD12EB .. .

Application Information

PCB Layout Recommendations The location and circuit board layout is critical to maximize the effectiveness of the LIN protection circuit. The following guidelines are recommended: Locate the protection devices as close as possible to the LIN connector. This allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the PCB. Minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. Avoid running protection conductors in parallel with unprotected conductors Use ground planes wherever possible to reduce the parasitic capacitance and inductance of the PCB that degrades the effectiveness of a filter device. Using shared transient return paths to a common ground point. LIN Protection IC AESD12EB LIN BUS REV 2017 07 24