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Technical content

Features

320 Watts Peak Pulse Power per Line (tp=8/20μs)

Protects one I/O or power line Low clamping voltage Working voltages: 3. 3V Low leakage current ESD/AESD03FB IEC Compatibility IEC61000-4-2 (ESD) ±30kV (air), ±30kV (contact) IEC61000-4-4 (EFT) 40A (5/50ηs) Mechanical Characteristics Molding Compound Flammability Rating:UL 94V-O Weight 0.5 Millgrams(Approximate) Quantity Per Reel:3000pcs Reel Size:7 inch Lead Finish:Lead Free

Applications

Cell Phone Handsets and Accessories Microprocessor based equipment Personal Digital Assistants(PDA's) Notebooks,Desktops,and Servers Portable Instrumentation Peripherals Pagers SOD-323 Pin Configuration AEC-Q101

/UNI77ac/UNI96f7/UNI7535/UNI5b50 SPSEMI www.spsemi.cn Page 2 of 3 Parameter Symbol Value Units Peak Pulse Power(tp=8/20μs) Lead Soldering Temperature Operating Temperature Range Storage Temperature Range P PP T L T J T STG 320 260(10 sec.) -55~150 -55~150 Watts Maximum Ratings (T =25 unless otherwise noted ) A

Electrical Characteristics

(T =25 unless otherwise specified ) A Parameter Symbol Conditions UnitsMin. Max. AESD03FB(Marking:2A) Reverse Stand-off Voltage Breakdown Voltage Reverse Leakage Current Junction Capacitance Clamping Voltage I R C I/O V RWM V BR V C 3.3 7.5 450 I= 1 m A T I =1A,tp=8/20μs PP I =18A,tp=8/20μs PP RWM 3.6 V V V V μA F p 0Vdc,f=1MHz Between I/O Pins and GND .. . Ratings and Characteristic Curves ESD/AESD03FB Fig.2 Pulse Waveform 501 0 3 0 150 Time( ) μs 20 25 100 110 Percent of I PP t= I / 2 d PP Waveform Parameters: tr=8μs t =20μs d e Fig.1 Non-Repetitive Pulse Power vs.Pulse Time 0 1 0.01 Pulse Duration-tp( ) μs 0.1 Peak Pulse Power-P (kW) PP 100 1000 REV 2017 07 24

/UNI77ac/UNI96f7/UNI7535/UNI5b50 SPSEMI www.spsemi.cn Page 3 of 3 Dimensions(SOD-323) SOD-323 Recommended Mounting Pad Layout 2.85 0.112 0.83 0.033 0.63 0.025 Dimensions in ( )millimeters inches D H E E b 1 2 A1C L A DIM A b C D E L H E Millimeters Min 0.80 0.00 0.25 0.089 1.60 1.15 0.08 2.30 Max 1.00 0.10 0.40 0.177 1.80 1.35 2.70 Min 0.031 0.000 0.010 0.003 0.062 0.045 0.003 0.090 Max 0.040 0.004 0.016 0.007 0.070 0.053 0.105 Inches 0.15REF 0.006REF 1.60 0.063

Application Information

PCB Layout Recommendations The location and circuit board layout is critical to maximize the effectiveness of the I/O protection circuit. The following guidelines are recommended: Locate the protection devices as close as possible to the I/O connector. This allows the protection devices to absorb the energy of the transient voltage before it can be coupled into the adjacent traces on the PCB. Minimize the loop area for the high.speed data lines, power and ground lines to reduce the radiated emissions. Avoid running protection conductors in parallel with unprotected conductors Use ground planes wherever possible to reduce the parasitic capacitance and inductance of the PCB that degrades the effectiveness of a filter device. Using shared transient return paths to a common ground point. I/O Protection ESD/AESD03FB AESD03FB I/O I/O I/O I/O AESD03FB .. .REV 2017 07 24