ADXRS450BEYZ-RL

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High Performance, Digital Output Gyroscope Preliminary Technical Data ADXRS450 Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Complete rate gyroscope on a single chip ±300°/sec angular rate sensing High vibration rejection over a wide frequency range Excellent 25°/hr null offset stability Internally temperature compensated 2000 g powered shock survivability SPI digital output with 16-bit data-word Low noise and low power

3.3 V and 5V operation

−40°C to +105°C operation Ultra small, light, and RoHS compliant Two package options Low cost SOIC_CAV package for yaw rate (Z-axis) response Innovative ceramic vertical mount package, which can be oriented for pitch, roll, or yaw response

APPLICATIONS

Rotation sensing medical applications Rotation sensing industrial and instrumentation High performance platform stabilization GENERAL DESCRIPTION The ADXRS450 is an angular rate sensor (gyroscope) intended for industrial, medical, instrumentation, stabilization, and other high performance applications. An advanced, differential, quad sensor design rejects the influence of linear acceleration, enabling the ADXRS450 to operate in exceedingly harsh environments where shock and vibration are present. The ADXRS450 utilizes an internal, continuous self-test archi- tecture. The integrity of the electromechanical system is checked by applying a high frequency electrostatic force to the sense structure to generate a rate signal that can be differentiated from the baseband rate data and internally analyzed. The ADXRS450 is capable of sensing angular rate of up to ±300°/sec. Angular rate data is presented as a 16-bit word, as part of a 32-bit SPI message. The ADXRS450 is available in a cavity plastic 16-lead SOIC (SOIC_CAV) and an SMT-compatible vertical mount package (LCC_V), and is capable of operating across both a wide voltage range (3.3 V to 5 V) and temperature range (−40°C to +105°C). FUNCTIONAL BLOCK DIAGRAM SPI INTERFACE MISO MOSI SCLK CS HIGH VOLTAGE GENERATION EEPROM PSS CP5 AVSS VX LDO REGULATOR PDD DVSS DVDD AVDD REGISTERS/MEMORY BAND-PASS FILTER FAULT DETECTION TEMPERATURE CALIBRATION DECIMATION FILTER ALU PHASE LOCKED LOOP CLOCK DIVIDER DEMOD Q FILTERQ DAQ P DAQ HV DRIVE ST CONTROL ADC 12 AMPLITUDE DETECT 08952-001 Z-AXIS ANGULAR RATE SENSOR ADXRS450 Figure 1.

ADXRS450 Preliminary Technical Data Rev. PrA | Page 2 of 28 TABLE OF CONTENTS

Preliminary Technical Data ADXRS450 Rev. PrA | Page 3 of 28 SPECIFICATIONS Specification conditions @ TA = TMIN to TMAX, PDD = 5 V , angular rate = 0°/sec, bandwidth = 80 Hz ±1 g, continuous self-test on. Table 1. Parameter Test Conditions/Comments Symbol Min Typ Max Unit MEASUREMENT RANGE Full-scale range FSR ±300 ±400 °/sec SENSITIVITY See Figure 2 Nominal Sensitivity 80 LSB/°/sec Sensitivity Tolerance ±3 % Nonlinearity1 Best fit straight line 0.05 0.25 % FSR rms Cross-Axis Sensitivity2 ±3 % NULL Null Accuracy ±3 °/sec NOISE PERFORMANCE Rate Noise Density TA = 25°C 0.015 °/sec/√Hz LOW-PASS FILTER Cut-Off (−3dB) Frequency f0/200, see Figure 6 fLP 80 Hz Group Delay3 f = 0 Hz tLP 3.25 4 4.75 ms SHOCK AND VIBRATION IMMUNITY Sensitivity to Linear Acceleration DC to 5 kHz 0.03 °/sec/g Vibration Rectification 0.003 °/sec/ g2 SELF-TEST See Continuous Self-Test Magnitude 2559 LSB Fault Register Threshold Compared to LOCST data 2239 2879 LSB Sensor Data Status Threshold Compared to LOCST data 1279 3839 LSB Frequency f 0/32 f ST 500 Hz ST Low-Pass Filter −3 dB Frequency f0/800, see Figure 7 2 Hz Group Delay3 52 64 76 ms SPI COMMUNICATIONS Clock Frequency 8.08 MHz Voltage Input High MOSI, CS, SCLK 0.85 × PDD PDD + 0.3 V Voltage Input Low MOSI, CS SCLK −0.3 PDD × 0.15 V Output Voltage Low MISO, current = 3 mA 0.5 V Output Voltage High MISO, current = −2 mA PDD − 0.5 V Pull up Current CS, PDD = 3.3 V, CS = 0.75 × PDD 50 200 μA CS, PDD = 5 V, CS = 0.75 × PDD 70 300 μA MEMORY REGISTERS See Memory Register Definitions Temperature Sensor Value at 45°C 0 LSB Scale Factor 5 LSB/°C Quad, ST, Rate, DNC Registers Scale Factor 80 LSB/°/sec POWER SUPPLY Supply Voltage PDD 3.15 5.25 V Quiescent Supply Current IDD 6.0 10.0 mA Turn-On Time Power on to 0.5°/sec of final 100 ms TEMPERATURE RANGE Independent of package type TMIN, TMAX −40 +105 °C 1 Maximum limit is guaranteed through ADI characterization. 2 Cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB). 3 Minimum and maximum limits are guaranteed by design.

Table 3. Thermal Resistance Figure 2. Rate Signal Increases with Clockwise Rotation

Figure 3. SOIC_CAV Pin Configuration Table 4. 14-Lead SOIC_CAV Pin Function Descriptions 1 DVDD Digital Regulated Voltage. See Figure 21 for the applications circuit diagram. 2 RSVD Reserved. This pin must be connected to DVSS. 3 NC Reserved. This pin must be connected to DVSS. 7 PSS Switching Regulator Ground. 8 VX High Voltage Switching Node. See Figure 21 for the applications circuit diagram. 9 CP5 High Voltage Supply. See Figure 21 for the applications circuit diagram. 10 NC Reserved. This pin must be connected to DVSS. 12 NC Reserved. This pin must be connected to DVSS. 13 DVSS Digital Signal Ground. 14 AVDD Analog Regulated Voltage. See Figure 21 for the applications circuit diagram. 15 MOSI Master Out/Slave In.

Figure 23. Primary Signal Chain and Associated Delays

the master device upon the initial command/response exchange. Table 7. SPI Signals

32 CLOCK

Figure 24. SPI Protocol Table 8. SPI Commands Table 9. SPI Responses

• All minimum and maximum timing values are guaranteed through characterization.
• All timing is shown with respect to 10% VDD and 90% of the actual delivered voltage waveform.
• All minimum and maximum timing values are valid for 3.0 V ≤ VDD ≤ 5.5 V .
• Capacitive load for all signals is assumed to be ≤80 pF.
• Ambient temperature is –40°C ≤ TA ≤ +105°C.
• MISO pull-up of 47 kΩ or 110 μA.
• Sequential transfer increases to 17 ms following any write operation limited by the EEPROM.

Table 10. SPI Command/Response Timing Characteristics

8.08 MHz

Figure 25. SPI Timings Figure 26. Device Data Latching

Table 11. Quick Guide—Bit Definitions for SPI Interface

• Master: data to be written to a memory register as specified in the A8 to A0 section.
• Slave: sensor rate output data.
• Slave: device data read from the memory register specified in the A8 to A0 section, as well as the data from the next sequential register.
• Slave: For a write command, the 16-bit data that is written to the specified memory register reflects back to the master device for correlation. SPI The SPI bit sets when any either of the following occur: too many/not enough bits are transmitted, or the message from the control module contains a parity error. Additionally, any error during a sensor data request results in the device issuing a read/write error. ST1 to ST0 The status bits (ST1 and ST0) are used to signal to the master device the type of data contained in the response message. The status bits are decoded as listed in Table 12.

Table 12. Status Bit Code Definitions

00 Error data for sensor data response

01 Valid sensor data

10 Sensor self-test data

11 Read/write response

• An invalid command is sent from the control module.
• The read/write command specifies an invalid memory register.
• The write command attempted to a nonwriteable memory register. DU As expressed in Table 10, the sequential transfer delay for writing data to a memory register (for example, DNC0) results in a sequential transfer delay of 17 ms. If a successive write command is issued to the device prior to the completion of the sequential transfer delay, the command is ignored and the device issues a DU error response. However, a read command

status bit does not deassert until it is read by the master device. by issuing a read command to Register 0x0A. Table 13. Quick Guide—Fault Register Bit Definitions the PLL has failed to achieve sync with the resonator structure. potentially invalid rate data. in the device. If this value exceeds 4096 LSB, a Q fault is issued. ADXRS450. Excessive quadrature is associated with offset errors. has contributed to an equivalent of 4°/sec (typical) of rate offset. the volatile memory upon a device power cycle. voltage (UV) fault is asserted, then the PWR bit is also asserted. fault bits must be analyzed. The ADXRS450 is designed with continuous self-test functionality.

• Self-test value > ±512 LSB from nominal results in an assertion of the self-test flag in the fault register
• Self-test value > ±1856 LSB from nominal results in both an assertion of the self-test flag in the fault register as well as setting the ST[1:0] bits to 0b00, indicating that the rate data contained in the sensor data response is potentially invalid. CHK The CHK bit is transmitted by the control module to the ADXRS450 as a method of generating faults. By asserting the CHK bit, the device creates conditions that result in the generation of all faults represented through the fault register. For example, the self-test amplitude is deliberately altered to exceed the fault detection threshold, resulting in a self test error. In this way, the device is capable of checking both its ability to detect a fault condition, as well as its ability to report that fault to the control module.

Preliminary Technical Data ADXRS450 Rev. PrA | Page 17 of 28 The fault conditions are initiated nearly simultaneously; however, the timing for receiving fault codes when the CHK bit is asserted is dependent upon the time required to generate each unique fault. It takes no more than 50 ms for all of the internal faults to be generated, and the fault register updated to reflect the condition of the device. Until the CHK bit is cleared, the status bits (ST[1:0]) are set to 0b10, indicating that the data should be interpreted by the control module as self-test data. After the CHK bit is deasserted, the fault conditions require an additional 50 ms to decay, and the device to return to normal operation. Refer to Figure 21 for the proper methodology for asserting the check bit. OV The OV fault bit asserts if the internally regulated voltage (nominally 3 V) is observed to exceed 3.3 V . This measurement is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When an OV fault has occurred, the PWR fault bit is asserted simultaneously. Because the OV fault bit is not transmitted as part of a sensor data request, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error. This allows the user to determine the specific error condition. UV The UV fault bit asserts if the internally regulated voltage (nominally 3 V) is observed to be less than 2.77 V . This measurement is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When a UV fault has occurred, the PWR fault bit is asserted simultaneously. As the UV fault bit is not transmitted as part of a sensor data request, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error. This allows the user to determine the specific error condition. FAIL The fail flag is asserted when a condition arises such that the ST[0:1] bits are set to 0b00. This indicates that the device has experienced a gross failure, and that the sensor data could potentially be invalid. AMP The amp fault bit is asserted when the measured amplitude of the silicon resonator has been significantly reduced. This condition can occur if the voltage supplied to CP5 has fallen below the requirements of the internal voltage regulator. This fault bit is OR’ ed with the CST fault such that during a sensor data request, the CST bit position represents either an amp failure or a CST failure. The full status register can then be read from memory to validate the specific failure. K-Bit Assertion: Recommended Start-Up Routine The following diagram illustrates a recommended start-up routine that can be implemented by the user. Alternate start-up sequences can be employed; however, ensure that the response from the ADXRS450 is handled correctly. If implemented immediately after power is applied to the device, the total time to implement the following fault detection routine is approx- imately 200 ms. As described in the Device Data Latching section, the data present in the device upon the assertion of the CS signal is used in the next sequential command/response exchange. This results in an apparent one transaction delay before the data resulting from the assertion of the CHK command is reported by the device. For all other read/write interactions with the device, no such delay exists, and the MOSI command is serviced during the next sequential command/ response exchange. Note that when the CHK bit is deasserted, if the user tries to obtain data from the device before the CST fault flag has cleared, the device reports the data as error data.

Figure 27. Recommended Startup Sequence

twos complement number, with a scale factor of 80 LSB/°/sec. is not guaranteed above ±24,000 LSB (±300°/sec). Table 14. Rate Data

next, sequential register to the memory address that was specified. the explanation of the significance of each memory register. Table 15. Memory Register Map

Preliminary Technical Data ADXRS450 Rev. PrA | Page 21 of 28 MEMORY REGISTER DEFINITIONS The SPI accessible memory registers are described in this section. As explained in the previous section, when requesting data from a memory register, only the first sequential memory address need be addressed. The data returned by the device contain 16 bits of memory register information. Bits[15:8] contain the MSB of the requested information, and Bits[7:0] contain the LSB. Rate Registers Addresses: 0x00 (Rate1) 0x01 (Rate0) Register update rate: 500 Hz Scale factor: 80 LSB/°/sec The rate registers contain the temperature compensated rate output of the device filtered to 80 Hz. This data can also be accessed by issuing a sensor data read request to the device. The data is presented as a 16-bit, twos complement number. M S B L S B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Temperature (TEMx) Registers Addresses: 0x02 (TEM1), 0x03 (TEM0) Register update rate: 500 Hz Scale factor: 5 LSB/°C The TEM register contains a value corresponding to the temperature of the device. The data is presented as a 10-bit, twos complement number. 0 LSB corresponds to a temperature of approximately 45°C. MSB LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (Unused) Table 16. Temperature Value of TEM1:TEM0 45°C 0000 0000 00XX XXXX 85°C 0011 0010 00XX XXXX 0°C 1100 0111 11XX XXXX Low CST (LOCST) Memory Registers Addresses: 0x04 (LOCST1) 0x05 (LOCST0) Register update rate: 1000 Hz Scale factor: 80 LSB/°/sec The LOCST memory registers contain the value of the temperature compensated and low-pass filtered continuous self-test delta. This value is a measure of the difference between the positive and negative self-test deflections and corresponds to the values presented in Table 1. The device issues a CST error if the value of self test exceeds the established self-test limits. The self-test data is filtered to 2 Hz to prevent false triggering of the CST fault bit. The data is presented as a 16-bit, twos complement number, with a scale factor of 80 LSB/°/sec. M S B L S B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 High CST (HICST) Memory Registers Addresses: 0x06 (HICST1), 0x07 (HICST0) Register update rate: 1000 Hz Scale factor: 80 LSB/°/sec The HICST register contains the unfiltered self-test information. The HICST data can be used to supplement fault diagnosis in safety critical applications as sudden shifts in the self-test response can be detected. However, the CST bit of the fault register is not set when the HICST data is observed to exceed the self-test limits. Only the LOCST memory registers, which are designed to filter noise and the effects of sudden temporary self-test spiking due to external disturbances, control the assertion of the CST fault bit. The data is presented as a 16-bit, twos complement number. M S B L S B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Quad Memory Registers Addresses: 0x08 (QUAD1) 0x09 (QUAD0) Register update rate: 250 Hz Scale factor: 80 LSB/°/sec equivalent The quad memory registers contain a value corresponding to the amount of quadrature error present in the device at a given time. Quadrature can be likened to a measurement of the error of the motion of the resonator structure, and can be caused by stresses and aging effects. The quadrature data is filtered to

80 Hz and can be read frequently to detect sudden shifts in the

level of quadrature. The data is presented as a 16-bit, twos complement number. M S B L S B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

ADXRS450 Preliminary Technical Data Rev. PrA | Page 22 of 28 Fault Registers Addresses: 0x0A (FAULT1) 0x0B (FAULT0) Register update rate: Not applicable Scale factor: Not applicable The fault register contains the state of the error flags in the device. The FAULT0 register is appended to the end of every device data transmission (see Table 13); however, this register can also be accessed independently through its memory location. The individual fault bits are updated asynchronously, requiring <5 μs to activate, as soon as the fault condition exists on-chip. When toggled, each fault bit remains active until the fault register is read or a sensor data command is received. If the fault is still active after the bit is read, the fault bit immediately reasserts itself. MSB LSB (Unused) FAIL AMP OV UV PLL Q NVM POR PWR ST CHK 0 Part ID (PID) Registers Addresses: 0x0C (PID1) 0x0D (PID0) Register update rate: Not applicable Scale factor: Not applicable The part identification registers contain a 16-bit number identifying the version of the ADXRS450. Combined with the serial number, this information allows for a higher degree of device individualization and tracking. The initial product ID is R01 (0x5201), with subsequent versions of silicon incrementing this value to R02, R03, and so forth. M S B L S B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Serial Number (SN) Registers Addresses: 0x0E (SN3) 0x0F (SN2) 0x10 (SN1) 0x11 (SN0) Register update rate: Not applicable Scale factor: Not applicable The serial number registers contain a 32-bit identification number that uniquely identifies the device. To read the entire serial number, two memory read requests must be initiated. The first read request to Register 0x0E returns the upper 16 bits of the serial number, and the following read request to Register 0x10 returns the lower 16 bits of the serial number. M S B L S B D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Dynamic Null Correction (DNC) Registers Addresses: 0x12 (DNC1) 0x13 (DNC0) Register update rate: Not applicable Scale factor: 80 LSB/°/sec The dynamic null correction register is the only register with write access available to the user. The user can make small adjustments to the rateout of the device by asserting these bits. This 10-bit register allows the user to adjust the static rateout of the device by up to ±6.4°/sec. M S B L S B (Unused) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 31. Sample LCC_V Solder Pad Layout for

Figure 32. Recommended Soldering Profile

Figure 33. LCC_V and SOIC_CAV Package Marking Codes Table 17. Package Code Designations

450 Series number

10.30 BSC

9.59 BSC

1.27 BSC

0.25 GAGE

Figure 34. 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV]

0.675 NOM

0.500 MIN

0.80 REF

Figure 35. 14-Terminal Ceramic Leadless Chip Carrier [LCC_V]

ADXRS450 Preliminary Technical Data Rev. PrA | Page 28 of 28 ORDERING GUIDE Model1 Temperature Range Package Description Package Option ADXRS450BRGZ –40°C to +105°C 16-Lead SOIC_CAV RG-16-1 ADXRS450BRGZ-RL –40°C to +105°C 16-Lead SOIC_CAV RG-16-1 ADXRS450BEYZ –40°C to +105°C 14-Terminal LCC_V EY-14-1 ADXRS450BEYZ-RL –40°C to +105°C 14-Lead LCC LCC_14 EVAL-ADXRS450Z Evaluation Board EVAL-ADXRS450Z-M Analog Devices Inertial Sensor Evaluation System, Includes ADXRS450 Satellite EVAL-ADXRS450Z-S ADXRS450 Satellite, Standalone 1 Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. PR08952-0-4/10(PrA)