ADXL312_V01 AD | Alldatasheet
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3-Axis, ±1.5 g/±3 g/±6 g/±12 g Digital Accelerometer Data Sheet ADXL312 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©2010–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
Ultralow power: as low as 57 µA in measurement mode and 0.1 µA in standby mode at VS = 3.3 V (typical) Power consumption scales automatically with bandwidth User-selectable resolution Fixed 10-bit resolution Full resolution, where resolution increases with g range, up to 13-bit resolution at ±12 g (maintaining 2.9 mg/LSB scale factor in all g ranges) Embedded FIFO technology minimizes host processor load Built-in motion detection functions for activity/inactivity monitoring Supply and I/O voltage range: 2.0 V to 3.6 V SPI (3- and 4-wire) and I2C digital interfaces Flexible interrupt modes mappable to either interrupt pin Measurement ranges selectable via serial command Bandwidth selectable via serial command Wide temperature range (−40 to +105°C) 10,000 g shock survival Pb free/RoHS compliant Small and thin: 5 mm × 5 mm × 1.45 mm LFCSP package Qualified for automotive applications
APPLICATIONS
Hill start aid (HSA) Electronic parking brake Data recorder (black box) GENERAL DESCRIPTION The ADXL3121 is a small, thin, low power, 3-axis accelerometer with high resolution (13-bit) measurement up to ±12 g. Digital output data is formatted as 16-bit twos complement and is accessible through either a serial port interface (SPI) (3- or 4-wire) or I2C digital interface. The ADXL312 is well suited for car alarm or black box applica- tions. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (2.9 mg/LSB) enables resolution of inclination changes of as little as 0.25°. A built-in FIFO facili- tates using oversampling techniques to improve resolution to as little as 0.05° of inclination. Several special sensing functions are provided. Activity and inactivity sensing detects the presence or absence of motion and whether the acceleration on any axis exceeds a user-set level. These functions can be mapped to interrupt output pins. An integrated 32 level FIFO can be used to store data to minimize host processor intervention. Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. The ADXL312 is supplied in a small, thin 5 mm × 5 mm × 1.45 mm, 32-lead, LFCSP package. FUNCTIONAL BLOCK DIAGRAM 3-AXIS SENSOR SENSE ELECTRONICS DIGITAL FILTER ADXL312 POWER MANAGEMENT CONTROL AND INTERRUPT LOGIC SERIAL I/O INT1 VS VDD I/O INT2 SDA/SDI/SDIO SDO/ALT ADDRESS SCL/SCLK GND ADC
32 LEVEL
Figure 1. ADXL312 Simplified Block Diagram 1 Protected by U.S. Patent 8,156,264B2.
Rev. B | Page 2 of 32 TABLE OF CONTENTS
REVISION HISTORY
4/2017—Rev. A to Rev. B 7/2015—Rev. 0 to Rev. A Changes to Serial Communications Section, SPI Section, Added Preventing Bus Traffic Errors Section and Figure 23; 12/2010—Revision 0: Initial Version
TA = −40°C to +105°C, VS = VDD I/O = 3.3 V, acceleration = 0 g, unless otherwise noted. Table 1. Specifications1
Rev. B | Page 4 of 32 Parameter Test Conditions/Comments Min Typ Max Unit POWER SUPPLY Operating Voltage Range (VS) 2.0 3.6 V Interface Voltage Range (VDD I/O) 1.7 VS V Supply Current Data rate > 100 Hz 100 170 300 µA Data rate < 10 Hz 30 55 110 µA Standby Mode Leakage Current T = 25°C 0.1 2 µA Over entire operating temperature range 17 µA Turn-On (Wake-Up) Time5 1.4 ms TEMPERATURE Operating Temperature Range −40 +105 °C 1 All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. 2 Cross-axis sensitivity is defined as coupling between any two axes. 3 Bandwidth is half the output data rate. 4 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register) minus the output (g) when the SELF_TEST bit = 0 (in the DATA_FORMAT register). Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). 5 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate).
3.9 V, whichever is less
soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
- NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
- THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE.
24 SDA/SDI/SDIO
23 SPO/ALT ADDRESS
22 RESERVED
21 INT2
20 INT1
Figure 2. Pin Configuration (Top View) Table 4. Pin Function Descriptions 1 GND This pin must be connected to ground. 2 Reserved Reserved. This pin must be connected to VS or left open. 3 GND This pin must be connected to ground. 4 GND This pin must be connected to ground. 7 Reserved Reserved. This pin must be left open. 8 to19 NC No Connect. Do not connect to this pin. 22 Reserved Reserved. This pin must be connected to GND. 23 SDO/ALT ADDRESS Serial Data Out, Alternate I 2C Address Select. 24 SDA/SDI/SDIO Serial Data (I2C), Serial Data In (SPI 4-Wire), Serial Data In/Out (SPI 3-Wire). 25 NC No Connect. Do not connect to this pin. 26 SCL/SCLK Serial Communications Clock. 27 to 30 NC No Connect. Do not connect to this pin. 31 V DD I/O Digital Interface Supply Voltage. EP The exposed pad must be soldered to the ground plane.
which allows it to be used as a tilt sensor. against acceleration forces. polarity of the acceleration. interface voltage, as long as VS is greater than or equal to VDD I/O. device in standby mode and then to enable measurement mode. Clearing the measure bit returns the device to the standby mode. Table 5. Power Sequencing
Table 6. Current Consumption vs. Data Rate Table 7. Current Draw vs. Data Rate, Low Power Mode automatically switch to sleep mode during periods of inactivity. standby mode preserves the contents of the FIFO.
add a logic gate in front of the SDI pin, as shown in Figure 23. Figure 23. Recommended SPI Connection Diagram when Using Multiple SPI Table 8. SPI Digital Input/Output 1 Limits based on characterization results, not production tested. Table 9. SPI Timing (TA = 25°C, VS = VDD I/O = 3.3 V)1 fSCLK 5 MHz SPI clock frequency. tSCLK 200 ns 1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40. tDELAY 5 ns CS falling edge to SCLK falling edge . tQUIET 5 ns SCLK rising edge to CS rising edge. tDIS 10 ns CS rising edge to SDO disabled. tCS,DIS 150 ns CS deassertion between SPI communications. tS 0.3 × tSCLK ns SCLK low pulse width (space). tM 0.3 × tSCLK ns SCLK high pulse width (mark). tSETUP 5 ns SDI valid before SCLK rising edge. tHOLD 5 ns SDI valid after SCLK rising edge. tSDO 40 ns SCLK falling edge to SDO/SDIO output transition. tR4 20 ns SDO/SDIO output high to output low transition. tF4 20 ns SDO/SDIO output low to output high transition. 1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. 2 Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested. 3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 8. 4 Output rise and fall times measured with capacitive load of 150 pF.
Table 11. I2C Timing (TA = 25°C, VS = VDD I/O = 3.3 V) 1 Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested. 2 All values referred to the VIH and the VIL levels given in Table 10. 3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge. undefined region of the falling edge of SCL. 5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal. 7 Cb is the total capacitance of one bus line in picofarads. Figure 29. I2C Timing Diagram
some functions may need to share interrupt pins. generation of an interrupt before desired. cleared when no new data is available. in the THRESH_ACT register (Address 0x24) is experienced. cleared when the contents of FIFO are read. Table 12. Interrupt Pin Digital Output 1 Limits based on characterization results, not production tested. 2 Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin. 3 Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin.
Rev. B | Page 18 of 32 FIFO The ADXL312 contains technology for an embedded memory management system with 32-level FIFO that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger (see Table 21). Each mode is selected by the settings of the FIFO_MODE bits in the FIFO_CTL register (Address 0x38). Bypass Mode In bypass mode, FIFO is not operational and, therefore, remains empty. FIFO Mode In FIFO mode, data from measurements of the x-, y-, and z-axes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data. After FIFO stops collecting data, the device continues to operate; therefore, features such as activity detection can be used after FIFO is full. The watermark interrupt continues to occur until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Stream Mode In stream mode, data from measurements of the x-, y-, and z- axes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples and holds the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt continues occurring until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. Trigger Mode In trigger mode, FIFO accumulates samples, holding the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs and an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), FIFO keeps the last n samples (where n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when FIFO is not full. A delay of at least 5 μs must be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples. Additional trigger events cannot be recognized until the trigger mode is reset. To reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode. Note that the FIFO data must be read first because placing the device into bypass mode clears FIFO. Retrieving Data from FIFO The FIFO data is read through the DATAX, DATAY , and DATAZ registers (Address 0x32 to Address 0x37). When the FIFO is in FIFO, stream, or trigger mode, reads to the DATAX, DATAY , and DATAZ registers read data stored in the FIFO. Each time data is read from the FIFO, the oldest x-, y-, and z-axes data is placed into the DATAX, DATAY and DATAZ registers. If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, all axes of interest must be read in a burst (or multiple-byte) read operation. To ensure that the FIFO has completely popped (that is, that new data has completely moved into the DATAX, DATAY, and DATAZ registers), there must be at least 5 μs between the end of reading the data registers and the start of a new read of the FIFO or a read of the FIFO_STATUS register (Address 0x39). The end of reading a data register is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high. For SPI operation at 1.6 MHz or less, the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped. For SPI operation greater than
1.6 MHz, it is necessary to deassert the
delay of 5 μs; otherwise, the delay will not be sufficient. The total delay necessary for 5 MHz operation is at most 3.4 μs. This is not a concern when using I2C mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads.
tests its mechanical and electronic systems simultaneously. 800 Hz or 3200 Hz for the self-test function to operate correctly. Figure 30. Self-Test Output Change Limits vs. Supply Voltage Table 13. Self-Test Output Scale Factors for Different Supply Table 14. Self-Test Output in LSB for ±1.5 g, 10-Bit or Full Table 15. Self-Test Output in LSB for ±3 g, 10-Bit Resolution Table 16. Self-Test Output in LSB for ±6 g, 10-Bit Resolution Table 17. Self-Test Output in LSB for ±12 g, 10-Bit
Table 18. Register Map 0x01 to 0x1D 1 to 29 Reserved Reserved. Do not access. 0x1E 30 OFSX R/W 00000000 X-axis offset. 0x1F 31 OFSY R/W 00000000 Y-axis offset. 0x20 32 OFSZ R/W 00000000 Z-axis offset. 0x21 33 Reserved Reserved. Do not access. 0x22 34 Reserved Reserved. Do not access. 0x23 35 Reserved Reserved. Do not access. 0x24 36 THRESH_ACT R/W 00000000 Activity threshold. 0x25 37 THRESH_INACT R/W 00000000 Inactivity threshold. 0x26 38 TIME_INACT R/W 00000000 Inactivity time. 0x27 39 ACT_INACT_CTL R/W 00000000 Axis enable control for activity and inactivity detection. 0x28 40 Reserved Reserved. Do not access. 0x29 41 Reserved Reserved. Do not access. 0x2A 42 Reserved Reserved. Do not access. 0x2B 43 Reserved Reserved. Do not access. 0x2C 44 BW_RATE R/W 00001010 Data rate and power mode control. 0x2D 45 POWER_CTL R/W 00000000 Power-saving features control. 0x2E 46 INT_ENABLE R/W 00000000 Interrupt enable control. 0x2F 47 INT_MAP R/W 00000000 Interrupt mapping control. 0x30 48 INT_SOURCE R 00000010 Source of interrupts. 0x31 49 DATA_FORMAT R/W 00000000 Data format control. 0x38 56 FIFO_CTL R/W 00000000 FIFO control. 0x39 57 FIFO_STATUS R 00000000 FIFO status.
Rev. B | Page 21 of 32 REGISTER DEFINITIONS Register 0x00—DEVID (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 0 0 1 0 1 The DEVID register holds a fixed device ID code of 0xE5. Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) The OFSX, OFSY , and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 11.6 mg/LSB (that is, 0x7F = +1.5 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. Register 0x24—THRESH_ACT (Read/Write) The THRESH_ACT register is eight bits and holds the threshold value for detecting activity. The data format is unsigned; therefore, the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 46.4 mg/LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled. Register 0x25—THRESH_INACT (Read/Write) The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity. The data format is unsigned; therefore, the magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 46.4 mg/LSB. A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. Register 0x26—TIME_INACT (Read/Write) The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered data (see the Threshold section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register. Register 0x27—ACT_INACT_CTL (Read/Write) D7 D6 D5 D4 ACT ac/dc ACT_X enable ACT_Y enable ACT_Z enable D3 D2 D1 D0 INACT ac/dc INACT_X enable INACT_Y enable INACT_Z enable ACT AC/DC and INACT AC/DC Bits A setting of 0 selects dc-coupled operation, and a setting of 1 enables ac-coupled operation. In dc-coupled operation, the current acceleration magnitude is compared directly with THRESH_ACT and THRESH_INACT to determine whether activity or inactivity is detected. In ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. New samples of acceleration are then compared to this reference value and, if the magnitude of the difference exceeds the THRESH_ACT value, the device triggers an activity interrupt. Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. After the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH_INACT. If the difference is less than the value in THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered. ACT_x Enable Bits and INACT_x Enable Bits A setting of 1 enables x-, y-, or z-axis participation in detecting activity or inactivity. A setting of 0 excludes the selected axis from participation. If all axes are excluded, the function is disabled. For activity detection, all participating axes are logically OR’ ed, causing the activity function to trigger when any of the participating axes exceeds the threshold. For inactiv- ity detection, all participating axes are logically AND’ ed, causing the inactivity function to trigger only if all participating axes are below the threshold for the specified period of time. Register 0x2C—BW_RATE (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 LOW_POWER Rate LOW_POWER Bit A setting of 0 in the LOW_POWER bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the Power Modes section for details). Rate Bits These bits select the device bandwidth and output data rate (see Table 6 and Table 7 for details). The default value is 0x0A, which translates to a 100 Hz output data rate. An output data rate must be selected that is appropriate for the communication protocol and frequency selected. Selecting too high of an output data rate with a low communication speed results in samples being discarded. Register 0x2D—POWER_CTL (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 0 0 Link AUTO_SLEEP Measure Sleep Wakeup Link Bit A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. This bit serially links the activity and inactivity functions.
of the sleep bit in this section for more information. was asleep when the bit was cleared. of operation, and a setting of 1 places the part into sleep mode. wake-up bits. In sleep mode, only the activity function can be used. asleep when the bit was cleared. Table 19. Frequency of Readings in Sleep Mode be configured before enabling their outputs. to the INT2 pin. All selected interrupts for a given pin are OR’ ed. are cleared by reading the INT_SOURCE register.
the ±12 g range, must be clipped to avoid rollover. and a value of 0 sets the device to 4-wire SPI mode. high, and a value of 1 sets the interrupts to active low. set by the range bits to maintain a 2.9 mg/LSB scale factor. and a setting of 0 selects right justified mode with sign extension. These bits set the g range as described in Table 20. Table 20. g Range Setting and Register 0x37 hold the output data for the z-axis. change in data between reads of sequential registers. These bits set the FIFO mode, as described in Table 21. Table 21. FIFO Modes 0 0 Bypass FIFO is bypassed. INT1, and a value of 1 links the trigger event to INT2. Table 22. Samples Bits Functions trigger a watermark interrupt. trigger a watermark interrupt. the FIFO buffer before a trigger event.
Rev. B | Page 24 of 32 0x39—FIFO_STATUS (Read Only) D7 D6 D5 D4 D3 D2 D1 D0 FIFO_TRIG 0 Entries FIFO_TRIG Bit A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, and a 0 means that a FIFO trigger event has not occurred. Entries Bits These bits report how many data values are stored in FIFO. Access to collect the data from FIFO is provided through the DATAX, DATAY , and DATAZ registers. FIFO reads must be done in burst or multiple-byte mode because each FIFO level is cleared after any read (single- or multiple-byte) of FIFO. FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device.
Rev. B | Page 26 of 32 USING SELF-TEST The self-test change is defined as the difference between the acceleration output of an axis with self-test enabled and the acceleration output of the same axis with self-test disabled (see Endnote 4 of Table 1). This definition assumes that the sensor does not move between these two measurements because, if the sensor moves, a non-self-test related shift corrupts the test. Proper configuration of the ADXL312 is also necessary for an accurate self-test measurement. The part must be set with a data rate greater than or equal to 100 Hz. This is done by ensuring that a value greater than or equal to 0x0A is written into the rate bits (Bit D3 through Bit D0) in the BW_RATE register (Address 0x2C). The part also must be placed into normal power operation by ensuring the LOW_POWER bit in the BW_RATE register is cleared (LOW_POWER bit = 0) for accurate self-test measurements. It is recommended that the part be set to full- resolution, 12 g mode to ensure that there is sufficient dynamic range for the entire self-test shift. This is done by setting Bit D3 of the DATA_FORMAT register (Address 0x31) and writing a value of 0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT register (Address 0x31). This results in a high dynamic range for measurement and a 2.9 mg/LSB scale factor. After the part is configured for accurate self-test measurement, several samples of x-, y-, and z-axis acceleration data must be retrieved from the sensor and averaged together. The number of samples averaged is a choice of the system designer, but a recom- mended starting point is 0.1 sec worth of data, which corresponds to 10 samples at 100 Hz data rate. The averaged values must be stored and labeled appropriately as the self-test disabled data, that is, X ST_OFF, YST_OFF, and ZST_OFF. Next, self-test must be enabled by setting Bit D7 of the DATA_FORMAT register (Address 0x31). The output needs some time (about four samples) to settle after enabling self-test. After allowing the output to settle, several samples of the x-, y-, and z-axis acceleration data must be taken again and averaged. It is recommended that the same number of samples be taken for this average as was previously taken. These averaged values must again be stored and labeled appropriately as the value with self-test enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then be disabled by clearing Bit D7 of the DATA_FORMAT register (Address 0x31). With the stored values for self-test enabled and disabled, the self-test change is as follows: XST = XST_ON − XST_OFF YST = YST_ON − YST_OFF ZST = ZST_ON − ZST_OFF Because the measured output for each axis is expressed in LSBs, X ST, YST, and ZST are also expressed in LSBs. These values can be converted to g’s of acceleration by multiplying each value by the 2.9 mg/LSB scale factor, if configured for full-resolution mode. Additionally, Table 14 through Table 17 correspond to the self- test range converted to LSBs and can be compared with the measured self-test change when operating at a V S of 3.3 V. For other voltages, the minimum and maximum self-test output values must be adjusted based on (multiplied by) the scale factors shown in Table 13. If the part was placed into ±1.5 g, 10-bit or full-resolution mode, the values listed in Table 14 must be used. Although the fixed 10-bit mode or a range other than 12 g can be used, a different set of values, as indicated in Table 15 through Table 17, must be used. Using a range below 6 g may result in insufficient dynamic range and must be considered when selecting the range of operation for measuring self-test. If the self-test change is within the valid range, the test is considered successful. Generally, a part is considered to pass if the minimum magnitude of change is achieved. However, a part that changes by more than the maximum magnitude is not necessarily a failure.
Rev. B | Page 30 of 32 SOLDER PROFILE SUPPLIER TP ≥ TC MAXIMUM RAMP UP RATE = 3°C/s MAXIMUM RAMP DOWN RATE = 6°C/s PREHEAT AREA TC TC –5°C TC –5°C TSMAX TL TP tP tL tS USER TP ≤ TC SUPPLIER tP USER tP TEMPERATURE TIME TIME 25°C TO PEAK25 TSMIN 08791-300 Figure 39: Recommended Soldering Profile Table 23: Recommended Soldering Profile1, 2 Profile Feature Condition Sn63/Pb37 Pb-Free Average Ramp Rate (TL to TP) 3°C/second maximum Preheat Minimum Temperature (TSMIN) 100°C 150°C Maximum Temperature (TSMAX) 150°C 200°C Time (TSMIN to TSMAX) (tS) 60 to 120 seconds 60 to 180 seconds TSMAX to TL Ramp-Up Rate 3°C/second Time Maintained Above Liquidous (TL) Liquidous Temperature (TL) 183°C 217°C Time (tL) 60 to 150 seconds 60 to 150 seconds Peak Temperature (TP) 240°C + 0°C/−5°C 260°C + 0°C/−5°C Time Within 5°C of Actual Peak Temperature (tP) 10 to 30 seconds 20 to 40 seconds Ramp-Down Rate 6°C/second maximum Time 25°C to Peak Temperature 6 minutes maximum 8 minutes maximum 1 Based on JEDEC standard J-STD-020D.1 2 For best results, the soldering profile must be in accordance with the recommendations of the manufacturer of the solder paste used.
0.05 MAX
0.02 NOM
0.20 REF
0.20 MIN
COMPLIANT TO JEDEC STANDARDS MO-254-LJJD. Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP] Figure 41. Sample Solder Pad Layout (Land Pattern)
Rev. B | Page 32 of 32 ORDERING GUIDE Model1, 2 Measurement Range Specified Voltage (V) Temperature Range Package Description Package Option ADXL312WACPZ ±1.5 g, ±3 g, ±6 g, ±12 g 3.3 −40°C to +105°C 32-Lead LFCSP CP-32-17 ADXL312WACPZ-RL ±1.5 g, ±3 g, ±6 g, ±12 g 3.3 −40°C to +105°C 32-Lead LFCSP CP-32-17 ADXL312ACPZ ±1.5 g, ±3 g, ±6 g, ±12 g 3.3 −40°C to +105°C 32-Lead LFCSP CP-32-17 ADXL312ACPZ-RL ±1.5 g, ±3 g, ±6 g, ±12 g 3.3 −40°C to +105°C 32-Lead LFCSP CP-32-17 EVAL-ADXL312Z Evaluation Board
1 Z = RoHS Compliant Part
2 W = Qualified for Automotive Applications
The ADXL312W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective ow ners. D08791-0-4/17(B)