ADXL210AQC

ADXL202 AD | Alldatasheet

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REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Low Cost 62 g/610 g Dual Axis iMEM S® Accelerometers with Digital Output ADXL202/ADXL210

FEATURES

2-Axis Acceleration Sensor on a Single IC Chip Measures Static Acceleration as Well as Dynamic Acceleration Duty Cycle Output with User Adjustable Period Low Power <0.6 mA Faster Response than Electrolytic, Mercury or Thermal Tilt Sensors Bandwidth Adjust ment with a Single Cap acitor Per Axis 5 m g Resolution at 60 Hz Bandwidth +3 V to +5.25 V Single Supply Operation 1000 g Shock Survival

APPLICATIONS

Battery Powered Motion Sensing AIN2 = Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 FUNCTIONAL BLOCK DIAGRAM DEMOD R FILT 32kV R FILT 32kV OSCILLATOR X SENSOR Y SENSOR ADXL202/ ADXL210 X OUT Y OUT SELF TESTXFILTVDDVDD C X +3.0V TO +5.25V C DC COM YFILT T2 C Y R SET C O U N T E R mP 0g = 50% DUTY CYCLE T2 = RSET /125MV DEMOD DUTY CYCLE MODULATOR (DCM) GENERAL DESCRIPTION The ADXL202/ADXL210 are low cost, low power, complete 2-axis accelerometers with a measurement range of either – 2 g/– 10 g. The ADXL202/ADXL210 can measure both dy- namic acceleration (e.g., vibration) and static acceleration (e.g., gravity). The outputs are digital signals whose duty cycles (ratio of pulse- width to period) are proportional to the acceleration in each of the 2 sensitive axes. These outputs may be measured directly with a microprocessor counter, requiring no A/D converter or glue logic. The output period is adjustable from 0.5 ms to 10 ms via a single resistor (R SET ). If a voltage output is desired, a voltage output proportional to acceleration is available from the X FILT and YFILT pins, or may be reconstructed by filtering the duty cycle outputs. The bandwidth of the ADXL202/ADXL210 may be set from 0.01 Hz to 5 kHz via capacitors C X and CY. The typical noise floor is 500 mg/ÖHz allowing signals below 5 m g to be resolved for bandwidths below 60 Hz. The ADXL202/ADXL210 is available in a hermetic 14-lead Surface Mount CERPAK, specified over the 0 °C to +70°C commercial or –40°C to +85°C industrial temperature range. iMEM S is a registered trademark of Analog Devices, Inc.

ADXL202/ADXL210–SPECIFICATIONS ADXL202/JQC/AQC ADXL210/JQC/AQC Parameter Conditions Min Typ Max Min Typ Max Units SENSOR INPUT Each Axis Measurement Range 1 – 1.5 – 2 – 8 – 10 g Nonlinearity Best Fit Straight Line 0.2 0.2 % of FS Alignment Error 2 – 1 – 1 Degrees Alignment Error X Sensor to Y Sensor – 0.01 – 0.01 Degrees Transverse Sensitivity 3 – 2 – 2% SENSITIVITY Each Axis Duty Cycle per g T1/T2 @ +25°C 10 12.5 15 3.2 4.0 4.8 %/ g Sensitivity, Analog Output At Pins X FILT, YFILT 312 100 mV/ g Temperature Drift 4 D from +25°C – 0.5 – 0.5 % Rdg ZERO g BIAS LEVEL Each Axis 0 g Duty Cycle T1/T2 25 50 75 42 50 58 % Initial Offset – 2 – 2 g 0 g Offset vs. Temperature 4 D from +25°C 2.0 2.0 m g/°C NOISE PERFORMANCE Noise Density5 @ +25°C 500 1000 500 1000 mg/ÖHz FREQUENCY RESPONSE 3 dB Bandwidth Duty Cycle Output 500 500 Hz 3 dB Bandwidth At Pins X FILT, YFILT 55 k H z Sensor Resonant Frequency 10 14 kHz FILTER RFILT Tolerance 32 k W Nominal – 15 – 15 % Minimum Capacitance At X FILT, YFILT 1000 1000 pF SELF TEST Duty Cycle Change Self-Test “0” to “1” 10 10 % DUTY CYCLE OUTPUT STAGE FSET 125 M W /RSET 125 M W /RSET FSET Tolerance R SET = 125 kW 0.7 1.3 0.7 1.3 kHz Output High Voltage I = 25 mAV S – 200 mV V S – 200 mV mV Output Low Voltage I = 25 mA 200 200 mV T2 Drift vs. Temperature 35 35 ppm/ °C Rise/Fall Time 200 200 ns POWER SUPPLY Operating Voltage Range 3.0 5.25 2.7 5.25 V Specified Performance 4.75 5.25 4.75 5.25 V Quiescent Supply Current 0.6 1.0 0.6 1.0 mA Turn-On Time6 To 99% 160 C FILT + 0.3 160 C FILT + 0.3 ms TEMPERATURE RANGE Operating Range JQC 0 +70 0 +70 °C Specified Performance AQC –40 +85 –40 +85 °C NOTES 1For all combinations of offset and sensitivity variation. 2Alignment error is specified as the angle between the true and indicated axis of sensitivity. 3Transverse sensitivity is the algebraic sum of the alignment and the inherent sensitivity errors. 4Specification refers to the maximum change in parameter from its initial at +25 °C to its worst case value at T MIN to TMAX. 5Noise density ( mg/ÖHz) is the average noise at any frequency in the bandwidth of the part. 6CFILT in mF. Addition of filter capacitor will increase turn on time. Please see the Application section on power cycling. All min and max specifications are guaranteed. Typical specifications are not tested or guaranteed. Specifications subject to change without notice. (TA = TMIN to TMAX, TA = +258C for J Grade only, V DD = +5 V, RSET = 125 kV, Acceleration = 0 g, unless otherwise noted) REV. B–2–

1 NC No Connect

3 ST Self Test

4 COM Common

5 T2 Connect R

6 NC No Connect

7 COM Common

8 NC No Connect

10 X OUT X Axis Duty Cycle Output

11 Y FILT Connect Capacitor for Y Filter

12 X FILT Connect Capacitor for X Filter

conditions for extended periods may affect device reliability. accumulate on the human body and test equipment and can discharge without detection. ESD precautions are recommended to avoid performance degradation or loss of functionality. should be exercised in handling to avoid damage. put changes appropriate to its scale. Figure 1. ADXL202/ADXL210 Nominal Response Due to

0 PERCENTAGE OF SAMPLES

Figure 8. Typical Sensitivity per g at +25 °C Figure 9. Typical Noise at X FILT Output Figure 10. Typical Noise at Digital Outputs Figure 11. Rotational Die Alignment

REV. B–6– DEFINITIONS T1 Length of the “on” portion of the cycle. T2 Length of the total cycle. Duty Cycle Ratio of the “on” time (T1) of the cycle to the total cycle (T2). Defined as T1/T2 for the ADXL202/ ADXL210. Pulsewidth Time period of the “on” pulse. Defined as T1 for the ADXL202/ADXL210. THEORY OF OPERATION The ADXL202/ADXL210 are complete dual axis acceleration measurement systems on a single monolithic IC. They contain a polysilicon surface-micromachined sensor and signal condition- ing circuitry to implement an open loop acceleration measure- ment architecture. For each axis, an output circuit converts the analog signal to a duty cycle modulated (DCM) digital signal that can be decoded with a counter/timer port on a micropro- cessor. The ADXL202/ADXL210 are capable of measuring both positive and negative accelerations to a maximum level of – 2 g or – 10 g. The accelerometer measures static accele ration forces such as gravity, allowing it to be used as a tilt sensor. The sensor is a surface micromachined polysilicon structure built on top of the silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. Deflection of the structure is mea- sured using a differential capacitor that consists of independent fixed plates and central plates attached to the moving mass. The fixed plates are driven by 180 ° out of phase square waves. An acceleration will deflect the beam and unbalance the differential capacitor, resulting in an output square wave whose amplitude is proportional to acceleration. Phase sensitive demodulation techniques are then used to rectify the signal and determine the direction of the acceleration. The output of the demodulator drives a duty cycle modulator (DCM) stage through a 32 k W resistor. At this point a pin is available on each channel to allow the user to set the signal bandwidth of the device by adding a capacitor. This filtering improves measurement resolution and helps prevent aliasing. After being low-pass filtered, the analog signal is converted to a duty cycle modulated signal by the DCM stage. A single resistor sets the period for a complete cycle (T2), which can be set be- tween 0.5 ms and 10 ms (see Figure 12). A 0 g acceleration produces a nominally 50% duty cycle. The acceleration signal can be determined by measuring the length of the T1 and T2 pulses with a counter/timer or with a polling loop using a low cost microcontroller. An analog output voltage can be obtained either by buffering the signal from the X FILT and YFILT pin, or by passing the duty cycle signal through an RC filter to reconstruct the dc value. The ADXL202/ADXL210 will operate with supply voltages as low as 3.0 V or as high as 5.25 V. 0g = 50% DUTY CYCLE T2(s) = RSET (V)/125MV Figure 12. Typical Output Duty Cycle For most applications a single 0.1 mF capacitor, CDC, will ad- equately decouple the accelerometer from signal and noise on the power supply. However, in some cases, especially where digital devices such as microcontrollers share the same power supply, digi- tal noise on the supply may cause interference on the ADXL202/ ADXL210 output. This is often observed as a slowly undulating fluctuation of voltage at X FILT and YFILT. If additional decou- pling is needed, a 100 W (or smaller) resistor or ferrite beads, may be inserted in the ADXL202/ADXL210’s supply line. DESIGN PROCEDURE FOR THE ADXL202/ADXL210 The design procedure for using the ADXL202/ADXL210 with a duty cycle output involves selecting a duty cycle period and a filter capacitor. A proper design will take into account the appli- cation requirements for bandwidth, signal resolution and acqui- sition time, as discussed in the following sections. VDD The ADXL202/ADXL210 have two power supply (V DD) Pins: 13 and 14. These two pins should be connected directly together. COM The ADXL202/ADXL210 have two commons, Pins 4 and 7. These two pins should be connected directly together and Pin 7 grounded. VTP This pin is to be left open; make no connections of any kind to this pin. Decoupling Capacitor C DC A 0.1 mF capacitor is recommended from V DD to COM for power supply decoupling. ST The ST pin controls the self-test feature. When this pin is set to V DD, an electrostatic force is exerted on the beam of the acceler- ometer. The resulting movement of the beam allows the user to test if the accelerometer is functional. The typical change in output will be 10% at the duty cycle outputs (corresponding to 800 mg). This pin may be left open circuit or connected to common in normal use. Duty Cycle Decoding The ADXL202/ADXL210’s digital output is a duty cycle modu- lator. Acceleration is proportional to the ratio T1/T2. The nominal out put of the ADXL202 is: 0 g = 50% Duty Cycle Scale factor is 12.5% Duty Cycle Change per g The nominal out put of the ADXL210 is: 0 g = 50% Duty Cycle Scale factor is 4% Duty Cycle Change per g These nominal values are affected by the initial tolerance of the device including zero g offset error and sensitivity error. T2 does not have to be measured for every measurement cycle. It need only be updated to account for changes due to tempera- ture, (a relatively slow process). Since the T2 time period is shared by both X and Y channels, it is necessary only to mea- sure it on one channel of the ADXL202/ADXL210. Decoding algorithms for various microcontrollers have been developed. Consult the appropriate Application Note.

duty cycle periods between 0.5 ms and 10 ms. parasitic capacitance at this node. applications where accelerations of greater than –2 g are expected. designs, and application notes are available from the factory. the various trade-offs that need to be considered. Resolution: the smallest signal change that needs to be detected. Bandwidth: the highest frequency that needs to be detected. Figure 13. Block Diagram

REV. B–8– Table IV gives typical noise output of the ADXL202/ADXL210 for various CX and CY values. Table IV. Filter Capacitor Selection, C X and CY Peak-to-Peak Noise Estimate 95% Bandwidth C X, CY rms Noise Probability (rms 3 4) 10 Hz 0.47 mF 1.9 m g 7.6 mg 50 Hz 0.10 mF 4.3 m g 17.2 mg 100 Hz 0.05 mF 6.1 m g 24.4 mg 200 Hz 0.027 mF 8.7 m g 35.8 mg 500 Hz 0.01 mF 13.7 m g 54.8 mg CHOOSING T2 AND COUNTER FREQUENCY: DESIGN TRADE-OFFS The noise level is one determinant of accelerometer resolution. The second relates to the measurement resolution of the counter when decoding the duty cycle output. The ADXL202/ADXL210’s duty cycle converter has a resolu- tion of approximately 14 bits; better resolution than the acceler- ometer itself. The actual resolution of the acceleration signal is, however, limited by the time resolution of the counting devices used to decode the duty cycle. The faster the counter clock, the higher the resolution of the duty cycle and the shorter the T2 period can be for a given resolution. The following table shows some of the trade-offs. It is important to note that this is the resolution due to the microprocessors’s counter. It is probable that the accelerometer’s noise floor may set the lower limit on the resolution, as discussed in the previous section. Table V. Trade-Offs Between Microcontroller Counter Rate, T2 Period and Resolution of Duty Cycle Modulator ADXL202/ Counter- ADXL210 Clock Counts RSET Sample Rate per T2 Counts Resolution T2 (ms) (k V) Rate (MHz) Cycle per g (mg) 1.0 124 1000 2.0 2000 250 4.0 1.0 124 1000 1.0 1000 125 8.0 1.0 124 1000 0.5 500 62.5 16.0 5.0 625 200 2.0 10000 1250 0.8 5.0 625 200 1.0 5000 625 1.6 5.0 625 200 0.5 2500 312.5 3.2 10.0 1250 100 2.0 20000 2500 0.4 10.0 1250 100 1.0 10000 1250 0.8 10.0 1250 100 0.5 5000 625 1.6 initial offset. The easiest way to null this offset is with a calibra- tion factor saved on the microcontroller or by a user calibration for zero g. In the case where the offset is calibrated during manu- facture, there are several options, including external EEPROM and microcontrollers with “one-time programmable” features. DESIGN TRADE-OFFS FOR SELECTING FILTER CHARACTERISTICS: THE NOISE/BW TRADE-OFF The accelerometer bandwidth selected will determine the mea- surement resolution (smallest detectable acceleration). Filtering can be used to lower the noise floor and improve the resolution of the accelerometer. Resolution is dependent on both the ana- log filter bandwidth at X FILT and YFILT and on the speed of the microcontroller counter. The analog output of the ADXL202/ADXL210 has a typical bandwidth of 5 kHz, much higher than the duty cycle stage is capable of converting. The user must filter the signal at this point to limit aliasing errors. To minimize DCM errors the analog bandwidth should be less than 1/10 the DCM frequency. Analog bandwidth may be increased to up to 1/2 the DCM frequency in many applications. This will result in greater dy- namic error generated at the DCM. The analog bandwidth may be further decreased to reduce noise and improve resolution. The ADXL202/ADXL210 noise has the characteristics of white Gaussian noise that contributes equally at all frequencies and is described in terms of mg per root Hz; i.e., the noise is proportional to the square root of the band- width of the accelerometer. It is recommended that the user limit bandwidth to the lowest frequency needed by the application, to maximize the resolution and dynamic range of the accelerometer. With the single pole roll-off characteristic, the typical noise of the ADXL202/ADXL210 is determined by the following equation: Noise rms() = 500 mg/ HzæŁ öł · BW · 1. 5æŁ öł At 100 Hz the noise will be: Noise rms() = 500 mg/ HzæŁ öł · 100 · (1. 5)æŁ öł = 6.12 mg Often the peak value of the noise is desired. Peak-to-peak noise can only be estimated by statistical methods. Table III is useful for estimating the probabilities of exceeding various peak values, given the rms value. Table III. Estimation of Peak-to-Peak Noise % of Time that Noise Nominal Peak-to-Peak Will Exceed Nominal Value Peak-to-Peak Value 2.0 · rms 32% 4.0 · rms 4.6% 6.0 · rms 0.27% 8.0 · rms 0.006% The peak-to-peak noise value will give the best estimate of the uncertainty in a single measurement.

shock or other accelerations. mum change in output per degree, the other is at its minimum.

3608 OF TILT 1g

Figure 15. Using a Two-Axis Accelerometer to Measure as an input vector to determine orientation of an object in space. tilted – 90° through gravity. Figure 14. How the X and Y Axes Respond to Changes in

REV. B–10– USING THE ANALOG OUTPUT The ADXL202/ADXL210 was specifically designed for use with its digital outputs, but has provisions to provide analog outputs as well. Duty Cycle Filtering An analog output can be reconstructed by filtering the duty cycle output. This technique requires only passive components. The duty cycle period (T2) should be set to 1 ms. An RC filter with a 3 dB point at least a factor of 10 less than the duty cycle frequency is connected to the duty cycle output. The filter resis- tor should be no less than 100 k W to prevent loading of the output stage. The analog output signal will be ratiometric to the supply voltage. The advantage of this method is an output scale factor of approximately double the analog output. Its disadvan- tage is that the frequency response will be lower than when using the X FILT, YFILT output. XFILT, YFILT Output The second method is to use the analog output present at the X FILT and YFILT pin. Unfortunately, these pins have a 32 k W output impedance and are not designed to drive a load directly. An op amp follower may be required to buffer this pin. The advantage of this method is that the full 5 kHz bandwidth of the accelerometer is available to the user. A capacitor still must be added at this point for filtering. The duty cycle converter should be kept running by using R SET <10 MW . Note that the acceler- ometer offset and sensitivity are ratiometric to the supply volt- age. The offset and sensitivity are nominally: 0 g Offset = V DD/2 2.5 V at +5 V ADXL202 Sensitivity = (60 mV · VS)/g 300 mV/g at +5 V, VDD ADXL210 Sensitivity = (20 mV · VS)/g 100 mV/g at +5 V, VDD USING THE ADXL202/ADXL210 IN VERY LOW POWER An application note outlining low power strategies for the ADXL202/ADXL210 is available. Some key points are pre- sented here. It is possible to reduce the ADXL202/ADXL210’s average current from 0.6 mA to less than 20 mA by using the following techniques: 1. Power Cycle the accelerometer. 2. Run the accelerometer at a Lower Voltage, (Down to 3 V). Power Cycling with an External A/D Depending on the value of the X FILT capacitor, the ADXL202/ ADXL210 is capable of turning on and giving a good reading in 1.6 ms. Most microcontroller based A/Ds can acquire a reading in another 25 ms. Thus it is possible to turn on the ADXL202/ ADXL210 and take a reading in <2 ms. If we assume that a

20 Hz sample rate is sufficient, the total current required to

take 20 samples is 2 ms · 20 samples/s · 0.6 mA = 24 mA aver- age current. Running the part at 3 V will reduce the supply current from 0.6 mA to 0.4 mA, bringing the average current down to 16 mA. The A/D should read the analog output of the ADXL202/ ADXL210 at the X FILT and YFILT pins. A buffer amplifier is recommended, and may be required in any case to amplify the analog output to give enough resolution with an 8-bit to 10-bit converter. Power Cycling When Using the Digital Output An alternative is to run the microcontroller at a higher clock rate and put it into shutdown between readings, allowing the use of the digital output. In this approach the ADXL202/ ADXL210 should be set at its fastest sample rate (T2 = 0.5 ms), with a 500 Hz filter at X FILT and YFILT. The concept is to ac- quire a reading as quickly as possible and then shut down the ADXL202/ADXL210 and the microcontroller until the next sample is needed. In either of the above approaches, the ADXL202/ADXL210 can be turned on and off directly using a digital port pin on the microcontroller to power the accelerometer without additional components. The port should be used to switch the common pin of the accelerometer so the port pin is “pulling down.” CALIBRATING THE ADXL202/ADXL210 The initial value of the offset and scale factor for the ADXL202/ ADXL210 will require calibration for applications such as tilt measurement. The ADXL202/ADXL210 architecture has been designed so that these calibrations take place in the software of the microcontroller used to decode the duty cycle signal. Cali- bration factors can be stored in EEPROM or determined at turn-on and saved in dynamic memory. For low g applications, the force of gravity is the most stable, accurate and convenient acceleration reference available. A reading of the 0 g point can be determined by orientating the device parallel to the earth’s surface and then reading the output. A more accurate calibration method is to make a measurements at +1 g and –1 g. The sensitivity can be determined by the two measurements. To calibrate, the accelerometer’s measurement axis is pointed directly at the earth. The 1 g reading is saved and the sensor is turned 180° to measure –1 g. Using the two readings, the sensi- tivity is: Let A = Accelerometer output with axis oriented to +1 g Let B = Accelerometer output with axis oriented to –1 g then: Sensitivity = [A – B]/2 g For example, if the +1 g reading (A) is 55% duty cycle and the –1 g reading (B) is 32% duty cycle, then: Sensitivity = [55% – 32%]/2 g = 11.5%/g These equations apply whether the output is analog, or duty cycle. Application notes outlining algorithms for calculating accelera- tion from duty cycle and automated calibration routines are available from the factory.

–11–REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead CERPAK (QC-14) 0.291 (7.391) 0.285 (7.239) 0.390 (9.906) MAX PIN 1 0.419 (10.643) 0.394 (10.008) 14 8 0.300 (7.62) 0.345 (8.763) 0.290 (7.366) 0.0125 (0.318) 0.009 (0.229) 0.050 (1.270) 0.016 (0.406) SEATING PLANE 0.020 (0.508) 0.004 (0.102) 0.020 (0.508) 0.013 (0.330) 0.050 (1.27) BSC 0.195 (4.953) 0.115 (2.921) 0.215 (5.461) 0.119 (3.023) C3037b–2–4/99PRINTED IN U.S.A.