ADV7175 AD | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 36
Technical content
REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder ADV7175/ADV7176 © Analog Devices, Inc., 1996 Tel: 617/329-4700 Fax: 617/326-8703
FEATURES
CCIR-601 YCrCb to PAL/NTSC Video Encoder Single 27 MHz Clock Required ( 32 Oversampling) Pixel Port Supports: CCIR-656 4:2:2 8-Bit Parallel Input Format 4:2:2 16-Bit Parallel Input Format SMPTE 170M NTSC Compatible Composite Video Output CCIR624/CCIR601 PAL Compatible Composite Video Output SCART/PeriTV Support YUV Output Mode Simultaneous Composite and S-VHS Y/C or RGB YUV Video Outputs Programmable Luma Filters (Low-Pass/Notch) Square Pixel Support (Slave Mode) Allows Subcarrier Phase Locking with External Video Source 10-Bit DAC Resolution for Encoded Video Channels 8-Bit DAC Resolution for RGB Output YUV Interpolation for Accurate Subcarrier Construction Programmable Subcarrier Frequency and Phase Programmable LUMA Delay Color Signal Control/Burst Signal Control Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Master/Slave Operation Supported Master Mode Timing Programmability Macrovision Antitaping Facility Rev 6.1/7.x (ADV7175 Only)* Close Captioning Support Teletext Support (Passthrough Mode) On-Board Color Bar Generation On-Board Voltage Reference 2-Wire Serial MPU Interface (I 2C Compatible) +5 V CMOS Monolithic Construction 44-Pin PQFP Thermally Enhanced Package
APPLICATIONS
Digital Satellite/Cable Systems (Set Top Boxes/IRDs) Video Games CD Video/Karaoke Professional Studio Quality PC Video/Multimedia GENERAL DESCRIPTION The ADV7175/ADV7176 is an integrated digital video encoder that converts Digital CCIR-601 4:2:2 component video data into a standard analog baseband television signal compatible with world wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In addition to the composite output signal, there is the facility to out- put S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or RGB format is simultaneously available at the analog outputs with the composite video signal. Each analog output generates a standard video-level signal into a doubly terminated 75 Ω load. (Continued on page 6) FUNCTIONAL BLOCK DIAGRAM YUV TO RBG MATRIXRESET VAA 888 10 888 10 888 10INTER- POLATOR YCrCb TO YUV MATRIX SIN/COS DDS BLOCK 10 10 M U L T I P L E X E R VIDEO TIMING GENERATOR I2C MPU PORT 4:2:2 TO 4:4:4 INTER- POLATOR VOLTAGE REFERENCE CIRCUIT SCLOCK SDATA ALSB HSYNC FIELD/VSYNC BLANK CLOCK GND GREEN/ LUMA/ Y RED/ CHROMA/ V BLUE/ COMPOSITE/ U COMPOSITE V REF R SET COMP V LOW-PASS FILTER ADD BURST ADV7175/ADV7176 10-BIT DAC COLOR DATA P7–P0 P15–P8 10-BIT DAC 10-BIT DAC REAL-TIME CONTROL CIRCUIT SCRESET/RTC INTER- POLATOR ADD BURST INTER- POLATOR ADD SYNC U LOW-PASS FILTER Y LOW-PASS FILTER 10-BIT DAC *This device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 and other intellectual property rights. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the devic e. Please contact sales office for latest Macrovision version available.
ADV7175/ADV7176–SPECIFICATIONS REV. A–2– Model ADV7175/ADV7176 Parameter Conditions 1 Min Typ Max Units STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity ± 1 LSB Differential Nonlinearity Guaranteed Monotonic ± 1 LSB DIGITAL INPUTS Input High Voltage, V INH 2V Input Low Voltage, V INL 0.8 V Input Current, IIN VIN = 0.4 V or 2.4 V ± 1 µA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output High Voltage, V OH ISOURCE = 400 µA 2.4 V Output Low Voltage, V OL ISINK = 3.2 mA 0.4 V Floating-State Leakage Current 10 µA Floating-State Output Capacitance 10 pF ANALOG OUTPUTS Output Current3 33 34.7 37 mA Output Current4 8m A Full-Scale DAC Output 182.5 IRE LSB Size 33.9 µA DAC-to-DAC Matching 25 % Output Compliance, V OC 0 +1.4 V Output Impedance, ROUT 15 k Ω Output Capacitance, C OUT IOUT = 0 mA 30 pF VOLTAGE REFERENCE Voltage Reference Range, V REF IVREFOUT = 20 µA 1.112 1.235 1.359 V POWER REQUIREMENTS5 VAA 5V IDAC 6 140 155 mA ICCT 7 110 150 mA Power Supply Rejection Ratio COMP = 0.1 µF 0.02 0.5 %/% DYNAMIC PERFORMANCE8 Luma Bandwidth9 (Low-Pass Filter) NTSC Mode Stopband Cutoff >50 dB Attenuation 7.5 MHz Pass Band Cutoff <0.06 dB Attenuation 2.3 MHz Chroma Bandwidth NTSC Mode Stopband Cutoff <40 dB Attenuation 3.6 MHz Pass Band Cutoff >0.1 dB Attenuation 1.0 MHz Luma Bandwidth9 (Low-Pass Filter) PAL MODE Stopband Cutoff >50 dB Attenuation 8.0 MHz Pass Band Cutoff <0.06 dB Attenuation 3.4 MHz Chroma Bandwidth PAL MODE Stopband Cutoff <40 dB Attenuation 4.0 MHz Pass Band Cutoff >0.1 dB Attenuation 1.3 MHz Differential Gain 0.8 % Differential Phase 0.8 Degree Differential Gain Lower Power Mode 7 % Differential Phase Lower Power Mode 2 Degree SNR RMS 60 dB rms SNR Peak Periodic 56 dB p-p Hue Accuracy 1.0 Degree Color Saturation Accuracy 1.0 % NOTES 1± 5% for all versions. 2Temperature range T MIN to TMAX: 0°C to 70°C. 3Full drive into 37.5 Ω load. 4Minimum drive with buffered/scaled output load. 5Power measurements are taken with Clock Frequency = 27 MHz. Max T J = 100°C. 6IDAC is the total current to drive all four DACs. Turning off one DAC reduces I DAC correspondingly. 7ICCT (Circuit Currrent) is the continuous currrent required to drive the device. 8Guaranteed by characterization. 9These specifications are for the low-pass filter only. For the other internal filters please see Figure 3. Specifications subject to change without notice. (VAA = +5 V1, VREF = 1.235 V RSET = 150 V. All specifications TMIN to TMAX 2 unless otherwise noted)
Parameter Min Typ Max Units Condition Chroma Nonlinear Gain 0.6 ± % Referenced to 40 IRE Chroma Nonlinear Phase 1 ±° NTSC Chroma Nonlinear Phase 1.7 ±° PAL Chroma/Luma Intermod 0.2 ± % Referenced to 714 mV (NTSC) Chroma/Luma Intermod 0.4 ± % Referenced to 700 mV (PAL) Chroma/Luma Gain Ineq 0.6 ± % Chroma/Luma Delay Ineq 1 ns Luminance Nonlinearity 0.8 ± % Chroma AM Noise 60 dB Chroma PM Noise 59 dB TIMING–SPECIFICATIONS2 Parameter Min Typ Max Units Condition MPU PORT1 SCLOCK Frequency 0 100 kHz SCLOCK High Pulse Width, t 1 4.0 µs SCLOCK Low Pulse Width, t 2 4.7 µs Hold Time (Start Condition), t 3 4.0 µs After this period the first clock pulse is gener ated Setup Time (Start Condition), t 4 4.7 µs Relevant for repeated start condition. Data Setup Time, t5 250 ns SDATA, SCLOCK Rise Time, t 6 1 µs SDATA, SCLOCK Fall Time, t 7 300 ns Setup Time (Stop Condition), t 8 4.7 µs ANALOG OUTPUTS1, 5 Analog Output Delay 5 ns DAC Analog Output Skew 0 ns CLOCK CONTROL AND PIXEL PORT6 FCLOCK 24.52 27 29.5 MHz Clock High Time t9 8n s Clock Low Time t10 8n s Data Setup Time t11 3.5 ns Data Hold Time t12 1n s Control Setup Time t 11 4n s Control Hold Time t 12 2n s Digital Output Access Time t 13 24 ns Digital Output Hold Time t 14 6n s Pipeline Delay t15 37 Clock Cycles NOTES 1Guaranteed by characterization. 2TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog Output Load ≤ 3 pF. 3± 5% for all versions. 4Temperature range (T MIN to TMAX); 0°C to +70°C. 5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. 6Pixel Port consists of the following inputs: Pixel Inputs: P15–P0 Pixel Controls: HSYNC, FIELD/VSYNC, BLANK Clock Input: CLOCK Specifications subject to change without notice. ADV7175/ADV7176 REV. A –3– (VAA = +5 V3, VREF = 1.235 V RSET = 150 V. All specifications TMIN to TMAX 4 unless otherwise noted)
REV. A –5– PIN DESCRIPTION Mnemonic Input/Output Function P15-P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or 16-Bit YCrCb Pixel Port (P15–P0). P0 represents the LSB. CLOCK I TTL Clock Input. Requires a stable 27 MHz reference Clock for proper operation. Alternatively a 24.52 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. HSYNC I/O HSYNC (Modes 1 & 2) Control Signal. This pin may be configured to output (Mas- ter Mode) or accept (Slave Mode) Sync signals. FIELD/VSYNC I/O Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This pin may be configured to output (Master Mode) or accept (Slave Mode) these control signals. BLANK I/O Video Blanking Control Signal. The pixel inputs are ignored when this is logic level “0.” This signal is optional. SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a subcarrier reset pin, in which case a high to low transition on this pin will reset the subcarrier to field 0. Alternatively it may be con- figured as a Real Time Control (RTC) input. V REF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.2 V). RSET I A 150 Ω resistor connected from this pin to GND is used to control full-scale ampli- tudes of the video signals. COMP O Compensation Pin. Connect a 0.1 µF capacitor from COMP to V AA. COMPOSITE O PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for NTSC and 1300 mV for PAL. RED/CHROMA/V O RED/S-VHS C/V Analog Output. GREEN/LUMA/Y O GREEN/S-VHS Y/Y Analog Output. BLUE/COMPOSITE/U O BLUE/Composite/U Analog Output. SCLOCK I MPU Port Serial Interface Clock Input. SDATA I/O MPU Port Serial Data Input/Output. ALSB I TTL Address Input. This signal set up the LSB of the MPU address. RESET I The input resets the on chip timing generator and sets the ADV7175/ADV7176 into default mode. This is NTSC operation, Timing Slave Mode 0, 8-bit operation, 2 × composite & S VHS out. VAA P +5 V Supply. GND G Ground Pin. PIN CONFIGURATION 12 13 14 15 16 17 18 19 20 21 22 40 39 3841424344 36 35 3437 PIN 1 IDENTIFIER TOP VIEW (Not to Scale) VREF COMPOSITE BLUE/COMPOSITE/U VAA GND VAA GREEN/LUMA/Y BLANK P13 P14 P15 HSYNC FIELD/ VSYNC ALSB VAA P10 P11 P12 GND V AA RED/CHROMA/V COMP SDATA SCLOCK GND VAA GND RESET CLOCK GND VAA GND SCRESET/ RTC R SET ADV7175/ADV7176 PQFP
Mode 0 (CCIR-656): Slave Option. The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data. (if not used) pins should be tied high in this mode.
268 PIXELS 1440 PIXELS
4 PIXELS 4 PIXELS
280 PIXELS 1440 PIXELS
Figure 13. Timing Mode 0 (Slave Mode) Mode 0 (CCIR-656): Master Option. relative to the video waveform are illustrated in Figure 16. Figure 14. Timing Mode 0 (NTSC Master Mode)
Figure 25. Timing Mode 3 (PAL)
- Burst is disabled on lines 1–5, 311–319 and 623–625 in
rect location for the new clock frequencies. the output timing control signals.
compatible) microprocessor bus driving multiple peripherals. carry information between any device connected to the bus. Figure 27. The LSB sets either a read or write operation.
1 X10101 A 1
0 WRITE
1 READ
0 X10101 A 1
quency registers should not be accessed independently.
- In Read Mode the highest subaddress register contents will
- In Write Mode, the data for the invalid byte will be not be
quence and the start and stop conditions. Figure 28. Bus Data Transfer Figure 29 shows bus write and read sequences. Figure 29. Write and Read Sequences
Figure 30. Subaddress Register address until a stop command on the bus is performed. NTSC pedestal control registers in terms of its configuration. The communications register is an eight bit write-only register. These bits are setup to point to the required starting address. Mode Register 0 is a 8-bit wide register. Mode Register 0. This register can be read from as well written to.
0 YC OUTPUT
1 RGB/YUV OUTPUT
0 DISABLE
1 ENABLE
0 PEDESTAL OFF
1 PEDESTAL ON
Figure 31. Mode Register 0
Mode Register 1 is a 8-bit wide register. Register 1. This register can be read from as well written to. if any of the DACs are not required in the application.
0 NORMAL
1 POWER DOWN
0 INTERLACED
1 NON-INTERLACED
Figure 32. Mode Register 1 PAL (M) and PAL (N) standard video. ADV7175/ADV7176 is configured in PAL mode. filter. The filters are illustrated in Figures 3 to 11.
Figure 33 shows how the frequency is set up by the 4 registers. Figure 33. Subcarrier Frequency Register This 8-bit wide register is used to set up the subcarrier phase. Timing Register 0 is a 8-bit wide register. represents a delay of 74 ns.
0 ENABLE
1 DISABLE
0 SLAVE TIMING
1 MASTER TIMING
Figure 34. Timing Register 0
0 ENABLE COLOR
1 DISABLE COLOR
0 RGB OUTPUT
1 YUV OUTPUT
0 ENABLE BURST
1 DISABLE BURST
0 CCIR624 OUTPUT
1 CCIR601 OUTPUT
Figure 38. Mode Register 2 Figure 40. Mode Register 3 must be set to Logic Level “1” before MR26 is set. odd and even fields. Figure 39 shows the four control registers. turning the pedestal off on the equivalent line. Figure 39. Pedestal Control Registers Mode Register 3 is an 8-bit wide register. switch when MR 37 is set to Logic “1”.
REV. A–22– APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of VAA pins on the ADV7175/ADV7176 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7175/ADV7176 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three terminal volt- age regulator for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the ADV7175/ADV7176 should be iso- lated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7175/ADV7176 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V CC), and not the analog power plane. Analog Signal Interconnect The ADV7175/ADV7176 should be located as close as possible to the output connectors to minimize noise pickup and reflec- tions due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital inputs, especially pixel data inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7175/ADV7176 so as to minimize reflections. The ADV7175/ADV7176 should have no inputs left floating. Any inputs that are not required should be tied to ground. The ADV7175/ADV7176 is a highly integrated circuit contain- ing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be ap- plied to the system level design such that high speed, accurate performance is achieved. The “Recommended Analog Circuit Layout” shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7175/ADV7176 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of V AA and GND pins should by minimized so as to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV7175/ADV7176 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7175/ADV7176, the analog output traces, and all the digital signal traces leading up to the ADV7175/ ADV7176. The ground plane is the board’s common ground plane. Power Planes The ADV7175/ADV7176 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (V AA). This power plane should be connected to the regular PCB power plane (V CC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7175/ADV7176. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7175/ADV7176 power pins and voltage refer- ence circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. Supply Decoupling For optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable
26 S VIDEO
35 SCRESET/RTC
Figure 41. Recommended Analog Circuit Layout ADV7175/ADV7176 in the correct sequence. Figure 42. Circuit to Generate 13.5 MHz
mission. Closed captioning is transmitted during the blanked active line time of line 21 of the odd fields. bit. These consist of two 8-bit bytes. The data for these bytes is stored in closed captioning data registers 0 and 1. on scan line 284. The data for this operation is stored in closed captioning extended data registers 0 and 1. ADV7176. All pixels inputs are ignored during lines 21 and 282.
50 IRE
40 IRE
Figure 43. Closed Captioning Waveform (NTSC)
130.8 IRE
100 IRE
7.5 IRE
0 IRE
Figure 44. NTSC Composite Video Levels Figure 45. NTSC Luma Video Levels Figure 46. NTSC Chroma Video Levels Figure 47. NTSC RGB Video Levels
Figure 48. NTSC Composite Video Levels Figure 49. NTSC Luma Video Levels Figure 50. NTSC Chroma Video Levels Figure 51. NTSC RGB Video Levels
REV. A–28– APPENDIX 4 REGISTER VALUES PAL (M) Mode Register 0 06 Hex Mode Register 1 00 Hex Subcarrier Frequency Register 0 A3 Hex Subcarrier Frequency Register 1 EF Hex Subcarrier Frequency Register 2 E6 Hex Subcarrier Frequency Register 3 21 Hex Subcarrier Phase Register 00 Hex Timing Register 0 08 Hex Closed Captioning Ext Register 0 00 Hex Closed Captioning Ext Register 1 00 Hex Closed Captioning Register 0 00 Hex Closed Captioning Register 1 00 Hex Timing Register 1 00 Hex Mode Register 2 00 Hex Pedestal Control Register 0 00 Hex Pedestal Control Register 1 00 Hex Pedestal Control Register 2 00 Hex Pedestal Control Register 3 00 Hex Mode Register 3 00 Hex PAL (N) Mode Register 0 05 Hex Mode Register 1 00 Hex Subcarrier Frequency Register 0 CB Hex Subcarrier Frequency Register 1 8A Hex Subcarrier Frequency Register 2 09 Hex Subcarrier Frequency Register 3 2A Hex Subcarrier Phase Register 00 Hex Timing Register 0 08 Hex Closed Captioning Ext Register 0 00 Hex Closed Captioning Ext Register 1 00 Hex Closed Captioning Register 0 00 Hex Closed Captioning Register 1 00 Hex Timing Register 1 00 Hex Mode Register 2 00 Hex Pedestal Control Register 0 00 Hex Pedestal Control Register 1 00 Hex Pedestal Control Register 2 00 Hex Pedestal Control Register 3 00 Hex Mode Register 3 00 Hex The ADV7175/ADV7176 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite o/p with all DACs powered up and with the BLANK input control disabled. Ad- ditionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. In the examples shown the timing mode is set to Mode 0 in slave format. TR02–TR00 of the timing register 0 control the timing modes. For a detailed explanation of each bit in the command registers, please turn to the register programming section of the data sheet. TR07 should be toggled after setting up a new tim- ing mode. Timing Register 1 provides additional control over the position and duration of the timing signals. In the examples this register is programmed in default mode. NTSC Mode Register 0 04 Hex Mode Register 1 00 Hex Subcarrier Frequency Register 0 16 Hex Subcarrier Frequency Register 1 7C Hex Subcarrier Frequency Register 2 F0 Hex Subcarrier Frequency Register 3 21 Hex Subcarrier Phase Register 00 Hex Timing Register 0 08 Hex Closed Captioning Ext Register 0 00 Hex Closed Captioning Ext Register 1 00 Hex Closed Captioning Register 0 00 Hex Closed Captioning Register 1 00 Hex Timing Register 1 00 Hex Mode Register 2 00 Hex Pedestal Control Register 0 00 Hex Pedestal Control Register 1 00 Hex Pedestal Control Register 2 00 Hex Pedestal Control Register 3 00 Hex Mode Register 3 00 Hex PAL (B, D, G, H, I) Mode Register 0 01 Hex Mode Register 1 00 Hex Subcarrier Frequency Register 0 CB Hex Subcarrier Frequency Register 1 8A Hex Subcarrier Frequency Register 2 09 Hex Subcarrier Frequency Register 3 2A Hex Subcarrier Phase Register 00 Hex Timing Register 0 08 Hex Closed Captioning Ext Register 0 00 Hex Closed Captioning Ext Register 1 00 Hex Closed Captioning Register 0 00 Hex Closed Captioning Register 1 00 Hex Timing Register 1 00 Hex Mode Register 2 00 Hex Pedestal Control Register 0 00 Hex Pedestal Control Register 1 00 Hex Pedestal Control Register 2 00 Hex Pedestal Control Register 3 00 Hex Mode Register 3 00 Hex
If an output filter is required for the composite output of the ADV7175/ADV7176. The following filter can be used. Plots of the filter characteristics can be produced on request. Figure 56. Output Filter
Figure 63. Modulated Ramp Measurements (PAL)
REV. A–34– INDEX Contents Page No. Contents Page No. APPENDIX 1. BOARD DESIGN AND LAYOUT
REV. A –35– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Plastic Quad Flatpack (S-44) 0.548 (13.925) 0.546 (13.875) TOP VIEW (PINS DOWN) 0.033 (0.84) 0.029 (0.74) 0.398 (10.11) 0.390 (9.91) 0.016 (0.41) 0.012 (0.30) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) SEATING PLANE 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) 8° 0.8°
C213a–4– /96PRINTED IN U.S.A. –36–