ADV7171WBSZ-REEL

ADV7171KSUZ AD | Alldatasheet

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Digital PAL/NTSC Video Encoder with 10-Bit SSAF™ and Advanced Power Management ADV7170/ADV7171 Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent ri ghts of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.

FEATURES

ITU-R1 BT601/656 YCrCb to PAL/NTSC video encoder High quality 10-bit video DACs SSAF (super sub-alias filter) Advanced power management features CGMS (copy generation management system) WSS (wide screen signalling) Simultaneous Y , U, V, C output format NTSC M, PAL M/N2, PAL B/D/G/H/I, PAL60 Single 27 MHz clock required (×2 oversampling) 80 dB video SNR 32-bit direct digital synthesizer for color subcarrier Multistandard video output support Composite (CVBS) Components S-Video (Y/C), YUV, and RGB EuroSCART output (RGB + CVBS/LUMA) Component YUV + CHROMA Video input data port supports CCIR-656 4:2:2 8-bit parallel input format 4:2:2 16-bit parallel input format Programmable simultaneous composite and S-Video or RGB (SCART)/YUV video outputs Programmable luma filters (low-pass [PAL/NTSC]) notch, ex tende d (SSA F, CIF, and Q CIF ) Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz, 1.2 MHz and 2.0 MHz], CIF and QCIF) Programmable VBI (vertical blanking interval) Programmable subcarrier frequency and phase Programmable LUMA delay Individual on/off control of each DAC CCIR and square pixel operation Integrated subcarrier locking to external video source Color signal control/burst signal control Interlaced/noninterlaced operation Complete on-chip video timing generator Programmable multimode master/slave operation Macrovision® AntiTaping Rev. 7.1 (ADV7170 only) Closed captioning support Teletext insertion port (PAL-WST) On-board color bar generation On-board voltage reference 2-wire serial MPU interface (I 2C®-compatible and Fast I2C) Single supply 5 V or 3.3 V operation Small 44-lead MQFP/TQFP packages Industrial temperature grade = −40°C to +85°C

APPLICATIONS

High performance DVD playback systems, portable video equipment including digital still cameras and laptop PCs, video games, PC video/multimedia and digital satellite/cable systems (set-top boxes/IRD)

1 ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced

CCIR recommendations). 2 Throughout the document N is referenced to PAL- Combination -N. 3 Protected by U.S. Patents 4,631,603;, 4,577,216, 4,819,098; and other intellectual property rights. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Please contact sales office for latest Macrovision version available. 4 Refer to Table 8 for complete operating details. 10-BIT DAC 10-BIT DAC 10-BIT DAC 10 10-BIT DAC M U L T I P L E X E R DAC D (PIN 27) DAC C (PIN 26) DAC B (PIN 31) DAC A (PIN 32) V REF RSET COMP VOLTAGE REFERENCE CIRCUIT ADV7170/ADV7171 GNDSCRESET/RTCALSB TTXREQ TTX SDATASCLOCKCLOCK REAL-TIME CONTROL CIRCUIT I2C MPU PORTVIDEO TIMING GENERATOR 4:2:2 TO 4:4:4 INTER- POLATOR 8 V U 8 Y YCrCb TO YUV MATRIX ADD BURST ADD SYNC POWER MANAGEMENT CONTROL (SLEEP MODE)VAA RESET COLOR DATA P7–P0 P15–P8 HSYNC BLANK FIELD/VSYNC INTER- POLATOR INTER- POLATOR PROGRAMMABLE LUMINANCE FILTER PROGRAMMABLE CHROMINANCE FILTER CGMS AND WSS INSERTION BLOCK TELETEXT INSERTION BLOCK 10 U V 1010 SIN/COS DDS BLOCK YUV TO RGB MATRIX 00221-001 Figure 1. Functional Block Diagram Protected by U.S. Patents 5,343,196; 5,442,355; and other intellectual property rights.

Rev. C | Page 2 of 64 TABLE OF CONTENTS Closed Captioning Even Field Data Register 1 to 0 (CED15 to Closed Captioning Odd Field Data Registers 1 to 0 (CCD15 NTSC Pedestal/PAL Teletext Control Registers 3 to 0 (PCE15 to PCE0, PCO15 to PCO0)/(TXE15 to TXE0, TXO15 to Teletext Request Control Register TC07 (TC07 to TC00) .... 36

Rev. C | Page 3 of 64 Appendix 3—Copy Generation Management System

REVISION HISTORY

3/09—Rev. B to Rev. C 6/05—Rev. A to Rev. B 6/02—Starting Rev. A to Rev. B Changes to Package Thermal Performance section...9

Rev. C | Page 4 of 64 SPECIFICATIONS VAA = 5 V ± 5%1, VREF = 1.235 V , RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted. Table 1. Parameter Conditions 1 Min Typ Max Unit STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity RSET = 300 Ω ±0.6 LSB Differential Nonlinearity Guaranteed monotonic ±1 LSB DIGITAL INPUTS Input High Voltage, VINH 2 V Input Low Voltage, VINL 0.8 V Input Current, IIN V IN = 0.4 V or 2.4 V ±1 μA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS Output High Voltage, VOH I SOURCE = 400 μA 2.4 V Output Low Voltage, VOL I SINK = 3.2 mA 0.4 V Three-State Leakage Current 10 μA Three-State Output Capacitance 10 pF ANALOG OUTPUTS Output Current3 RSET = 150 Ω, RL = 37.5 Ω 3 34.7 37 mA Output Current4 RSET = 1041 Ω, RL = 262.5 Ω 5 mA DAC-to-DAC Matching 1.5 % Output Compliance, VOC 0 +1.4 V Output Impedance, ROUT 30 kΩ Output Capacitance, COUT I OUT = 0 mA 30 pF VOLTAGE REFERENCE Reference Range, VREF I VREFOUT = 20 μA 1.142 1.235 1.327 V POWER REQUIREMENTS5 VAA 4.75 5.0 5.25 V Normal Power Mode IDAC (max)6 RSET = 150 Ω, RL = 37.5 Ω 150 155 mA IDAC (min)6 RSET = 1041 Ω, RL = 262.5 Ω 20 mA ICCT7 75 95 mA Low Power Mode IDAC (max)6 80 mA IDAC (min)6 20 mA ICCT7 75 95 mA Sleep Mode IDAC8 0.1 μA ICCT9 0.001 μA Power Supply Rejection Ratio COMP = 0.1 μF 0.01 0.5 %/% 1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Full drive into 37.5 Ω doubly terminated load. 4 Minimum drive current (used with buffered/scaled output load). 5 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C. 6 IDAC is the total current (min corresponds to 5 mA output per DAC; max corresponds to 37 mA output per DAC) to drive all four DACs. Turning off individual DACs reduces IDAC correspondingly. 7 ICCT (circuit current) is the continuous current required to drive the device. 8 Total DAC current in sleep mode. 9 Total continuous current during sleep mode.

Rev. C | Page 5 of 64 Table 2. Parameter Conditions 1 Min Typ Max Unit STATIC PERFORMANCE3 Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity RSET = 300 Ω ±0.6 LSB Differential Nonlinearity Guaranteed monotonic ±1 LSB DIGITAL INPUTS3 Input High Voltage, VINH 2 V Input Low Voltage, VINL 0.8 V Input Current, IIN3, 4 VIN = 0.4 V or 2.4 V ±1 μA Input Capacitance, CIN 10 pF DIGITAL OUTPUTS3 Output High Voltage, VOH I SOURCE = 400 μA 2.4 V Output Low Voltage, VOL I SINK = 3.2 mA 0.4 V Three-State Leakage Current 10 μA Three-State Output Capacitance 10 pF ANALOG OUTPUTS3 Output Current4, 5 RSET = 150 Ω, RL = 37.5 Ω 33 34.7 37 mA Output Current6 RSET = 1041 Ω, RL = 262.5 Ω 5 mA DAC-to-DAC Matching 2.0 % Output Compliance, VOC 0 1.4 V Output Impedance, ROUT 30 kΩ Output Capacitance, COUT I OUT = 0 mA 30 pF POWER REQUIREMENTS3, 7 VAA 3.0 3.3 3.6 V Normal Power Mode IDAC (max)8 RSET = 150 Ω, RL = 37.5 Ω 150 155 mA IDAC (min)8 RSET = 1041 Ω, RL = 262.5 Ω 20 mA ICCT9 35 mA Low Power Mode IDAC (max)8 80 mA IDAC (min)8 20 mA ICCT9 35 mA Sleep Mode IDAC10 0.1 μA ICCT11 0.001 μA Power Supply Rejection Ratio COMP = 0.1 μF 0.01 0.5 %/% 1 The min/max specifications are guaranteed over this range. The min/max values are typical over 3.0 V to 3.6 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Guaranteed by characterization. 4 Full drive into 37.5 Ω load. 5 DACs can output 35 mA typically at 3.3 V (RSET = 150 Ω and RL = 37.5 Ω); optimum performance obtained at 18 mA DAC current (RSET = 300 Ω and RL = 75 Ω). 6 Minimum drive current (used with buffered/scaled output load). 7 Power measurements are taken with clock frequency = 27 MHz. Max TJ = 110°C. 8 IDAC is the total current (min corresponds to 5 mA output per DAC, max corresponds to 38 mA output per DAC) to drive all four DACs. Turning off individual DACs reduces IDAC correspondingly. 9 ICCT (circuit current) is the continuous current required to drive the device. 10 Total DAC current in sleep mode. 11 Total continuous current during sleep mode.

Rev. C | Page 6 of 64 DYNAMIC SPECIFICATIONS VAA = 5 V ± 5%1, VREF = 1.235 V , RSET = 150 Ω. All specifications TMIN to TMAX2, unless otherwise noted. Table 3. Parameter Conditions 1 Min Typ Max Unit Differential Gain3, 4 Normal power mode 0.3 0.7 % Differential Phase3, 4 Normal power mode 0.4 0.7 Degrees Differential Gain3, 4 Lower power mode 1.0 2.0 % Differential Phase3, 4 Lower power mode 1.0 2.0 Degrees SNR3, 4(Pedestal) RMS 80 dB rms SNR3, 4(Pedestal) Peak periodic 70 dB p-p SNR3, 4(Ramp) RMS 60 dB rms SNR3, 4(Ramp) Peak periodic 58 dB p-p Hue Accuracy3, 4 0.7 1.2 Degrees Color Saturation Accuracy3, 4 0.9 1.4 % Chroma Nonlinear Gain3, 4 Referenced to 40 IRE 0.6 ±% Chroma Nonlinear Phase3 4 0.3 0.5 ±Degrees Chroma/Luma Intermod3, 4 0.2 0.4 ±% Chroma/Luma Gain Inequality3, 4 1.0 1.4 ±% Chroma/Luma Delay Inequality3, 4 0.5 2.0 ns Luminance Nonlinearity3, 4 0.8 1.4 ±% Chroma AM Noise3, 4 82 85 dB Chroma PM Noise3, 4 79 81 dB 1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Guaranteed by characterization. 4 These specifications are for the low-pass filter only and are guaranteed by design. Table 4. Parameter Conditions 1 Min Typ Max Unit Differential Gain3 Normal power mode 1.0 % Differential Phase3 Normal power mode 0.5 Degrees Differential Gain3 Lower power mode 0.6 % Differential Phase3 Lower power mode 0.5 Degrees SNR3 (Pedestal) RMS 78 dB rms SNR3 (Pedestal) Peak periodic 70 dB p-p SNR3 (Ramp) RMS 60 dB rms SNR3 (Ramp) Peak periodic 58 dB p-p Hue Accuracy3

1.0 Degrees

Color Saturation Accuracy3 1.0 % Luminance Nonlinearity3, 4 1.4 ±% Chroma AM Noise3, 4 80 dB Chroma PM Noise3, 4 79 dB Chroma Nonlinear Gain3, 4 Referenced to 40 IRE 0.6 ±% Chroma Nonlinear Phase3, 4 0.3 0.5 ±Degrees Chroma/Luma Intermod3, 4 0.2 0.4 ±% 1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 Guaranteed by characterization. 4 These specifications are for the low-pass filter only and are guaranteed by design. For other internal filters, see Table 10.

Rev. C | Page 7 of 64 TIMING SPECIFICATIONS Table 5. Parameter Conditions Min Typ Max Unit MPU PORT3, 4 SCLOCK Frequency 0 400 kHz SCLOCK High Pulse Width, t1 0.6 μs SCLOCK Low Pulse Width, t2 1.3 μs Hold Time (Start Condition), t3 After this period the first clock is generated Relevant for repeated start condition 0.6 μs Setup Time (Start Condition), t4 0.6 μs Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 μs ANALOG OUTPUTS3, 5 Analog Output Delay 7 ns DAC Analog Output Skew 0 ns CLOCK CONTROL AND PIXEL PORT5, 6 fCLOCK 27 MHz Clock High Time, t9 8 ns Clock Low Time, t10 8 ns Data Setup Time, t11 3.5 ns Data Hold Time, t12 4 ns Control Setup Time, t11 4 ns Control Hold Time, t12 3 ns Digital Output Access Time, t13 11 16 ns Digital Output Hold Time, t144 8 ns Pipeline Delay, t154

48 Clock cycles

TELETEXT3, 4, 7 Digital Output Access Time, t16 20 ns Data Setup Time, t17 2 ns Data Hold Time, t18 6 ns RESET CONTROL3, 4 RESET Low Time 6 ns 1 The min/max specifications are guaranteed over this range. The min/max values are typical over 4.75 V to 5.25 V range. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 TTL input values are 0 V to 3 V, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤ 10 pF.

4 Guaranteed by characterization

5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.

6 Pixel port consists of the following:

Pixel inputs: P15–P0 Pixel controls: HSYNC, FIELD/VSYNC, BLANK Clock input: CLOCK

7 Teletext port consists of the following:

Teletext output: TTXREQ Teletext input: TTX

Rev. C | Page 8 of 64 Table 6. Parameter Conditions Min Typ Max Unit MPU PORT3, 4 SCLOCK Frequency 0 400 kHz SCLOCK High Pulse Width, t1 0.6 μs SCLOCK Low Pulse Width, t2 1.3 μs Hold Time (Start Condition), t3 After this period the first clock is generated Relevant for repeated start condition 0.6 μs Setup Time (Start Condition), t4 0.6 μs Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 μs ANALOG OUTPUTS3, 5 Analog Output Delay 7 ns DAC Analog Output Skew 0 ns CLOCK CONTROL AND PIXEL PORT4, 5, 6 fCLOCK 27 MHz Clock High Time, t9 8 ns Clock Low Time, t10 8 ns Data Setup Time, t11 3.5 ns Data Hold Time, t12 4 ns Control Setup Time, t11 4 ns Control Hold Time, t12 3 ns Digital Output Access Time, t13 12 ns Digital Output Hold Time, t14 8 ns Pipeline Delay, t15 48 Clock cycles TELETEXT3, 4, 7 Digital Output Access Time, t16 23 ns Data Setup Time, t17 2 ns Data Hold Time, t18 6 ns RESET CONTROL3, 4 RESET Low Time 6 ns 1 The max/min specifications are guaranteed over this range. The max/min values are typical over 3.0 V to 3.6 V range. 2 Ambient temperature range TMIN to TMAX: −40°C to +85°C. The die temperature, TJ, must always be kept below 110°C. 3 TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load ≤10 pF. 5 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition Pixel inputs: P15–P0 Pixel controls: HSYNC, FIELD/VSYNC, BLANK Clock input: CLOCK Teletext output: TTXREQ Teletext input: TTX

Figure 2. MPU Port Timing Diagram Figure 3. Pixel and Control Data Timing Diagram

4 CLOCK

3 CLOCK

Figure 4. Teletext Timing Diagram

1 Analog output short circuit to any power supply or GND can be of an

an ADI patented thermal coastline lead frame construction. TQFP package, θJA in still air on a four-layer PCB is 53.2°C/W . Output Current + ICCT) × θJA] + Ambient Temperature. Table 8. Allowable Operating Conditions for KS and KSU

4 DAC ON Double 75R1 Yes +70°C max +70°C max No

4 DAC ON Low Power2 Yes Yes Yes No

4 DAC ON Buffering3 Yes Yes Yes Yes

3 DAC ON Double 75R Yes Yes Yes No

3 DAC ON Low Power Yes Yes Yes Yes

3 DAC ON Buffering Yes Yes Yes Yes

4 DAC ON Buffering Yes Yes

1 DAC ON Double 75R refers to a condition where the DACs are terminated

in a double 75R load and low power mode is disabled.

2 DAC ON Low Power refers to a condition where the DACs are terminated

in a double 75R load and low power mode is enabled.

3 DAC ON Buffering refers to a condition where the DAC current is reduced

to 5 mA and external buffers are used to drive the video load. degradation or loss of functionality.

32 DAC A

31 DAC B

30 VAA

27 DAC D

28 VAA

29 GND

33 VREF

26 DAC C

25 COMP

24 SDATA

23 SCLOCK

Figure 5. Pin Configuration Table 9. Pin Function Descriptions P15 to P0 I 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7 to P0) or 16-Bit YCrCb Pixel Port (P15 to P0). mode) or accept (slave mode) sync signals. configured to output (master mode) or accept (slave mode) these control signals. 18 ALSB I TTL Address Input. This signal sets up the LSB of the MPU address.

22 RESET I The input resets the on-chip timing generator and sets the ADV7170/ADV7171 into default

S-Video out, and DAC B powered on and DAC D powered off. 23 SCLOCK I MPU Port Serial Interface Clock Input. 24 SDATA I/O MPU Port Serial Data Input/Output. 26 DAC C O RED/S-Video C/V Analog Output. 27 DAC D O GREEN/S-Video Y/Y Analog Output. 31 DAC B O BLUE/Composite/U Analog Output. 33 V REF I/O Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

34 R SET I A 150 Ω resistor connected from this pin to GND is used to control full-scale amplitudes

Rev. C | Page 12 of 64 Pin No. Mnemonic Input/ Output Description 35 SCRESET/RTC I This pin can be configured as an input by setting MR22 and MR21 of Mode Register 2. It can be configured as a subcarrier reset pin, in which case a low-to-high transition on this pin resets the subcarrier to Field 0. Alternatively, it may be configured as a real-time control (RTC) input. 36 TTXREQ O Teletext Data Request Signal. Defaults to GND when teletext not selected. Enables backward compatibility to ADV7175/ADV7176. 37 TTX I Teletext Data. Defaults to VAA when teletext not selected. Enables backward compatibility to ADV7175/ADV7176. 44 CLOCK I TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation.

Rev. C | Page 13 of 64 GENERAL DESCRIPTION The ADV7170/ADV7171 are integrated digital video encoders that convert digital CCIR-601 4:2:2 8- or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. The on-board SSAF (super sub-alias filter) with extended luminance frequency response and sharp stop band attenuation enables studio-quality video playback on modern TVs, giving optimal horizontal line resolution. An advanced power management circuit enables optimal control of power consumption in both normal operating modes and power-down or sleep modes. The ADV7170/ADV7171 support both PAL and NTSC square pixel operation. The parts also incorporate WSS and CGMS-A data control generation. The output video frames are synchronized with the incoming data timing reference codes. Optionally, the encoder accepts and can generate HSYNC, VSYNC, and FIELD timing signals. These timing signals can be adjusted to change pulse width and position while the part is in the master mode. The encoder requires a single, two-times pixel rate (27 MHz) clock for standard operation. Alternatively, the encoder requires a 24.5454 MHz clock for NTSC or 29.5 MHz clock for PAL square pixel mode operation. All internal timing is generated on-chip. A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. The ADV7170/ADV7171 modes are set up over a 2-wire, serial bidirectional port (I 2C-compatible) with two slave addresses. Functionally, the ADV7170 and ADV7171 are the same with the exception that the ADV7170 can output the Macrovision anticopy algorithm. The ADV7170/ADV7171 are packaged in a 44-lead MQFP package and a 44-lead TQFP package. DATA PATH DESCRIPTION For PAL B/D/G/H/I/M/N, and NTSC M and N modes, Y crCb 4:2:2 data is input via the CCIR-656 compatible pixel port at a 27 MHz data rate. The pixel data is demultiplexed to form three data paths. Y typically has a range of 16 to 235; Cr and Cb typically have a range of 128 ± 112. However, it is possible to input data from 1 to 254 on Y , Cb, and Cr. The ADV7170/ ADV7171 support PAL (B, D, G, H, I, M, N) and NTSC (with and without pedestal) standards. The appropriate SYNC, BLANK , and burst levels are added to the YCrCb data. Macrovision antitaping (ADV7170 only), closed-captioning, and teletext levels are also added to Y , and the resultant data is interpolated to a rate of 27 MHz. The interpolated data is filtered and scaled by three digital FIR filters. The U and V signals are modulated by the appropriate sub- carrier sine/cosine phases and added together to make up the chrominance signal. The luma (Y) signal can be delayed 1 to 3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. The luma and chroma signals are then added together to make up the composite video signal. All edges are slew rate limited. The YCrCb data is also used to generate RGB data with appropriate SYNC and BLANK levels. The RGB data is in synchronization with the composite video output. Alternatively, analog YUV data can be generated instead of RGB. The four 10-bit DACs can be used to output the following: Composite video + RGB video. Composite video + YUV video. Two composite video signals + LUMA and CHROMA (Y/C) signals. Alternatively, each DAC can be individually powered off if not required. Video output levels are illustrated in Appendix 6—Waveforms.

responses, a CIF response, and a QCIF response that are shown in Table 10 and Table 11 and Figure 6 to Figure 18. Table 10. Luminance Internal Filter Specifications Table 11. Chrominance Internal Filter Specifications

Figure 18. QCIF Chroma Filter

Rev. C | Page 18 of 64 The ADV7170/ADV7171 can be configured to generate 100/7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for PAL. These are enabled by setting MR17 of Mode Register 1 to Logic Level 1. SQUARE PIXEL MODE The ADV7170/ADV7171 can be used to operate in square pixel mode. For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. When the ADV7171 is configured for PAL square pixel mode, it supports 768 active pixels per line. NTSC square pixel mode supports 640 active pixels per line. COLOR SIGNAL CONTROL The color information can be switched on and off the video output using Bit MR24 of Mode Register 2. BURST SIGNAL CONTROL The burst information can be switched on and off the video output using Bit MR25 of Mode Register 2. NTSC PEDESTAL CONTROL The pedestal on both odd and even fields can be controlled on a line-by-line basis using the NTSC pedestal control registers. This allows the pedestals to be controlled during the vertical blanking interval. PIXEL TIMING DESCRIPTION The ADV7170/ADV7171 operate in either 8-bit or 16-bit YCrCb mode. 8-Bit YCrCb Mode This default mode accepts multiplexed YCrCb inputs through the P7 to P0 pixel inputs. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, and so on. The Y , Cb, and Cr data are input on a rising clock edge. 16-Bit YCrCb Mode This mode accepts Y inputs through the P7 to P0 pixel inputs and multiplexed CrCb inputs through the P15 to P8 pixel inputs. The data is loaded on every second rising edge of CLOCK. The inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, and so on. SUBCARRIER RESET Together with the SCRESET/RTC pin and Bit MR22 and Bit MR21 of Mode Register 2, the ADV7170/ADV7171 can be used in subcarrier reset mode. The subcarrier resets to Field 0 at the start of the following field when a low-to-high transition occurs on this input pin. REAL-TIME CONTROL Together with the SCRESET/RTC pin and Bit MR22 and Bit MR21 of Mode Register 2, the ADV7170/ADV7171 can be used to lock to an external video source. The real-time control mode allows the ADV7170/ADV7171 to automatically alter the subcarrier frequency to compensate for line length variation. When the part is connected to a device that outputs a digital data stream in the RTC format (such as a ADV7185 video decoder, shown in Figure 19), the part automatically changes to the compensated subcarrier frequency on a line-by-line basis. This digital data stream is 67 bits wide, and the subcarrier is contained in Bit 0 to Bit 21. Each bit is 2 clock cycles long. 00Hex should be written into all four subcarrier frequency registers when using this mode. VIDEO TIMING DESCRIPTION The ADV7170/ADV7171 are intended to interface to off-the- shelf MPEG1 and MPEG2 decoders. Consequently, the ADV7170/ADV7171 accept 4:2:2 YCrCb pixel data via a CCIR-656 pixel port, and they have several video timing modes of operation that allow them to be configured as either system master video timing generators or as slaves to the system video timing generator. The ADV7170/ADV7171 generate all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7170/ADV7171 calculate the width and placement of analog sync pulses, blanking levels, and color burst envelopes. Color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. In addition, the ADV7170/ADV7171 support a PAL or NTSC square pixel operation in slave mode. The part requires an input pixel clock of 24.5454 MHz for NTSC and an input pixel clock of 29.5 MHz for PAL. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. The ADV7170/ADV7171 have four distinct master and four distinct slave timing configurations. Timing Control is established with the bidirectional SYNC , BLANK, and FIELD/VSYNC pins. Timing Mode Register 1 can also be used to vary the timing pulse widths where they occur in relation to each other.

5 BITS

4 BITS

14 BITS

BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7170/ADV7171. Figure 19. RTC Timing and Connections video) and EAV (end active video) time codes in the pixel data. before and after each line during active picture and retrace.

268 CLOCK 1440 CLOCK

4 CLOCK 4 CLOCK

280 CLOCK 1440 CLOCK

Figure 20. Timing Mode 0 (Slave Mode)

After power-up, it is necessary to execute a reset operation. ADV7171 is automatically set up to operate in NTSC mode. Mode Register 0 are set to Logic Level 0, except Bit MR44. enables the 7.5 IRE pedestal. SCH phase jumps at the start of the four or eight field sequence. which means the output video tracks the unstable input video. SCH phase resets to Field 0). compatible) microprocessor bus driving multiple peripherals. carry information between any devices connected to the bus. each device and are shown in Figure 33 and Figure 34. the ADV7170/ADV7171 to Logic Level 0 or Logic Level 1.

1 X10101 A 1

0 WRITE

1 READ

Figure 33. ADV7170 Slave Address

0 X10101 A 1

Figure 34. ADV7171 Slave Address reads information from the peripheral.

010010 NTSC PEDESTAL CONTROL REG 0/

010011 NTSC PEDESTAL CONTROL REG 1/

010101 NTSC PEDESTAL CONTROL REG 3/

010100 NTSC PEDESTAL CONTROL REG 2/

SHOULD BE PROGRAMMED TO 1F FOR ACCURATE FSC. Figure 37. Subaddress Register Map

0 NORMAL

1 POWER-DOWN

0 INTERLACED

1 NONINTERLACED

0 DISABLE

1 ENABLE

Figure 39. Mode Register 1

0 ENABLE COLOR

1 DISABLE COLOR

0 ENABLE BURST

1 DISABLE BURST

Figure 40. Mode Register 2

0 COMPOSITE

1 GREEN/LUMA/Y

1 BIT REQUEST

Figure 41. Mode Register 3 configures the SCRESET/RTC pin as a subcarrier reset input. This bit switches between two active video line durations. (710 pixels NTSC; 702 pixels PAL). ADV7171, reducing the DAC current by 45%.

A Logic Level 0 must be written to this bit. various operations under the control of Mode Register 3. These bits are read-only and indicate the revision of the device. control has priority; that is, VBI data insertion does not work. configurations is shown in Table 12. fourth DAC (0 = CVBS; 1 = CHROMA). forces the output color to black for 00000000 pixel input video data. Table 12. DAC Output Configuration Matrix

0 YC OUTPUT

1 RGB/YUV OUTPUT

0 PEDESTAL OFF

1 PEDESTAL ON

0 RGB OUTPUT

1 YUV OUTPUT

Figure 42. Mode Register 4 various operations under the control of Mode Register 4. information encoded on all RGB outputs. signal for 3 lines in NTSC mode and 2.5 lines in PAL mode. ADV7170/ADV7171 are configured in PAL mode. selected. This mode is enabled by a Logic Level 1. and resume normal operation. A Logic Level 0 should be written to this bit.

0 ENABLE

1 DISABLE

0 SLAVE TIMING

1 MASTER TIMING

Figure 43. Timing Register 0 These bits control the timing mode of the ADV7170/ ADV7171. the Timing and Control section. represents a delay of 74 ns. power-up, reset or changing to a new timing mode. Timing Register 1 is an 8-bit-wide register. the master mode timing signals. These bits adjust the HSYNC pulse width. Mode 2, these bits adjust the VSYNC pulse width. data. This allows the Cr and Cb components to be swapped.

Figure 50. Teletext Control Register Figure 51. CGMS_WSS Register 0 shows the operations under the control of this register. These bits are CGMS data bits only. shows the operations under the control of this register. Figure 52. CGMS_WSS Register 1 Figure 53. CGMS_ WSS Register 2

Rev. C | Page 38 of 64 APPENDICES APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7170/ADV7171 are highly integrated circuits containing both precision analog and high speed digital circuitry. They have been designed to minimize interference effects of the high speed digital circuitry on the integrity of the analog circuitry. It is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. Figure 54 shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7170/ADV7171 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of V AA and GND pins should be minimized to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV7170/ADV7171 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7170/ADV7171, the analog output traces, and all the digital signal traces leading up to the ADV7170/ ADV7171. The ground plane is the board’s common ground plane. Power Planes The ADV7170, the ADV7171, and any associated analog circuitry should each have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7170/ADV7171. The metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7170/ADV7171 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 μF ceramic capacitor decoupling. Each group of V AA pins on the ADV7170/ ADV7171 must have at least one 0.1 μF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7170/ADV7171 contain circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three- terminal voltage regulator for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the ADV7170/ADV7171 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7170/ADV7171 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V CC) and not to the analog power plane. Analog Signal Interconnect The ADV7170/ADV7171 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. Digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7170/ADV7171 to minimize reflections. The ADV7170/ADV7171 should have no inputs left floating. Any inputs that are not required should be tied to ground.

35 SCRESET/RTC

15 HSYNC

16 FIELD/VSYNC

17 BLANK

22 RESET

37 TTX

36 TTXREQ

44 CLOCK

Figure 54. Recommended Analog Circuit Layout Figure 55. Circuit to Generate 13.5 MHz

Captioning Extended Data Register 1. captioning data, unlike other 2-byte deep buffering systems. are double bytes, on Line 21, or a TV does not recognize them.

50 IRE

40 IRE

7 CYCLES

Figure 56. Closed Captioning Waveform (NTSC)

and even fields. CGMS data can only be transmitted when the ADV7170/ADV7171 are configured in NTSC mode. registers (no CRC is calculated; it must be calculated by the user).

0 IRE

Figure 57. CGMS Waveform Diagram

The ADV7170/ADV7171 support wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. of each of these bits is as shown below. falling edge of HSYNC) is available for the insertion of video.

0 Camera Mode

1 Film Mode

0 Standard Coding

1 Motion Adaptive Color Plus

0 No Helper

1 Modulated Helper

0 No surround sound information

1 Surround sound mode

Figure 58. WSS Waveform Diagram

signal in order to deliver TTX data. window is not open if the teletext enable bit (MR35) is set to 0. lines is controlled by teletext setup registers.

45 BYTES (360 BITS) – PAL

Figure 59. Teletext VBI Line Figure 60. Teletext Functionality Diagram

Figure 61. NTSC Composite Video Levels Figure 62. NTSC Luma Video Levels Figure 63. NTSC Chroma Video Levels Figure 64. NTSC RGB Video Levels

Figure 65. NTSC Composite Video Levels Figure 66. NTSC Luma Video Levels Figure 67. NTSC Chroma Video Levels Figure 68. NTSC RGB Video Levels

powered up and with the BLANK input control disabled. this register is programmed in default mode. Table 13. PAL B/D/G/H/I (F Table 14. PAL M (F

Table 15. PAL N (FSC = 4.43361875 MHz) Table 16. PAL60 (FSC = 4.43361875 MHz) Table 17. Power-Up Reset Values NTSC (FSC = 3.5795454 MHz)

625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = SOURCE

Figure 83. 100/0/75/0 PAL Color Bars

625 LINE PAL NO FILTERING SYNCHRONOUS SYNC = A

Figure 84. 100/0/75/0 PAL Color Bars Luminance

Figure 85. 100/0/75/0 Pal Color Bars Chrominance

525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = A

Figure 86. 100/7.5/75/7.5 NTSC Color Bars

525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = SOURCE

Figure 87. 100/7.5/75/7.5 NTSC Color Bars Luminance

525 LINE NTSC NO FILTERING SYNCHRONOUS SYNC = B

Figure 88. 100/7.5/75/7.5 NTSC Color Bars Chrominance

625 LINE PAL

Figure 89. PAL Vector Plot

525 LINE NTSC

Figure 90. NTSC Vector Plot

0.25 MIN

0.80 BSC

1.95 REF

Figure 103. 44-Lead Thin Plastic Quad Flat Package [MQFP]

12.00 BSC SQ

0.08 MAX

Figure 104. 44-Lead Thin Plastic Quad Flat Package [TQFP]

1.60 REF

Figure 105. 44-Lead Metric Quad Flat Package [MQFP]

Rev. C | Page 63 of 64 NOTES

Rev. C | Page 64 of 64 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. Printed in the U.S.A. D00221-0-3/09(C)