ADV7160/ADV7172 96-Bit, 220 MHz True-Color Video RAM-DAC
Document overview
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Technical content
REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a 96-Bit, 220 MHz True-Color Video RAM-DAC ADV7160/ADV7162 © Analog Devices, Inc., 1995 Tel: 617/329-4700 Fax: 617/326-8703 MODES OF OPERATION 1600× 1200× 30/24-Bit Resolution @ 85 Hz Screen Refresh 1600× 1200× 16/15-Bit Resolution @ 85 Hz Screen Refresh 1600× 1200× 8-Bit Resolution @ 85 Hz Screen Refresh
APPLICATIONS
High Resolution, True Color Graphics Professional Color Prepress Imaging Digital TV (HDTV, Digital Video) SPEED GRADES @ 220 MHz @ 170 MHz @ 140 MHz GENERAL DESCRIPTION The ADV7160/ADV7162® is a 96-bit pixel port Video RAM- DAC with color enhanced triple 10-bit DACs. The device also includes a PLL and 64 × 64 hardware cursor. The ADV7160/ ADV7162 is specifically designed for use in the graphics sub- system of high performance, color graphics workstations and windows accelerators. (Continued on page 15)
FEATURES
96-Bit Pixel Port for 1600 × 1280 × 24 Screen Resolution
220 MHz, 24-Bit (30-Bit Gamma Corrected) True-Color
Triple 10-Bit “Gamma Correcting” D/A Converters 2% (max) DAC to DAC Color Matching Triple 256 × 10 (256 x 30) Color Palette RAM On-Board User Definable Cursor (64 × 64 × 2) Three Color Overlay Cursor Palette RAM Fully Programmable On-Board PLL RS-343A/RS-170 Compatible RGB Analog Outputs Tri-Level SYNC Functionality TTL Compatible Digital Inputs Standard MPU I/O Interface Programmable Pixel Port: 24-Bit, 16-Bit, 15-Bit & 8-Bit (Pseudo) Pixel Data Serializer: Multiplexed Pixel Input Ports; 2:1, 4:1, 8:1 +5 V CMOS Monolithic Construction 160-Lead Plastic Quad Flatpack (QFP): ADV7162 160-Lead “Thermally Enhanced” QFP (PQUAD): ADV7160 FUNCTIONAL BLOCK DIAGRAM ADV is a registered trademark of Analog Devices, Inc. P I X E L I N P U T M U L T I P L E X E R JTAG TEST ACCESS PORT TDOMPU PORT 10 (8+2) DATA TO PALETTES CONTROL REGISTERS PIXEL MASK REGISTER COMMAND REGISTERS (CR1-CR5) GNDTDITCKTMSC1 D9–D0C0 PIXEL DATA (P7-P0) ODD/ EVEN LOADIN SCKIN LOADOUT COMP CLOCK CONTROL 3 x 256 COLOR PALETTE
3 COLOR OVERLAY PALETTE
A PALETTE SELECTS (PS0, PS1) SYNCOUT IOR CLOCK PRGCKOUT SCKOUT SELECTOR ADDRESS REGISTER (A10-A0) TRISYNC SYNC BLANK B C D S E L E C T O R CER/W GREEN REGISTER BLUE REGISTER RED REGISTER ADV7160/ ADV7162
2 COLOR CURSOR PALETTE
(MR1) BYPASS COLOR MODE MATRIX PIXEL MASK COLOR MODE MATRIX RED 256 x 10 GREEN 256 x 10 BLUE 256 x 10 RED 3 x 10 GREEN 3 x 10 BLUE 3 x 10 PS FUNCTION DECODE LOGIC 2 10 RED 3 x 10 GREEN 3 x 10 BLUE 3 x 10 64 x 64 CURSOR GENERATOR GREEN DAC BLUE DAC RED DAC BLANK AND SYNC LOGIC VREF R SET 10 10 CLOCK DIVIDE & SYNCHRONIZATION CIRCUITRY ÷32, ÷16, ÷8, ÷4 VOLTAGE REFERENCE CIRCUIT REVISION REGISTER PLL REGISTERS CURSOR REGISTERS TEST REGISTERS ID REGISTER STATUS REGISTER VAA
ADV7160/ADV7162–SPECIFICATIONS REV. 0–2– Parameter Min Typ Max Units Test Conditions/Comments STATIC PERFORMANCE (DAC Gain Setting = 3996) Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity ± 1 LSB Differential Nonlinearity ± 1 LSB Guaranteed Monotonic Gray Scale Error ± 5 % Gray Scale Coding Binary DIGITAL INPUTS Input High Voltage, V INH 2V Input Low Voltage, V INL 0.8 V Input Current, IIN ± 10 µAV IN = 0.4 V or 2.4 V Input Capacitance, C IN 10 pF CLOCK INPUTS (CLOCK, CLOCK) Input High Voltage, V INH VAA – 1.0 V Input Low Voltage, V INL VAA – 1.6 V Input Current, IIN ± 10 µAV IN = 0.4 V or 2.4 V Input Current, IIN (JTAG Inputs) ± 50 µAV IN = 0.4 V or 2.4 V Input Capacitance, C IN 10 pF DIGITAL OUTPUTS Output High Voltage, V OH 2.4 V I SOURCE = 400 µA Output Low Voltage, V OL 0.4 V I SINK = 3.2 mA Floating-State Leakage Current 20 µA Floating-State Output Capacitance 20 pF ANALOG OUTPUTS (DAC Gain Setting = 3996) Gray Scale Current Range 15 22 mA Output Current White Level Relative to Blank 17.69 19.05 20.40 mA White Level Relative to Black 16.74 17.62 18.50 mA Black Level Relative to Blank 0.95 1.44 1.90 mA Blank Level 0 5 50 µA Sync Disabled Blank Level 6.29 7.62 8.96 mA Sync Enabled Sync Level 0 5 50 µA Tri-Sync Level Relative to Blank 6.29 7.62 8.96 mA LSB Size 17.22 µA DAC to DAC Matching 1 3 % Output Compliance, V OC 0 +1.4 V Output Impedance, ROUT 30 k Ω Output Capacitance, C OUT 30 pF I OUT = 0 mA VOLTAGE REFERENCE Voltage Reference Range, V REF 1.14 1.235 1.26 V V REF = 1.235 V for Specified Performance Input Current, IVREF 5 µA POWER REQUIREMENTS VAA 5V IAA 3 475 mA For 220 MHz Operation (ADV7160) 440 mA For 170 MHz Operation (ADV7160) 410 mA For 140 MHz Operation (ADV7160) IAA 3 450 mA For 220 MHz Operation (ADV7162) 400 mA For 170 MHz Operation (ADV7162) 360 mA For 140 MHz Operation (ADV7162) Power Supply Rejection Ratio 0.1 %/% COMP = 0.1 µF DYNAMIC PERFORMANCE Clock and Data Feedthrough 4, 5 –30 dB Glitch Impulse 50 pV secs DAC to DAC Crosstalk6 –23 dB NOTES 1± 5% for all versions. 2Temperature range (T MIN to TMAX): 0°C to +70°C. 3Pixel Port is continuously clocked with data corresponding to a linear ramp. T J = 100oC. 4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 6DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions. Specifications subject to change without notice. (VAA 1 = +5 V; VREF = +1.235 V; RSET = 280 Ω . IOR, IOG, IOB (RL = 37.5 Ω , CL = 10 pF). All specifications TMIN to TMAX 2 unless otherwise noted.)
REV. 0 –3– CLOCK CONTROL AND PIXEL PORT 4 Parameter 220 MHz 170 MHz 140 MHz Units Conditions/Comments Version Version Version fCLOCK 220 170 140 MHz max Pixel CLOCK Rate t1 4.5 5.88 7.14 ns min Pixel CLOCK Cycle Time t2 2.0 2.5 2.86 ns min Pixel CLOCK High Time t3 2.0 2.5 2.86 ns min Pixel CLOCK Low Time t4 10 10 10 ns max Pixel CLOCK to LOADOUT Delay fLOADIN LOADIN Clocking Rate 2:1 Multiplexing 110 85 70 MHz max 4:1 Multiplexing 55 42.5 35 MHz max 8:1 Multiplexing 27.5 21.25 17.5 MHz max t
5 LOADIN Cycle Time
2:1 Multiplexing 9.1 11.77 14.29 ns min 4:1 Multiplexing 18.18 23.53 28.58 ns min 8:1 Multiplexing 36.36 47.1 57.16 ns min t
6 LOADIN High Time
2:1 Multiplexing 4 5 6 ns min 4:1 Multiplexing 8 9 12 ns min 8:1 Multiplexing 15 18 23 ns min t
7 LOADIN Low Time
2:1 Multiplexing 4 5 6 ns min 4:1 Multiplexing 8 9 12 ns min 8:1 Multiplexing 15 18 23 ns min t 8 0 0 0 ns min Pixel Data Setup Time t9 5 5 5 ns min Pixel Data Hold Time t10 0 0 0 ns min LOADOUT to LOADIN Delay τ-t11 5 τ-5 τ-5 τ-5 ns max LOADOUT to LOADIN Delay tPD
6 Pipeline Delay
2:1 Multiplexing 9 9 9 CLOCKs (1 × CLOCK = t1) 4:1 Multiplexing 11 11 11 CLOCKs 8:1 Multiplexing 15 15 15 CLOCKs t 12 10 10 10 ns max Pixel CLOCK to PRGCKOUT Delay t13 5 5 5 ns max SCKIN to SCKOUT Delay t14 5 5 5 ns min BLANK to SCKIN Setup Time t15 0 0 0 ns min BLANK to SCKIN Hold Time ANALOG OUTPUTS 7 Parameter 220 MHz 170 MHz 140 MHz Units Conditions/Comments Version Version Version t16 25 25 25 ns typ Analog Output Delay t17 1 1 1 ns typ Analog Output Rise/Fall Time t18 25 25 25 ns typ Analog Output Transition Time tSK 2 2 2 ns max RGB Analog Output Skew 0 0 0 ns typ TIMING CHARACTERISTICS1 (VAA 2= +5 V; VREF = +1.235 V; RSET = 280 Ω . IOR, IOG, IOB (RL = 37.5 Ω , CL = 10 pF). All specifications TMIN to TMAX 3 unless otherwise noted.)
1TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are VAA–0.8 V to VAA–1.8 V, with input rise/fall times ≤ 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Data-Bus (D0–D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT & SCKOUT ≤ 30 pF. 3Temperature range (T MIN to TMAX); 0°C to +70°C. 7Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10% and 90% points of full-scale transition. clock and data feedthrough). 8t23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V. true values for the device and as such are independent of external loading capacitances. Specifications subject to change without notice. Figure 1. Load Circuit for Databus Access and Relinquish Times
40 MHz max
1TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 3Temperature range (T MIN to TMAX); 0°C to +70°C. after the delay. This measurement is repeated multiple times and the RMS value is determined. Specifications subject to change without notice. Figure 2. JTAG Timing
Figure 14. Microprocessor Port (MPU) Interface Timing maximum rating conditions for extended periods may affect device reliability. accumulate on the human body and test equipment and can discharge without detection. ESD precautions are recommended to avoid performance degradation or loss of functionality.
220 MHz 170 MHz 140 MHz
1All devices are specified for 0 °C to +70°C operation. 2Contact Sales Office for latest information on package design. 4ADV7162 is packaged in a standard 160-pin plastic quad flatpack, QFP.
REV. 0–12– ADV7160/ADV7162 ADV7160/ADV7162 PIN ASSIGNMENTS Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic 1G 2 A 41 CLOCK 81 D9 121 R1 C 2G 2 B 42 SCKIN 82 D8 122 R1 D 3G 2 C 43 SCKOUT 83 D7 123 R2 A 4G 2 D 44 V AA 84 D6 124 R2 B 5G 3 A 45 PRGCKOUT 85 D5 125 R2 C 6G 3 B 46 GND 86 D4 126 R2 D 7G 3 C 47 LOADOUT 87 D3 127 R3 A 8G 3 D 48 LOADIN 88 D2 128 R3 B 9G 4 A 49 B0 A 89 D1 129 R3 C
10 G4 B 50 B0 B 90 D0 130 R3 D
11 G4 C 51 B0 C 91 C1 131 R4 A
12 G4 D 52 B0 D 92 C0 132 V AA
13 G5 A 53 B1 A 93 R /W 133 V AA
14 G5 B 54 B1 B 94 CE 134 GND
15 G5 C 55 B1 C 95 TCK 135 GND
16 G5 D 56 B1 D 96 TMS 136 R4 B
17 G6 A 57 B2 A 97 GND 137 R4 C
18 G6 B 58 B2 B 98 V AA 138 R4 D
19 G6 C 59 B2 C 99 TDO 139 R5 A
20 G6 D 60 B2 D 100 TDI 140 R5 B
21 G7 A 61 B3 A 101 SYNCOUT 141 R5 C
22 V AA 62 B3 B 102 TRISYNC 142 R5 D
23 V AA 63 B3 C 103 ODD/ EVEN 143 R6 A
24 GND 64 B3 D 104 SYNC 144 R6 B
25 GND 65 B4 A 105 BLANK 145 R6 C
26 V AA 66 B4 B 106 V REF 146 R6 D
27 GND 67 B4 C 107 IOB 147 R7 A
28 PLL REF 68 B4 D 108 COMP 148 R7 B
29 G7 B 69 B5 A 109 R SET 149 R7 C
30 G7 C 70 B5 B 110 V AA 150 GND
31 G7 D 71 B5 C 111 V AA 151 V AA
32 PS0 A 72 B5 D 112 GND 152 R7 D
33 PS0 B 73 B6 A 113 IOG 153 G0 A
34 PS0 C 74 B6 B 114 IOR 154 G0 B
35 PS0 D 75 B6 C 115 R0 A 155 G0 C
36 PS1 A 76 B6 D 116 R0 B 156 G0 D
37 PS1 B 77 B7 A 117 R0 C 157 G1 A
38 PS1 C 78 B7 B 118 R0 D 158 G1 B
39 PS1 D 79 B7 C 119 R1 A 159 G1 C
40 CLOCK 80 B7 D 120 R1 B 160 G1 D
REV. 0 –13– PIN FUNCTION DESCRIPTION Mnemonic Function Pixel Port (TTL Compatible Inputs): 96 pixel select inputs, with 8 bits each for Red, Green and Blue. Each bit is multiplexed [A-D] 4:1 or 2:1. It can be configured for 24-Bit True-Color Data, 8-Bit Pseudo-Color Data, 16-Bit True-Color and 15-Bit True-Color Data formats. In 8-Bit Pseudo-Color Mode, there is a special case whereby 8:1 multiplexing is also available. It will be explained in more detail later. Pixel Data is latched into the device on the rising edge of LOADIN. PS0 Palette Priority Selects (TTL Compatible Inputs): The eight PS inputs provide two Bits after input multiplexing. These pixel port select inputs can be configured for three separate functions. In Overlay Mode, these inputs provide a three color overlay function. With any value other than “00” on the overlay inputs, the color displayed comes from the overlay palette instead of the main pixel inputs. For the ADV7160, in Bypass Mode, PS1 specifies for each pixel whether it should pass through the Color Matrix and Color Palette or bypass the Matrix and Palette. PS0 acts as an overlay input. (This mode is not available for the ADV7162.) Palette Select Mode is used to multiplex the RGB outputs of a number of devices. When the palette mode inputs match the PS bits in the mode register, the part operates as normal. When there is a mismatch, the RGB outputs are switched to zero, allowing the RGB outputs of another device to drive the monitor. LOADIN Pixel Data Load Input (TTL Compatible Input): This input latches the multiplexed pixel data, in- cluding PS0-PS1, BLANK, TRISYNC, SYNC and ODD/EVEN into the device. LOADOUT Pixel Data Load Output (TTL Compatible Output): This output control signal runs at a divided down frequency of the pixel clock. Its frequency is a function of the multiplex rate. It can be used to directly or indirectly drive LOADIN. f LOADOUT = fCLOCK/M where (M = 2 for 2:1 Multiplex Mode) (M = 4 for 4:1 Multiplex Mode) (M = 8 for 8:1 Multiplex Mode) PRGCKOUT Programmable Clock Output (TTL Compatible Output): This output control signal runs at a divided down frequency of the pixel Clock. Its frequency is user programmable and is determined by bits CR30 and CR31 of Command Register 3. f PRGCKOUT = fCLOCK/N where N = 4, 8, 16 & 32 SCKIN Video Shift Clock Input (TTL Compatible Input): The signal on this input is internally gated syn- chronously with the BLANK signal. The resultant output, SCKOUT, is a video clocking signal that is stopped during video blanking periods. It is normally driven by a divided down version of the CLOCK frequency. SCKOUT Video Shift Clock Output (TTL Compatible Output): This output is a synchronously gated version of SCKIN and BLANK. SCKOUT is a video clocking signal that is stopped during video blanking periods. CLOCK, CLOCK Clock Inputs (ECL Compatible Inputs): These differential clock inputs are designed to be driven by ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the pixel clock rate of the system. PLL REF PLL Clock Input (TTL Compatible Input): This clock input is designed to be driven by TTL logic levels. The PLL is then configured to output a specific frequency depending on the PLL Registers. See PLL section for more detail. BLANK Composite Blank (TTL Compatible Input): This video control signal drives the analog outputs to the blanking level. SYNC Composite-Sync Input (TTL Compatible Input): This video control signal drives any of the analog outputs to the SYNC level. It is only asserted during the blanking period. CR22 in Command Register 2 must be set if SYNC is to be decoded onto the IOG analog output, CR41 in Command Register 4 must be set if SYNC is to be decoded onto the IOR analog output, CR42 in Command Register 4 must be set if SYNC is to be decoded onto the IOB analog output, otherwise the SYNC input is ignored.
REV. 0–14– ADV7160/ADV7162 Mnemonic Function SYNCOUT Composite-Sync Output (TTL Compatible Output). This video output is a delayed version of SYNC. The delay corresponds to the number of pipeline stages of the device. TRISYNC Composite-Sync HDTV Control (TTL Compatible Output). This video input is enabled using Bit CR17 in Command Register 1. When TRISYNC is low, any DAC output which has Sync enabled, goes to the tri-sync level. As with the SYNC input, it should only be activated while BLANK is low. D9–D0 Data Bus (TTL Compatible Input/Output Bus). Data, including color palette values and device con- trol information is written to and read from the device over this 10-bit, bidirectional databus. 10-bit data or 8-bit data can be used. The databus can be configured for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any unused bits of the data bus should be terminated through a resistor to either the digital power plane (V CC) or GND. ODD/EVEN Odd/Even Control (TTL Compatible Input). This input indicates which field of the frame is being displayed. It is required to ensure proper operation of the ADV7160/ADV7162 cursor when inter- laced display mode is selected. It is ignored when noninterlaced display mode is selected. This input should change only during the vertical blank period. It is assumed that an odd field will always follow an even field and vice versa. CE Chip Enable (TTL Compatible Input). This input must be at Logic “0” when writing to or reading from the device over the data bus (D0–D9). Internally, data is latched on the rising edge of CE. R/W Read/Write Control (TTL Compatible Input). This input determines whether data is written to or read from the device’s registers and color palette RAM. R /W and CE must be at Logic “0” to write data to the part. R/W must be at Logic “1” and CE at Logic “0” to read from the device. C0, C1 Command Controls (TTL Compatible Inputs). These inputs determine the type of read or write op- eration being performed on the device over the data bus, (see Interface Truth Table). Data on these inputs is latched on the falling edge of CE. IOR, IOG, IOB Red, Green & Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 75 Ω loads. VREF Voltage Reference Input (Analog Input): An external 1.235 V voltage reference is required to drive this input. An AD589 (2-terminal voltage reference) or equivalent is recommended. (Note: It is not recommended to use a resistor network to generate the voltage reference.) R SET Output Full Scale Adjust Control (Analog Input). A resistor connected between this pin and analog ground controls the absolute amplitude of the output video signal. For a value of R SET of nominally 280 Ω , with 37.5 Ω termination and using CR43 and CR44 of Command Register 4 to set the DAC Gain as shown, the required Video Standard can be achieved. CR44 CR43 Video Standard DAC Gain Black to White 0 0 RS343A, Sync & Pedestal 3996 660 mV 17.62 mA 0 1 RS343A, Sync & No Pedestal 4224 699 mV 18.63 mA 1 0 RS343A, No Sync & No Pedestal 4311 714 mV 19.05 mA 1 1 RS170, Sync & Pedestal 5592 925 mV 24.67 mA Alternatively, R SET can be calculated by the following equation: RSET DAC Gain × VREF Black toWhite Current COMP Compensation Pin. A 0.1 µF capacitor should be connected between this pin and V AA. VAA Power Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be connected together to one common +5 V filtered analog power supply. GND: Analog Ground. The part contains multiple ground pins, all should be connected together to the system’s ground plane. TMS, TCK, These four pins control the JTAG test access port. TDI, TDO See Appendix 6 for more detail
high speed, 10-bit, digital-to analog converters (RGB DACs). There are two video data paths through the ADV7160/ADV7162. video window on a graphics background. through the microprocessor (MPU) port. Figure 15. Multiplexed Color Inputs for the put as an RGB analog video signal.
- Pixel Port and Clock Control Circuit
- MPU Port, Registers and Color Palette
- Digital-to-Analog Converters and Video Outputs
to the video/graphics pipeline of a computer graphics subsystem. Callibration. This allows effective 30-bit True-Color operation. conditions are unpredictable and uncontrollable.
REV. 0–16– ADV7160/ADV7162 Other pixel data signals latched into the device by LOADIN include SYNC, BLANK, TRISYNC and PS0A-D – PS1A-D. Internally, data is pipelined through the part by the differential pixel clock inputs, CLOCK and CLOCK or by the internal pixel clock generated by the PLL on-board. The LOADIN control signal need only have a frequency synchronous relation- ship to the pixel CLOCK (see “Pipeline Delay & On-Board Calibration” section). A completely phase independent LOADIN signal can be used with the ADV7160/ADV7162, allowing the CLOCK to occur anywhere during the LOADIN cycle. Alternatively, the LOADOUT signal of the ADV7160/ADV7162 can be used. LOADOUT can be connected either directly or indirectly to LOADIN. Its frequency is automatically set to the correct LOADIN requirement. SYNC, BLANK The BLANK and SYNC video control signals drive the analog outputs to the Blank and Sync levels respectively. These signals are latched into the part on the rising edge of LOADIN. The SYNC information is encoded onto the IOG analog signal when Bit CR22 of Command Register 2 is set to “1,” the IOR analog signal when Bit CR41 of Command Register 4 is set to “1” and the IOB analog signal when Bit CR42 of Command Register 4 is set to “1.” The SYNC input is ignored if CR22, CR41 and CR42 are set to logic “0.” SYNCOUT In some applications where it is not permissible to encode SYNC on green (IOG), blue (IOB), or red (IOR), SYNCOUT can be used as a separate TTL digital SYNC output. This has the advantage over an independent (of the ADV7160/ADV7162) SYNC in that it does not necessitate knowing the absolute pipe- line delay of the part. This allows complete independence between LOADIN/Pixel Data and CLOCK. The SYNC input is connected to the device as normal with Bit CR22 of Com- mand Register 2, Bit CR41 of Command Register 4 and Bit CR42 of Command Register 4 are set to “0” thereby preventing SYNC from being encoded onto IOG, IOR and IOB. The out- put signal generates a TTL SYNCOUT with correct pipeline delay which is capable of directly driving the composite SYNC signal of a computer monitor. TRISYNC This input is used to generate a HDTV Sync on any of the DAC outputs. Bit CR17 of Command Register 1 is set to “1”, en- abling TRISYNC. When TRISYNC is low, the analog output which has Sync enabled goes to the tri-sync level. PS0A-D–PS1A-D (Palette Priority Select Inputs) These multifunctional TTL compatible inputs can be config- ured for three separate functions. The eight PS inputs are mul- tiplexed to provide two bits which are used to provide one of three different functions. The function is selected by Bit CR14 and Bit CR15 of Command Register 1. CR15 CR14 Color Mode 0 0 Palette Select Mode 0 1 Bypass Mode Control (ADV7160 Only) 1 0 Overlay Color Mode 1 1 Ignore PS Inputs However, in 8:1 Mode, for 8-Bit Pseudo Color, the unused Blue Pixel Inputs are used to provide 8 extra PS inputs. The bypass mode is unavailable in this case. Palette Select Mode These pixel port select inputs effectively determine whether the devices RGB analog outputs are turned-on or shut down. When the analog outputs are shut down, IOR, IOG and IOB are forced to 0 mA regardless of the state of the pixel and control data inputs. This state is determined on a pixel by pixel basis as the PS0–PS1 inputs are multiplexed in exactly the same format as the pixel port color data. These controls allow for switching between multiple palette devices. If the values of PS0 and PS1 match the values programmed into bits MR16 and MR17 of the Mode Register, then the device is selected, if there is no match the device is effectively shut down. Bypass Mode Control (ADV7160 Only) In this mode PS1 is used to switch between one of the color modes through the Color Palette and one of the Palette Bypass modes on a pixel by pixel basis. The color mode through the palette is selected using Bits CR27–CR24 of Command Regis- ter 2. The Bypass Color Mode is selected using Bits CR17 and CR16 of Command Register 1. PS1 then switches between the Palette Color Mode, and the Bypass Color Mode. The PS0 in- put continues to act as an overlay input, allowing Overlay Color 1 to be displayed. PS0 PS1 Color Mode 0 0 Palette Color Mode (CR27–CR24) 0 1 Bypass Color Mode (CR17–CR16) 1 x Overlay Color 1 This mode is not available if using the ADV7162. Overlay Color Mode In this mode, the PS inputs provide control for a three color overlay. Whenever the value other than “00” is placed on the overlay inputs, the corresponding overlay color is displayed. When the overlay inputs contain “00” the color is specified by the main pixel inputs. CLOCK CONTROL CIRCUIT The ADV7160/ADV7162 has an integrated Clock Control Cir- cuit (Figure 16). This circuit is capable of both generating the ADV7160/ADV7162’s internal clocking signals as well as exter- nal graphics subsystem clocking signals. Total system synchro- nization can be attained by using the parts output clocking signals to drive the controlling graphics processor’s master clock as well as the video frame buffers shift clock signals. CLOCK, CLOCK Inputs The Clock Control Circuit is driven by the pixel clock inputs, CLOCK and CLOCK. These inputs can be driven by a differ- ential ECL oscillator running from a +5 V supply.
trol the overall graphics system clocking and synchronization. Figure 19. ADV7160/ADV7162 Interface Using SCKIN The on-board PLL can be used as an alternative clock source. registers can be programmed to set up the frequency required. Figure 20. PLL Block Diagram phase frequency detector to be matched in frequency and phase. one, or from 130 to 258 in steps of two by setting the RSEL bit. set to 00H. If this register contains 00H, then the PLL stops. Figure 21. PLL Transfer Function block diagram shown in Figure 21.
120 MHz < F VCO < 260 MHz
tween jitter performance and F OUT accuracy. Figure 22. PLL Jitter
Figure 34. Internal Register Configuration and Address Decoding
The output clocking signals are also set during this reset period. red after a blue write or whenever the address register is written. similar red, green and blue palette read sequence is performed. Figure 35. 8-Bit Data Bus Using 10-Bit DACs
the ADV7162 it will always return the hexadecimal value 79H. and CR18 are returned as zeros. LOADOUT synchronization circuit on every vertical Sync. Figure 40. Command Register 1 (CR1) (CR19–CR10) This bit enables access to the Hi Byte of the Address Register. when using the PS bits to select a bypass mode at the pixel rate. (CR15 = “0,” CR14 = “1”), is reserved and should not be used. “00,” the color is specified by the pixel inputs.
1 ENABLE TEST
0 DISABLE
IT IS RESERVED ON THE ADV7162.
0 NO ACCESS TO HI-BYTE
1 CALIBRATES ON
1 ACCESS TO HI-BYTE
(CR39 and CR38 are both reserved). this control is useful in de-skewing the pipeline differential. also determines the frequency of the LOADOUT signal. LOADOUT is a divided down version of the pixel CLOCK. (CR29 and CR28 are both reserved). mode, CR29 and CR28 are returned as zeros. coded onto the IOG analog output or ignored. tal is to be generated on the video outputs. mode and three 8-bit pseudo color modes. Figure 41. Command Register 2 (CR2) (CR29–CR20) *THESE BITS ARE READ-ONLY RESERVED BITS.
0 IGNORE
1 DECODE
Figure 42. Command Register 3 (CR3) (CR39–CR30) (CR49 and CR48 are both reserved). mode, CR49 and CR48 are both returned as zeros. coded onto the IOR analog output or ignored. coded onto the IOB analog output or ignored. pedestal is automatically disabled independently of CR23. This bit enables or disables the clock to the signature analyzer. Figure 43. Command Register 4 (CR4) (CRF49–CR40)
0 DISABLE TRI-SYNC
1 ENABLE TRI-SYNC
0 ENABLE
1 DISABLE
1 ENABLE
0 DISABLE CLOCK
1 ENABLE CLOCK
done to give a known starting point before acquiring a signature. “Test Diagnostic” section for more information. write mode, zero should be written to CR57 and CR55–CR50. In read mode, CR59 and CR58 are both returned as zeros. (PCR9 and PCR8 are both reserved). This bit enables or disables PLL. the PLL. Reference Divider = (1 + RSEL) × (R+2). feedback divider value of the PLL. is used in the generation of lower frequencies. These bits set up the S value in the PLL transfer function. back divider value of the PLL. are reserved bits, containing zeros. Bit R7 is a read only bit. trols the reference divider of the on-board PLL. Figure 44. Command Register (PCR) (PCR9–PCR0)
0 DISABLE PLL
1 ENABLE PLL
REV. 0 –31– PLL V Register (Address Reg (A10–A0) = 00FH) This register is a read only 10-bit register. However V9–V8 are reserved bits, containing zeros. Bit V7 is a read only bit. This bit should be masked in software on readback as its value may be indeterminate. Therefore, the PLL V Register may be treated as a 7-bit wide register. This register, together with the VSEL Bit in the PLL Control Register, controls the feedback divider of the on-board PLL. 64 × 64 Cursor The ADV7160/ADV7162 has a 64 × 64 cursor generator on board. Several of the control registers control the cursor. These will be described in detail. The Cursor-X and Cursor-Y registers specify the position the cursor is to be placed on the screen. The origin (0, 0) of the cursor is top left. The position of the cursor is taken relative to this point, allowing the Cursor- X and Cursor-Y registers to be programmed with negative num- bers and thus allow the cursor to be partially or completely off the screen. The cursor can work as an X-11 or XGA cursor, controlled by Bits CCR0 and CCR1 of the Cursor Control Register. The screen X and Y coordinates are measured from the rising edge of BLANK. The first pixel after the rising edge of BLANK corresponds to the origin (0, 0). The Vertical retrace time is ex- tracted from the composite SYNC and BLANK inputs. The start of Vertical Retrace is recognized by counting a second ris- ing edge on SYNC while BLANK remains low. The next rising edge on BLANK is the start of line 0. Cursor X-Lo and Cursor X-Hi Register (Address Reg (A10–A0) = 200H and 201H) These 8-bit registers together form a 16-bit 2s complement rep- resentation of the cursor x-coordinate on the screen. The valid range for the cursor x-coordinate is ± FFFH. The negative number representation allows for part or all of the cursor to be displayed off the left-hand edge of the screen Cursor Y-Lo and Cursor Y-Hi Register (Address Reg (A10–A0) = 202H and 203H) These 8-bit registers together form a 16-bit 2s complement rep- resentation of the cursor x-coordinate on the screen. The valid range for the cursor x-coordinate is ± FFFH. The negative number representation allows for part or all of the cursor to be displayed off the top/left of the screen. When accessing the cursor X and Y registers, the Address Regis- ter auto-increments after each access. There are no restrictions on updating the cursor coordinate registers other than they must all be written in the order X-Low, X-Hi, Y-Low, Y-Hi to update the coordinates. Only one cursor is displayed per frame, at the last X and Y coordinates written. Access to these registers is independent of the databus being configured for 8- or 10-bit operation. Cursor Color 1 and Cursor Color 2 Register (Address Reg (A10–A0) = 304H and 303H) Each of these color registers are 30 bits wide, made up of 10 bits for Red, 10 bits for Green and 10 bits for Blue. Access to these registers behaves in the same way as access to the Color Palette with respect to the different combinations of 10/8-bit databus and 10/8-bit DAC resolution. Cursor Image (Address Reg (A10–A0) = 400H–7FFH) This region contains the 64 × 64 × 2-bit Cursor Image. Eight bits are stored at each address. With two bits per cursor pixel, four horizontally adjacent pixels are stored at each address. As each address location in the Cursor Image is filled, the progres- sion is from left to right until a line is filled and top to bottom until all the lines are filled. The cursor can be displayed on both an interlaced and noninterlaced system, as controlled by CCR3 of the Cursor Control Register. On an interlaced system, only one cursor can be displayed per field. The ODD/ EVEN input indicates which field of the frame is being displayed. Cursor Y Coordinate Even The Even field starts with line 0 of the cursor image on line Y of the frame. Subsequent even lines of the cursor image are dis- played on subsequent lines of the Even field. On the Even field, the frame line counter starts at 0 and increments by 2 at the end of every Even field line. The Odd field starts with line 1 of the cursor image on line Y + 1 of the frame. Subsequent odd lines of the cursor image are displayed on subsequent lines of the Odd field. On the Odd field, the frame line counter starts at 1 and increments by 2 at the end of every Odd field line. Cursor Y Coordinate Odd The Even field starts with line 1 of the cursor image on line Y + 1 of the frame. Subsequent even lines of the cursor image are displayed on subsequent lines of the Even field. On the Even field, the frame line counter starts at 1 and increments by 2 at the end of every Even field line. The Odd field starts with line 0 of the cursor image on line Y of the frame. Subsequent odd lines of the cursor image are displayed on subsequent lines of the Odd field. On the Odd field, the frame line counter starts at 0 and increments by 2 at the end of every Odd field line. Cursor Control Register (Address Reg (A10–A0) = 204H) This register contains a number of control bits. CCR is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (CCR8 and CCR9 are both reserved). In write mode zero should be written to CCR4 to CCR7. In read mode, CCR8 and CCR9 are all returned as zeros. Figure 45 shows the various operations under the control of CCR. CURSOR CONTROL REGISTER BIT DESCRIPTION CURSOR MODE CONTROL (CCR1–CCR0) These bits specify which type of cursor is being used. Each cur- sor pixel value controls the color differently in each mode. Table II. Bit 1 Bit 0 X-11 Cursor XGA Cursor 0 0 Transparent Color 1 0 1 Transparent Color 2 1 0 Color 1 Transparent 1 1 Color 2 Bit-Wise Complement Cursor Enable Control (CCR2) This bit turns the cursor on and off. Interlace Control (CCR3) This bit determines whether the cursor is being used in inter- laced or noninterlaced mode.
Figure 45. Cursor Control Register (CCR) (CCR9–CCR0) Figure 46. DAC Output Termination Figure 47. Composite Video Waveform SYNC Decoded; The analog video outputs are high impedance current sources. rectly drive a 37.5 Ω load (doubly terminated 75 Ω ).
0 NONINTERLACED
1 INTERLACED
92.5 IRE
7.5 IRE
40 IRE
waveforms are shown in the diagrams.
4224 RS343A, SYNC decoded on output; Pedestal = 0 IRE
4311 RS343A, No SYNC decoded; Pedestal = 0 IRE
100 IRE
43 IRE
Figure 48. Composite Video Waveform SYNC Figure 49. Composite Video Waveform SYNC and Figure 50. Composite Video Waveform Pedestal = 0
REV. 0–34– ADV7160/ADV7162 APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7160/ADV7162 is a highly integrated circuit contain- ing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be ap- plied to the system level design such that high speed, accurate performance is achieved. The “Recommended Analog Circuit Layout” shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7160/ADV7162 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of V AA and GND pins should by minimized so as to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV7160/ADV7162 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7160/ADV7162, the analog output traces, and all the digital signal traces leading up to the ADV7160/ ADV7162. The ground plane is the graphics board's common ground plane. Power Planes The ADV7160/ADV7162 and any associated analog circuitry should have it’s own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (V CC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7160/ADV7162. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7160/ADV7162 power pins and voltage refer- ence circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. Supply Decoupling For optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of V AA pins on the ADV7160/ADV7162 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7160/ADV7162 con- tains circuitry to reject power supply noise, this rejection de- creases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three terminal volt- age regulator for supplying power to the analog power plane. Digital Signal Interconnect The digital inputs to the ADV7160/ADV7162 should be iso- lated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7160/ADV7162 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V CC), and not the analog power plane. Analog Signal Interconnect The ADV7160/ADV7162 should be located as close as possible to the output connectors to minimize noise pickup and reflec- tions due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital Inputs, especially Pixel Data Inputs and clocking signals (CLOCK, LOADOUT, LOADIN, etc.) should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the analog outputs (IOR, IOG, IOB) should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7160/ADV7162 so as to minimize reflections.
REV. 0 –35– Recommended Analog Circuit Layout ADV7160 VREF R SET IOR IOG IOB COMP VAA GND R SET 280Ω AD589 (1.2V REF) 0.1µF1kΩ (1% METAL) +5V (VAA ) 75Ω 75Ω 75Ω +5V (VAA ) 0.1µF 33µF 0.1µF 75Ω 75Ω 75Ω MONITOR (CRT) BNC CONNECTORS L1 (FERRITE BEAD)+5V (VAA ) +5V (V CC ) ANALOG POWER PLANE POWER SUPPLY DECOUPLING (0.1µF CAPACITOR FOR EACH V AA GROUP) NOTES: 1. ALL RESISTERS ARE 1% METAL FILM 2. 0.1µF AND 0.01µF CAPACITORS ARE CERAMIC 3. ADDITIONAL DIGITAL CIRCUITRY OMITTED FOR CLARITY COAXIAL CABLE (75Ω )
REV. 0–36– ADV7160/ADV7162 APPENDIX 2 TYPICAL FRAME BUFFER INTERFACE ADV7160/ ADV7162 LOADOUT DIVIDE BY M (÷M) LOADIN BLANK SCKOUT SCKIN LATCH ENABLE MULTIPLEXER VRAM (BANK D)
50 MHZVRAM
(BANK A) (BANK B) (BANK C)
50 MHZ
PALETTE/RAM & DAC GRAPHICS PROCESSOR/ CONTROLLER CLOCK BLANK FRAME BUFFER/ VIDEO MEMORY SYNC / TRISYNC SYNC / TRISYNC CLOCK CLOCK ECL TO TTL PRGCKOUT S E L E C T PLL REF DIVIDE BY N (÷N) PLL
REV. 0 –37– GAMMA CORRECTION 8 Bits vs. 10 Bits Gamma Corrected Quantized to Quantized to 8-Bit Data (2.7) 8 Bits 10 Bits 240 0.977797 250 1001 241 0.979304 250 1002 242 0.980807 251 1004 243 0.982306 251 1005 244 0.983801 251 1007 245 0.985292 252 1008 246 0.986780 252 1010 247 0.988264 252 1011 248 0.989744 253 1013 249 0.991220 253 1015 250 0.992693 254 1016 251 0.994161 254 1018 252 0.995626 254 1019 253 0.997088 255 1021 254 0.998546 255 1022 255 1.000000 255 1023 INPUT CODE – DECIMAL DAC OUTPUT – NORMALISED TO 1) 1.00 0.20 0 256 32 64 96 128 160 192 224 0.90 0.60 0.50 0.40 0.30 0.80 0.70 GAMMA CORRECTION CURVE CRT RESPONSE LINEAR RESPONSE RECIEVED BY THE EYE 0.00 0.10 Gamma Correction Curve (Gamma Value = 2.7) APPENDIX 3 10-BIT DACs AND GAMMA CORRECTION 10-Bit DACs 10-Bit RAM-DAC resolution allows for nonlinear video correc- tion, in particular Gamma Correction. The ADV7160/ADV7162 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. In true-color mode, for example, the part effectively op- erates as a 24-bit to 30-bit color look-up table. Up to now we have assumed that there exists a linear relation- ship between the actual RGB values input to a monitor and the intensity produced on the screen. This, however, is not the case. Half scale digital input (1000 0000) might correspond to only 20% output intensity on the CRT (Cathode Ray Tube). The intensity (I CRT) produced on a CRT by an input value I IN is given by: ICRT = (IIN)c where c ranges from 2.0 to 2.8. If the individual values of c for red, green and blue are known, then so called “Gamma Correction” can be applied to each of the three video input signals (I IN); therefore: IIN(corrected) = k(IIN)1/c Traditionally, there has been a trade-off between implementing a nonlinear graphics function, such as gamma correction, and color dynamic range. The ADV7160/ADV7162 overcomes this by increasing the individual color resolution of each of the red, green and blue primary colors from 8 bits per color channel to 10 bits per channel (24 bits to 30 bits). The table highlights the loss of resolution when 8-bit data is gamma-corrected to a value of 2.7 and quantized in a traditional 8-bit system. Note that there is no change in the 8-bit quan- tized data for linear changes in the input data over much of the transfer function. On the other hand, when quantized to 10 bits via the 10-bit RAMs and 10-bit DACs of the ADV7160/ ADV7162, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data. The graph shows a typical gamma curve corresponding to a gamma value of 2.7. This is programmed to the red, green and blue RAMs of the color look-up table instead of the more tradi- tional linear function. Different curves corresponding to any particular gamma value can be independently programmed to each of the red, green and blue RAMs. Other applications of the 10-bit RAM-DAC include closed-loop monitor color calibration.
REV. 0–38– ADV7160/ADV7162 APPENDIX 4 INITIALIZATION AND PROGRAMMING ADV7160/ADV7162 INITIALIZATION After power has been supplied, the ADV7160/ADV7162 must be initialized. The Mode Register and Control Registers must then be set up. The values written to the various registers will be determined by the desired operating mode of the part, i.e., True-Color/ Pseudo-Color, 4:1 Muxing/2:1 Muxing, PLL on/off, Bypass Mode on/off etc. . . . The following section gives a recommended initialization of the ADV7160/ADV7162 and an example of the ADV7162 operating in a specific mode. ADV7160/ADV7162 Initialization C1 C0 R/ W Comment Write (xx000xx1)* to Mode Register (MR1) 1 1 0 Resets ADV7160/62 Write (xx000xx0)* to Mode Register (MR1) 1 1 0 Write (xx000xx1)* to Mode Register (MR1) 1 1 0 Write 05H to Address Register (A7–A0) 0 0 0 Address Reg points to Command Register 1 (CR1) Write (xxxx100x)* to Command Register 1 (CR1) 0 0 0 Address Reg points to CR1 for high byte access Write 06H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 2 (CR2) Write (xxxxxx00)* to Command Reg 2 (CR2) 1 0 0 Setup CR2 as required Write 07H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 3 (CR3) Write (xx0xxxxx)* to Command Reg 3 (CR3) 1 0 0 Setup CR3 as required Write 08H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 4 (CR4) Write (xxxxxxxx)* to Command Reg 4 (CR4) 1 0 0 Setup CR4 as required Write 0DH to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 5 (CR5) Write (0x000000)* to Command Reg 5 (CR5) 1 0 0 Setup CR 5 as required Write 04H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Pixel Mask Register Write (xxxxxxxx)* to Pixel Mask Register 1 0 0 Set up Pixel Mask as required Write 04H to Address Register (A7–A0) 0 0 0 Necessary only if CCR to be used Write 02H to Address Register (A10–A8) 0 0 0 Address Reg points to Cursor Control Register (CCR) Write (xxxxxxxx)* to Cursor Control Register 1 0 0 Set up CCR as required Write 0FH to Address Register (A7–A0) 0 0 0 Necessary only if PLL to be used Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to PLL V Register Write (xxxxxxxx)* to PLL V Register 1 0 0 Set up V as required Write 0CH to Address Register (A7–A0) 0 0 0 Necessary only if PLL to be used Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to PLL R Register Write (xxxx0xxx)* to PLL R Register 1 0 0 Set up R as required Write 09H to Address Register (A7–A0) 0 0 0 Necessary only if PLL to be used Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to PLL Command Register (PCR) Write (xxxxxxxx)* to PLLCommand Register 1 0 0 Set up PCR as required Write (xx0xxxxx)* to Mode Register (MR1) 1 1 0 Necessary only if manual claibration is required Write (xx1xxxxx)* to Mode Register (MR1) 1 1 0 Toggles MR15 Write (xx0xxxxx)* to Mode Register (MR1) 1 1 0 *x represents either a 0 or 1 value that the bit should be set to, depending on the desired operating mode of the ADV7160/ADV7162.
REV. 0 –39– Example Color Mode: 24-Bit Gamma Corrected True Color (30-Bits) through Color Palette Multiplexing: 2:1, Databus: 10-Bit, RAM-DAC Resolution: 10-Bit, SYNC: on Green, Pedestal: 0 IRE, Calibration: Every Vertical Sync, Internal PLL: 220 MHz (Reference = 15 MHz) Register Initialization C1 C0 R/ W Comment Write 07H to Mode Register (MR1) 1 1 0 Resets ADV7162* Write 06H to Mode Register (MR1) 1 1 0 10-Bit Data Bus, 10-Bit DAC Resolution Write 07H to Mode Register (MR1) 1 1 0 Write 05H to Address Register (A7–A0) 0 0 0 Address Reg points to Command Register 1 (CR1) Write 09H to Command Register 1 (CR1) 0 0 0 High byte access, Calibrate every Vertical Sync Write 06H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 2 (CR2) Write E4H to Command Reg 2 (CR2) 1 0 0 24-Bit True Color, 0 IRE, Sync on Green Write 07H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 3 (CR3) Write 40H to Command Reg 3 (CR3) 1 0 0 2:1 Muxing, PRGCKOUT = CLOCK ÷ 4 Write 08H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 4 (CR4) Write 00H to Command Reg 4 (CR4) 1 0 0 DAC GAIN = 3996 Write 0DH to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Command Register 5 (CR5) Write 40H to Command Reg 5 (CR5) 1 0 0 Internal PLL to be used Write 04H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to Pixel Mask Register Write FFH to Pixel Mask Register 1 0 0 Set up Pixel Mask Write 0FH to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to PLL V Register Write 09H to PLL V Register 1 0 0 Set up V value Write 0CH to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to PLL R Register Write 01H to PLL R Register 1 0 0 Set up R value Write 09H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Address Reg points to PLL Command Register (PCR) Write 06H to PLL Command Register 1 0 0 Set up PCR as required Color Palette RAM Initialization C1 C0 R/ W Comment Write 00H to Address Register (A7–A0) 0 0 0 Write 00H to Address Register (A10–A8) 0 0 0 Points to Color Palette RAM Write 00H (red data) to RAM location (00H) 0 1 0 (Initializes Palette RAM Write 00H (green data) to RAM location (00H) 0 1 0 (to a Linear Ramp Write 00H (blue data) to RAM location (00H) 0 1 0 ( Write 01H (red data) to RAM location (01H) 0 1 0 ( Write 01H (green data) to RAM location (01H) 0 1 0 ( Write 01H (blue data) to RAM location (01H) 0 1 0 ( .. . ( .. . ( Write FFH (red data) to RAM location (FFH) 0 1 0 ( Write FFH (green data) to RAM location (FFH) 0 1 0 ( Write FFH (blue data) to RAM location (FFH) 0 1 0 ( RAM Initialization Complete These command lines reset the ADV7162. The pipelines for each of the Red, Green & Blue pixel inputs are synchronously reset to the Multiplexer's “A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” **This sequence of instructions would, of course, normally be coded using some form of loop instruction.
REV. 0–40– ADV7160/ADV7162 3. CR45 of Command Register 4 is set to Logic “0” during the following vertical retrace and the acquired signature is read. At least 20 clock cycles should be allowed for the final pixels of the frame to travel down the pipeline of the ADV7160/ ADV7162 before the signature clock is disabled. The signature analyzer is read from control registers 010H to 013H. These are read only 10-bit registers. The access to these registers depends whether the part is in 8-bit or 10-bit data bus mode and operates in the same way as accessing the color palette. Address Register CONTROL (A10–A0) REGISTERS CONTENTS 0013H Signature Misc Register 0 0 0 0 0 0 0 S32 S31 S0 0012H Signature Blue Register S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 0011H Signature Green Register S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 0010H Signature Red Register S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 APPENDIX 5 SIGNATURE ANALYZER Signature Register The ADV7160/ADV7162 co ntains onboard circuitry that enables both device and system level test diagnostics. The ADV7160/ ADV7162 has a signature analyzer in the pixel datapath, just before the DAC decoders. The signature analyzer consists of a 33-bit linear feedback shift register. The 30-bit pixel value is fed as a parallel input into the analyzer. The signature analyzer only accumulates a signature during active display time when BLANK is high. Bit CR45 to CR47 of Command Register 4 control the signature analyzer. When CR45 of Command Reg- ister 4 is set to Logic “1,” the clock to the signature analyzer is enabled. Toggling CR46 low and then high resets the signature analyzer. This is done to give a known starting point before ac- quiring a signature. CR47 of Command Register 4 controls the feedback inputs to the analyzer. When CR47 of Command Register 4 is a Logic “0,” the feedback is disabled and on each clock cycle, the 30-bit pixel value is latched directly into the analyzer. To acquire a signature as the analyzer is clocked, CR47 of Command Register 4 is set to Logic “1.” To acquire a signature the following procedure must be followed: 1. CR45 and CR47 of Command Register 4 are set to Logic “1” during vertical retrace and CR46 of Command Register 4 is toggled to reset the analyzer. 2. A signature is acquired during the following active screen. CR42 S19 S32 CR42 S19 '0' '0' S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 SIGNATURE REGISTER I/P SIGNATURE CELL
REV. 0 –41– JTAG Test Port JTAG Test Port is a 4-pin interface consisting of: TCK: Test Clock TMS: Test Mode Select TDI: Test Data Input TDO: Test Data Output To put the ADV7160/ADV7162 into the required mode, the In- struction Register must be loaded. INSTRUCTION EXTEST SAMPLE/PRELOAD IDCODE PRIVATE 1 BYPASS BYPASS BYPASS BYPASS INSTRUCTION REGISTER CODE 000 001 010 011 100 101 110 111 The ADV7160 implementation has the mandatory instructions: Bypass, Sample/Preload and Extest, and the optional instruc- tion: IDCode. There is also one private instruction: Private1. The Private1 instruction is for internal use in production test only. The IDCode is a 32-bit number which can be scanned out through TDO. Its contents are defined below: VERSION (4 BITS) PART NUMBER (16 BITS) 2776H 2779H MANUFACTURER ID (11 BITS) 0E5H 0E5H LSB ADV7160 ADV7162 The Boundary Scan Chain is a fundamental feature of the JTAG Test Port. It allows all the digital input and output pins on the part to be connected into a shift register between the TDI and TDO pins. The digital pins can be sampled, or con- trolled over the JTAG port to carry out testing. The is no boundary scan cell on the PLL REF pin. The Three-State Control cell controls the three-state status of the microport databus. There are 131 cells in total on the Boundary Scan Chain. APPENDIX 6 JTAG TEST PORT (IEEE1149.1) CE R/W THREE-STATE CONTROL LOADIN SCKIN SCKOUT CLOCK CLOCK LOADOUT PRGCKOUT PS0 A PS0 B PS0 C PS0 D PS1 A PS1 B PS1 C PS1 D R0 A R0 B R0 C R0 D R1 A R1 B R1 C R1 D R2 A R2 B R2 C R2 D R3 A R3 B R3 C R3 D R4 A R4 B R4 C R4 D R5 A R5 B R5 C R5 D R6 A R6 B R6 C R6 D R7 A R7 B R7 C R7 D G0 A G0 B G0 C G0 D TDI G1 A G1 B G1 C G1 D G2 A G2 B G2 C G2 D G3 A G3 B G3 C G3 D G4 A G4 B G4 C G4 D G5 A G5 B G5 C G5 D G6 A G6 B G6 C G6 D G7 A G7 B G7 C G7 D B0 A B0 B B0 C B0 D B1 A B1 B B1 C B1 D B2 A B2 B B2 C B2 D B3 A B3 B B3 C B3 D B4 A B4 B B4 C B4 D B5 A B5 B B5 C B5 D B6 A B6 B B6 C B6 D B7 A B7 B B7 C B7 D TRISYNC ODD/ EVEN SYNC BLANK SYNCOUT TDO JTAG Boundary Scan Chain
REV. 0–42– ADV7160/ADV7162 APPENDIX 7 THERMAL AND ENVIRONMENTAL CONSIDERATIONS The ADV7160/ADV7162 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and envi- ronmental conditions which the ADV7160/ADV7162 must op- erate in. Reliability of the device is enhanced by keeping it as cool as possible. In order to avoid destructive damage to the de- vice, the absolute maximum junction temperature of 150 °C must never be exceeded. Certain applications, depending on ambient temperature and pixel data rates may require forced air cooling or external heatsinks. The following data is intended as a guide in evaluating the operating conditions of a particular ap- plication so that optimum device and system performance is achieved. It should be noted that information on package characteristics published herein may not be the most up to date at the time of reading this. Advances in package compounds and manufacture will inevitably lead to improvements in the thermal data. Please contact your local sales office for the most up-to-date information. Power Dissipation The diagrams show graphs of power dissipation in watts versus pixel clock frequency for the ADV7160 and ADV7162. When using the ADV7162 in Bypass Mode, the Pixel Mask Register should be programmed to 00H to reduce power further. PIXEL CLOCK FREQUENCY – MHz 2.00 0.50 60 100 140 180 220 1.50 1.25 1.00 0.75 1.75 260 2.25 POWER DISSIPATION – Watts VAA = +5V VREF = +1.2V TA = +25°C ADV7160 ADV7162 Note: The "Worst Case On-Screen Pattern" corresponds to full-scale transition on each pixel value for every CLOCK edge (00H, FFH, 00H, ...). The "Typical On-Screen Pattern" corresponds to linear changes in tne pixel input (i.e., a Black to White Ramp). In general, color images tend to approximate this characteristic. Typical Power Dissipation vs. Pixel Rate Package Characteristics The tables of thermal characteristics show typical information for the ADV7160 (160-Lead Plastic Power QFP) and AD7162 (160-Lead Plastic QFP) using various values of Airflow. Junction-to-Case (θ JC) Thermal Resistance for this particular part is: θJC (AD7160) = 0.4°C/W θJC (AD7162) = 6.7°C/W (Note: θJC is independent of airflow.) Heatsinks The maximum silicon junction temperature should be limited to 100°C. Temperatures greater than this will reduce long-term device reliability. To ensure that the silicon junction tempera- ture stays within prescribed limits, the addition of an external heatsink may be necessary. Heatsinks will reduce θ JA as shown in the Thermal Characteristics vs. Airflow table. Table A. Thermal Characteristics vs. Airflow–ADV7160* Air Velocity 0 50 100 200 (Linear Feet/min (Still Air) θJA °C/W No Heatsink 25.5 23 21 19 EG&G D10100-28 Heatsink 23 20 18 16 Thermalloy 2290 Heatsink 19 17 15 12 *These figures do not include thermal conduction through the package leads into the PCB. Thermal conduction through the leads can provide up to oC/W reduction in θJA. Table B. Thermal Characteristics vs. Airflow–ADV7162* Air Velocity 0 50 100 200 (Linear Feet/min) (Still Air) θJA °C/W No Heatsink 37 32 30 28 EG&G D10850-40 Heatsink 28 24 22 19 EG&G D10851-36 Heatsink 32 24 19 14 *These figures do not include thermal conduction through the package leads into the PCB. Thermal conduction through the leads can provide up to 5oC/W reduction in θJA. Thermal Model The junction temperature of the device in a specific application is given by: TJ = TA + PD (θJC + θCA) (1) or TJ = TA + PD (θJA) (2) where: TJ = Junction Temperature of Silicon ( °C) TA = Ambient Temperature ( °C) PD = Power Dissipation (W) θJC = Junction to Case Thermal Resistance ( °C/W) θCA = Case to Ambient Thermal Resistance ( °C/W) θJA = Junction to Ambient Thermal Resistance ( °C/W) The standard PQFP package has been enhanced to a PowerQuad2 package. This supports an improved thermal performance compared to standard PQFP. In this case, the die is attached to a heat slug so that the power that is dissipated can be conducted to the external surface of the package. This pro- vides a highly efficient path for the transfer of heat to the pack- age surface. The pac kage configuration also provides and efficient thermal path from the ADV7160 to the Printed Circuit Board.
REV. 0 –43– PAGE INDEX Topic Page APPENDIX 1 APPENDIX 2 APPENDIX 3 APPENDIX 4 APPENDIX 5 APPENDIX 6 APPENDIX 7 FIGURE INDEX Figure Title
1 Load Circuit for Data-Bus Access &Relinquish Times
2 JTAG Port Timing
3 LOADOUT vs. Pixel Clock Input 4 LOADIN vs. Pixel Input Data
5 Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (8:1 Mode)
6 Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (8:1 Mode)
7 Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (4:1 Mode)
8 Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (4:1 Mode)
9 Pixel Input to Analog Output Pipeline with Minimum
LOADOUT to LOADIN Delay (2:1 Mode)
10 Pixel Input to Analog Output Pipeline with Maximum
LOADOUT to LOADIN Delay (2:1 Mode) 11 Pixel Clock Input vs. Programmable Clock Output 12 SCKIN vs. SCKOUT
13 Analog Output Response vs, Pixel Clock
14 MPU Timing
15 Multiplexed Color Inputs
16 Clock Control Circuit
17 LOADOUT vs. Pixel Clock
18 SCKOUT Generation Circuit
19 Interface Using SCKIN and SCKOUT
20 PLL Block Diagram
21 PLL Transfer Function
22 PLL Jitter
23 24-Bit to 30-Bit True Color Configuration 24 15-Bit to 24-Bit True Color Configuration 25 8-Bit to 30-Bit Pseudo Color Configuration 26 16-Bit Tue Color Mapping Using R7–R0 and G7–G0 27 15-Bit True Color Mapping Using R7–R3, G7–G3 and B7–B3 28 15-Bit True Color Mapping Using R6–R0 and G7–G0 29 16-Bit True Color (Bypass) Using R7–R0 and G7–G0 30 15-Bit True Color (Bypass) Using R6–R0 and G7–G0
31 Direct Interfacing of Video Memory
32 8-Bit Pseudo Color in 8:1 Multiplexing Mode
33 MPU Port and Register Configuration
34 Internal Register Configuration and Address Decoding
35 8-Bit Databus Using 10-Bit DACs 36 8-Bit Databus Using 8-Bit DACs 37 10-Bit Databus Using 10-Bit DACs 38 10-Bit Databus Using 8-Bit DACs
39 Mode Register 1
40 Command Register 1
41 Command Register 2
42 Command Register 3
43 Command Register 4
44 PLL Command Register
45 Cursor Control Register
46 DAC Output Termination
47 Composite Video Waveform, SYNC decoded;
Pedestal = 7.5 IRE; DAC Gain = 3996
48 Composite Video Waveform, SYNC decoded;
Pedestal = 0 IRE; DAC Gain = 4224
49 Composite Video Waveform, SYNC & TRISYNC
decoded; Pedestal = 7.5 IRE; DAC Gain = 5592
50 Composite Video Waveform, Pedestal = 0 IRE;
DAC Gain = 4311
REV. 0–44– ADV7160/ADV7162 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). S-160 160-Lead Plastic Quad Flatpack TOP VIEW (PINS DOWN) PIN 1 121 160 120 0.014 (0.35) 0.011 (0.27) 1.239 (31.45) 1.219 (30.95) 1.107 (28.10) 1.100 (27.90) SQ SQ 0.026 (0.65) MIN SEATING PLANE 0.160 (4.07) MAX 0.037 (0.95) 0.026 (0.65) 0.004 (0.10) MAX 0.145 (3.67) 0.125 (3.17) 0.070 (1.77) 0.062 (1.57) 0.070 (1.77) 0.062 (1.57) 10° 6°±4° 4°±4° MAX PRINTED IN U.S.A. C2013–6–4/95