ADV7150 AD | Alldatasheet
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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC ADV7150 © Analog Devices, Inc., 1996 Tel: 617/329-4700 Fax: 617/326-8703 @ 85 MHz 8-Bit Pseudo Color 15-Bit True Color
APPLICATIONS
High Resolution, True Color Graphics Professional Color Prepress Imaging GENERAL DESCRIPTION The ADV7150 (ADV®) is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is spe- cifically designed for use in high performance, color graphics workstations. The ADV7150 integrates a number of graphic functions onto one device allowing 24-bit direct True-Color op- eration at the maximum screen update rate of 220 MHz. The ADV7150 implements 30-bit True Color in 24-bit frame buffer designs. The part also supports other modes, including 15-bit True Color and 8-bit Pseudo or Indexed Color. Either the Red, Green or Blue input pixel ports can be used for Pseudo Color. (Continued on page 12) ADV is a registered trademark of Analog Devices, Inc.
FEATURES
220 MHz, 24-Bit (30-Bit Gamma Corrected) True Color
Triple 10-Bit “Gamma Correcting” D/A Converters Triple 256 3 10 (256 3 30) Color Palette RAM On-Chip Clock Control Circuit Palette Priority Select Registers RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs Standard MPU l/O Interface 10-Bit Parallel Structure 8+2 Byte Structure Programmable Pixel Port: 24-Bit, 15-Bit and Programmable Pixel Port: 8-Bit (Pseudo) Pixel Data Serializer Multiplexed Pixel Input Ports; 1:1, 2:1, 4:1 +5 V CMOS Monolithic Construction 160-Lead Plastic Quad Flatpack (QFP) Thermally Enhanced to Achieve u JC < 1.0 8C/W MODES OF OPERATION 24-Bit True Color (30-Bit Gamma Corrected) @ 220 MHz @ 170 MHz @ 135 MHz @ 110 MHz FUNCTIONAL BLOCK DIAGRAM 256-COLOR/GAMMA PALETTE RAM 10 10-BIT RED DAC 10-BIT BLUE DAC IOR C D A B P I X E L P O R T MUX 4:1 RED 256 x 10 MPU PORT D9 – D0 10 (8+2) CE R/W C0 C1 LOADIN CLOCK LOADOUT PRGCKOUT SCKIN SCKOUT CLOCK DIVIDE SYNCHRONIZATION CIRCUIT ADDR (A7–A0) REVISION REGISTER COMMAND REGISTERS (CR1–CR3)TEST REGISTERS (MR1) VOLTAGE REFERENCE CIRCUIT ECL TO CMOS ADV7150 VREF R SET C OMP SYNC OUTPUT IPLL RED (R7–R0), GREEN (G7–G0), BLUE (B7–B0) COLOR DATA VAA GND DATA TO PALETTES CONTROL REGISTERS COLOR REGISTERS CLOCK CONTROL MODE REGISTER ADDRESS REGISTER GREEN 256 x 10 BLUE 256 x 10 PALETTE SELECTS (PS0, PS1) ID REGISTER GREEN REGISTER PIXEL MASK REGISTER IOR IOG IOG IOB IOB 10-BIT GREEN DAC BLUE REGISTER RED REGISTER SYNC BLANK CLOCK SYNCOUT MUX 4:1
REV. A–2– ADV7150–SPECIFICATIONS(VAA 1 = +5 V; VREF = +1.235 V; RSET = 280 V. IOR, IOG, IOB (RL = 37.5 V, CL = 10 pF); IOR, IOG, IOB = GND. All specifications T MIN to TMAX 2 unless otherwise noted.) Parameter All Versions Unit Test Conditions/Comments STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Accuracy (Each DAC) Integral Nonlinearity ± 1 LSB max Differential Nonlinearity ± 1 LSB max Guaranteed Monotonic Gray Scale Error ± 5 % Gray Scale max Coding Binary DIGITAL INPUTS (Excluding CLOCK, CLOCK) Input High Voltage, V INH 2 V min Input Low Voltage, V INL 0.8 V max Input Current, I IN ± 10 µA max V IN = 0.4 V or 2.4 V Input Capacitance, C IN 10 pF max CLOCK INPUTS (CLOCK, CLOCK) Input High Voltage, V INH VAA – 1.0 V min Input Low Voltage, V INL VAA – 1.6 V max Input Current, I IN ± 10 µA max V IN = 0.4 V or 2.4 V Input Capacitance, C IN 10 pF typ DIGITAL OUTPUT Output High Voltage, V OH 2.4 V min I SOURCE = 400 µA Output Low Voltage, V OL 0.4 V max I SINK = 3.2 mA Floating-State Leakage Current 20 µA max Floating-State Output Capacitance 20 pF typ ANALOG OUTPUTS Gray Scale Current Range 15/22 mA min/max Output Current White Level Relative to Blank 17.69/20.40 mA min/max Typically 19.05 mA White Level Relative to Black 16.74/18.50 mA min/max Typically 17.62 mA Black Level Relative to Blank 0.95/1.90 mA min/max Typically 1.44 mA Blank Level on IOR, IOB 0/50 µA min/max Typically 5 µA Blank Level on IOG 6.29/8.96 mA min/max Typically 7.62 mA Sync Level on IOG 0/50 µA min/max Typically 5 µA LSB Size 17.22 µA typ DAC-to-DAC Matching 3 % max Typically 1% Output Compliance, V OC 0/+1.4 V min/V max Output Impedance, R OUT 100 k Ω typ Output Capacitance, C OUT 30 pF max I OUT = 0 mA VOLTAGE REFERENCE Voltage Reference Range, V REF 1.14/1.26 V min/V max V REF = 1.235 V for Specified Performance Input Current, I VREF +5 µA typ POWER REQUIREMENTS VAA 5 V nom IAA 3 400 mA max 220 MHz Parts IAA 3 370 mA max 170 MHz Parts IAA 350 mA max 135 MHz Parts IAA 330 mA max 110 MHz Parts IAA 315 mA max 85 MHz Parts Power Supply Rejection Ratio 0.5 %/% max Typically 0.12%/%: COMP = 0.1 µF DYNAMIC PERFORMANCE Clock and Data Feedthrough 4, 5 –30 dB typ Glitch Impulse 50 pV secs typ DAC-to-DAC Crosstalk 6 –23 dB typ NOTES 1± 5% for all versions. 2Temperature range (T MIN to TMAX): 0°C to +70 °C; TJ (Silicon Junction Temperature) ≤ 100°C. 3Pixel Port is continuously clocked with data corresponding to a linear ramp. T J = 100°C. 4Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5TTL input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 6DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. Specifications subject to change without notice.
–3–REV. A TIMING CHARACTERISTICS1 CLOCK CONTROL AND PIXEL PORT 4
220 MHz 170 MHz 135 MHz 110 MHz 85 MHz
Parameter Version Version Version Version Version Units Conditions/Comments fCLOCK 220 170 135 110 85 MHz max Pixel CLOCK Rate t2 2 2.5 3.2 4 4 ns min Pixel CLOCK High Time t3 2 2.5 3 4 4 ns min Pixel CLOCK Low Time t4 10 10 10 10 10 ns max Pixel CLOCK to LOADOUT Delay fLOADIN LOADIN Clocking Rate 1:1 Multiplexing 110 110 110 110 85 MHz max 2:1 Multiplexing 110 85 67.5 55 42.5 MHz max 4:1 Multiplexing 55 42.5 33.75 27.5 21.25 MHz max t5 LOADIN Cycle Time t6 LOADIN High Time 1:1 Multiplexing 44444 n s m i n 2:1 Multiplexing 45689 n s m i n 4:1 Multiplexing 8 9 12 15 18 ns min t7 LOADIN Low Time 1:1 Multiplexing 44444 n s m i n 2:1 Multiplexing 45689 n s m i n 4:1 Multiplexing 8 9 12 15 18 ns min t8 00000 n s m i n Pixel Data Setup Time t9 55555 n s m i n Pixel Data Hold Time t10 00000 n s m i n LOADOUT to LOADIN Delay τ–t11 5 τ–5 τ–5 τ–5 τ–5 τ–5 ns max LOADOUT to LOADIN Delay tPD
6 Pipeline Delay
1:1 Multiplexing 55555 CLOCKs (1 × CLOCK = t1) 2:1 Multiplexing 66666 CLOCKs 4:1 Multiplexing 88888 CLOCKs t12 10 10 10 10 10 ns max Pixel CLOCK to PRGCKOUT Delay t13 55555 n s m a x SCKIN to SCKOUT Delay t14 55555 n s m i n BLANK to SCKIN Setup Time t15 11111 n s m i n BLANK to SCKIN Hold Time ANALOG OUTPUTS 7 Parameter Version Version Version Version Version Units Conditions/Comments t16 15 15 15 15 15 ns typ Analog Output Delay t17 11111 n s t y p Analog Output Rise/Fall Time t18 15 15 15 15 15 ns typ Analog Output Transition Time tSK 22222 n s m a x Analog Output Skew (IOR, IOG, IOB) 00000 n s t y p MPU PORTS8, 9 Parameter Version Version Version Version Version Units Conditions/Comments t19 33333 n s m i n R / W, C0, C1 to CE Setup Time t20 10 10 10 10 10 ns min R/ W, C0, C1 to CE Hold Time t21 45 45 45 45 45 ns min CE Low Time t22 25 25 25 25 25 ns min CE High Time t23 8 55555 n s m i n CE Asserted to Databus Driven t24 9 45 45 45 45 45 ns max CE Asserted to Data Valid t25 9 20 20 20 20 20 ns max CE Disabled to Databus Three-Stated 55555 n s m i n t26 20 20 20 20 20 ns min Write Data (D0–D9) Setup Time t27 55555 n s m i n Write Data (D0–D9) Hold Time (VAA 2 = +5 V; VREF = +1.235 V; RSET = 280 V. IOR, IOG, IOB (RL = 37.5 V, CL = 10 pF); IOR, IOG, I0B = GND. All specifications T MIN to TMAX 3 unless otherwise noted.)
accumulate on the human body and test equipment and can discharge without detection. precautions are recommended to avoid performance degradation or loss of functionality. maximum rating conditions for extended periods may affect device reliability.
220 MHz ADV7150LS220 110 MHz ADV7150LS110
170 MHz ADV7150LS170 85 MHz ADV7150LS85
135 MHz ADV7150LS135
1ADV7150 is packaged in a 160-pin plastic quad flatpack, QFP. 2All devices are specified for 0 °C to +70 °C operation. 3Contact sales office for latest information on package design. Figure 11. Microprocessor Port (MPU) Interface Timing
–9–REV. A ADV7150 PIN ASSIGNMENTS Pin Pin Pin Pin Number Mnemonic Number Mnemonic Number Mnemonic Number Mnemonic 1G 3 A 41 PS1 D 81 NC 121 R1 A 2G 3 B 42 B0 A 82 D2 122 R1 B 3G 3 C 43 B0 B 83 NC 123 R1 C 4G 3 D 44 B0 C 84 GND 124 R1 D 5G 4 A 45 B0 D 85 GND 125 R2 A 6G 4 B 46 B1 A 86 GND 126 R2 B 7G 4 C 47 B1 B 87 D3 127 R2 C 8G 4 D 48 B1 C 88 D4 128 R2 D 9G 5 A 49 B1 D 89 D5 129 R3 A
10 G5 B 50 B2 A 90 V AA 130 R3 B
11 G5 C 5 1 B2 B 91 D6 131 R3 C
12 G5 D 52 B2 C 92 D7 132 R3 D
13 CLOCK 53 B2 D 93 D8 133 R4 A
14 CLOCK 54 B3 A 94 D9 134 R4 B
15 LOADIN 55 B3 B 95 GND 135 R4 C
16 LOADOUT 56 B3 C 96 GND 136 R4 D
17 V AA 57 B3 D 97 GND 137 R5 A
18 V AA 58 B4 A 98 IOB 138 R5 B
19 PRGCKOUT 59 B4 B 99 IOR 139 R5 C
20 SCKIN 60 B4 C 100 IOG 140 R5 D
21 SCKOUT 61 B4 D 101 IOB 141 R6 A
22 SYNCOUT 62 B5 A 102 IOG 142 R6 B
23 GND 63 B5 B 103 V AA 143 R6 C
24 GND 64 B5 C 104 V AA 144 R6 D
25 GND 65 B5 D 105 V AA 145 R7 A
26 G6 A 66 B6 A 106 IOR 146 R7 B
27 G6 B 67 B6 B 107 COMP 147 R7 C
28 G6 C 68 B6 C 108 V REF 148 R7 D
29 G6 D 69 B6 D 109 R SET 149 G0 A
30 G7 A 70 B7 A 110 I PLL 150 G0 B
31 G7 B 71 B7 B 111 GND 151 G0 C
32 G7 C 72 B7 C 112 V AA 152 G0 D
33 G7 D 73 B7 D 113 V AA 153 G1 A
34 PS0 A 74 CE 114 V AA 154 G1 B
35 PS0 B 75 R/ W 115 SYNC 155 G1 C
36 PS0 C 76 C0 116 BLANK 1 56 G1 D
37 PS0 D 77 C1 117 R0 A 157 G2 A
38 PS1 A 78 D0 118 R0 B 158 G2 B
39 PS1 B 79 D1 119 R0 C 159 G2 C
40 PS1 C 80 GND 120 R0 D 160 G2 D
NC = No Connect.
–10– REV. A PIN FUNCTION DESCRIPTION Mnemonic Function Data formats. Pixel Data is latched into the device on the rising edge of LOADIN. mine whether or not the device’s pixel data port is selected on a pixel by pixel basis. The palette selects allow switching between multiple palette devices. The device can be preprogrammed to completely shut off the DAC analog outputs. If the values of PS0 and PS1 match the values programmed into bits MR16 and MR17 of the Mode Regis- ter, then the device is selected. Each bit is multiplexed [A-D] 4:1, 2:1 or 1:1. PS0 and PS1 are latched into the device on the rising edge of LOADIN. LOADIN Pixel Data Load Input (TTL Compatible Input). This input latches the multiplexed pixel data, including PS0–PS1, BLANK and SYNC into the device. LOADOUT Pixel Data Load Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the pixel CLOCK input. Its frequency is a function of the multiplex rate. It can be used to directly or indirectly drive LOADIN f LOADOUT = fCLOCK/M where M = 1 for 1:1 Multiplex Mode where M = 2 for 2:1 Multiplex Mode where M = 4 for 4:1 Multiplex Mode. PRGCKOUT Programmable Clock Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the pixel CLOCK input. Its frequency is user programmable and is determined by bits CR30 and CR31 of Command Register 3 fPRGCKOUT = fCLOCK/N where N = 4, 8, 16 and 32. SCKIN Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally gated synchronously with the BLANK signal. The resultant output, SCKOUT, is a video clocking signal that is stopped during video blanking periods. SCKOUT Video Shift Clock Output (TTL Compatible Output). This output is a synchronously gated version of SCKIN and BLANK. SCKOUT, is a video clocking signal that is stopped during video blanking periods. CLOCK, CLOCK Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to be driven by ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the pixel clock rate of the system. BLANK Composite Blank (TTL Compatible Input). This video control signal drives the analog outputs to the blanking level. SYNC Composite-Sync Input (TTL Compatible Input). This video control signal drives the IOG analog output to the SYNC level. It is only asserted during the blanking period. CR22 in Command Register 2 must be set if SYNC is to be decoded onto the analog output, otherwise the SYNC input is ignored. SYNCOUT Composite-Sync Output (TTL Compatible Output). This video output is a delayed version of SYNC. The delay corresponds to the number of pipeline stages of the device. D0–D9 Databus (TTL Compatible Input/Output Bus). Data, including color palette values and device control information is written to and read from the device over this 10-bit, bidi- rectional databus. 10-bit data or 8-bit data can be used. The databus can be configured for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any un- used bits of the databus should be terminated through a resistor to either the digital power plane (V CC) or GND. CE Chip Enable (TTL Compatible Input). This input must be at Logic “0,” when writing to or reading from the device over the databus (D0–D9). Internally, data is latched on the rising edge of CE.
–11–REV. A Mnemonic Function R/W Read/Write Control (TTL Compatible Input). This input determines whether data is written to or read from the device’s registers and color palette RAM. R/ W and CE must be at Logic “0” to write data to the part. R/ W must be at Logic “1” and CE at Logic “0” to read from the device. C0, C1 Command Controls (TTL Compatible Inputs). These inputs determine the type of read or write operation being performed on the device over the databus (see Interface Truth Table). Data on these inputs is latched on the falling edge of CE. IOR; IOR, IOG; IOG, IOB; Red, Green and Blue Current Outputs (High Impedance Current Sources). These RGB IOB video outputs are specified to directly drive RS-343A and RS-170 video levels into dou- bly terminated 75 Ω loads. IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. These out- puts can be tied to GND if it is not required to use differential outputs. VREF Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is re- quired to drive this input. An AD589 (2-terminal voltage reference) or equivalent is rec- ommended. (Note: It is not recommended to use a resistor network to generate the voltage reference.) R SET Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin and analog ground controls the absolute amplitude of the output video signal. The value of RSET is derived from the full-scale output current on IOG according to the following equations: RSET (Ω ) = C1 × VREF/IOG (mA); SYNC on GREEN RSET (Ω ) = C2 × VREF/IOG (mA); NO SYNC on GREEN. Full-Scale output currents on IOR and IOB for a particular value of R SET are given by: IOR (mA)= C2 × VREF(V)/RSET (Ω ) and IOB (mA) = C2 × VREF (V)/RSET (Ω ) where C1 = 6,050; PEDESTAL = 7.5 IRE where C1 = 5,723; PEDESTAL = 0 IRE and where C2 = 4,323; PEDESTAL = 7.5 IRE where C1 = 3,996; PEDESTAL = 0 IRE. COMP Compensation Pin. A 0.1 µF capacitor should be connected between this pin and V AA. IPLL Phase Lock Loop Output Current (High Impedance Current Source). This output is used to enable multiple ADV7150s along with ADV7151s to be synchronized together with pixel resolution when using an external PLL. This output is triggered either from the falling edge of SYNC or BLANK as determined by bit CR21 of Command Register 2. When activated, it supplies a current corresponding to: IPLL (mA) = 1,728 × VREF(V)/RSET (Ω ) When not using the I PLL function, this output pin should be tied to GND. VAA Power Supply (+5 V ± 5%). The part contains multiple power supply pins, all should be connected together to one common +5 V filtered analog power supply. GND Analog Ground. The part contains multiple ground pins, all should be connected together to the system’s ground plane.
as an RGB analog video signal.
- Pixel port and clock control circuit
- MPU port, registers and color palette
- Digital-to-analog converters and video outputs
tween other devices in the ADV715x series of workstation parts.
220 MHz – True Color • •
220 MHz – Pseudo Color • • •
*See ADV7151 and ADV7150 data sheets for more information on these parts. nected together for use in multipalette and window applications. tive 30-Bit True-Color operation. erator chip circuit, such as the AD730. standards, without requiring external buffering. users system level debugging. Control Circuit of the part operational . Figure 12. Multiplexed Color Inputs for the ADV7150
devices can be connected, in parallel, directly to the device.
132 MHz
Figure 13. Direct Interfacing of Video Memory to ADV7150 data formats in 4:1, 2:1 and 1:1 multiplex modes. buffers shift clock signals. Figure 14. Clock Control Circuit of the ADV7150 include SYNC, BLANK and PS0–PS1. anywhere during the LOADIN cycle. signals are latched into the part on the rising edge of LOADIN. signal of a computer monitor. there is no match the device is effectively shut down.
Register 1 which executes a calibration on every Vertical Sync. Bit MR11 of Mode Register 1 determine the color mode. Figure 19. 24-Bit to 30-Bit True-Color Configuration Corrected True-Color Images. This mode sets the part into direct 24-bit True-Color operation. Red, Green and Blue) and essentially acts as a bypass RAM. Figure 20. 24-Bit to 24-Bit Direct True-Color Configuration DACs with 30-bit data (10 bits each for Red, Green and Blue).
8 RED
Figure 21. 8-Bit to 30-Bit Pseudo-Color Configuration of a total palette of millions of addressable colors. DACs with 24-bit data (8 bits each for Red, Green and Blue). Figure 22. 8-Bit to 24-Bit Pseudo-Color Configuration of a total palette of millions of addressable colors.
Figure 26. 15-Bit True-Color Mapping Using R0–R7 and internal register configuration. CE input latches data to or from the part.
–19–REV. A Table III. Interface Truth Table (10-Bit Databus Mode) R/W C1 C0 Databus (D9–D0) Operation Result 0 1 1 DB7–DB0 Write to Mode Register DB7–DB0 Õ MR17–MR10 0 0 0 DB7–DB0 Write to Address Register DB7–DB0 Õ A7–A0 0 1 0 DB7–DB0 Write to Control Registers DB7–DB0 Õ Control Register (Particular Control Register Determined by Address Register ) 0 0 1 DB9–DB0 Write to RED Register DB9–DB0 Õ R9–R0 0 0 1 DB9–DB0 Write to GREEN Register DB9–DB0 Õ G9–G0 0 0 1 DB9–DB0 Write to BLUE Register DB9–DB0 Õ B9–B0 Write RGB Data to RAM Location Pointed to by Address Register (A7–A0) Address Register = Address Register + 1 1 1 1 DB7–DB0 Read Mode Register MR17–MR10 Õ DB7–DB0 1 0 0 DB7–DB0 Read Address Register A7–A0 Õ DB7–DB0 1 1 0 DB7–DB0 Read Control Registers Register Data Õ DB7–DB0 (Particular Control Register Determined by Address Register) 1 0 1 DB9–DB0 Read RED RAM Location R9–R0 Õ DB9–DB0 1 0 1 DB9–DB0 Read GREEN RAM Location G9–G0 Õ DB9–DB0 1 0 1 DB9–DB0 Read BLUE RAM Location B9–B0 Õ DB9–DB0 (RAM Location Pointed to by Address Register(A7–A0)) Address Register = Address Register + 1 DB = Data Bit. Table IV. Interface Truth Table (8-Bit Databus Mode)* R/W C1 C0 Databus (D7–D0) Operation Result 0 1 1 DB7–DB0 Write to Mode Register DB7–DB0 Õ MR17–MR10 0 0 0 DB7–DB0 Write to Address Register DB7–DB0 Õ A7–A0 0 1 0 DB7–DB0 Write to Control Registers DB7–DB0 Õ Control Registers (Particular Control Register Determined by Address Register (A7–A0)) 0 0 1 DB9–DB2 Write to RED Register DB9–DB2 Õ R9–R2 0 0 1 DB1–DB0 Write to RED Register DB1–DB0 Õ R1–R0 0 0 1 DB9–DB2 Write to GREEN Register DB9–DB2 Õ G9–G2 0 0 1 DB1–DB0 Write to GREEN Register DB1–DB0 Õ G1–G0 0 0 1 DB9–DB2 Write to BLUE Register DB9–DB2 Õ B9–B2 0 0 1 DB1–DB0 Write to BLUE Register DB1–DB0 Õ B1–B0 Write RGB Data to RAM Location Pointed to by Address Register (A7-A0) Address Register = Address Register + 1 1 1 1 DB7–DB0 Read Mode Register MR17–MR10 Õ DB7–DB0 1 0 0 DB7–DB0 Read Address Register A7–A0 Õ DB7–DB0 1 1 0 DB7–DB0 Read Control Registers Register Data Õ DB7–DB0 (Particular Control Register Determined by Address Register) 1 0 1 DB9–DB2 Read RED RAM Location R9–R2 Õ DB9–DB2 1 0 1 DB1–DB0 Read RED RAM Location R1–R0 Õ DB1–DB0 1 0 1 DB9–DB2 Read GREEN RAM Location G9–G2 Õ DB9–DB2 1 0 1 DB1–DB0 Read GREEN RAM Location G1–G0 Õ DB1–DB0 1 0 1 DB9–DB2 Read BLUE RAM Location B9–B2 Õ DB9–DB2 1 0 1 DB1–DB0 Read BLUE RAM Location B1–B0 Õ DB1–DB0 (RAM Location Pointed to by Address Register (A7–A0)) Address Register = Address Register + 1 *Writing or reading 10-bit data (DB9–DB0) over an 8-bit databus (D7–D0) requires two write or two read cycles. :DB9–DB2 is mapped to D7–D0 on the first cycle. :DB1–DB0 is mapped to D1–D0 on the second cycle. DB = Data Bit.
–20– REV. A Power-On Reset On power-up of the ADV7150 executes a power-on reset opera- tion. This initializes the pixel port such that the pixel sequence ABCD starts at A. The Mode Register (MR17–MR10), Com- mand Register 2 (CR27–CR20) and Command Register 3 (CR37–CR30) have all bits set to a Logic “1.” Command Regis- ter 1 (CR17–CR10) has all bits set to a Logic “0.” The output clocking signals are also set during this reset period. PRGCKOUT = CLOCK/32 LOADOUT = CLOCK/4 The power-on reset is activated when V AA goes from 0 V to 5 V. This reset is active for 1 µs. The ADV7150 should not be accessed during this reset period. The pixel clock should be applied at power-up. REGISTER PROGRAMMING The following section describes each register, including Address Register, Mode Register and each of the nine Control Registers in terms of its configuration. Address Register (A7–A0) As illustrated in the previous tables, the C0 and C1 control in- puts, in conjunction with this address register specify which control register, or color palette location is accessed by the MPU port. The address register is 8-bits wide and can be read from as well as written to. When writing to or reading from the color palette on a sequential basis, only the start address needs to be written. After a red, green and blue write sequence, the address register is automatically incremented. MODE REGISTER MR1 (MR19–MR10) The mode register is a 10-bit wide register. However for pro- gramming purposes, it may be considered as an 8-bit wide regis- ter (MR18 and MR19 are both reserved). It is denoted as MR17–MR10 for simplification purposes. The diagram shows the various operations under the control of the mode register. This register can be read from as well written to. In read mode, if MR18 and MR19 are read back, they are both returned as zeros. Mode Register (MR17–MR10) Bit Description Reset Control (MR10) This bit is used to reset the pixel port sampling sequence. This ensures that the pixel sequence ABCD starts at A. It is reset by writing a “1” followed by a “0” followed by a “1.” This bit must be run through this cycle during the initialization sequence. RAM-DAC Resolution Control (MR11) When this is programmed with a “1,” the RAM is 30 bits deep (10 bits each for red, green and blue) and each of the three DACs is configured for 10-bit resolution. When MR11 is programmed with a “0,” the RAM is 24-bits deep (8 bits each for red, green and blue) and the DACs are configured for 8-bit resolution. The two LSBs of the 10-bit DACs are pulled down to zero in 8-bit RAM-DAC mode. MPU Databus Width (MR12) This bit determines the width of the MPU port. It is configured as either a 10-bit wide (D9–D0) or 8-bit wide (D7–D0) bus. 10-bit data can be written to the device when configured in 8-bit wide mode. The 8 MSBs are first written on D7–D0, then the two LSBs are written over D1–D0. Bits D9–D8 are zeros in 8-bit mode. Operational Mode Control (MR14–MR13) When MR14 is “0” and MR13 is “1,” the part operates in normal mode. Calibrate LOADIN (MR15) This bit automatically calibrates the onboard LOADIN/ LOADOUT synchronization circuit. A “0” to “1” transition initiates calibration. This bit is set to “0” in normal operation. See “Pipeline Delay and Calibration” section. This bit must be run through this cycle during the initialization sequence. MR17 MR16 * THESE BITS ARE READ-ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00." RESERVED* MR16 PS0 MR17 PS1 PALETTE SELECT MATCH BITS CONTROL RAM-DAC RESOLUTION CONTROL 0 8-BIT 1 10-BIT MR11 MPU DATA BUS WIDTH 0 8-BIT (D7–D0) 1 10-BIT (D9–D0) MR12 CALIBRATE LOADIN MR15 RESET CONTROL MR10 OPERATIONAL MODE CONTROL 0 0 RESERVED 0 1 NORMAL OPERATION 1 0 RESERVED 1 1 RESERVED MR14 MR13 MR19 MR18 MR15 MR14 MR13 MR12 MR11 MR10 Mode Register 1 (MR1) (MR19–MR10)
–21–REV. A Palette Select Match Bits Control (MR17–MR16) These bits allow multiple palette devices to work together. When bits PS1 and PS0 match MR17 and MR16 respectively, the device is selected. If these bits do not match, the device is not selected and the analog video outputs drive 0 mA, see “Palette Priority Select Inputs” section. CONTROL REGISTERS The ADV7150 has 9 control registers. To access each register, two write operations must be performed. The first write to the address register specifies which of the 9 registers is to be ac- cessed. The second access determines the value written to that particular control register. Pixel Test Register (Address Reg (A7–A0) = 00H) This register is used when the device is in test/diagnostic mode. It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide read-only register which allows the MPU to read data on the pixel port, see “Test Diagnostic” section. DAC Test Register (Address Reg (A7–A0) = 01H) This register is used when the device is in test/diagnostic mode. It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide read-only register which allows MPU access to the DAC port, see “Test Diagnostic” section. SYNC, BLANK and IPLL Test Register (Address Reg (A7–A0) = 02H) This register is used when the device is in test/diagnostic mode. It is a 3-bit wide (3 LSBs) read/write register which allows MPU access to these particular pixel control bits, see “Test Diagnos- tic” section. ID Register (Address Reg (A7–A0) = 03H) This is an 8-bit wide “Identification” read-only register. For the ADV7150 it will always return the hexadecimal value 8EH. Pixel Mask Register (Address Reg (A7–A0) = 04H) The contents of the pixel mask register are individually bit-wise logically AND-ed with the Red, Green and Blue pixel input stream of data. It is an 8-bit read/write register with D0 corre- sponding to R0, G0 and B0. For normal operation, this register is set with FFH. COMMAND REGISTER 1 (CR1) (Address Reg (A7–A0) = 05H) This register contains a number of control bits as shown in the diagram. CR1 is a 10-bit wide register. However for program- ming purposes, it may be considered as an 8-bit wide register (CR18 to CR19 are reserved). The diagram below shows the various operations under the con- trol of CR1. This register can be read from as well as written to. In write mode, “0” should be written to CR11 and CR13 to CR17. In read mode, CR11 and CR13 to CR19 are returned as zeros. COMMAND REGISTER 1-BIT DESCRIPTION Calibration Control (CR10) This bit automatically calibrates the onboard LOADIN/ LOADOUT synchronization circuit. MR15 of Mode Register MR1 must be set to “0.” SYNCOUT Control (CR12) This bit specified whether the video SYNCOUT signal is to be enabled. On power up a “0” is written to the bit and “SYNCOUT” is set three-state. *THESE BITS ARE READ–ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00." CR12
0 DISABLE
1 ENABLE
CR17 CR16 CR15 CR14 CR12 CR11 CR10CR13 RESERVED* CR11 (0) THIS BIT SHOULD BE SET TO ZERO CALIBRATION CONTROL CR10 DISABLE CALIBRATES ON EVERY VERTICAL SYNC (MR15=0) CR17-CR13 (00000) THESE BITS SHOULD BE SET TO ZERO CR18CR19 Command Register 1 (CR1) (CR19–CR10)
–22– REV. A COMMAND REGISTER 2 (CR2) (Address Reg (A7–A0) = 06H) This register contains a number of control bits as shown in the diagram. CR2 is a 10-bit wide register. However, for program- ming purposes, it may be considered as an 8-bit wide register (CR28 and CR29 are both reserved). The diagram shows the various operations under the control of CR2. This register can be read from as well written to. In read mode, CR28 and CR29 are both returned as zeros. COMMAND REGISTER 2-BIT DESCRIPTION R7 Trigger Polarity Control (CR20) This bit is used when the device is in test/diagnostic mode. It determines whether the pixel data is latched into the test regis- ters in the rising or falling edge of R7. (See “Test Diagnostics” section.) IPLL Trigger Control (CR21) This bit specifies whether the I PLL output is triggered from BLANK or SYNC. SYNC Recognition Control (CR22) This bit specifies whether the video SYNC input is to be encoded onto the IOG analog output or ignored. Pedestal Enable Control (CR23) This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes- tal is to be generated on the video outputs. True-Color/Pseudo-Color Mode Control (CR27–CR24) These 4 bits specify the various color modes. These include a 24-bit true-color mode, two 15-bit true-color modes and three 8-bit pseudo color modes. CR20 RESERVED* CR26 CR25 CR24CR27 CR21 IPLL TRIGGER CONTROL SYNC BLANK R7 TRIGGER POLARITY CONTROL CR20 CR29 CR28 CR22
0 IGNORE
1 DECODE
*THESE BITS ARE READ- ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00." CR21CR23 CR22 TRUE COLOR/PSEUDO-COLOR MODE CONTROL MODE 0111 1000 1 000 110 1 CR27 CR26 CR24 CR25 11 0 0 0 0 00 8-BIT PSEUDO COLOR ON R7–R0 8-BIT PSEUDO COLOR ON G7–G0 8-BIT PSEUDO COLOR ON B7–B0 15-BIT TRUE COLOR ON R7–R3, G7–G3, B7–B3 15-BIT TRUE COLOR ON R7–R0, G6–G0 24-BIT TRUE COLOR R7–R0, G7–G0, B7–B0 PEDESTAL ENABLE CONTROL CR23 0 0 IRE 1 7.5 IRE Command Register 2 (CR2) (CR29–CR20)
–23–REV. A COMMAND REGISTER 3 (CR3) (Address Reg (A7–A0) = 07H) This register contains a number of control bits as shown in the diagram. CR3 is a 10-bit wide register. However for program- ming purposes, it may be considered as an 8-bit wide register (CR38 and CR39 are both reserved). The diagram shows the various operations under the control of CR3. This register can be read from as well written to. In read mode, CR38 and CR39 are both returned as zeros. COMMAND REGISTER 3-BIT DESCRIPTION PRGCKOUT Frequency Control (CR31–CR30) These bits specify the output frequency of the PRGCKOUT output. PRGCKOUT is a divided down version of the pixel CLOCK. BLANK Pipeline Delay Control (CR35–CR32) These bits specify the additional pipeline delay that can be added to the BLANK function, relative to the overall device pipeline delay (tPD). As the BLANK control normally enters the video DAC from a shorter pipeline than the video pixel data, this control is useful in deskewing the pipeline differential. Pixel Multiplex Control (CR37–CR36) These bits specify the device’s multiplex mode. It, therefore, also determines the frequency of the LOADOUT signal. LOADOUT is a divided down version of the pixel CLOCK. Revision Register (Address Reg (A7–A0) = 0BH) This register is a read only register containing the revision of silicon. CR39 CR38 CR37 CR36 CR35 CR34 CR32 CR31 CR30 CR33 *THESE BITS ARE READ- ONLY RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00." PRGCKOUT FREQUENCY CONTROL CR31 CR30 CLOCK ‚ 4 CLOCK ‚ 8 CLOCK ‚ 16 CLOCK ‚ 32 RESERVED* PIXEL MULTIPLEX CONTROL CR37 CR36 1:1 MUXING: LOADOUT = CLOCK ‚ 1 2:1 MUXING LOADOUT = CLOCK ‚ 2 RESERVED 4:1 MUXING :LOADOUT = CLOCK ‚ 4 EXTRA BLANK PIPELINE DELAY CONTROL (ADDS TO PIXEL PIPELINE DELAY; tPD ) CR35 CR34 CR33 CR32 tPD tPD + 1 x LOADOUT tPD + 2 x LOADOUT tPD + 15 x LOADOUT Command Register 3 (CR3) (CR39–CR30)
signals IOR (red video), IOG (green video) and IOB (blue video). The analog video outputs are high impedance current sources. directly drive a 37.5 Ω load (doubly terminated 75 Ω ). Figure 29. DAC Output Termination (Doubly Terminated corresponding control input stimuli.
7.5 IRE
40 IRE
Figure 30. Composite Video Waveform ( SYNC Decoded forms are shown in the diagrams. Decoded on IOG; Pedestal = 0 IRE; R SET = 265 Ω .
100 IRE
43 IRE
Figure 31. Composite Video Waveform SYNC
92.5 IRE
Figure 32. Composite Video Waveform Figure 33. Composite Video Waveform
265 SYNC decoded on IOG; Pedestal = 0 IRE
259 No SYNC decoded; Pedestal = 0 IRE
–26– REV. A APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS VAA VREF R SET IOR IOG IOB IPLL GND COMP IOR IOG IOB R SET 280W 1kW (1% METAL) AD589 (1.2V REF) 0.1mF +5V (VAA ) 75W 75W 75W 75W 75W 75W COMPLIMENTARY OUTPUTS CO-AXIAL CABLE (75W ) BNC CONNECTORS MONITOR (CRT) +5V (VAA ) 0.1mF ANALOG POWER PLANE 33mF +5V (VAA ) 0.1mF +5V (VCC ) (FERRITE BEAD) NOTES: 1. ALL RESISTORS ARE 1% METAL FILM 2. 0.1mF AND 0.01mF CAPACITORS ARE CERAMIC 3. ADDITIONAL DIGITALCIRCUITRY OMITTED FOR CLARITY ADV7150 POWER SUPPLY DECOUPLING (0.1 mF AND 0.01mF CAPACITOR FOR EACH V AA GROUP) Recommended Analog Circuit Layout power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7150. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7150 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode. Supply Decoupling For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable opera- tion, to reduce the lead inductance. Best performance is obtained with 0.1 µF ceramic capacitor decoupling. Each group of V AA pins on the ADV7150 must have at least one 0.1 µF decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7150 contains cir- cuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power sup- ply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. The ADV7150 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is impera- tive that these same design and layout techniques be applied to the system level design such that high speed, accurate perfor- mance is achieved. The “Recommended Analog Circuit Layout” shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7150 power and ground lines by shielding the digital inputs and pro- viding good decoupling. The lead length between groups of V AA and GND pins should by minimized so as to minimize inductive ringing. Ground Planes The ground plane should encompass all ADV7150 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7150, the analog output traces, and all the digital signal traces leading up to the ADV7150. The ground plane is the graphics board’s common ground plane. Power Planes The ADV7150 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB
–27–REV. A Digital Signal Interconnect The digital inputs to the ADV7150 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7150 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (V CC), and not the analog power plane. Analog Signal Interconnect The ADV7150 should be located as close as possible to the out- put connectors to minimize noise pick-up and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital Inputs, especially Pixel Data Inputs and clocking signals (CLOCK, LOADOUT, LOADIN, etc.) should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the analog outputs (IOR, IOG, IOB) should each have a 75 Ω load resistor connected to GND. These resistors should be placed as close as possible to the ADV7150 so as to minimize reflections. Normally, the differen- tial analog outputs ( IOR, IOG, IOB) are connected directly to GND. In some applications, improvements in performance are achieved by terminating these differential outputs with a resis- tive load similar in value to the video load. For a doubly termi- nated 75 Ω load, this means that IOR, IOG, IOB are each terminated with 37.5 Ω resistors. APPENDIX 2 TYPICAL FRAME BUFFER INTERFACE CLOCK ADV7150 CLOCK LOADOUT PRGCKOUT LOADIN SCKOUT SCKIN BLANK LATCH ENABLESYNC ECL TO TTL DIVIDE BY N (‚ N) VRAM (BANK A) VRAM (BANK B) FRAME BUFFER/ VIDEO MEMORY MULTIPLEXER 24 TO PALETTE/RAM & DAC 2424 2424 BLANK SYNC CLOCK GRAPHICS PROCESSOR/ CONTROLLER VRAM (BANK C) 2424 VRAM (BANK D) 2424 33MHz 33MHz 33MHz 33MHz DIVIDE BY M (‚ M) CLOCK GENERATOR
–28– REV. A 10-Bit DACs 10-Bit RAM-DAC resolution allows for nonlinear video correc- tion, in particular Gamma Correction. The ADV7150 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. In true-color mode, for example, the part effectively operates as a 24-bit to 30-bit color look-up table. Up to now we have assumed that there exists a linear relation- ship between the actual RGB values input to a monitor and the intensity produced on the screen. This, however, is not the case. Half scale digital input (1000 0000) might correspond to only 20% output intensity on the CRT (Cathode Ray Tube). The intensity CRT) produced on a CRT by an input value I IN is given by: ICRT = (IIN)χ where χ ranges from 2.0 to 2.8. If the individual values of χ for red, green and blue are known, then so called “Gamma Correction” can be applied to each of the three video input signals (I IN); therefore: I IN(corrected) = k(IIN)1/χ (k = 1, normally) Traditionally, there has been a tradeoff between implementing a nonlinear graphics function, such as gamma correction, and color dynamic range. The ADV7150 overcomes this by increas- ing the individual color resolution of each of the red, green and blue primary colors from 8 bits per color channel to 10 bits per channel (24 bits to 30 bits). The table highlights the loss of resolution when 8-bit data is gamma-corrected to a value of 2.7 and quantized in a tradi- tional 8-bit system. Note that there is no change in the 8-bit quantized data for linear changes in the input data over much of the transfer function. On the other hand, when quantized to 10 bits via the 10-bit RAMs and 10-bit DACs of the ADV7150, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data. The graph shows a typical gamma curve corresponding to a gamma value of 2.7. This is programmed to the red, green and blue RAMs of the color lookup table instead of the more tradi- tional linear function. Different curves corresponding to any particular gamma value can be independently programmed to each of the red, green and blue RAMs. Other applications of the 10-bit RAM-DAC include closed-loop monitor color calibration. Gamma Correction 8 Bits vs. 10 Bits Gamma Corrected Quantized to Quantized to 8-Bit Data (2.7) 8 Bits 10 Bits 240 0.977797 250 1001 241 0.979304 250 1002 242 0.980807 251 1004 243 0.982306 251 1005 244 0.983801 251 1007 245 0.985292 252 1008 246 0.986780 252 1010 247 0.988264 252 1011 248 0.989744 253 1013 249 0.991220 253 1015 250 0.992693 254 1016 251 0.994161 254 1018 252 0.995626 254 1019 253 0.997088 255 1021 254 0.998546 255 1022 255 1.000000 255 1023 1.00 0.00 256 0.30 0.10 0.20 0.60 0.40 0.50 0.70 0.80 0.90 2241921601289664 INPUT CODE – Decimal DAC OUTPUT – Normalized to 1 GAMMA CORRECTION CURVE LINEAR RESPONSE PRECEIVED BY THE EYE CRT RESPONSE Gamma Correction Curve (Gamma Value = 2.7) APPENDIX 3 10-BIT DACS AND GAMMA CORRECTION
–29–REV. A APPENDIX 4 MULTIPLE PALETTE APPLICATIONS Palette Priority Select Inputs The palette priority selection inputs allow up to four separate palette devices to be used in a single system to drive a single monitor with subpixel resolution. The IOR, IOG and IOB ana- log video output signals of each device are connected together, as shown. Signal inputs (PS0, PS1) determine on a pixel by pixel basis which palette device drives the monitor. This allows for implementation of multiple windows applications with each device acting as an in dependent palette. During initialization, each device is assigned two match bits, MR16 (PS0) and MR17 (PS1) in Mode Register MR1. PS0 and PS1 inputs will select one of the preprogrammed devices at any instant when PS0, PS1 matches MR16, MR17, respectively. PS0 and PS1 are multi- plexed similar to the pixel data, thus allowing for subpixel resolu- tion. The diagrams show an example of one ADV7150 operating in conjunction with three ADV7151’s (Pseudo-Color RAM-DACs). Each displayed window on the monitor is driven by one of the four devices, as determined on a pixel basis by PS0, PS1. Each device’s analog output signals are connected together as shown. Note: Only one palette device is selected at any particular instant. The analog output levels of the unselected devices will be 0 mA. Other applications for the palette priority function using a mini- mum of two devices (one ADV7150 and one ADV7151) include: Cursor Overlay on 24-Bit Graphics Active Live Video Overlay (from Frame Grabber) Text/Character Generation and Overlay DACs IOR, IOG, IOB ZO = 75Ω ZS = 75Ω (SOURCE TERMINATION) ZL = 75Ω (MONITOR) (CABLE) DACs IOR, IOG, IOB (DEVICE: 2) (DEVICE: 1) Multiple Devices Termination for a Single Monitor ADV7150 ADV7151 (1) 256 x 30 RAM 256 x 30 PALETTE PALETTE SELECT BITS ANALOG O/P RGB ANALOG VIDEO VIDEO TO MONITOR PS0, PS1 256 x 30 PALETTE RGB ANALOG VIDEO RGB ANALOG VIDEO ADV7151 (2) ADV7151 (3) R0–R7 G0–G7 B0–B7 WINDOW 1 (Pseudo-Color) PS0=0: PS1=1 WINDOW 3 (Pseudo-Color) PS0=1: PS1=1 MONITOR WINDOW 2 (Pseudo-Color) PS0=1: PS1=0 TRUE-COLOR BACKGROUND MR16 MR17 0 0 PALETTE SELECT BITS MR16 MR17 0 1 PALETTE SELECT BITS MR16 MR17 1 0 PALETTE SELECT BITS MR16 MR17 1 1 256 x 30 PALETTE P0–P7 Multiple Devices Driving a Multiwindow Application
–30– REV. A ADV7150 Initialization After power has been supplied, the ADV7150 must be initial- ized. The Mode Register and Control Registers must be set. The values written to the various registers will be determined by the desired operating mode of the part, i.e., True Color/Pseudo Color, 2:1 Muxing/2:1 Muxing, etc. The following section gives examples of initialization of the ADV7150 operating in various modes. Example 1 Color Mode 24-Bit True Color Multiplexing 2:1 Databus 8-Bit RAM-DAC Resolution 8-Bit SYNC Enabled on IOG Pedestal 7.5 IRE Register Initialization C1 C0 R/ W Comment Write 09H to Mode Register (MR1) 1 1 0 Resets to Normal Operation, 8-Bit Bus/RAM-DAC Write 08H to Mode Register (MR1) 1 1 0 *(Initializes Pipelining Write 09H to Mode Register (MR1) 1 1 0 *( “ Write 29H to Mode Register (MR1) 1 1 0 *(Calibrates LOADOUT/LOADIN Timing Write 09H to Mode Register (MR1) 1 1 0 *( “ Write 04H to Address Register (A7–A0) 0 0 0 Address Reg Points to Pixel Mask Register Write FFH to Pixel Mask Register 1 0 0 Sets the Pixel Mask to All “1s” Write 05H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 1 (CR1) Write 00H to Command Reg 1 (CR1) 1 0 0 Write 06H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 2 (CR2) Write ECH to Command Reg 2 (CR2) 1 0 0 Sets 24-Bit Color, 7.5 IRE, SYNC on Green (IOG) Write 07H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 3 (CR3) Write C0H to Command Reg 3 (CR3) 1 0 0 Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/4 Color Palette RAM Initialization C1 C0 R/ W Comment Write 00H to Address Register (A7–A0) 0 0 0 Points to Color Palette RAM Write 00H (Red Data) to RAM Location (00H) 0 1 0 (Initializes Palette RAM Write 00H (Green Data) to RAM Location (00H) 0 1 0 ( to a Linear Ramp Write 00H (Blue Data) to RAM Location (00H) 0 1 0 ( Write 01H (Red Data) to RAM Location (01H) 0 1 0 ( Write 01H (Green Data) to RAM Location (01H) 0 1 0 ( Write 01H (Blue Data) to RAM Location (01H) 0 1 0 ( Write FFH (Red Data) to RAM Location (FFH) 0 1 0 ( Write FFH (Green Data) to RAM Location (FFH) 0 1 0 ( Write FFH (Blue Data) to RAM Location (FFH) 0 1 0 (RAM Initialization Complete These four command lines reset the ADV7150. The pipelines for each of the Red, Creen and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” input. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed by a “1” followed by a “0” to Mode Register MR15. **This sequence of instructions would, of course, normally be coded using some form of loop instruction. APPENDIX 5 INITIALIZATION AND PROGRAMMING
–31–REV. A Example 2 Color Mode 24-Bit Gamma Corrected True Color (30 Bits) Multiplexing 2:1 Databus 10 Bit RAM-DAC Resolution 10 Bit SYNC Ignored Pedestal 0 IRE Calibration Every Vertical Sync Register Initialization C1 C0 R/ W Comment Write 0FH to Mode Register (MR1) 1 1 0 Resets to Normal Operation, 10-Bit Bus/RAM-DAC Write 0EH to Mode Register (MR1) 1 1 0 *(Initializes Pipelining Write 0FH to Mode Register (MR1) 1 1 0 *( “ Write 2FH to Mode Register (MR1) 1 1 0 *(Calibrates LOADOUT/LOADIN Timing Write 0FH to Mode Register (MR1) 1 1 0 *( “ Write 04H to Address Register (A7–A0) 0 0 0 Address Reg Points to Pixel Mask Register Write FFH to Pixel Mask Register 1 0 0 Sets the Pixel Mask to All “1s” Write 05H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 1 (CR1) Write 01H to Command Reg 1 (CR1) 0 0 0 Calibrates Every Vertical Sync Write 06H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 2 (CR2) Write E0H to Command Reg 2 (CR2) 1 0 0 Sets 24-Bit Color, 0 IRE, No SYNC Write 07H to Address Register (A7–A0) 0 0 0 Address Reg Points to Command Register 3 (CR3) Write 41H to Command Reg 3 (CR3) 1 0 0 Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/8 Color Palette RAM Initialization C1 C0 R/ W Comment Write 00H to Address Register (A7–A0) 0 0 0 Points to Color Palette RAM Write 000H (Red Data) to RAM Location (00H) 0 1 0 (Initializes Palette RAM Write 000H (Green Data) to RAM Location (00H) 0 1 0 ( to a “Gamma” Ramp Write 000H (Blue Data) to RAM Location (00H) 0 1 0 ( Write xxxH (Red Data) to RAM Location (01H) 0 1 0 ( Write xxxH (Green Data) to RAM Location (01H) 0 1 0 ( Write xxxH (Blue Data) to RAM Location (01H) 0 1 0 ( Write 3FFH (Red Data) to RAM Location (FFH) 0 1 0 ( Write 3FFH (Green Data) to RAM Location (FFH) 0 1 0 ( Write 3FFH (Blue Data) to RAM Location (FFH) 0 1 0 (RAM Initialization Complete These four command lines reset the ADV7150 The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexer’s “A” in- put. Mode Register bit MR10 is written by a “1” followed by “0” followed by “1.” LOADIN/LOADOUT timing is internally synchronized by writing a “0” followed by a “1” followed by a “0” to Mode Register MR15. **Data for a gamma curve characteristic is obtainable in Appendix 3. REGISTER DIAGNOSTIC TESTING The previous examples show the register initialization sequence for the ADV7150. These show control data going to the regis- ters and palette RAM. As well as this writing function, it may also be necessary, due to system diagnostic requirements, to confirm that correct data has been transferred to each register and palette RAM location. There are two ways to incorporate register value/RAM value checking: 1. READ after each WRITE: After data is written to a particular register, it can be read back immediately. The following table shows an example with Command Registers CR2 and CR3. C1 C0 R/ W D0–D7 Comment 0 0 0 06H Select Command Register 2 (CR2) 1 0 0 E0H Sets 24-Bit True-Color 1 0 1 E0H Command Reg 2 Value Read-Back 0 0 0 07H Select Command Register 3 (CR3) 1 0 0 40H Set 2:1 Mux Mode 1 0 1 40H Command Reg 3 Value Read-Back 2. READ after all WRITEs completed: All registers and the color palette RAM are written to and set. Once this is complete, all registers are again accessed but this time in Read-Only mode. The table below shows this method for Command Registers CR2 and CR3. C1 C0 R/ W D0–D7 Comment 0 0 0 06H Select Command Register 2 (CR2) 1 0 0 E0H Sets 24-Bit True-Color 0 0 0 07H Select Command Register 3 (CR3) 1 0 0 40H Set 2:1 Mux Mode 0 0 0 06H Select CR2 1 0 1 E0H CR2 Value Read-Back 0 0 0 07H Select CR3 1 0 1 40H CR3 Value Read-Back 1 0 1 40H CR3 Value Read-Back It is clear that this latter case requires more command lines than the previous READ after each WRITE case.
–32– REV. A the graphics pipeline and after a number of clocks get latched into the DAC Test Register. This data can then be read from the Pixel Test Register and the DAC Test Registers over the MPU Port. This data will remain in the Pixel Test Registers and the DAC Test Registers until the next rising edge of R7 causes new data to be latched in. In the above example, the next rising edge of R7 occurs on the Pixel n input. Therefore the data in the Pixel Test Registers and DAC Test Registers must be read over the MPU before the Pixel n data is applied, otherwise they will be overwritten by the Pixel n data and the Pixel 2 data will be lost. Pixel Test Register The read-only Pixel Test Register is 24 bits wide, 8 bits each for red green and blue. It is situated directly after the Pixel Mask Register. After data is latched into this register by a transition on R7, it is read in three cycles over the MPU Port as described in the “Microprocessor (MPU) Port” section. DAC Test Register The DAC Test Register is latched with data some CLOCKs after the Pixel Test Register. The DAC Test Register is a 30-bit wide read-only register, corresponding to 10 bits each for red, green and blue data. It is located the Color Palette RAM. If the RAM-DAC is in 8-bit after resolution mode, the upper two bits of the red, green and blue data will be zero. After data is latched into the DAC Test Register by a transition on R7, it is read in three or six cycles over the MPU Port as described in the “Microprocessor (MPU) Port” section. SYNC, BLANK and IPLL Test Register This is an 8-bit wide register but with only three effective bits. The three lower bits correspond to SYNC, BLANK and IPLL respectively. The upper bits should be masked in software. This register is at the same position in the graphics pipeline as the DAC Test Register. When pixel data is latched into the DAC Test Register, the corresponding status of SYNC, BLANK and IPLL is latched into this register. It is read over the MPU Port as described in the “Microprocessor (MPU) Port” section. (Note: If BLANK is low, the corresponding pixel data to the DAC Test Register will be all “0s.”) The ADV7150 contains onboard circuitry which enables both device and system level test diagnostics. The test circuitry can be used to test the frame buffer memory as well as the function- ality of the ADV7150. A number of test registers are integrated into the part which effectively allow for monitoring of the graph- ics pipeline. Pixel data is read from the graphics pipeline inde- pendent of the pixel CLOCK. The pixel data itself contains the triggering information that latches data into the test registers. This allows for system diagnostics in a continuously clocked graphics system. The test register data is then read by the micro- processor over the MPU. Access to the test registers is as described in the “Microproces- sor (MPU) Port” section. This section also gives the address decode locations for the various test registers. Test Trigger (R7) The test trigger is decoded from the pixel data stream. Bit R7 of the RED channel is assigned the task of latching pixel data into the test registers. A “0” to “1” or a “1” to “0” (as determined by bit CR20 of Command Register 2) transition on R7, fills the test register with the corresponding pixel data. This effectively means that a sequence of data travels along the graphics pipe- line, with the test registers taking a sample only when there is a transition on Bit R7. The following example shows a sequence with the ADV7150 preset to sample the graphics pipeline on a low to high transition of R7. RED GREEN BLUE Pixel 0: 00000000 00000000 00000000 In the above sequence of pixels, there is a rising edge on R7 on Pixel 2. The Red, Green and Blue data for Pixel 2, therefore, gets latched into the Pixel Test Register. Pixel 2 continues down APPENDIX 6 TEST DIAGNOSTICS MPU PORT CE R/W C0 C1 D0–D9 PIXEL TEST REGISTER DAC TEST REGISTERS COLOR REGISTERS COLOR PALETTE RAM TRIGGER DECODE TRIGGER DECODE GRAPHICS PIPELINE GRAPHICS PIPELINEINPUT MUX PIXEL DATA SYNC BLANK DACs SYNC BLANK IPLL REGISTER TEST Test/Diagnostic Block Diagram
–33–REV. A APPENDIX 7 THERMAL AND ENVIRONMENTAL CONSIDERATIONS The ADV7150 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and environmental conditions in which the ADV7150 must operate. Reliability of the device is significantly enhanced by keeping it as cool as pos- sible. In order to avoid destructive damage to the device, the absolute maximum junction temperature of 150 °C must never be exceeded. Certain applications, depending on pixel data rates, may require forced air cooling, or external heatsinks. The following data is intended as a guide in evaluating the operating conditions of a particular application so that optimum device and system performance is achieved. It should be noted that information on package characteristics pub- lished herein may not be the most up to date at the time of reading this. Advances in package compounds and manufacture will inevita- bly lead to improvements in the thermal data. Please co ntact your local sales office for the most up-to-date information. Power Dissipation The diagram shows graphs of power dissipation in watts vs. pixel clock frequency for the ADV7150. POWER DISSIPATION – W atts 1.50 0.50 1.25 0.75 1.00 PIXEL CLOCK FREQUENCY – MHz 60 220 80 180 200 160140120100 VAA = 5V VREF = 1.2V TA = +25°C NOTE: THE "WORST CASE ON-SCREEN PATTERN" CORRESPONDS TO FULL-SCALE TRANSITION ON EACH PIXEL VALUE FOR EVERY CLOCK EDGE (00H, FFH, 00H, ... ). THE "TYPICAL ON-SCREEN PATTERN" CORRESPONDS TO LINEAR CHANGES IN THE PIXEL INPUT (I. E., A BLACK TO WHITE RAMP). IN GENERAL, COLOR IMAGES TEND TO APPROXIMATE THIS CHARACTERISTIC. Typical Power Dissipation vs. Pixel Rate Package Characteristics The table of thermal characteristics shows typical information for the ADV7150 (160-Lead Plastic Power QFP) using various values of Airflow. Junction to Case (θJC) Thermal Resistance for this particular part is: θJC (160-Lead Plastic Power QFP) = 1.0°C/W (Note: θJC is independent of airflow.) Table A. Thermal Characteristics vs. Airflow Air Velocity 0 50 100 200 (Linear feet/min) (Still Air) θJA (°C/W) No Heatsink 25.5 23 21 19 EG&G D10100-28 Heatsink 23 20 18 16 Thermalloy 2290 Heatsink 19 17 15 12 Thermal Model The junction temperature of the device in a specific application is given by: TJ = TA + PD (θJC + θCA) (1) or TJ = TA + PD (θJA) (2) where: TJ = Junction Temperature of Silicon ( °C) TA = Ambient Temperature ( °C) PD = Power Dissipation (W) θJC = Junction to Case Thermal Resistance ( °C/W) θCA = Case to Ambient Thermal Resistance ( °C/W) θJA = Junction to Ambient Thermal Resistance ( °C/W) Package Enhancements The standard QFP package has been enhanced to a PowerQuad2 package. This supports an improved thermal performance com- pared to standard QFP. In this case, the die is attached to heatslug so that the power that is dissipated can be conducted to the external surface of the package. This provides a highly effi- cient path for the transfer of heat to the package surface. The package configuration also provides an efficient thermal path from the ADV7150 to the Printed Circuit Board via the leads. Heatsinks The maximum silicon junction temperature should be limited to 100°C. Temperatures greater than this will reduce long term device reliability. To ensure that the silicon junction tempera- ture stays within prescribed limits, the addition of an external heatsink may be necessary. Heatsinks, will reduce θ JA as shown in the “Thermal Characteristics vs. Airflow” table.
–34– REV. A APPENDIX 8 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). S-160 160-Lead Plastic Power Quad Flatpack TOP VIEW (PINS DOWN) PIN 1 121 160 120 0.014 (0.35) 0.011 (0.27) 1.239 (31.45) 1.219 (30.95) 1.107 (28.10) 1.100 (27.90) SQ SQ 0.026 (0.65) MIN SEATING PLANE 0.160 (4.07) MAX 0.037 (0.95) 0.026 (0.65) 0.004 (0.10) MAX 0.145 (3.67) 0.125 (3.17) 0.070 (1.77) 0.062 (1.57) 0.070 (1.77) 0.062 (1.57) 10° 6°±4° 4°±4° MAX
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C1695–10–8/94PRINTED IN U.S.A. –36– REV. A