ADV7127KRUZ140

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADV7127 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 CMOS, 240 MHz 10-Bit High Speed Video DAC FUNCTIONAL BLOCK DIAGRAM D9–D0 GND R SET IOUT IOUT COMP ADV7127 VREFVOLTAGE* REFERENCE CIRCUIT PDOWN* POWER– DOWN MODE VAA DAC10DATA REGISTER CLOCK PSAVE *ON TSSOP VERSION ONLY

FEATURES

240 MSPS Throughput Rate

–70 dB typ: f CLK = 50 MHz; f OUT = 1 MHz –53 dB typ: f CLK = 140 MHz; f OUT = 40 MHz RS-343A/RS-170 Compatible Output Complementary Outputs DAC Output Current Range: 2 mA to 26 mA TTL Compatible Inputs Internal Voltage Reference (1.23 V) on TSSOP Package Single Supply +5 V/+3.3 V Operation 28-Lead SOIC Package and 24-Lead TSSOP Package Low Power Dissipation (30 mW min @ 3 V) Low Power Standby Mode (10 mW min @ 3 V) Power-Down Mode (60 mW min @ 3 V) Power-Down Mode Available on TSSOP Package Industrial Temperature Range (–40 8C to +85 8C)

APPLICATIONS

Digital Video Systems (1600 3 1200 @ 100 Hz) High Resolution Color Graphics Digital Radio Modulation Image Processing Instrumentation Video Signal Reconstruction Direct Digital Synthesis (DDS) Wireless LAN GENERAL DESCRIPTION The ADV7127 (ADV®) is a high speed, digital-to-analog con- vertor on a single monolithic chip. It consists of a 10-bit, video D/A converter with on-board voltage reference, comple- mentary outputs, a standard TTL input interface and high impedance analog output current sources. The ADV7127 has a 10-bit wide input port. A single +5 V/ +3.3 V power supply and clock are all that are required to make the part functional. The ADV7127 is fabricated in a CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7127 is available in a small outline 28-lead SOIC or 24-lead TSSOP package. The ADV7127 TSSOP package also has a power-down mode. Both ADV7127 packages have a power standby mode. The ADV7127 TSSOP package has an on-board voltage refer- ence circuit. The ADV7127 SOIC package requires an external reference. PRODUCT HIGHLIGHTS 1. 240 MSPS Throughput. 2. Guaranteed monotonic to 10 bits. 3. Compatible with a wide variety of high resolution color graphics systems including RS-343A and RS-170A. ADV is a registered trademark of Analog Devices, Inc.

–2– REV. 0 ADV7127–SPECIFICATIONS

5 V SOIC SPECIFICATIONS

Parameter Min Typ Max Units Test Conditions STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Integral Nonlinearity (BSL) –1 0.4 +1 LSB Differential Nonlinearity –1 0.25 +1 LSB Guaranteed Monotonic DIGITAL AND CONTROL INPUTS Input High Voltage, V IH 2V Input Low Voltage, V IL 0.8 V Input Current, IIN –1 +1 µAV IN = 0.0 V or VAA PSAVE Pull-Up Current 20 µA Input Capacitance, C IN 10 pF ANALOG OUTPUTS Output Current 2.0 18.5 mA Output Compliance Range, V OC 0 +1.4 V Output Impedance, ROUT 100 k Ω Output Capacitance, C OUT 10 pF I OUT = 0 mA Offset Error –0.025 +0.025 % FSR Tested with DAC Output = 0 V Gain Error2 –5.0 +5.0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE (Ext.) Reference Range, VREF 1.12 1.235 1.35 V POWER DISSIPATION Digital Supply Current3 3.4 9 mA f CLK = 50 MHz Digital Supply Current3 10.5 15 mA f CLK = 140 MHz Digital Supply Current3 18 25 mA f CLK = 240 MHz Analog Supply Current 33 37 mA R SET = 560 Ω Analog Supply Current 5 mA R SET = 4933 Ω Standby Supply Current4 2.1 5.0 mA PSAVE = Low, Digital and Control Inputs at VAA Power Supply Rejection Ratio 0.1 0.5 %/% NOTES 1Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz. 2Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V REF /RSET × K × (3FFH) and K = 7.9896. 3Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. 4These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range. Specifications subject to change without notice. (VAA = +5 V 6 5%, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications T MIN to TMAX unless otherwise noted, TJ MAX = 1108C)

–3–REV. 0 ADV7127

5 V TSSOP SPECIFICATIONS

Parameter Min Typ Max Units Test Conditions STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Integral Nonlinearity (BSL) –1 0.4 +1 LSB Differential Nonlinearity –1 0.25 +1 LSB Guaranteed Monotonic DIGITAL AND CONTROL INPUTS Input High Voltage, V IH 2V Input Low Voltage, V IL 0.8 V PDOWN Input High Voltage 2 3V PDOWN Input Low Voltage2 1V Input Current, IIN –1 +1 µAV IN = 0.0 V or VAA PSAVE Pull-Up Current 20 µA PDOWN Pull-Up Current 20 µA Input Capacitance, C IN 10 pF ANALOG OUTPUTS Output Current 2.0 18.5 mA Output Compliance Range, V OC 0 +1.4 V Output Impedance, ROUT 100 k Ω Output Capacitance, C OUT 10 pF I OUT = 0 mA Offset Error –0.025 +0.025 % FSR Tested with DAC Output = 0 V Gain Error3 –5.0 +5.0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE (Ext. and Int.) 4 Reference Range, VREF 1.12 1.235 1.35 V POWER DISSIPATION Digital Supply Current5 1.5 3 mA f CLK = 50 MHz Digital Supply Current5 46 m A f CLK = 140 MHz Digital Supply Current5 6.5 10 mA f CLK = 240 MHz Analog Supply Current 23 27 mA R SET = 560 Ω Analog Supply Current 5 mA R SET = 4933 Ω Standby Supply Current6 3.8 6 mA PSAVE = Low, Digital and Control Inputs at VAA PDOWN Supply Current 2 1m A Power Supply Rejection Ratio 0.1 0.5 %/% NOTES 1Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz. 2This power-down feature is only available on the ADV7127 in the TSSOP package. 3Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V REF /RSET × K × (3FFH ) and K = 7.9896. 4Internal voltage reference is available only on the ADV7127 TSSOP package. 5Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. 6These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range. Specifications subject to change without notice. (VAA = +5 V 6 5%, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications T MIN to TMAX unless otherwise noted, TJ MAX = 1108C)

–4– REV. 0 ADV7127–SPECIFICATIONS

3.3 V SOIC SPECIFICATIONS1

Parameter Min Typ Max Units Test Conditions STATIC PERFORMANCE Resolution (Each DAC) 10 Bits R SET = 680 Ω Integral Nonlinearity (BSL) –1 0.5 +1 LSB R SET = 680 Ω Differential Nonlinearity –1 0.25 +1 LSB R SET = 680 Ω DIGITAL AND CONTROL INPUTS Input High Voltage, V IH 2.0 V Input Low Voltage, V IL 0.8 V Input Current, IIN –1 +1 µAV IN = 0.0 V or VDD PSAVE Pull-Up Current 20 µA Input Capacitance, C IN 10 pF ANALOG OUTPUTS Output Current 2.0 18.5 mA Output Compliance Range, V OC 0 +1.4 V Output Impedance, ROUT 70 k Ω Output Capacitance, C OUT 10 pF Offset Error 0 0 % FSR Tested with DAC Output = 0 V Gain Error3 0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE (Ext.) Reference Range, VREF 1.12 1.235 1.35 V POWER DISSIPATION Digital Supply Current4 2.2 5.0 mA f CLK = 50 MHz Digital Supply Current4 6.5 12.0 mA f CLK = 140 MHz Digital Supply Current4 11 15 mA f CLK = 240 MHz Analog Supply Current 32 35 mA R SET = 560 Ω Analog Supply Current 5 mA R SET = 4933 Ω Standby Supply Current 2.4 5.0 mA PSAVE = Low, Digital and Control Inputs at VDD Power Supply Rejection Ratio 0.1 0.5 %/% NOTES 1These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range. 2Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz. 3Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100) , where Ideal = V REF /RSET × K × (3FFH) and K = 7.9896. 4Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. Specifications subject to change without notice. (VAA = +3.0 V–3.6 V, V REF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications T MIN to TMAX unless otherwise noted, T J MAX = 1108C)

–5–REV. 0 ADV7127

3.3 V TSSOP SPECIFICATIONS1

Parameter Min Typ Max Units Test Conditions STATIC PERFORMANCE Resolution (Each DAC) 10 Bits R SET = 680 Ω Integral Nonlinearity (BSL) –1 0.5 +1 LSB R SET = 680 Ω Differential Nonlinearity –1 0.25 +1 LSB R SET = 680 Ω DIGITAL AND CONTROL INPUTS Input High Voltage, V IH 2.0 V Input Low Voltage, V IL 0.8 V PDOWN Input High Voltage 3 2.1 V PDOWN Input Low Voltage3 0.6 V Input Current, IIN –1 +1 µAV IN = 0.0 V or VDD PSAVE Pull-Up Current 20 µA Input Capacitance, C IN 10 pF ANALOG OUTPUTS Output Current 2.0 18.5 mA Output Compliance Range, V OC 0 +1.4 V Output Impedance, ROUT 70 k Ω Output Capacitance, C OUT 10 pF Offset Error 0 0 % FSR Tested with DAC Output = 0 V Gain Error4 0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE (Ext.) Reference Range, VREF 1.12 1.235 1.35 V VOLTAGE REFERENCE (Int.) 5 Reference Range, VREF 1.235 V POWER DISSIPATION Digital Supply Current6 12 m A f CLK = 50 MHz Digital Supply Current6 2.5 4.5 mA f CLK = 140 MHz Digital Supply Current6 46 m A f CLK = 240 MHz Analog Supply Current 22 25 mA R SET = 560 Ω Analog Supply Current 5 mA R SET = 4933 Ω Standby Supply Current 2.6 3 mA PSAVE = Low, Digital and Control Inputs at VDD PDOWN Supply Current 20 µA Power Supply Rejection Ratio 0.1 0.5 %/% NOTES 1These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range. 2Temperature range T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz. 3This power-down feature is only available on the ADV7127 in the TSSOP package. 4Gain error = ((Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V REF /RSET × K × (3FFH) and K = 7.9896. 5Internal voltage reference is available only on the ADV7127 TSSOP package. 6Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V DD. Specifications subject to change without notice. (VAA = +3.0 V–3.6 V, V REF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications T MIN to TMAX unless otherwise noted, T J MAX = 1108C)

–6– REV. 0 ADV7127–SPECIFICATIONS 5 V/3.3 V DYNAMIC SPECIFICATIONS Parameter Min Typ Max Units DAC PERFORMANCE Glitch Impulse2, 3 10 pVs Data Feedthrough2, 3 22 dB Clock Feedthrough2, 3 33 dB NOTES 1These max/min specifications are guaranteed by characterization. 2TTL input values are for 0 V and 3 V with input rise/fall times ≤3 ns, measured at the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 3Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includ es clock and data feedthrough. Specifications subject to change without notice. (VAA = (3 V–5.25 V) 1, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications are for TA = +258C unless otherwise noted, T J MAX = 1108C)

5 V TIMING SPECIFICATIONS1

Parameter Min Typ Max Units Condition ANALOG OUTPUTS Analog Output Delay, t6 5.5 ns Analog Output Rise/Fall Time, t 74 1.0 ns Analog Output Transition Time, t 85 15 ns Analog Output Skew, t96 12 n s CLOCK CONTROL fCLK7 0.5 50 MHz 50 MHz Grade fCLK7 0.5 140 MHz 140 MHz Grade fCLK7 0.5 240 MHz 240 MHz Grade Data and Control Setup, t 1 1.5 ns Data and Control Hold, t 2 2.5 ns Clock Pulsewidth High, t 4 1.875 1.1 ns f MAX = 240 MHz Clock Pulsewidth Low t5 1.875 1.25 ns f MAX = 240 MHz Clock Pulsewidth High t 4 2.85 ns f MAX = 140 MHz Clock Pulsewidth Low t5 2.85 ns f MAX = 140 MHz Clock Pulsewidth High t 4 8.0 ns f MAX = 50 MHz Clock Pulsewidth Low t5 8.0 ns f MAX = 50 MHz Pipeline Delay, tPD6 1.0 1.0 1.0 Clock Cycles PSAVE Up Time, t106 21 0 n s PDOWN Up Time, t118 320 ns NOTES 1Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (V IL) 0 for both 5 V and 3.3 V supplies. 2These maximum and minimum specifications are guaranteed over this range. 3Temperature range: T MIN to TMAX: –40°C to +85°C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz. 4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a ful l-scale transition. 5Measured from 50% point of full-scale transition to 2% of final value. 6Guaranteed by characterization. 7fCLK max specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization. 8This power-down feature is only available on the ADV7127 in the TSSOP package. Specifications subject to change without notice. (VAA = +5 V 6 5%2, VREF = 1.235 V, RSET = 560 V, CL = 10 pF. All specifications T MIN to TMAX unless otherwise noted, T J MAX = 1108C)

3.3 V TIMING SPECIFICATIONS1

1Timing specifications are measured with input levels of 3.0 V (V IH) and 0 V (V IL) 0 for both 5 V and 3.3 V supplies. 2These maximum and minimum specifications are guaranteed over this range. 3Temperature range: T MIN to TMAX: –40°C to +85 °C at 50 MHz and 140 MHz, 0 °C to +70°C at 240 MHz. 4Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a ful l-scale transition. 5Measured from 50% point of full-scale transition to 2% of final value. 6Guaranteed by characterization. 7fCLK max specification production tested at 125 MHz and 5 V limits specified here are guaranteed by characterization. 8This power-down feature is only available on the ADV7127 in the TSSOP package. Specifications subject to change without notice.

1. OUTPUT DELAY ( t6) MEASURED FROM THE 50% POINT OF THE RISING

EDGE OF CLOCK TO THE 50% POINT OF FULL SCALE TRANSITION.

1. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND

90% POINTS OF FULL SCALE TRANSITION.

1. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL

SCALE TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. Figure 1. Timing Diagram

–8– REV. 0 ORDERING GUIDE1 Speed Options Package 50 MHz 140 MHz 240 MHz R-282 ADV7127KR50 ADV7127KR140 ADV7127JR240 RU-243 ADV7127KRU50 ADV7127KRU140 ADV7127JRU240 NOTES 150 MHz and 140 MHz devices are specified for –40°C to +85°C operation; 240 MHz devices are specified for 0 °C to +70°C. ABSOLUTE MAXIMUM RATINGS 1 NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration. PIN CONFIGURATIONS 24-Lead TSSOP 28-Lead SOIC TOP VIEW (Not to Scale) ADV7127 NC = NO CONNECT NC PDOWN VAA NC CLOCK GND GND VAA PSAVE R SET VREF IOUT COMP IOUT TOP VIEW (Not to Scale) ADV7127 VAA VAA VAA VAA VAA VAA CLOCK GND GND VAA IOUT VAA PSAVE VAA R SET VAA COMP VREF CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7127 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE

–9–REV. 0 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Function CLOCK Clock Input (TTL Compatible). The rising edge of CLOCK latches the R0–R9, G0–G9, B0–B9, SYNC and BLANK pixel and control inputs. It is typically the pixel clock rate of the video system. CLOCK should be driven by a dedicated TTL buffer. D0–D9 Data Inputs (TTL Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit. Unused data inputs should be connected to either the regular PCB power or ground plane. IOUT Current Output. This high impedance current source is capable of directly driving a doubly terminated 75 Ω coaxial cable. RSET Full-Scale Adjust Control. A resistor (R SET) connected between this pin and GND controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between R SET and the full-scale output current on I OUT is given by: IOUT (mA) = 7968 × VREF(V)/RSET(Ω ) COMP Compensation Pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor must be connected between COMP and V AA. VREF Voltage Reference Input. An external 1.23 V voltage reference must be connected to this pin. The use of an exter- nal resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA. VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7127 must be connected. GND Ground. All GND pins must be connected. I OUT Differential Current Output. Capable of directly driving a doubly terminated 75 Ω load. If not required, this out- put should be tied to ground. PSAVE Power Save Control Pin. The part is put into standby mode when PSAVE is low. The internal voltage reference circuit is still active on the TSSOP in this case. PDOWN Power-Down Control Pin (24-Lead TSSOP Only). The ADV7127 completely powers down, including the voltage reference circuit, when PDOWN is low. TERMINOLOGY Color Video (RGB) This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Gray Scale The discrete levels of video signal between reference black and reference white levels. A 10-bit DAC contains 1024 different levels, while an 8-bit DAC contains 256. Raster Scan The most basic method of sweeping a CRT one line at a time to generate and display images. Reference Black Level The maximum negative polarity amplitude of the video signal. Reference White Level The maximum positive polarity amplitude of the video signal. Video Signal That portion of the composite video signal which varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion that may be visually observed.

5 V–Typical Performance Characteristics

Figure 2. SFDR vs. f OUT @ fCLOCK =

140 MHz (Single-Ended and

Figure 5. THD vs. f CLOCK @ fOUT =

2 MHz (2nd, 3rd and 4th Harmonics)

Figure 8. SFDR (Single-Tone) @ Figure 3. SFDR vs. f OUT @ fCLOCK =

50 MHz (Single-Ended and

Figure 6. Linearity vs. I OUT Figure 9. Single-Tone SFDR @ f CLOCK Figure 4. SFDR vs. Temperature @ Figure 7. Typical Linearity Figure 10. Dual-Tone SFDR @ f CLOCK

14.5 MHz)

3 V–Typical Performance Characteristics

Figure 11. SFDR vs. f OUT @ fCLOCK = Figure 14. THD vs. f CLOCK @ fOUT = Figure 17. Single-Tone SFDR @ Figure 12. SFDR vs. f OUT @ fCLOCK = Figure 15. Linearity vs. I OUT Figure 18. Single-Tone SFDR @ Figure 13. SFDR vs. Temperature @ Figure 16. Typical Linearity Figure 19. Dual-Tone SFDR @ f CLOCK

is also integrated on board the part. output waveform. See Figure 20. All these digital inputs are specified to accept TTL logic levels. Horiz Res = Number of Pixels/Line. Vert Res = Number of Lines/Frame.

60 Hz for a noninterlaced system or 30 Hz

The required CLOCK frequency is thus 78.6 MHz. input to the ADV7127 be driven by a TTL buffer (e.g., 74F244).

100 IRE

Figure 21. I OUT Video Output Waveform can be reduced to 60µW at 3 V. pin is normally terminated to V AA through a 0.1 µF capacitor. external 1.23 V reference (AD1580).

should be located within three inches of the ADV7127. a reduction in plane-to-plane noise coupling. use of multiple decoupling capacitors (see Figure 25). leads as short as possible, thus minimizing lead inductance. using a three terminal voltage regulator. Figure 25. Typical Connection Diagram and Component List

–15–REV. 0 Digital Signal Interconnect The digital signal lines to the ADV7127 should be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7127 should be avoided so as to minimize noise pickup. Any active pull-up termination resistors for the digital inputs should be connected to the regular PCB power plane (V CC), and not the analog power plane. Analog Signal Interconnect The ADV7127 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. For optimum performance, the analog outputs should each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should be as close as possible to the ADV7127 so as to mini- mize reflections. Additional information on PCB design is available in an applica- tion note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” This application note is available from Analog Devices, publication number E1309-15-10/89.

–16– C3259–8–4/98PRINTED IN U.S.A. ADV7127 REV. 0 28-Lead SOIC (R-28) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 0.0291 (0.74) 0.0098 (0.25)x 45° 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 28 15 141 24-Lead TSSOP (RU-24) 24 13 121 0.311 (7.90) 0.303 (7.70) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) PIN 1 SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) OUTLINE DIMENSIONS Dimensions shown in inches and (mm).