ADV7127 (Rev. A)
Document overview
- Manufacturer or author: Analog Devices, Inc.
- PDF pages: 18
Technical content
CMOS, 240 MHz, 10-Bit, High Speed Video DAC Data Sheet ADV7127 Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 ©1998–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
240 MSPS throughput rate
10-bit digital-to-analog converter (DAC) RS-343A-/RS-170-compatible output Complementary outputs DAC output current range: 2 mA to 18.5 mA TTL-compatible inputs Internal voltage reference Single supply 5 V or 3.3 V operation 24-lead thin shrink small outline package (TSSOP) package Low power dissipation Low power standby mode Power-down mode Industrial temperature range (−40°C to +85°C)
APPLICATIONS
Digital video systems (1600 × 1200 at 100 Hz) High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction Direct digital synthesis (DDS) Wireless local area networks (LANs) FUNCTIONAL BLOCK DIAGRAM D9 TO D0 GND RSET IOUT IOUT COMP ADV7127 VREF VOLTAGE REFERENCE CIRCUIT PDOWN POWER-DOWN MODE VAA DAC10DATA REGISTER CLOCK PSAVE 14959-001 Figure 1. GENERAL DESCRIPTION The ADV7127 is a high speed, DAC on a single monolithic chip. It consists of a 10-bit, video DAC with an on-board voltage reference, complementary outputs, a standard TTL input interface, and high impedance analog output current sources. The ADV7127 has a 10-bit wide input port. A single 5 V or
3.3 V power supply and clock are all that are required to make
the device functional. The ADV7127 is fabricated in a complementary metal-oxide semiconductor (CMOS) process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The ADV7127 is available in a 24-lead TSSOP package which includes a power-down mode and an on-board voltage reference circuit. PRODUCT HIGHLIGHTS 1. 240 MSPS throughput. 2. Guaranteed monotonic to 10 bits. 3. Compatible with a wide variety of high resolution color graphics systems including RS-343A and RS-170.
Rev. A | Page 2 of 18 TABLE OF CONTENTS
REVISION HISTORY
1/2017—Rev. 0 to Rev. A Changed Circuit Description and Operation Section to Theory Changes to Supply Decoupling Section and Analog Signal 4/1998—Revision 0: Initial Version
Rev. A | Page 3 of 18 SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VAA = 5 V ± 5%, VREF = 1.235 V , RSET = 560 Ω, CL = 10 pF . All specifications TMIN to TMAX,1 unless otherwise noted. TJ MAX = 110°C. Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Integral Nonlinearity (INL) –1 +0.4 +1 LSB Differential Nonlinearity –1 +0.25 +1 LSB Guaranteed monotonic DIGITAL AND CONTROL INPUTS Input Voltage High VIH 2 V Low VIL 0.8 V PDOWN Input Voltage High 3 V Low 1 V Input Current IIN –1 +1 µA VIN = 0.0 V or VAA Pull-Up Current PSAVE 20 µA PDOWN 20 µA Input Capacitance CIN 10 pF ANALOG OUTPUTS Output Current 2.0 18.5 mA Output Compliance Range VOC 0 1.4 V Output Impedance ROUT 100 kΩ Output Capacitance COUT 10 pF IOUT = 0 mA Offset Error –0.025 +0.025 % FSR Tested with DAC output = 0 V Gain Error2 –5.0 +5.0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE (EXTERNAL AND INTERNAL)3 Reference Range VREF 1.12 1.235 1.35 V POWER DISSIPATION Supply Current Digital 1.5 3 mA fCLK = 50 MHz 4 6 mA fCLK = 140 MHz 6.5 10 mA fCLK = 240 MHz Analog 23 27 mA RSET = 560 Ω 5 mA RSET = 4933 Ω Standby4 3.8 6 mA PSAVE = low, digital and control inputs at VAA PDOWN 1 mA Power Supply Rejection Ratio PSRR 0.1 0.5 %/% 1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz. 2 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896. 3 The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD. 4 These typical/maximum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
Rev. A | Page 4 of 18
3.3 V ELECTRICAL CHARACTERISTICS
Table 2. Parameter2 Symbol Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE R SET = 680 Ω Resolution (Each DAC) 10 Bits Integral Nonlinearity (INL) –1 +0.5 +1 LSB Differential Nonlinearity –1 +0.25 +1 LSB DIGITAL AND CONTROL INPUTS Input Voltage High V IH 2.0 V Low V IL 0.8 V PDOWN Input Voltage High 2.1 V Low 0.6 V Input Current IIN –1 +1 μA V IN = 0.0 V or VDD PSAVE Pull-Up Current 20 μA Input Capacitance CIN 10 pF ANALOG OUTPUTS Output Current 2.0 18.5 mA Output Compliance Range V OC 0 1.4 V Output Impedance ROUT 70 kΩ Output Capacitance COUT 10 pF Offset Error 0 0 % FSR Tested with DAC output = 0 V Gain Error3 0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE (EXTERNAL) Reference Range VREF 1.12 1.235 1.35 V VOLTAGE REFERENCE (INTERNAL) Reference Range VREF 1.235 V POWER DISSIPATION Supply Current Digital4 1 2 mA f CLK = 50 MHz 2.5 4.5 mA f CLK = 140 MHz 4 6 mA f CLK = 240 MHz Analog 22 25 mA R SET = 560 Ω 5 mA RSET = 4933 Ω Standby 2.6 3 mA PSAVE = low, digital and control inputs at VDD PDOWN 20 μA Power Supply Rejection Ratio PSRR 0.1 0.5 %/% 1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz and 0°C to 70°C at 240 MHz. 2 These maximum/minimum specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range. 3 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0x3FF) and K = 7.9896. 4 The digital supply is measured with a continuous clock, with data input corresponding to a ramp pattern, and with an input level at 0 V and VDD.
Rev. A | Page 5 of 18
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V , RSET = 560 Ω, CL = 10 pF . All specifications TMIN to TMAX,2 unless otherwise noted. TJ MAX = 110°C. Table 3. Parameter3 Symbol Min Typ Max Unit Test Conditions/Comments ANALOG OUTPUTS Delay t6 5.5 ns Rise/Fall Time4 t7 1.0 ns Transition Time5 t8 15 ns Skew6 t9 1 2 ns Not shown in Figure 2 CLOCK CONTROL7 fCLK 0.5 50 MHz 50 MHz grade 0.5 140 MHz 140 MHz grade 0.5 240 MHz 240 MHz grade Data and Control Setup t1 1.5 ns Hold t2 2.5 ns Clock Pulse Width High t4 1.875 1.1 ns fMAX = 240 MHz 2.85 ns fMAX = 140 MHz 8.0 ns fMAX = 50 MHz Low t5 1.875 1.25 ns fMAX = 240 MHz 2.85 ns fMAX = 140 MHz 8.0 ns fMAX = 50 MHz Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles Not shown in Figure 2 Up Time PSAVE6 t10 2 10 ns Not shown in Figure 2 PDOWN t11 320 ns Not shown in Figure 2 1 Maximum and minimum specifications are guaranteed over this range in Table 3. 2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified in Table 3 are guaranteed by characterization.
3.3 V TIMING SPECIFICATIONS
140 MHz 140 MHz grade
240 MHz 240 MHz grade
1 The values stated in Table 4 were obtained using VAA in the range of 3.0 V to 3.6 V. 2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, and 0°C to 70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, and fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 3.3 V. Limits specified in Table 4 are guaranteed by characterization.
- OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING
EDGE OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
- OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND
90% POINTS OF FULL-SCALE TRANSITION.
- TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE. Figure 2. Timing Diagram
Rev. A | Page 7 of 18 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating VAA to GND 7 V Voltage on Any Digital Pin GND − 0.5 V to VAA + 0.5 V Ambient Operating Temperature Range (TA) −40°C to +85°C Storage Temperature Range(TS) −65°C to +150°C Junction Temperature (TJ) 150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase Soldering (1 Minute) 220°C IOUT to GND1 0 V to VAA
1 Analog output short circuit to any power supply or common can be of an
indefinite duration. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Figure 3. Pin Configuration Table 6. Pin Function Descriptions D0 to D9 Data Inputs (TTL-Compatible). Data is latched on the rising edge of CLOCK. D0 is the least significant data bit. inputs are red, green, or blue pixel inputs. 10, 17 V AA Analog Power Supply (5 V ± 5%). All V AA pins on the ADV7127 must be connected. 12, 13 DNC Do Not Connect. Do not connect to these pins. 15, 16 GND Ground. All GND pins must be connected. this output is tied to ground. relationship between RSET and the full-scale output current on IOUT is given by IOUT (mA) = 7968 × VREF (V)/R SET (Ω).
Rev. A | Page 13 of 18 TERMINOLOGY Color Video (RGB) Color video (RGB) usually refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Gray Scale Gray scale is the discrete levels of video signal between the reference black and reference white levels. A 10-bit DAC contains 1024 different levels, whereas an 8-bit DAC contains 256. Raster Scan Raster scan is the most basic method of sweeping a CRT one line at a time to generate and display images. Reference Black Level Reference black level is the maximum negative polarity amplitude of the video signal. Reference White Level Reference white level is the maximum positive polarity amplitude of the video signal. Video Signal Video signal is the portion of the composite video signal that varies in gray scale levels between reference white and reference black. It is also referred to as the picture signal, which is the portion that can be visually observed.
also integrated on board the device. output waveform (see Figure 22). Figure 22. Video Data Input/Output All of these digital inputs are specified to accept TTL logic levels. Horizontal Resolution is the number of pixels per line. Ver tical Resolution is the number of lines per frame. 30 Hz for an interlaced system. total duration of each frame (for example, 0.8). The required CLOCK frequency is 78.6 MHz. ADV7127 be driven by a TTL buffer (for example, 74F244).
100 IRE
Figure 23. IOUT RS-343A Video Output Waveform Table 7. Video Output Truth Table (RSET = 560 Ω, RLOAD = is normally terminated to VAA through a 0.1 µF capacitor. external 1.23 V reference (AD1580). yields the analog output levels quoted in Specifications section. waveform values shown in Figure 23. and power supply variations.
Rev. A | Page 16 of 18 PCB LAYOUT CONSIDERATIONS The ADV7127 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. To complement the excellent noise performance of the ADV7127, it is imperative that great care be given to the PCB layout. Figure 27 shows a recommended connection diagram for the ADV7127. The PCB layout is optimized for lowest noise on the ADV7127 power and ground lines. Radiated and conducted noise can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins is minimized to inductive ringing. GROUND PLANES The ADV7127 and associated analog circuitry have a separate ground plane referred to as the analog ground plane. This ground plane connects to the regular PCB ground plane at a single point through a ferrite bead, as illustrated in Figure 27. The ferrite bead is located as close as possible (within 3 inches) to the ADV7127. The analog ground plane encompasses all ADV7127 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces, and any output amplifiers. The regular PCB ground plane area encompasses all the digital signal traces, excluding the ground pins, leading up to the ADV7127. POWER PLANES The PCB layout has two distinct power planes: one for analog circuitry and one for digital circuitry. The analog power plane encompasses the ADV7127 (VAA) and all associated analog circuitry. This power plane is connected to the regular PCB power plane (VCC) at a single point through a ferrite bead, as illustrated in Figure 27. This bead is located within 3 inches of the ADV7127. The PCB power plane provides power to all digital logic on the PCB, and the analog power plane provides power to all ADV7127 power pins, voltage reference circuitry, and any output amplifiers. The PCB power and ground planes do not overlay portions of the analog power plane. Keeping the PCB power and ground planes from overlaying the analog power plane contributes to a reduction in plane to plane noise coupling. SUPPLY DECOUPLING Noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see Figure 27). Optimum performance is achieved by the use of 0.1 µF ceramic capacitors. Each of the two groups of VAA is individually decoupled to ground. The VAA pins (Pin 10 and Pin 17) must be decoupled with capacitors to GND. Decouple the pins by placing the capacitors as close as possible to the device with the capacitor leads as short as possible between the VAA and GND pins, thus minimizing lead inductance. It is important to note that while the ADV7127 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer must pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) provides an electromagnetic interface (EMI) suppression between the switching power supply and the main PCB. Alternatively, consider using a 3-terminal voltage regulator. DIGITAL SIGNAL INTERCONNECT The digital signal lines to the ADV7127 must be isolated as much as possible from the analog outputs and other analog circuitry. Digital signal lines must not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7127 must be avoided to minimize noise pickup. Any active pull-up termination resistors for the digital inputs are connected to the regular PCB power plane (V CC) and not the analog power plane. ANALOG SIGNAL INTERCONNECT The ADV7127 is located as close as possible to the output connectors, which minimizes noise pickup and reflections due to impedance mismatch. The video output signals overlay the ground plane and not the analog power plane, thereby maximizing the high frequency power supply rejection. For optimum performance, the analog outputs each have a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance must be as close as possible to the ADV7127 to minimize reflections. Additional information on PCB design is available in the Graphics System for Reduced EMI.
Figure 27. Typical Connection Diagram and Component List
6.40 BSC
0.10 COPLANARITY
Figure 28. 24-Lead Thin Shrink Small Outline Package [TSSOP] registered trademarks are the property of their respective owners.