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CMOS, 330 MHz Triple 8-Bit High Speed Video DAC Data Sheet ADV7125 Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 © 2002–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
330 MSPS throughput rate
RS-343A-/RS-170-compatible output Complementary outputs DAC output current range: 2.0 mA to 26.5 mA TTL-compatible inputs Internal reference (1.235 V) Single-supply +5 V/+3.3 V operation 48-lead LQFP and LFCSP Low power dissipation (30 mW minimum at 3 V) Low power standby mode (6 mW typical at 3 V) Industrial temperature range (−40°C to +85°C) RoHS compliant packages Qualified for automotive applications
APPLICATIONS
High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction Automotive infotainment units FUNCTIONAL BLOCK DIAGRAM D ATA REGISTER DAC DAC BLANK SYNC R7 TO R0 G7 TO G0 B7 TO B0 PSAVE CLOCK DAC ADV7125 D ATA REGISTER D ATA REGISTER BLANK AND SYNC LOGIC POWER-DOWN MODE VO LTAGE REFERENCE CIRCUIT IOR IOR IOG IOG IOB V REF R SET VAA COM PGND IOB 03097-001 Figure 1. GENERAL DESCRIPTION The ADV7125 (ADV®) is a triple high speed, digital-to-analog converter (DAC) on a single monolithic chip. It consists of three high speed, 8-bit video DACs with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source. The ADV7125 has three separate 8-bit-wide input ports. A single +5 V/+3.3 V power supply and clock are all that are required to make the device functional. The ADV7125 has additional video control signals, composite SYNC and BLANK, as well as a power save mode. The ADV7125 is fabricated in a 5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7125 is available in 48- lead LQFP and 48-lead LFCSP packages. PRODUCT HIGHLIGHTS 1. 330 MSPS (3.3 V only) throughput. 2. Guaranteed monotonic to eight bits. 3. Compatible with a wide variety of high resolution color graphics systems, including RS-343A and RS-170.
Rev. D | Page 2 of 17 TABLE OF CONTENTS
REVISION HISTORY
4/16— Rev. C to Rev. D 2/11— Rev. B to Rev. C 7/10— Rev. A to Rev. B 3/09— Rev. 0 to Rev. A Changes to Features Section, Applications Section, and Deleted Ground Planes Section, Power Planes Section, and Changes to Table 7, Analog Outputs Section, Figure 6, and Changes to Video Output Buffers Section, PCB Layout Changes to Analog Signal Interconnect Section and Figure 10 .... 14 10/02— Revision 0: Initial Version
Rev. D | Page 3 of 17 SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VAA = 5 V ± 5%, VREF = 1.235 V , RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments1 STATIC PERFORMANCE Resolution (Each DAC) 8 Bits Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic DIGITAL AND CONTROL INPUTS Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current, IIN −1 +1 μA V IN = 0.0 V or VDD PSAVE Pull-Up Current 20 μA Input Capacitance, CIN 10 pF ANALOG OUTPUTS Output Current 2.0 26.5 mA Green DAC, SYNC = high 2.0 18.5 mA RGB DAC, SYNC = low DAC-to-DAC Matching 1.0 5 % Output Compliance Range, VOC 0 1.4 V Output Impedance, ROUT 100 kΩ Output Capacitance, COUT 10 pF I OUT = 0 mA Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V Gain Error2 −5.0 +5.0 % FSR FSR = 18.62 mA VOLTAGE REFERENCE, EXTERNAL AND INTERNAL Reference Range, VREF 1.12 1.235 1.35 V POWER DISSIPATION Digital Supply Current3 3.4 9 mA f CLK = 50 MHz 10.5 15 mA f CLK = 140 MHz 18 25 mA f CLK = 240 MHz Analog Supply Current 67 72 mA R SET = 530 Ω 8 mA R SET = 4933 Ω Standby Supply Current4 2.1 5.0 mA PSAVE = low, digital, and control inputs at VDD Power Supply Rejection Ratio 0.1 0.5 %/% 1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz. 2 Gain error = ((Measured (FSC)/Ideal (FSC) − 1) × 100), where Ideal = VREF/RSET × K × (0xFFH) × 4 and K = 7.9896. 3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD. 4 These maximum/minimum specifications are guaranteed by characterization in the 4.75 V to 5.25 V range.
Rev. D | Page 4 of 17
3.3 V ELECTRICAL CHARACTERISTICS
Table 2. Parameter2 Min Typ Max Unit Test Conditions/Comments1 STATIC PERFORMANCE Resolution (Each DAC) 8 Bits R SET = 680 Ω Integral Nonlinearity (BSL) −1 ±0.5 +1 LSB R SET = 680 Ω Differential Nonlinearity −1 ±0.25 +1 LSB R SET = 680 Ω DIGITAL AND CONTROL INPUTS Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Input Current, IIN −1 +1 μA V IN = 0.0 V or VDD PSAVE Pull-Up Current 20 μA Input Capacitance, CIN 10 pF ANALOG OUTPUTS Output Current 2.0 26.5 mA Green DAC, SYNC = high 2.0 18.5 mA RGB DAC, SYNC = low DAC-to-DAC Matching 1.0 % Output Compliance Range, VOC 0 1.4 V Output Impedance, ROUT 70 kΩ Output Capacitance, COUT 10 pF Offset Error 0 0 % FSR Tested with DAC output = 0 V Gain Error3 0 % FSR FSR = 18.62 mA VOLTAGE REFERENCE, EXTERNAL Reference Range, VREF 1.12 1.235 1.35 V VOLTAGE REFERENCE, INTERNAL Voltage Reference, VREF 1.235 V POWER DISSIPATION Digital Supply Current4 2.2 5.0 mA fCLK = 50 MHz 6.5 12.0 mA f CLK = 140 MHz 11 15 mA f CLK = 240 MHz 16 mA f CLK = 330 MHz Analog Supply Current 67 72 mA R SET = 560 Ω 8 mA R SET = 4933 Ω Standby Supply Current 2.1 5.0 mA PSAVE = low, digital, and control inputs at VDD Power Supply Rejection Ratio 0.1 0.5 %/% 1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz. 2 These max/min specifications are guaranteed by characterization in the 3.0 V to 3.6 V range. 3 Gain error = ((Measured (FSC)/Ideal (FSC) −1) × 100), where Ideal = VREF/RSET × K × (0xFFH) × 4 and K = 7.9896. 4 Digital supply is measured with continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
Rev. D | Page 5 of 17
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V , RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C. Table 3. Parameter3 Symbol Min Typ Max Unit Test Conditions/Comments ANALOG OUTPUTS Analog Output Delay t 6 5.5 ns Analog Output Rise/Fall Time4 t 7 1.0 ns Analog Output Transition Time5 t 8 15 ns Analog Output Skew6 t 9 1 2 ns CLOCK CONTROL CLOCK Frequency7 f CLK 0.5 50 MHz 50 MHz grade 0.5 140 MHz 140 MHz grade 0.5 240 MHz 240 MHz grade Data and Control Setup6 t 1 0.5 ns Data and Control Hold6 t 2 1.5 ns CLOCK Period t 3 4.17 ns CLOCK Pulse Width High6 t 4 1.875 ns f CLK_MAX = 240 MHz CLOCK Pulse Width Low6 t 5 1.875 ns f CLK_MAX = 240 MHz CLOCK Pulse Width High6 t 4 2.85 ns f CLK_MAX = 140 MHz CLOCK Pulse Width Low6 t 5 2.85 ns f CLK_MAX = 140 MHz CLOCK Pulse Width High t4 8.0 ns fCLK_MAX = 50 MHz CLOCK Pulse Width Low t 5 8.0 ns f CLK_MAX = 50 MHz Pipeline Delay6 t PD 1.0 1.0 1.0 Clock cycles PSAVE Up Time6 t10 2 10 ns 1 The maximum and minimum specifications are guaranteed over this range. 2 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization.
3.3 V TIMING SPECIFICATIONS
140 MHz 140 MHz grade
240 MHz 240 MHz grade
330 MHz 330 MHz grade
1 These maximum and minimum specifications are guaranteed over this range. 2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to +70°C at 240 MHz and 330 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) for 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz and 5 V. Limits specified here are guaranteed by characterization. t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
- TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE
Figure 2. Timing Diagram
Rev. D | Page 7 of 17 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating VAA to GND 7 V Voltage on Any Digital Pin GND − 0.5 V to VAA + 0.5 V Ambient Operating Temperature Range (TA) −40°C to +85°C Storage Temperature Range (TS) −65°C to +150°C Junction Temperature (TJ) 150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase Soldering (1 Minute) 220°C IOUT to GND1 0 V to VAA
1 Analog output short circuit to any power supply or common GND can be of
an indefinite duration. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION
Rev. D | Page 9 of 17 Pin No. Mnemonic Description 37 R SET A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 11,445 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by: IOG (mA) = 11,444.8 × VREF (V)/RSET (Ω) (SYNC being asserted) IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied permanently low. 38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is active. 0 EPAD Exposed Paddle. The exposed paddle must be connected to GND.
Figure 5. LQFP Pin Configuration Table 7. LQFP Pin Function Descriptions GND Ground. All GND pins must be connected. regular printed circuit board (PCB) power or ground plane. BLANK is a Logic 0, the R0 to R7, G0 to G7, and B0 to B7 pixel inputs are ignored. edge of CLOCK. If sync information is not required on the green channel, the SYNC input should be tied to Logic 0. 13, 29, 30 V AA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7125 must be connected. the complementary outputs are not required, these outputs should be tied to ground. not they are all being used. must be connected between COMP and VAA. 36 V REF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). 37 RSET A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. 38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7125 when this pin is active.
Rev. D | Page 11 of 17 TERMINOLOGY Blanking Level The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level that shuts off the picture tube, resulting in the blackest possible picture. Color Video (RGB) This refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Sync Signal (SYNC The position of the composite video signal that synchronizes the scanning process. Gray Scale The discrete levels of video signal between reference black and reference white levels. An 8-bit DAC contains 256 different levels. Raster Scan The most basic method of sweeping a CRT one line at a time to generate and display images. Reference Black Level The maximum negative polarity amplitude of the video signal. Reference White Level The maximum positive polarity amplitude of the video signal. Sync Level The peak level of the SYNC signal. Video Signal The portion of the composite video signal that varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion that can be visually observed.
frequency power supply rejection. Graphics System for Reduced EMI.
41 TO 48
12 SYNC
11 BLANK
24 CLOCK
38 PSAVE
3 TO 10
16 TO 23
Figure 12. Typical Connection Diagram
Figure 13. 48-Lead Low Profile Quad Flat Package [LQFP]
0.80 MAX
0.65 TYP
5.50 REF
0.20 REF
0.05 MAX
0.02 NOM
0.60 MAX
0.25 MIN
Figure 14. 48-Lead Lead Frame Chip Scale Package [LFCSP]
COMPLIANT TO JEDEC STANDARDS MO-220- WKKD . Figure 15. 48-Lead Lead Frame Chip Scale Package [LFCSP] 2 W = Qualified for Automotive Applications. ADV7125JSTZ330 is available in a 3.3 V option only. obtain the specific Automotive Reliability reports for these models. registered trademarks are the property of their respective owners.