ADV7123KST140-RL

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CMOS, 330 MHz Triple 10-Bit High Speed Video DAC ADV7123 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

330 MSPS throughput rate

Triple 10-bit digital-to-analog converters (DACs) SFDR −70 dB at f CLK = 50 MHz; fOUT = 1 MHz −53 dB at fCLK = 140 MHz; fOUT = 40 MHz RS-343A-/RS-170-compatible output Complementary outputs DAC output current range: 2.0 mA to 26.5 mA TTL-compatible inputs Internal reference (1.235 V) Single-supply 5 V/3.3 V operation 48-lead LQFP package Low power dissipation (30 mW minimum @ 3 V) Low power standby mode (6 mW typical @ 3 V) Industrial temperature range (−40°C to +85°C) Pb-free (lead-free) package

APPLICATIONS

Digital video systems (1600 × 1200 @ 100 Hz) High resolution color graphics Digital radio modulation Image processing Instrumentation Video signal reconstruction FUNCTIONAL BLOCK DIAGRAM DATA REGISTER DAC DAC BLANK SYNC R9 TO R0 G9 TO G0 B9 TO B0 PSAVE CLOCK DAC ADV7123 DATA REGISTER DATA REGISTER BLANK AND SYNC LOGIC POWER-DOWN MODE VOLTAGE REFERENCE CIRCUIT IOR IOR IOG IOG IOB VREF RSET VAA COMPGND IOB 00215-001 Figure 1. GENERAL DESCRIPTION The ADV7123 (ADV®) is a triple high speed, digital-to-analog converter on a single monolithic chip. It consists of three high speed, 10-bit, video DACs with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source. The ADV7123 has three separate 10-bit-wide input ports. A single 5 V/3.3 V power supply and clock are all that are required to make the part functional. The ADV7123 has additional video control signals, composite SYNC and BLANK. The ADV7123 also has a power save mode. The ADV7123 is fabricated in a 5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7123 is available in a 48-lead LQFP package. PRODUCT HIGHLIGHTS 1. 330 MSPS throughput. 2. Guaranteed monotonic to 10 bits. 3. Compatible with a wide variety of high resolution color graphics systems, including RS-343A and RS-170. ADV is a registered trademark of Analog Devices, Inc.

Rev. D | Page 3 of 24 SPECIFICATIONS

5 V SPECIFICATIONS

VAA = 5 V ± 5%, VREF = 1.235 V , RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C. Table 1. Parameter Min Typ Max Unit Test Conditions1 STATIC PERFORMANCE Resolution (Each DAC) 10 Bits Integral Nonlinearity (BSL) −1 ±0.4 +1 LSB Differential Nonlinearity −1 ±0.25 +1 LSB Guaranteed Monotonic DIGITAL AND CONTROL INPUTS Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD PSAVE Pull-Up Current 20 μA Input Capacitance, CIN 10 pF ANALOG OUTPUTS Output Current 2.0 26.5 mA Green DAC, SYNC = high 2.0 18.5 mA RGB DAC, SYNC = low DAC-to-DAC Matching 1.0 5 % Output Compliance Range, VOC 0 1.4 V Output Impedance, ROUT 100 kΩ Output Capacitance, COUT 10 pF IOUT = 0 mA Offset Error −0.025 +0.025 % FSR Tested with DAC output = 0 V Gain Error2 −5.0 +5.0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE, EXTERNAL AND INTERNAL Reference Range, VREF 1.12 1.235 1.35 V POWER DISSIPATION Digital Supply Current3 3.4 9 mA fCLK = 50 MHz 10.5 15 mA fCLK = 140 MHz 18 25 mA fCLK = 240 MHz Analog Supply Current 67 72 mA RSET = 560 Ω 8 mA RSET = 4933 Ω Standby Supply Current4 2.1 5.0 mA PSAVE = low, digital, and control inputs at VDD Power Supply Rejection Ratio 0.1 0.5 %/% 1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz. 2 Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF /RSET × K × (0x3FFH) and K = 7.9896. 3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD. 4 These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.

Rev. D | Page 4 of 24

3.3 V SPECIFICATIONS

Table 2. Parameter2 Min Typ Max Unit Test Conditions1 STATIC PERFORMANCE Resolution (Each DAC) 10 Bits RSET = 680 Ω Integral Nonlinearity (BSL) −1 +0.5 +1 LSB RSET = 680 Ω Differential Nonlinearity −1 +0.25 +1 LSB RSET = 680 Ω DIGITAL AND CONTROL INPUTS Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Input Current, IIN −1 +1 μA VIN = 0.0 V or VDD PSAVE Pull-Up Current 20 μA Input Capacitance, CIN 10 pF ANALOG OUTPUTS Output Current 2.0 26.5 mA Green DAC, SYNC = high 2.0 18.5 mA RGB DAC, SYNC = low DAC-to-DAC Matching 1.0 % Output Compliance Range, VOC 0 1.4 V Output Impedance, ROUT 70 kΩ Output Capacitance, COUT 10 pF Offset Error 0 0 % FSR Tested with DAC output = 0 V Gain Error3 0 % FSR FSR = 17.62 mA VOLTAGE REFERENCE, EXTERNAL Reference Range, VREF 1.12 1.235 1.35 V VOLTAGE REFERENCE, INTERNAL Voltage Reference, VREF 1.235 V POWER DISSIPATION Digital Supply Current4 2.2 5.0 mA fCLK = 50 MHz 6.5 12.0 mA fCLK = 140 MHz 11 15 mA fCLK = 240 MHz 16 mA fCLK = 330 MHz Analog Supply Current 67 72 mA RSET = 560 Ω 8 mA RSET = 4933 Ω Standby Supply Current 2.1 5.0 mA PSAVE = low, digital, and control inputs at VDD Power Supply Rejection Ratio 0.1 0.5 %/% 1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz. 2 These maximum/minimum specifications are guaranteed by characterization to be over the 3.0 V to 3.6 V range. 3 Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF/RSET × K × (0x3FFH) and K = 7.9896. 4 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.

Rev. D | Page 5 of 24

5 V DYNAMIC SPECIFICATIONS

VAA = 5 V ± 5%,1 VREF = 1.235 V , RSET = 560 Ω, CL = 10 pF. All specifications are TA = 25°C, unless otherwise noted, TJ MAX = 110°C. Table 3. Parameter1 Min Typ Max Unit AC LINEARITY Spurious-Free Dynamic Range to Nyquist2 Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz 67 dBc fCLK = 50 MHz; fOUT = 2.51 MHz 67 dBc fCLK = 50 MHz; fOUT = 5.04 MHz 63 dBc fCLK = 50 MHz; fOUT = 20.2 MHz 55 dBc fCLK = 100 MHz; fOUT = 2.51 MHz 62 dBc fCLK = 100 MHz; fOUT = 5.04 MHz 60 dBc fCLK = 100 MHz; fOUT = 20.2 MHz 54 dBc fCLK = 100 MHz; fOUT = 40.4 MHz 48 dBc fCLK = 140 MHz; fOUT = 2.51 MHz 57 dBc fCLK = 140 MHz; fOUT = 5.04 MHz 58 dBc fCLK = 140 MHz; fOUT = 20.2 MHz 52 dBc fCLK = 140 MHz; fOUT = 40.4 MHz 41 dBc Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz 70 dBc fCLK = 50 MHz; fOUT = 2.51 MHz 70 dBc fCLK = 50 MHz; fOUT = 5.04 MHz 65 dBc fCLK = 50 MHz; fOUT = 20.2 MHz 54 dBc fCLK = 100 MHz; fOUT = 2.51 MHz 67 dBc fCLK = 100 MHz; fOUT = 5.04 MHz 63 dBc fCLK = 100 MHz; fOUT = 20.2 MHz 58 dBc fCLK = 100 MHz; fOUT = 40.4 MHz 52 dBc fCLK = 140 MHz; fOUT = 2.51 MHz 62 dBc fCLK = 140 MHz; fOUT = 5.04 MHz 61 dBc fCLK = 140 MHz; fOUT = 20.2 MHz 55 dBc fCLK = 140 MHz; fOUT = 40.4 MHz 53 dBc Spurious-Free Dynamic Range Within a Window Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 77 dBc fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span 73 dBc fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span 64 dBc Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 74 dBc fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span 73 dBc fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span 60 dBc Total Harmonic Distortion fCLK = 50 MHz; fOUT = 1.00 MHz TA = 25°C 66 dBc TMIN to TMAX 65 dBc fCLK = 50 MHz; fOUT = 2.00 MHz 64 dBc fCLK = 100 MHz; fOUT = 2.00 MHz 63 dBc fCLK = 140 MHz; fOUT = 2.00 MHz 55 dBc

Rev. D | Page 6 of 24 Parameter1 Min Typ Max Unit DAC PERFORMANCE Glitch Impulse 10 pV-sec DAC-to-DAC Crosstalk3 23 dB Data Feedthrough4, 5 22 dB Clock Feedthrough4, 5 33 dB 1 These maximum/minimum specifications are guaranteed by characterization over the 4.75 V to 5.25 V range. 2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF. 3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. 4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5 TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured from the 10% and 90% points. Timing reference points are 50% for inputs and outputs.

3.3 V DYNAMIC SPECIFICATIONS

Table 4. Parameter Min Typ Max Unit AC LINEARITY Spurious-Free Dynamic Range to Nyquist2 Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz 67 dBc fCLK = 50 MHz; fOUT = 2.51 MHz 67 dBc fCLK = 50 MHz; fOUT = 5.04 MHz 63 dBc fCLK = 50 MHz; fOUT = 20.2 MHz 55 dBc fCLK = 100 MHz; fOUT = 2.51 MHz 62 dBc fCLK = 100 MHz; fOUT = 5.04 MHz 60 dBc fCLK = 100 MHz; fOUT = 20.2 MHz 54 dBc fCLK = 100 MHz; fOUT = 40.4 MHz 48 dBc fCLK = 140 MHz; fOUT = 2.51 MHz 57 dBc fCLK = 140 MHz; fOUT = 5.04 MHz 58 dBc fCLK = 140 MHz; fOUT = 20.2 MHz 52 dBc fCLK = 140 MHz; fOUT = 40.4 MHz 41 dBc Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz 70 dBc fCLK = 50 MHz; fOUT = 2.51 MHz 70 dBc fCLK = 50 MHz; fOUT = 5.04 MHz 65 dBc fCLK = 50 MHz; fOUT = 20.2 MHz 54 dBc fCLK = 100 MHz; fOUT = 2.51 MHz 67 dBc fCLK = 100 MHz; fOUT = 5.04 MHz 63 dBc fCLK = 100 MHz; fOUT = 20.2 MHz 58 dBc fCLK = 100 MHz; fOUT = 40.4 MHz 52 dBc fCLK = 140 MHz; fOUT = 2.51 MHz 62 dBc fCLK = 140 MHz; fOUT = 5.04 MHz 61 dBc fCLK = 140 MHz; fOUT = 20.2 MHz 55 dBc fCLK = 140 MHz; fOUT = 40.4 MHz 53 dBc Spurious-Free Dynamic Range Within a Window Single-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 77 dBc fCLK = 50 MHz; fOUT = 5.04 MHz; 2 MHz Span 73 dBc fCLK = 140 MHz; fOUT = 5.04 MHz; 4 MHz Span 64 dBc Double-Ended Output fCLK = 50 MHz; fOUT = 1.00 MHz; 1 MHz Span 74 dBc fCLK = 50 MHz; fOUT = 5.00 MHz; 2 MHz Span 73 dBc fCLK = 140 MHz; fOUT = 5.00 MHz; 4 MHz Span 60 dBc

Rev. D | Page 7 of 24 Parameter Min Typ Max Unit Total Harmonic Distortion fCLK = 50 MHz; fOUT = 1.00 MHz TA = 25°C 66 dBc TMIN to TMAX 65 dBc fCLK = 50 MHz; fOUT = 2.00 MHz 64 dBc fCLK = 100 MHz; fOUT = 2.00 MHz 64 dBc fCLK = 140 MHz; fOUT = 2.00 MHz 55 dBc DAC PERFORMANCE Glitch Impulse 10 pV-sec DAC-to-DAC Crosstalk3 23 dB Data Feedthrough4, 5 22 dB Clock Feedthrough4, 5 33 dB 1 These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range. 2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF. 3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. 4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5 TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.

5 V TIMING SPECIFICATIONS

VAA = 5 V ± 5%,1 VREF = 1.235 V , RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C. Table 5. Parameter3 Symbol Min Typ Max Unit Conditions ANALOG OUTPUTS Analog Output Delay t6 5.5 ns Analog Output Rise/Fall Time4 t7 1.0 ns Analog Output Transition Time5 t8 15 ns Analog Output Skew6 t9 1 2 ns CLOCK CONTROL CLOCK Frequency7 f CLK 0.5 50 MHz 50 MHz grade 0.5 140 MHz 140 MHz grade 0.5 240 MHz 240 MHz grade Data and Control Setup t1 0.5 ns Data and Control Hold t2 1.5 ns CLOCK Period t3 4.17 ns CLOCK Pulse Width High t4 1.875 ns fCLK_MAX = 240 MHz CLOCK Pulse Width Low t5 1.875 ns fCLK_MAX = 240 MHz CLOCK Pulse Width High t4 2.85 ns fCLK_MAX = 140 MHz CLOCK Pulse Width Low t5 2.85 ns fCLK_MAX = 140 MHz CLOCK Pulse Width High t4 8.0 ns fCLK_MAX = 50 MHz CLOCK Pulse Width Low t5 8.0 ns fCLK_MAX = 50 MHz Pipeline Delay6 tPD 1.0 1.0 1.0 Clock cycles PSAVE Up Time 6 t10 2 10 ns 1 These maximum and minimum specifications are guaranteed over this range. 2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.

3.3 V TIMING SPECIFICATIONS

140 MHz 140 MHz grade

240 MHz 240 MHz grade

330 MHz 330 MHz grade

1 These maximum and minimum specifications are guaranteed over this range. 2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz. 3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies. 4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition. 5 Measured from 50% point of full-scale transition to 2% of final value. 6 Guaranteed by characterization. 7 fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.

1. OUTPUT DELAY (t6) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF CLOCK TO THE 50% POINT
2. OUTPUT RISE/FALL TIME (t7) MEASURED BETWEEN THE 10% AND 90% POINTS OF FULL-SCALE TRANSITION.
3. TRANSITION TIME (t8) MEASURED FROM THE 50% POINT OF FULL-SCALE TRANSITION TO WITHIN 2% OF THE

Figure 2. Timing Diagram

Rev. D | Page 9 of 24 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Rating VAA to GND 7 V Voltage on Any Digital Pin GND − 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) −40°C to +85°C Storage Temperature (TS) −65°C to +150°C Junction Temperature (TJ) 150°C Lead Temperature (Soldering, 10 sec) 300°C Vapor Phase Soldering (1 Minute) 220°C IOUT to GND1 0 V to VAA 1Analog output short circuit to any power supply or common GND can be of an indefinite duration. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION

Figure 3. Pin Configuration Table 8. Pin Function Descriptions regular printed circuit board (PCB) power or ground plane. BLANK is a Logic 0, the R0 to R9, G0 to G9, and B0 to B9 pixel inputs are ignored. 13, 29, 30 VAA Analog Power Supply (5 V ± 5%). All VAA pins on the ADV7123 must be connected. 25, 26 GND Ground. All GND pins must be connected. the complementary outputs are not required, these outputs should be tied to ground. not they are all being used. must be connected between COMP and VAA. 36 V REF Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

Rev. D | Page 11 of 24 Pin No. Mnemonic Description 37 R SET A resistor (RSET) connected between this pin and GND controls the magnitude of the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output current. For nominal video levels into a doubly terminated 75 Ω load, RSET = 530 Ω. The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to IOG) is given by: RSET (Ω) = 11,445 × VREF (V)/IOG (mA) The relationship between RSET and the full-scale output current on IOR, IOG, and IOB is given by: IOG (mA) = 11,445 × VREF (V)/ RSET (Ω) (SYNC being asserted) IOR, IOB (mA) = 7989.6 × VREF (V)/RSET (Ω) The equation for IOG is the same as that for IOR and IOB when SYNC is not being used, that is, SYNC tied permanently low. 38 PSAVE Power Save Control Pin. Reduced power consumption is available on the ADV7123 when this pin is active.

5 V TYPICAL PERFORMANCE CHARACTERISTICS

VAA = 5 V , VREF = 1.235 V , IOUT = 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C, unless otherwise noted. Figure 4. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential) Figure 7. THD vs. fCLK @ fOUT = 2 MHz (Second, Third, and Fourth Harmonics) Figure 5. SFDR vs. fOUT @ fCLK = 50 MHz (Single-Ended and Differential) Figure 8. Linearity vs. IOUT

70.4 SFDR (dBc)

Figure 6. SFDR vs. Temperature @ fCLK = 50 MHz (fOUT = 1 MHz) Figure 9. Typical Linearity (INL)

3 V TYPICAL PERFORMANCE CHARACTERISTICS

VAA = 3 V , VREF = 1.235 V , IOUT = 17.62 mA, 50 Ω doubly terminated load, differential output loading, TA = 25°C. Figure 13. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential) Figure 14. SFDR vs. fOUT @ fCLK = 140 MHz (Single-Ended and Differential) Figure 15. SFDR vs. Temperature @ fCLK = 50 MHz, (fOUT = 1 MHz) Figure 16. THD vs. fCLK @ fOUT = 2 MHz (Second, Third, and Fourth Harmonics) Figure 17. Linearity vs. IOUT Figure 18. Typical Linearity

Rev. D | Page 16 of 24 TERMINOLOGY Blanking Level The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch. At 0 IRE units, it is the level that shuts off the picture tube, resulting in the blackest possible picture. Color Video (RGB) This refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. In RGB monitors, three DACs are required, one for each color. Sync Signal (SYNC The position of the composite video signal that synchronizes the scanning process. Gray Scale The discrete levels of video signal between reference black and reference white levels. A 10-bit DAC contains 1024 different levels, while an 8-bit DAC contains 256. Raster Scan The most basic method of sweeping a CRT one line at a time to generate and display images. Reference Black Level The maximum negative polarity amplitude of the video signal. Reference White Level The maximum positive polarity amplitude of the video signal. Sync Level The peak level of the SYNC signal. Video Signal The portion of the composite video signal that varies in gray scale levels between reference white and reference black. Also referred to as the picture signal, this is the portion that can be visually observed.

frequency power supply rejection. Analog Devices at www.analog.com.

39 TO 48

12 SYNC

11 BLANK

24 CLOCK

38 PSAVE

14 TO 23

Figure 28. Typical Connection Diagram

Figure 29. 48-Lead Low Profile Quad Flat Package [LQFP] 2 ADV7123JSTZ330 is available in a 3.3 V version only.

Rev. D | Page 22 of 24 NOTES

Rev. D | Page 23 of 24 NOTES

Rev. D | Page 24 of 24 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D00215-0-7/10(D)