ADV611JST

ADV611 AD | Alldatasheet

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REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a ADV611/ADV612 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 Closed Circuit TV Digital Video Codec FUNCTIONAL BLOCK DIAGRAM QUANTIZER & ENTROPY CODING HOST I/O PORT & FIFO HOST ADV611/ ADV612 256K 3 16-BIT DRAM COMPONENT VIDEO I/O BIN WIDTH CONTROL LOCATION, SIZE AND CONTRAST CONTROL SUBBAND STATISTICS 8 16/32DIGITAL VIDEO I/O PORT WAVELET FILTERS, DECIMATOR & INTERPOLATOR QUALITY BOX CONTROL ON-CHIP TRANSFORM BUFFER DRAM MANAGER

FEATURES

Programmable “Quality Box” Industrial Temperature Range (ADV612) Hardware Frame Rate Reduction 100% Bitstream Compatible with the ADV601 and ADV601LC Precise Compressed Bit Rate Control Field Independent Compression 8-Bit Video Interface Supports CCIR-656 and Multi- plexed Philips Formats General Purpose 16- or 32-Bit Host Interface with

512 Deep 32-Bit FIFO

Real-Time Compression or Decompression of CCIR-601 to Video: 720 3 288 @ 50 Fields/Sec — PAL 720 3 243 @ 60 Fields/Sec — NTSC Compression Ratios from Visually Loss-Less to 7500:1 Visually Loss-Less Compression At 4:1 on Natural Images (Typical)

APPLICATIONS

Time-Lapse Video Tape Recorders Time-Lapse Video Disk Recorders Wireless CCTV Cameras Fiber CCTV Systems GENERAL DESCRIPTION The ADV611/ADV612 are low cost, single chip, dedicated func- tion, all-digital-CMOS-VLSI devices capable of supporting visually loss-less to 7500:1 real-time compression and decom- pression of CCIR -601 digital video at very high image quality levels. The chips integrate glueless video and host interfaces with on-chip SRAM to permit low part count, system level implementations suitable for a broad range of applications. The ADV611/ADV612 are 100% bitstream compatible with the ADV601. The ADV611/ADV612 comes in a 120-lead LQFP package. The ADV611/ADV612 are video encoders/decoders optimized for closed circuit TV (CCTV) applications. With the ADV611/ ADV612, you can define a portion of each video field to be at a higher quality level relative to the rest of the field. This “quality box” feature significantly increases compression of less impor- tant background details, while retaining the image’s overall context. Additionally, the unique subband coding architecture of the ADV611/ADV612 offer many application-specific advantages. A review of the G eneral Theory of Operation and Applying the ADV611/ADV612 sections will help you get the most use out of the ADV 611/ADV612 in any given application. The ADV611/ADV612 accept component digital video through the Video Interface and outputs a compressed bitstream though the Host Interface in Encode Mode. While in Decode Mode, the ADV611/ADV612 accept compressed bitstream through the Host Interface and outputs component digital video through the Video Interface. The host accesses all of the ADV611/ADV612’s control and status registers using the Host Interface. Figure 2 summarizes the basic function of the part. (continued on page 2) ADV7185 DECODER ADV611/ ADV612 ADSP-21xx ANALOG VIDEO SIGNAL IMAGE SENSOR SIGNAL OR QUALITY BOX CONTROLS FROM REMOTE SITE SERIAL OR PARALLEL BITSTREAM FOR TRANSMISSION OR STORAGE DIGITIZER Figure 1. Typical Application

Figure 2. Functional Block Diagram field size is 720 by 288. The maximum pixel rate is 13.50 MHz. the Programmable Quantizer section. 1The maximum active field size is 720 by 288. 2The maximum pixel rate is 13.5 MHz.

–3–REV. 0 The ADV611/ADV612 are real-time compression integrated circuits designed for remote video surveillance or closed circuit television (CCTV) applications. The most important feature of these two devices is the “Quality Box.” With this feature the user can define a box of any size and location within each field of video that will be compressed at full contrast while the re- mainder outside the box, or background of the image, is com- pressed at a lower level of contrast. The background contrast level is controlled by the user. The lower the contrast level, the more the image will be compressed. The objective in a given Table II. Differences Between the ADV601, ADV601LC, ADV611 and ADV612 ADV601 ADV601LC ADV611 ADV612 Bits per Component 10 8 8 8 DSP Serial Port Yes No No No Package 160 PQFP 120 LQFP 120 LQFP 120 LQFP Pin Assignments Unique Unique 98% Similar to ADV601LC 98% Similar to ADV601LC Temperature Range 0 °C to +70°C0 °C to +70°C0 °C to +70°C –25 °C to +85°C q JA 31°C/W 35 °C/W 35 °C/W 35 °C/W qJC 7.5°C/W 5 °C/W 5 °C/W 5 °C/W Field Rate Reduction Software Software Hardware Hardware Stall Mode No No Yes Yes Field Truncation No No Yes Yes Field Size Register No No Yes Yes Field Bit Polarity Control No No Yes Yes Evaluation Board VideoLab VideoPipe CCTVPIPE CCTVPIPE Target Applications Professional Consumer CCTV Industrial CCTV Figure 3. application is to adjust the background contrast to a level that ensures both a recognizable and useful background as well as the highest possible compression. Figure 3 shows how this qual- ity box appears in final video. The ADV611/ADV612 is housed in a plastic LQFP package suitable for cost-sensitive commercial applications. COMPARING THE ADV6xx FAMILY VIDEO CODECS The ADV6xx video codecs support a range of interface, pack- age, and compression features. Table II compares these codecs: Original Video Image Image after compression/decompression shown with different box size and position PROGRAMMABLE QUALITY BOX VARIABLE CONTRAST BACKGROUND

–4– REV. 0 INTERNAL ARCHITECTURE The ADV611/ADV612 is composed of eight blocks. Three of these blocks are interface blocks and five are processing blocks. The interface blocks are the Digital Video I/O Port, the Host I/O Port and the external DRAM manager. The processing blocks are the Wavelet Kernel, the On-Chip Transform Buffer, the Programmable Quantizer, the Run Length Coder and the Huffman Coder. Digital Video I/O Port Provides a real-time uncompressed video interface to support a broad range of component digital video formats, including “D1.” Host I/O Port and FIFO Carries control, status, and compressed video to and from the host processor. A 512 position by 32-bit FIFO buffers the com- pressed video stream between the host and the Huffman Coder. Hardware Field Rate Reduction In CCTV applications it is often desirable to reduce the field rate to achieve the highest possible compression. The ADV611/ ADV612 have special hardware to permit this function. It is possible to set a register on the ADV611/ADV612 during en- code mode that will automatically reduce the field rate. This is a 5-bit register that allows up to 31 fields to be “skipped.” Stall Mode It is possible to stall or halt the ADV611/ADV612 at any time during Encode Mode. This allows the user to feed uncompressed video data to these parts and to stop indefinitely between fields or even between pixels. This feature is useful when compressing video that is not coming into the ADV611/ADV612 at sustained V CLK rates. Stall Mode is enabled by asserting the Stall pin at any time during encode. Stall mode is enabled on the next clock cycle after the pin is asserted. Field Size Reporting The ADV611/ADV612 have a read-only register that allows the user to read the field size of the most recently compressed field. This feature is useful in the feedback loop of a precise bit rate controller. The data is valid after LCODE (unless an entire compressed field resides in the internal FIFO). DRAM Manager Performs all tasks related to writing, reading and refreshing the external DRAM. The external host buffer DRAM is used for reordering and buffering quantizer input and output values. Wavelet Kernel (Filters, Decimator, and Interpolator) Gathers statistics on a per-field basis and includes a block of filters, interpolators and decimators. The kernel calculates for- ward and backward bi-orthogonal, two-dimensional, separable wavelet transforms on horizontal scanned video data. This block uses the internal transform buffer when performing wavelet transforms calculated on an entire image’s data and so elimi- nates any need for extremely fast external memories in an ADV611/ADV612-based design. On-Chip Transform Buffer Provides an internal set of SRAM for use by the wavelet trans- form kernel. Its function is to provide enough delay line storage to support calculation of separable two dimensional wavelet transforms for horizontally scanned images. Programmable Quantizer Quantizes wavelet coefficients. Quantize controls are calculated by the external DSP or host processor during encode operations and de-quantize controls are extracted from the compressed bitstream during decode. Each quantizer Bin Width is com- puted by the BW calculator software to maintain a constant compressed bit rate or constant quality bit rate. A Bin Width is a per-block parameter the quantizer uses when determining the number of bits to allocate to each block (subband). Quality Box The quality box is defined using the Video Area Registers that are described in the Registers Descriptions section. The back- ground contrast is controlled using Background Contrast Regis- ters that are defined later in this document. It is possible to control both parameters on a per-field basis during Encode Mode. This enables the quality box to either move slowly across the image or to instantaneously jump from one location to the next. Run Length Coder Performs run length coding on zero data and models nonzero data, encoding or decoding for more efficient Huffman coding. This data coding is optimized across the subbands and varies depending on the block being coded. Huffman Coder Performs Huffman coder and decoder functions on quantized run-length coded coefficient values. The Huffman coder/de- coder uses three ROM-coded Huffman tables that provide ex- cellent performance for wavelet transformed video. Field Truncation It is possible to set a hard upper limit to the field size of each field during Encode Mode. The Huffman Coder is able to de- tect if the field size exceeds a preset threshold and then causes the remaining Mallat block data to be zeroed out, therefore, truncating the field’s data. The bitstream is truncated in such a way that all end-of-field markers are inserted. This means that the compressed bitstream can still be decompressed by any hardware or software ADV6xx decoder. The only penalty is the loss of Mallat blocks which, depending on how many are lost, will degrade the image quality of the truncated field. GENERAL THEORY OF OPERATION The ADV611/ADV612 processor’s compression algorithm is based on the bi-orthogonal (7, 9) wavelet transform, and imple- ments field independent subband coding. Subband coders trans- form two-dimensional spatial video data into spatial frequency filtered subbands. The quantization and entropy encoding pro- cesses provide the ADV611/ADV612’s data compression. The wavelet theory, on which the ADV611/ADV612 is based, is a new mathematical apparatus first explicitly introduced by Morlet and Grossman in their works on geophysics during the mid 80s. This theory became very popular in theoretical physics and applied math. The late 80s and 90s have seen a dramatic growth in wavelet applications such as signal and image process- ing. For more on wavelet theory by Morlet and Grossman, see Decomposition of Hardy Functions into Square Integrable Wavelets of Constant Shape (journal citation listed in References section).

Figure 8. Wavelet Filter Tree Structure

Figure 10. Typical Quantization of Mallat Data Blocks (Graphed) decode data formats used by the quantizer. pattern in Figure 10 appears in Table III.

15.17 DATA

15.0 BIN

Figure 9. Programmable Quantizer Data Flow

–9–REV. 0 Table III. Typical Quantization of Mallat Data Block Data 1 Mallat Bin Width Reciprocal Bin Blocks Factors Width Factors 39 0x007F 0x0810 40 0x009A 0x06a6 41 0x009A 0x06a6 36 0x00BE 0x0564 33 0x00BE 0x0564 30 0x00E4 0x047e 34 0x00E6 0x0474 35 0x00E6 0x0474 37 0x00E6 0x0474 38 0x00E6 0x0474 31 0x0114 0x03b6 32 0x0114 0x03b6 27 0x0281 0x0199 24 0x0281 0x0199 21 0x0301 0x0155 25 0x0306 0x0153 26 0x0306 0x0153 28 0x0306 0x0153 29 0x0306 0x0153 22 0x03A1 0x011a 23 0x03A1 0x011a 5 0x0A16 0x0066 18 0x0A16 0x0066 12 0x0C1A 0x0055 20 0x0C2E 0x0054 19 0x0C2E 0x0054 17 0x0C2E 0x0054 16 0x0C2E 0x0054 14 0x0E9D 0x0046 13 0x0E9D 0x0046 6 0x1DDC 0x0022 9 0x1DDC 0x0022 3 0x23D5 0x001d 11 0x2410 0x001c 10 0x2410 0x001c 8 0x2410 0x001c 7 0x2410 0x001c 5 0x2B46 0x0018 4 0x2B46 0x0018 0 0xA417 0x0006 2 0xC62B 0x0005 1 0xC62B 0x0005 NOTE 1The Mallat block numbers, Bin Width factors, and Reciprocal Bin Width factors in Table III correspond to the shading per-cent fill) of Mallat blocks in Figure 10. THE RUN LENGTH CODER AND HUFFMAN CODER This block contains two types of entropy coders that achieve mathematically loss-less compression: run-length and Huffman. The run-length coder looks for long strings of zeros and replaces them with short hand symbols. Table IV illustrates an example of how compression is possible. The Huffman coder is a digital compressor/decompressor that can be used for compressing any type of digital data. Essentially, an ideal Huffman coder creates a table of the most commonly occurring code sequences (typically zero and small values near zero) and then replaces those codes with some shorthand. The ADV611/ADV612 employs three fixed Huffman tables; it does not create tables. The filters and the quantizer increase the number of zeros and strings of zeros, which improves the performance of the entropy coders. The higher the selected compression ratio, the more zeros and small value sequences the quantizer needs to generate. The transformed image in Figure 7 shows that the filter bank concentrates zeros and small values in the higher frequency blocks. Encoding vs. Decoding The decoding of compressed video follows the exact path as encoding but in reverse order. There is no need to calculate bin widths during decode because the bin width is stored in the compressed image during encode. PROGRAMMER’S MODEL A host device configures the ADV611/ADV612 using the Host I/O Port. The host reads from status registers and writes to control registers through the Host I/O Port. Table V. Register Description Conventions Register Name Register Type (Indirect or Direct, Read or Write) and Address Register Functional Description Text Bit [#] or Bit or Bit Field Name and Usage Description Bit Range [High:Low]

0 Action or Indication When Bit Is Cleared (Equals 0)

1 Action or Indication When Bit Is Set (Equals 1)

Table IV. Uncompressed Versus Compressed Data Using Run-Length Coding 0000000000000000000000000000000000000000000000000000000000000000000(uncompressed)

57 Zeros (Compressed)

Figure 11. Map of ADV611/ADV612 Direct and Indirect Registers

–11–REV. 0 ADV611/ADV612 REGISTER DESCRIPTIONS Indirect Address Register Direct (Write) Register Byte Offset 0x00. This register holds a 16-bit value (index) that selects the indirect register accessible to the host through the indirect data register. All indirect write registers are 16 bits wide. The address in this register is auto-incremented on each subsequent access of the in direct data register. This capability enhances I/O performance during modes of operation where the host is calculating Bin Width contr ols. [15:0] Indirect Address Register, IAR[15:0]. Holds a 16-bit value (index) that selects the indirect register to read or write through the indirect data register (undefined at reset). [31:16] Reserved (undefined read/write zero) Indirect Register Data Direct (Read/Write) Register Byte Offset 0x04 This register holds a 16-bit value read or written from or to the indirect register indexed by the Indirect Address Register. [15:0] I ndirect Register Data, IRD[15:0]. A 16-bit value read or written to the indexed indirect register. Undefined at reset. [31:16] Reserved (undefined read/write zero) Compressed Data Register Direct (Read/Write) Register Byte Offset 0x08 This register holds a 32-bit sequence from the compressed video bitstream. This register is buffered by a 512 position, 32-bit FIFO. For Word (16-bit) accesses, ac cess Word0 (Byte 0 and Byte 1) then Word1 (Byte 2 and Byte 3) for correct auto-increment. For a description of the data sequence, see the Compressed Data Stream Definition section. [31:0] Compressed Data Register, CDR[31:0]. 32-bit value containing compressed video stream data. At reset, contents undefined. Interrupt Mask / Status Register Direct (Read/Write) Register Byte Offset 0x0C This 16-bit register contains interrupt mask and status bits that control the state of the ADV611/ADV612’s HIRQ pin. With the seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR), select the con- ditions that are ORed together to determine the output of the HIRQ pin. Six of the status bits (LCODE, STATSR, FIFOSTP, MERR, FIFOERR, CCIRER) indicate active interrupt conditions and are sticky bits that stay set until read. Because sticky status bits are cleared when read, and these bits are set on the positive edge of the condition coming true, they cannot be read or tested for stable level true conditions multiple times. The FIFOSRQ bit is not sticky. This bit can be polled to monitor for a FIFOSRQ true condition. Note: Enable this monitoring by using the FIFOSRQ bit and correctly programming DSL and ESL fields within the FIFO control registers. [0] CCIR-656 Error in CCIR-656 data stream, CCIRER. This read only status bit indicates the following:

0 No CCIR-656 Error condition, reset value

1 Unrecoverable error in CCIR-656 data stream (missing sync codes)

[1] Statistics Ready, STATSR. This read only status bit indicates the following:

0 No Statistics Ready condition, reset value (STATS_R pin LO)

1 Statistics Ready for BW calculator (STATS_R pin HI)

[2] Last Code Read, LCODE. This read only status bit indicates the last compressed data word for field will be retrieved from the FIFO on the next read from the host bus.

0 No Last Code condition, reset value (LCODE pin LO)

1 Next read retrieves last word for field in FIFO (LCODE pin HI)

[3] FIFO Service Request, FIFOSRQ. This read only status bit indicates the following:

0 No FIFO Service Request condition, reset value (FIFO_SRQ pin LO)

1 FIFO is nearly full (encode) or nearly empty (decode) (FIFO_SRQ pin HI)

[4] FIFO Error, FIFOERR. This condition indicates that the host has been unable to keep up with the ADV611/ADV612’s compressed data supply or demand requirements. If this condition occurs during encode, the data stream will not be corrupted until MERR indicates that the DRAM has also overflowed. If this condition occurs during decode, the video output will be corrupted. If the system overflows the FIFO (disregarding a FIFOSTP condition) with too many writes in decode mode, FIFOERR is asserted. This read only status bit indicates the following:

0 No FIFO Error condition, reset value (FIFO_ERR pin LO)

1 FIFO overflow (encode) or underflow (decode) (FIFO_ERR pin HI)

–12– REV. 0 [5] FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode. In decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when FIFOSTP is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely be performed. This status bit indicates the following:

0 No FIFO Stop condition, reset value (FIFO_STP pin LO)

1 FIFO empty (encode) or full (decode) (FIFO_STP pin HI)

[6] Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can be caused by a defective DRAM, the inability of the Host to keep up with the ADV611/ADV612 compressed data stream, or bit errors in the data stream. Note that the ADV611/ADV612 recovers from this condition without host intervention.

0 No memory error condition, reset value

1 Memory error

[7] Reserved (always read/write zero) [8] Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:

0 Disable CCIR-656 data error interrupt, reset value

1 Enable interrupt on error in CCIR-656 data

[9] Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:

0 Disable Statistics Ready interrupt, reset value

1 Enable interrupt on Statistics Ready

[10] Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:

0 Disable Last Code Read interrupt, reset value

1 Enable interrupt on Last Code Read from FIFO

[11] Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:

0 Disable FIFO Service Request interrupt, reset value

1 Enable interrupt on FIFO Service Request

[12] Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:

0 Disable FIFO Stop interrupt, reset value

1 Enable interrupt on FIFO Stop

[13] Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:

0 Disable FIFO Error interrupt, reset value

1 Enable interrupt on FIFO Error

[14] Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:

0 Disable memory error interrupt, reset value

1 Enable interrupt on memory error

[15] Reserved (always read/write zero) Mode Control Register Indirect (Read/Write) Register Index 0x00 This register holds configuration data for the ADV611/ADV612’s video interface format and controls several other video interfac e features. For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions: [3:0] Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all other values are reserved): 0x0 CCIR-656, reset value 0x2 MLTPX (Philips) [4] VCLK Output Divided by two, VCLK2. This bit controls the following:

0 Do not divide VCLK output (VCLKO = VCLK), reset value

1 Divide VCLK output by two (VCLKO = VCLK/2)

[5] Video Interface Master/Slave Mode Select, M/S. This bit selects the following: 0 Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value

1 Master mode video interface (ADV611/ADV612 controls video timing, HSYNC-VSYNC are outputs)

[6] Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following: 0 525 mode video interface, reset value 1 625 mode video interface

–13–REV. 0 [7] Video Interface Encode/Decode Mode Select, E/D. This bit selects the following:

0 Decode mode video interface (compressed-to-raw)

1 Encode mode video interface (raw-to-compressed), reset value

[8] Reserved (always write zero) [9] Video Interface Bipolar/Unipolar Color Component Select, BUC. This bit selects the following:

0 Bipolar color component mode video interface, reset value

1 Unipolar color component mode video interface

[10] Reserved (always write zero) [11] Video Interface Software Reset, SWR. This bit has the following effects on ADV611/ADV612 operations:

0 Normal operation

1 Software Reset. This bit is set on hardware reset and must be cleared before the ADV611/ADV612 can begin processing. (reset value) When this bit is set during encode, the ADV611/ADV612 completes processing the current field then suspends operation until the SWR bit is cleared. When this bit is set during decode, the ADV611/ADV612 suspends operation immediately and does not resume operation until the SWR bit is cleared. Note that this bit must be set whenever any other bit in the Mode register is changed. [12] HSYNC pin Polarity, PHSYNC. This bit has the following effects on ADV611/ADV612 operations:

0 HSYNC is HI during blanking, reset value

1 HSYNC is LO during blanking (HI during active)

[13] HIRQ pin Polarity, PHIRQ. This bit has the following effects on ADV611/ADV612 operations:

0 HIRQ is active LO, reset value

1 HIRQ is active HI

[14] Quality Box Enable, QBE. This bit has the following effect on ADV611/ADV612 operations: 0 Video area registers (HSTART, HEND, VSTART, VEND). Crop video area, setting cropped area to all 0 quantizations (ADV601 mode), reset value 1 Video area registers (HSTART, HEND, VSTART, VEND). Select Quality Box. Quantization of the area outside the box is selected with the background Contrast Control register. See the video area registers for more information on the Quality Box. [15] Video Stall Enable, VSE. This bit has the following effect on ADV611/ADV612 operations:

0 Video Stall disabled (ADV601 mode), reset value

1 Video Stall enabled. FIFO Control Register Indirect (Read/Write) Register Index 0x01 This register holds the service-request settings for the ADV611/ADV612’s host interface FIFO, causing interrupts for the “nearly full” and “nearly empty” levels. Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by 32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV611/ADV612 uses these settings to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin). [3:0] Encode Service Level, ESL[3:0]. The value in this field determines when the FIFO is considered nearly full on encode; a condi- tion that generates a FIFO service request condition in encode mode. Since this register is four bits (16 states), and the FIFO is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the register and their meaning. ESL Interrupt When . . .

0000 Disables service requests (FIFO_SRQ never goes HI during encode)

0001 FIFO has only 32 positions filled (FIFO_SRQ when >= 32 positions are filled)

1000 FIFO is 1/2 full, reset value

1111 FIFO has only 32 positions empty (480 positions filled)

[7:4] Decode Service Level, DSL[7:4]. The value in this field determines when the FIFO is considered nearly empty in decode; a condition that generates a FIFO service request in decode mode. Because this register is four bits (16 states), and the FIFO is 512 positions, the step size for each bit in this register is 32 positions. The following table summarizes sample states of the register and their meaning. DSL Interrupt When . . .

0000 Disables service requests (FIFO_SRQ never goes HI)

0001 FIFO has only 32 positions filled (480 positions empty)

1000 FIFO is 1/2 empty, reset value

1111 FIFO has only 32 positions empty (FIFO_SRQ when >= 32 positions are empty)

[15:8] Reserved (always write zero)

register is usually set to zero, but in cases where you wish to crop incoming video it is possible to do so by changing HST. than the max size of the selected video mode, the ADV611/ADV612 uses the max size of the selected mode for HEND. register is usually set to zero unless you want to crop the active video. which field is being processed next. than the max size of the selected video mode, the ADV611/ADV612 uses the max size of the selected mode for VEND. (encode only), but do not change the image size. Figure 12 shows how the video area registers work together.

• The vertical numbers include the blanking areas of the video. Specifically, a VSTART value of 21 will include the first line of active video, and the first pixel in a line corresponds to a value HSTART of 0 (for NTSC regular). Note that the vertical coordinates start with 1, whereas the horizontal coordinates start with 0.
• The default cropping mode is set for the entire frame. Specifi- cally, Field 2 starts at a VSTART value of 283 (for NTSC regular). When the quality box is enabled (Mode Control register, Bit 14 = 1), the area defined by the HSTART, HEND, VSTART and VEND registers is the quality box area, and the rest of the video area is attenuated according to the value in the background Contrast Control register (Indirect Register Index 0x9). In this mode, the range of values for VSTART and VEND is 1–243 for NTSC and 1–288 for PAL. Also note that VSTART and VEND do not need to be updated for each field in this mode. VSTART VEND HSTART HEND ZERO ZERO ZERO X, Y ACTIVE VIDEO AREA 0, 0 ZERO ZERO ZERO ZERO ZERO MAX FOR SELECTED VIDEO MODE

Figure 12. Video Area and Video Area Registers

–15–REV. 0 To vertically crop video while encoding, program the VSTART and VEND registers with actual video line numbers, which differ for each field. The VSTART and VEND contents must be updated on each field, unless the quality box is enabled. Perform this updating as part of the field-by-field BW register update process. To perform this dynamic update correctly, the update software must keep track of which field is being processed next. [9:0] Vertical End, VEN[9:0]. 10-bit value defining the ending line of the active video region, with line numbers from 1-to-625 in PAL and 1-to-525 in NTSC. (0x3FF at reset—this value is larger than the max size of the largest video mode) [15:10] Reserved (always write zero) Compressed Field Size Limit Indirect (Read/Write) Register Index 0x8 [15:0] The DWORD Max Count 16 MSBs register selects the maximum number of double (32-bit) words for an encoded field. When the value in the DWORD count registers reaches the DWORD Max Count, the Quantizer zeroes out all remaining samples in the field. To enable the DWORD Max Counts operation, you must set (= 1) Bit 4 in Indirect register 0x7; all other bits in Indirect register 0x7 are reserved ( = 0). Note that the 4 LSBs of the max count are 0000, so the max count is selectable in 16-word increments. Contains bits [19:4] of the DWORD max count, reset to 0xffff Mode Control #2 Indirect (Read/Write) Register Index 0x9 [2:0] These bits control the contrast/attenuation of the area outside the quality box when the quality box is enabled. The following settings control background contrast. Setting Contrast/Attenuation

000 Illegal

[3] Field Polarity Bit. This bit reverses the polarity of the FIELD pin. This bit operates as follows:

0 Normal Field Polarity (ADV601 Mode), reset value

1 Reverse Field Polarity. Polarity is opposite to the polarity in the FIELD pin timing diagrams. [8:4] Field Rate Reduction. To reduce this compressed data rate, the ADV601 can discard some video fields. Set field rate reduction to zero to capture all fields, one to discard every other field, two to discard two fields out of three and so on. Maximum possible field rate reduction send only one field out of 32. [9] Reserved, must set to 1. This bit must be set to take advantage of MERR detection logic. Resets to 0. [10] Reserved, resets to 1. [11] Ignore Field bit in decode, setting this bit eliminates black fields if field bits repeat from field to field in decode mod e, resets to 0. Sum of Squares [0–41] Registers Indirect (Read Only) Register Index 0x080 through 0x0A9 The Sum of Squares [0–41] registers hold values that correspond to the summation of squared values in corresponding Mallat bloc ks [0–41]. These registers let the Host or DSP read sum of squares statistics from the ADV611/ADV612; using these values (with the Sum of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV611/ADV612 indicates that the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the statistics at any time. The Host reads these values through the Host Interface. [15:0] Sum of Squares, STS[15:0]. 16-bit values [0-41] for corresponding Mallat blocks [0-41] (undefined at reset). Sum of Square values are 16-bit codes that represent the Most Significant Bits of values ranging from 40 bits for small blocks to 48 bits for large blocks. The 16-bit codes have the following precision: Blocks Precision Sum of Squares Precision Description 0–2 48.–32 48.-bits wide, left shift code by 32-bits, and zero fill 3–11 46.–30 46.-bits wide, left shift code by 30-bits, and zero fill 12–20 44.–28 44.-bits wide, left shift code by 28-bits, and zero fill 21–29 42.–26 42.-bits wide, left shift code by 26-bits, and zero fill 30–41 40.–24 40.-bits wide, left shift code by 24-bits, and zero fill If the Sum of Squares code were 0x0 025 for block 10, the actual value would be 0x000940000000; if using that same code, 0x0025, for block 30, the actual value would be 0x0025000000. [31:0] Reserved (always read zero)

–16– REV. 0 Sum of Luma Value Register Indirect (Read Only) Register Index 0x0AA The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The Host reads these values through the Host Interface. [15:0] Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset) [31:0] Reserved (always read zero) Sum of Cb Value Register Indirect (Read Only) Register Index 0x0AB The Sum of Cb Value register lets the host or DSP read the sum of pixel values for the Cb component in block 40. The Host reads these values through the Host Interface. [15:0] Sum of Cb, SCB[15:0]. 16-bit component pixel values (undefined at reset) [31:0] Reserved (always read zero) Sum of Cr Value Register Indirect (Read Only) Register Index 0x0AC The Sum of Cr Value register lets the host or DSP read the sum of pixel values for the Cr component in block 41. The Host reads these values through the Host Interface. [15:0] Sum of Cr, SCR[15:0]. 16-bit component pixel values (undefined at reset) [31:0] Reserved (always read zero) MIN Luma Value Register Indirect (Read Only) Register Index 0x0AD The MIN Luma Value register lets the host or DSP read the minimum pixel value for the Luma component in the unprocessed data. The Host reads these values through the Host Interface. [15:0] Minimum Luma, MNL[15:0]. 16-bit component pixel value (undefined at reset) [31:0] Reserved (always read zero) MAX Luma Value Register Indirect (Read Only) Register Index 0x0AE The MAX Luma Value register lets the host or DSP read the maximum pixel value for the Luma component in the unprocessed data. The Host reads these values through the Host Interface. [15:0] Maximum Luma, MXL[15:0]. 16-bit component pixel value (undefined at reset) [31:0] Reserved (always read zero) MIN Cb Value Register Indirect (Read Only) Register Index 0x0AF The MIN Cb Value register lets the host or DSP read the minimum pixel value for the Cb component in the unprocessed data. The Host reads these values through the Host Interface. [15:0] Minimum Cb, MNCB[15:0], 16-bit component pixel value (undefined at reset) [31:0] Reserved (always read zero) MAX Cb Value Register Indirect (Read Only) Register Index 0x0B0 The MAX Cb Value register lets the host or DSP read the maximum pixel value for the Cb component in the unprocessed data. The Host reads these values through the Host Interface. [15:0] Maximum Cb, MXCB[15:0].16-bit component pixel value (undefined at reset) [31:0] Reserved (always read zero)

–17–REV. 0 MIN Cr Value Register Indirect (Read Only) Register Index 0x0B1 The MIN Cr Value register lets the host or DSP read the minimum pixel value for the Cr component in the unprocessed data. The Host reads these values through the Host Interface. [15:0] Minimum Cr, MNCR[15:0]. 16-bit component pixel value (undefined at reset) [31:0] Reserved (always read zero) MAX Cr Value Register Indirect (Read Only) Register Index 0x0B2 The MAX Cr Value register lets the host or DSP read the maximum pixel value for the Cr component in the unprocessed data. The Host reads these values through the Host Interface. [15:0] Maximum Cr, MXCR[15:0]. 16-bit component pixel value (undefined at reset) [31:0] Reserved (always read zero) Compressed Field Size [HI] Indirect (Read Only) Register Index 0x83 [15:0] The DWORD Count registers hold the count of double (32-bit) words contained in the previously encoded field. This count is useful for bit rate control algorithms that use a servo loop, which is locked to the expected number of double words in the field. The registers are double buffered to ensure that the count remains constant while the next field's count accumu- lates. Contains bits [19:4] of the DWORD count, reset is 0. Compressed Field Size [LO] Indirect (Read Only) Register Index 0xB4 [3:0] Contains bits [3:0] of the DWORD count, reset is 0. For more information, see the DWORD Count 16 MSB Register description. Bin Width and Reciprocal Bin Width Registers Indirect (Read/Write) Register Index 0x0100-0x0153 The RBW and BW values are calculated by the host or DSP from data in the Sum of Squares [0-41], Sum of Value, MIN Value, and MAX Value registers; then are written to RBW and BW registers during encode mode to control the quantizer. The Host writes thes e values through the Host Interface. These registers contain a 16-bit interleaved table of alternating RBW/BW (RBW-even addresses and BW-odd addresses) values as indexed on writes by address register. Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are 6.10 , un- signed, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries) ( undefined at reset). [15:0] Bin Width Values, BW[15:0] [15:0] Reciprocal Bin Width Values, RBW[15:0]

–18– REV. 0 PIN FUNCTION DESCRIPTIONS Clock Pins Name Pins I/O Description VCLK/XTAL 2 I A single clock (VCLK) or crystal input (across VCLK and XTAL). An acceptable 50% duty cycle clock signal is 27 MHz (CCIR-601 NTSC/PAL). If using a clock crystal, use a parallel resonant, microprocessor grade clock crystal. If using a clock input, use a TTL level input, 50% duty cycle clock with 1 ns (or less) jitter (measured rising edge to rising edge). Slowly varying, low jitter clocks are acceptable; up to 5% frequency variation in 0.5 sec. VCLKO 1 O VCLK Output or VCLK Output divided by two. Select function using Mode Control register. Video Interface Pins Name Pins I/O Description VSYNC 1 I or O Vertical Sync or Vertical Blank. This pin can be either an output (Master Mode) or an input (Slave Mode). The pin operates as follows:

• Output (Master) HI during inactive lines of video and LO otherwise
• Input (Slave) a HI on this input indicates inactive lines of video HSYNC 1 I or O Horizontal Sync or Horizontal Blank. This pin can be either an output (Master Mode) or an input (Slave Mode). The pin operates as follows:
• Output (Master) HI during inactive portion of video line and LO otherwise
• Input (Slave) a HI on this input indicates inactive portion of video line Note that the polarity of this signal is modified using the Mode Control register. For detailed timing information, see the Video Interface section. FIELD 1 I or O Field # or Frame Sync. Polarity of FIELD Pin can be reversed by setting Bit 3 in Mode Control Register 2. The pin operates as follows:
• Output (Master) HI during Field1 lines of video and LO otherwise
• Input (Slave) a HI on this input indicates Field1 lines of video ENC 1 O Encode or Decode. This output pin indicates the coding mode of the ADV611/ ADV612 and operates as follows:
• LO Decode Mode (Video Interface is output)
• HI Encode Mode (Video Interface is input) Note that this pin can be used to control bus enable pins for devices connected to the ADV611/ADV612 Video Interface. VDATA[7:0] 8 I/O 4:2:2 Video Data (8-bit digital component video data). These pins are inputs during encode mode and outputs during decode mode. When outputs (decode) these pins are compatible with 50 pF loads (rather than 30 pF as all other busses) to meet the high performance and large number of typical loads on this bus. The performance of these pins varies with the Video Interface Mode set in the Mode Control register, see the Video Interface section of this data sheet for pin assignments in each mode. Note that the Mode Control register also sets whether the color component is treated as either signed or unsigned. STALL 1 I Stall Mode. This pin stalls incoming video data driving encode.

–19–REV. 0 DRAM Interface Pins Name Pins I/O Description DDAT[15:0] 16 I/O DRAM Data Bus. The ADV611/ADV612 uses these pins for 16-bit data read/ write operations to the external 256K · 16-bit DRAM. (The operation of the DRAM interface is fully automatic and controlled by internal functionality of the ADV611/ADV612.) These pins are compatible with 30 pF loads. DADR[8:0] 9 O DRAM Address Bus. The ADV611/ADV612 uses these pins to form the multi- plexed row/column address lines to the external DRAM. (The operation of the DRAM interface is fully automatic and controlled by internal functionality of the ADV611/ADV612.) These pins are compatible with 30 pF loads. RAS 1 O DRAM Row Address Strobe. This pin is compatible with 30 pF loads. CAS 1 O DRAM Column Address Strobe. This pin is compatible with 30 pF loads. WE 1 O DRAM Write Enable. This pin is compatible with 30 pF loads. Note that the ADV611/ ADV612 does not have a DRAM OE pin. Tie the DRAM’s OE pin to ground. Host Interface Pins Name Pins I/O Description DATA[31:0] 32 I/O Host Data Bus. These pins make up a 32-bit wide host data bus. The host controls this asynchronous bus with the WR, RD, BE and CS pins to commu- nicate with the ADV611/ADV612. These pins are compatible with 30 pF loads. ADR[1:0] 2 I Host DWord Address Bus. These two address pins let you address the ADV611/ADV612’s four directly addressable host interface registers. For an illustration of how this addressing works, see the Control and Write Register Map figure and Status and Read Register Map figure. The ADR bits permit register addressing as follows: ADR1 ADR0 DWord Address Byte Address 0 0 0 0x00 0 1 1 0x04 1 0 2 0x08 1 1 3 0x0C BE0–BE1 2 I Host Word Enable pins. These two input pins select the words that the ADV611/ BE2–BE3 ADV612’s direct and indirect registers access through the Host Interface; BE0–BE1 access the least significant word, and BE2–BE3 access the most significant word. For a 32-bit interface only, tie these pins to ground, making all words available. Some important notes for 16-bit interfaces are as follows:

• When using these byte enable pins, the byte order is always the lowest byte
• to the higher bytes.
• The ADV611/ADV612 advances to the next 32-bit compressed data FIFO
• location after the BE2–BE3 pin is asserted then de-asserted (when accessing the
• Compressed Data register); so the FIFO location only advances when and if
• the host reads or writes the MSW of a FIFO loca tion.
• The ADV611/ADV612 advances to the next 16-bit indirect register after the
• BE0–BE1 pin is asserted then de-asserted; so the register selection only advances
• when and if the host reads or writes the MSW of a 16-bit indirect register. CS 1 I Host Chip Select. This pin operates as follows:
• LO Qualifies Host Interface control signals
• HI Three-states DATA[31:0] pins WR 1 I Host Write. Host register writes occur on the rising edge of this signal. RD 1 I Host Read. Host register reads occur on the low true level of this signal.

–20– REV. 0 Host Interface Pins (Continued) Name Pins I/O Description ACK 1 O Host Acknowledge. The ADV611/ADV612 acknowledges completion of a Host Interface access by asserting this pin. Most Host Interface accesses (other than the compressed data register access) result in ACK being held high for at least one wait cycle, but some exceptions to that rule are as follows:

• A full FIFO during decode operations causes the ADV 611/ADV612 to de-assert
• (drive HI) the ACK pin, holding off further writes of compressed data until
• the FIFO has one available location.
• An empty FIFO during encode operations causes the ADV611/ADV612 to de-
• assert (drive HI) the ACK pin, holding off further reads until one location is filled. FIFO_SRQ 1 O FIFO Service Request. This pin is an active high signal indicating that the FIFO needs to be serviced by the host. (see FIFO Control register). The state of this pin also appears in the Interrupt Mask/Status register. Use the interrupt m ask to assert a Host interrupt (HIRQ pin) based on the state of the FIFO_SRQ pin. This pin oper- ates as follows:
• LO No FIFO Service Request condition (FIFOSRQ bit LO)
• HI FIFO needs service is nearly full (encode) or nearly empty (decode) During encode, FIFO_SRQ is LO when the SWR bit is cleared (0) and goes HI when the FIFO is nearly full (see FIFO Control register). During decode, FIFO_SRQ is HI when the SWR bit is cleared (0), because FIFO is empty, and goes LO when the FIFO is filled beyond the nearly empty condition (see FIFO Control register). STATS_R 1 O Statistics Ready. This pin indicates the Wavelet Statistics (contents of Sum of Squares, Sum of Value, MIN Value, MAX Value registers) have been updated and are ready for the Bin Width calculator to read them from the host in terface. The frequency of this interrupt will be equal to the field rate. The state of this pin also appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a Host interrupt (HIRQ pin) based on the state of the STATS_R pin. This pin oper- ates as follows:
• LO No Statistics Ready condition (STATSR bit LO)
• HI Statistics Ready for BW calculator (STATSR bit HI) LCODE 1 O Last Compressed Data (for field). This bit indicates the last compressed data word for field will be retrieved from the FIFO on the next read from the host bus. The frequency of this interrupt is similar to the field rate, but varies depending on compression and host response. The state of this pin also appears in the Interrupt Mask/Status register. Use the interrupt mask to assert a Host interrupt ( HIRQ pin) based on the state of the LCODE pin. This pin operates as follows:
• LO No Last Code condition (LCODE bit LO)
• HI Last data word for field has been read from FIFO (LCODE bit HI) HIRQ 1 O Host Interrupt Request. This pin indicates an interrupt request to the Host. The Interrupt Mask/Status register can select conditions for this interrupt based on any or all of the following: FIFOSTP, FIFOSRQ, FIFOERR, LCODE, STATR or CCIR-656 unrecoverable error. Note that the polarity of the HIRQ pin can be modified using the Mode Control register. RESET 1 I ADV611/ADV612 Chip Reset. Asserting this pin returns all registers to reset state. Note that the ADV611/ADV612 must be reset at least once after power-up with this active low signal input. For more information on reset, see the SWR bit description. Power Supply Pins Name Pins I/O Description GND 16 I Ground VDD 13 I +5 V dc Digital Power

–21–REV. 0 Video Interface The ADV611/ADV612 video interface supports two types of component digital video (D1) interfaces in both compression (input) and decompression (output) modes. These digital video interfaces include support for the Multiplexed Philips 4:2:2 and CCIR-656/SMPTE125M—international standard. Video interface master and slave modes allow for the generation or receiving of synchronization and blanking signals. Definitions for the different formats can be found later in this section. For recom- mended connections to popular video decoders and encoders, see the Connecting the ADV611/ADV612 to Popular Video Decoders and Encoders section. A complete list of supported video interfaces and sampling rates is included in Table VI. Table VI. Component Digital Video Interfaces Nominal Bits/ Color Date Name Component Space Sampling Rate (MHz) I/F Width CCIR-656 8 YCrCb 4:2:2 27 8 Multiplex Philips 8 YUV 4:2:2 27 8 Internally, the video interface translates all video formats to one consistent format to be passed to the wavelet kernel. This con- sistent internal video standard is 4:2:2 at 16 bits accuracy. VITC and Closed Captioning Support The video interface also supports the direct loss-less extraction of 90-bit VITC codes during encode and the insertion of VITC codes during decode. Closed Captioning data (found on active Video Line 21) is handled just as normal active video on an active scan line. As a result, no special dedicated support is necessary for Closed Captioning. The data rates for Closed Captioning data are low enough to ensure robust operation of this mechanism at compression ratios of 50:1 and higher. Note that you must include Video Line 21 in the ADV611/ADV612’s defined active video area for Closed Caption support.

27 MHz Nominal Sampling

There is one clock input (VCLK) to support all internal process- ing elements. This is a 50% duty cycle signal and must be syn- chronous to the video data. Internally this clock is doubled using a phase locked loop to provide for a 54 MHz internal processing clock. The clock interface is a two pin interface that allows a crystal oscillator to be tied across the pins or a clock oscillator to drive one pin. The nominal clock rate for the video interface is 27 MHz. Note that the ADV611/ADV612 also supports a pixel rate of 13.5 MHz. Video Interface and Modes In all, there are seven programmable features that configure the video interface. These are:

• Encode-Decode Control In addition to determining what functions the internal pro- cessing elements must perform, this control determines the direction of the video interface. In decode mode, the video interface outputs data. In encode mode, the interface receives data. The state of the control is reflected on the ENC pin. This pin can be used as an enable input by external line driv- ers. This control is maintained by the host processor.
• Master-Slave Control This control determines whether the ADV611/ADV612 gen- erates or receives the VSYNC, HSYNC, and FIELD signals. In master mode, the ADV611/ADV612 generates these sig- nals for external hardware synchronization. In slave mode, the ADV611/ADV612 receives these signals. Note that some video formats require the ADV611/ADV612 to operate in slave mode only. This control is maintained by the host processor.
• 525-625 (NTSC-PAL) Control This control determines whether the ADV611/ADV612 is operating on 525/NTSC video or 625/PAL video. This infor- mation is used when the ADV611/ADV612 is in master and decode modes so that the ADV611/ADV612 knows where and when to generate the HSYNC, VSYNC, and FIELD Pulses as well as when to insert the SAV and EAV time codes (for CCIR-656 only) in the data stream. This control is main- tained by the host processor. Table VII shows how the 525- 625 Control in the Mode Control register works. Table VII. Square Pixel Control, 525-625 Control, and Video Formats Max Max 525-625 Horizontal Field Control Size Size NTSC-PAL 0 720 243 CCIR-601 NTSC 1 720 288 CCIR-601 PAL
• Bipolar/Unipolar Color Component This mode determines whether offsets are used on color com- ponents. In Philips mode, this control is usually set to Bipo- lar, since the color components are normal twos-compliment signed values. In CCIR-656 mode, this control is set to Uni- polar, since the color components are offset by 128. Note that it is likely the ADV611/ADV612 will function if this control is in the wrong state, but compression performance will be degraded. It is important to set this bit correctly.
• Active Area Control Four registers HSTART (horizontal start), HEND (horizon- tal end), VSTART (vertical start) and VEND (vertical end) determine the active video area. The maximum active video area is 720 by 288 pixels for a single field.
• Video Format This control determines the video format that is supported. In general, the goal of the various video formats is to support glueless interfaces to the wide variety of video formats periph- eral components expect. This control is maintained by the host processor. Table VIII shows a synopsis of the supported video formats. Definitions of each format can be found later in this section. For Video Interface pins descriptions, see the Pin Function Descriptions.

–22– REV. 0 Table IX. CCIR-656 Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality HSYNC, VSYNC and FIELD Master Mode (HSYNC, VSYNC Slave Mode (HSYNC, VSYNC Functionality for CCIR-656 and FIELD Are Outputs) and FIELD Are Inputs) Encode Mode (video data is input Pins are driven to reflect the states of the These pins are used to control the to the chip) received time codes: EAV and SAV. This blanking of video and sequencing (used functionality is independent of the state of with video decoders that do not con- the 525-625 mode control. An encoder is form to the correct number of samples most likely to be in master mode. per line [e.g., the Harris 8115]). Decode Mode (video data is output Pins are output to the precise timing definitions Undefined—Use Master Mode from the chip) for CCIR-656 interfaces. The state of the pins reflect the state of the EAV and SAV timing codes that are generated in the output video data. These definitions are different for 525 and 625 line systems. The ADV611/ADV612 completely manages the generation and timing of these pins. Clocks and Strobes All video data is synchronous to the video clock (VCLK). The rising edge of VCLK is used to clock all data into the ADV611/ADV612. Synchronization and Blanking Pins Three signals, which can be configured as inputs or outputs, are used for video frame and field horizontal synchronization and blanking. These signals are VSYNC, HSYNC, and FIELD. VDATA Pins Functions With Differing Video Interface Formats The functionality of the Video Interface pins depends on the current video format. Video Formats—CCIR-656 The ADV611/ADV612 supports a glueless video interface to CCIR-656 devices when the Video Format is programmed to CCIR-656 mode. CCIR-656 requires that 4:2:2 data (8 bits per component) be multiplexed and transmitted over a single 8-bit physical interface. A 27 MHz clock is transmitted along with the data. This clock is synchronous with the data. The color space of CCIR-656 is YCrCb. When in master mode, the CCIR-656 mode does not require any external synchronization or blanking signals to accompany digital video. Instead, CCIR-656 includes special time codes in the stream syntax that define horizontal blanking periods, Table VIII. Component Digital Video Formats Nominal Bit/ Color Data Rate Master/ Format Name Component Space Sampling (MHz) Slave I/F Width Number CCIR-656 8 YCrCb 4:2:2 27 Master 8 0x0 Multiplex Philips 8 YUV 4:2:2 27 Either 8 0x2 vertical blanking periods, and field synchronization (horizontal and vertical synchronization information can be derived). These time codes are called End-of-Active-Video (EAV) and Start-of- Active-Video (SAV). Each line of video has one EAV and one SAV time code. EAV and SAV have three bits of embedded information to define HSYNC, VSYNC and Field information as well as error detection and correction bits. VCLK is driven with a 27 MHz, 50% duty cycle clock which is synchronous with the video data. Video data is clocked on the rising edge of the VCLK signal. When decoding, the VCLK signal is typically transmitted along with video data in the CCIR-656 physical interface. Electrically, CCIR-656 specifies differential ECL levels to be used for all interfaces. The ADV611/ADV612, however, only supports unipolar, TTL logic thresholds. Systems designs that interface to strictly conforming CCIR-656 devices (especially when interfacing over long cable distances) must include ECL level shifters and line drivers. The functionality of HSYNC, VSYNC and FIELD Pins is dependent on three programmable modes of the ADV611/ ADV612: Master-Slave Control, Encode-Decode Control and 525-625 Control. Table X summarizes the functionality of these pins in various modes.

–23–REV. 0 Video Formats—References For more information on video interface standards, see the following reference texts.

• For the definition of CCIR-601: 1992 – CCIR Recommendations RBT series Broadcasting Service (Television) Rec. 601-3 Encoding Parameters of digital television for studios, page 35, September 15, 1992.
• For the definition of CCIR-656: 1992 – CCIR Recommendations RBT series Broadcasting Service (Television) Rec. 656-1 Interfaces for digital component video signals in 525 and 626 line television systems operating at the 4:2:2 level of Rec. 601 , page 46, September 15, 1992. Host Interface The ADV611/ADV612 host interface is a high performance interface that passes all command and real-time compressed video data between the host and codec. A 512 position by 32-bit wide, bidirectional FIFO buffer passes compressed video data to and from the host. The host interface is capable of burst transfer rates of up to 132 million bytes per second (4 · 33 MHz). For host interface pins descriptions, see the Pin Function De- scriptions section. For host interface timing information, see the Host Interface Timing section. Video Formats — Multiplexed Philips Video The ADV611/ADV612 supports a hybrid mode of operation that is a cross between standard dual lane Philips and single lane CCIR-656. In this mode, video data is multiplexed in the same fashion in CCIR-656, but the values 0 and 255 are not reserved as signaling values. Instead, external HSYNC and VSYNC pins are used for signaling and video synchronization. VCLK may range up to 27 MHz. VCLK is driven with up to a 27 MHz 50% duty cycle clock synchronous with the video data. Video data is clocked on the rising edge of the VCLK signal. The functionality of HSYNC, VSYNC, and FIELD pins is dependent on three programmable modes of the ADV611/ADV612; Master-Slave Control, Encode- Decode Control, and 525-625 Control. Table IX summarizes the functionality of these pins in various modes. Table X. Philips Multiplexed Video Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality HSYNC, VSYNC and FIELD Functionality for Multiplexed Master Mode (HSYNC, VSYNC Slave Mode (HSYNC, VSYNC Philips and FIELD Are Outputs) and FIELD Are Inputs) Encode Mode (video data is input The ADV611/ADV612 completely manages the generation These pins are used to control the to the chip) and timingof these pins. The device driving the ADV611/ blanking of video and sequencing. ADV612 video interface must use these outputs to remain in sync with the ADV611/ADV612. It is expected that this combination of modes would not be used freque ntly. Decode Mode (video data is output The ADV611/ADV612 completely manages the generation These pins are used to control the from the chip) and timing of these pins. blanking of video and sequencing. DRAM Manager The DRAM Manager provides a sorting and reordering func- tion on the subband coded data between the Wavelet Kernel and the Programmable Quantizer. The DRAM manager pro- vides a pipeline delay stage to the ADV611/ADV612. This pipeline lets the ADV611/ADV612 extract current field image statistics (min/max pixel values, sum of pixel values, and sum of squares) used in the calculation of bin widths and reorder wavelet transform data. The use of current field statistics in the bin width calculation results in precise control over the com- pressed bit rate. The DRAM manager manages the entire opera- tion and refresh of the DRAM. The interface between the ADV611/ADV612 DRAM man- ager and D RAM is designed to be transparent to the user. The ADV611/ADV612 DRAM pins should be connected to the DRAM as called out in the Pin Function Descriptions section. The ADV611/ADV612 requires one 256K word by 16-bit, 60 ns DRAM. The following is a selected list of manufacturers and part numbers. All parts can be used with the ADV611/ ADV612 at all VCLK. Any DRAM used with the ADV611/ ADV612 must meet the minimum specifications outlined for the Hyper Mode DRAMs listed in Table XI. For DRAM Inter- face pins descriptions, see the Pin Function Descriptions. Table XI. Compatible DRAMs Manufacturer Part Number Notes Toshiba TC514265DJ/DZ/DFT-60 None NEC mPD424210ALE-60 None NEC mPD42S4210ALE-60 CBR Self-Refresh feature of this product is not needed by the ADV611/ADV612. Hitachi HM514265CJ-60 None

Figure 13. Hierarchical Structure of Wavelet Compressed Frame Data (Data Block Order) as a modified Mallat diagram.

–25–REV. 0 Table XII. Pseudo-Code Describing a Sequence of Video Fields Complete Sequence: <Field 1 Sequence> “Frame N; Field 1” <Field 2 Sequence> “Frame N; Field 2” <Field 1 Sequence> “Frame N+1; Field 1” <Field 2 Sequence> “Frame N+1; Field 2” (Field Sequences) <Field 1 Sequence> “Frame N+M; Field 1” <Field 2 Sequence> “Frame N+M; Field 2” #EOS “Required in decode to let the ADV611/ADV612 know the sequence of fields is complete.” Field 1 Sequence: #SOF1 <VITC> <First Block Sequence> <Complete Block Sequence> Field 2 Sequence: #SOF2 <VITC> <First Block Sequence> <Complete Block Sequence> First Block Sequence: <TYPE4> <BW> <Huff_Data> Complete Block Sequence: <Block Sequence> ... (Block Sequences) ... <Block Sequence> Block Sequence: #SOB1, #SOB2, #SOB3, #SOB4 or #SOB5 <BW> <Huff_Data>

32 Cr COMPONENT

Figure 14. Block Order of Wavelet Compressed Field Data (Modified Mallat Diagram)

–27–REV. 0 Table XIII. Pseudo Code of Compressed Video Data Bitstream for One Field of Video Block Sequence Data For Mallat Block Number . . . #SOFn<VITC><TYPE4><BW><Huff_Data> n indicates field 1 or 2 Huff_Data indicates Mallat block 6 data A typical Bin Width (BW) factor for this block is 0x1DDC #SOB4<BW><Huff_Data> Mallat block 9 data—Typical BW = 0x1DDC #SOB3<BW><Huff_Data> Mallat block 20 data—Typical BW = 0x0C2E #SOB3<BW><Huff_Data> Mallat block 22 data—Typical BW = 0x03A1 #SOB3<BW><Huff_Data> Mallat block 19 data—Typical BW = 0x0C2E #SOB3<BW><Huff_Data> Mallat block 23 data—Typical BW = 0x03A1 #SOB3<BW><Huff_Data> Mallat block 17 data—Typical BW = 0x0C2E #SOB3<BW><Huff_Data> Mallat block 25 data—Typical BW = 0x0306 #SOB3<BW><Huff_Data> Mallat block 16 data—Typical BW = 0x0C2E #SOB3<BW><Huff_Data> Mallat block 26 data—Typical BW = 0x0306 #SOB3<BW><Huff_Data> Mallat block 14 data—Typical BW = 0x0E9D #SOB3<BW><Huff_Data> Mallat block 28 data—Typical BW = 0x0306 #SOB3<BW><Huff_Data> Mallat block 13 data—Typical BW = 0x0E9D #SOB3<BW><Huff_Data> Mallat block 29 data—Typical BW = 0x0306 #SOB3<BW><Huff_Data> Mallat block 11 data—Typical BW = 0x2410 #SOB1<BW><Huff_Data> Mallat block 31 data—Typical BW = 0x0114 #SOB3<BW><Huff_Data> Mallat block 10 data—Typical BW = 0x2410 #SOB1<BW><Huff_Data> Mallat block 32 data—Typical BW = 0x0114 #SOB3<BW><Huff_Data> Mallat block 8 data—Typical BW = 0x2410 #SOB1<BW><Huff_Data> Mallat block 34 data—Typical BW = 0x00E5 #SOB3<BW><Huff_Data> Mallat block 7 data—Typical BW = 0x2410 #SOB1<BW><Huff_Data> Mallat block 35 data—Typical BW = 0x00E6 #SOB3<BW><Huff_Data> Mallat block 5 data—Typical BW = 0x2B46 #SOB1<BW><Huff_Data> Mallat block 37 data—Typical BW = 0x00E6 #SOB3<BW><Huff_Data> Mallat block 4 data—Typical BW = 0x2B46 #SOB1<BW><Huff_Data> Mallat block 38 data—Typical BW = 0x00E6 #SOB3<BW><Huff_Data> Mallat block 2 data—Typical BW = 0xC62B #SOB1<BW><Huff_Data> Mallat block 40 data—Typical BW = 0x009A #SOB3<BW><Huff_Data> Mallat block 1 data—Typical BW = 0xC62B #SOB1<BW><Huff_Data> Mallat block 41 data—Typical BW = 0x009A #SOB4<BW><Huff_Data> Mallat block 0 data—Typical BW = 0xA417 #SOB2<BW><Huff_Data> Mallat block 39 data—Typical BW = 0x007F #SOB4<BW><Huff_Data> Mallat block 12 data—Typical BW = 0x0C1A #SOB2<BW><Huff_Data> Mallat block 36 data—Typical BW = 0x00BE #SOB4<BW><Huff_Data> Mallat block 15 data—Typical BW = 0x0A16 #SOB2<BW><Huff_Data> Mallat block 33 data—Typical BW = 0x00BE #SOB4<BW><Huff_Data> Mallat block 18 data—Typical BW = 0x0A16 #SOB2<BW><Huff_Data> Mallat block 30 data—Typical BW = 0x00E4 #SOB2<BW><Huff_Data> Mallat block 21 data—Typical BW = 0x0301 #SOB2<BW><Huff_Data> Mallat block 27 data—Typical BW = 0x0281 #SOB2<BW><Huff_Data> Mallat block 24 data—Typical BW = 0x0281 #SOB4<BW><Huff_Data> Mallat block 3 data—Typical BW = 0x23D5 Table XIV specifies the Mallat block transfer order and associated Start of Block (SOB) codes. Any of these SOB codes can be replaced with an SOB#5 code for a zero data block. Table XIV. Pseudo Code of Compressed Video Data Bitstream for One Sequence of Video Fields Block Sequence Data For Mallat Block Number ... (41 #SOBn blocks) ... (41 #SOBn blocks) . (any number of Fields in sequence) #EOS /* Required in decode to end field sequence*/

–28– REV. 0 Table XV. ADV611/ADV612 Field and Block Delimiters (Codes) Code Name Code Description (Align all #Delimiter Codes to 32-Bit Boundaries) #SOF1 0xffffffff40000000Start of Field delimiter identifies Field1 data. #SOF1 resets the Huffman decoder and is sufficient on its own to reset the processing of the chip during decode. Please note that this code or #SOF2 are the only delimiters necessary between adjacent fields. #SOF1 operates identically to #SOF2 except that during decode it can be used to differentiate between Field1 and Field2 in the generation of the Field signal (master mode) and/or SAV/EAV codes for CCIR-656 modes. #SOF2 0xffffffff41000000Start of Field delimiter identifies Field2 data. #SOF resets the Huffman decoder and is sufficient on its own to reset the processing of the chip during decode. Please note that this code or #SOF1 are the only delimiters necessary between adjacent fields. #SOF2 operates identically to #SOF1 except that during decode it can be used to differentiate between Field2 and Field1 in the generation of the Field signal (master mode) and/or SAV/EAV codes for CCIR-656 modes. <VITC> (96 bits) This is a 12-byte string of data extracted by the video interface during encode operations and inserted by the video interface into the video data during decode operations. The data content is 90 bits in length. For a complete description of VITC format, see pages 175-178 of Video Demystified: A Handbook For The Digital Engineer (listed in References section). <TYPE1> 0x81 This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model

1 Chroma)

<TYPE2> 0x82 This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model

1 Luma)

<TYPE3> 0x83 This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model

2 Chroma)

<TYPE4> 0x84 This is an 8-bit delimiter-less type code for the first subband block of wavelet data. (Model

2 Luma)

#SOB1 0xffffffff81Start of Block delimiter identifies the start of Huffman coded subband data. This #SOB2 0xffffffff82delimiter will reset the Huffman decoder if a system ever experiences bit errors or gets #SOB3 0xffffffff83out of sync. The order of blocks in the frame is fixed and therefore implied in the bit #SOB4 0xffffffff84stream and no unique #SOB delimiters are needed per block. There are 41 #SOB #SOB5 0xffffffff8fdelimiters and associated BW and Huffman data within a field. #SOB1 is differenti ated from #SOB2, #SOB3 and #SOB4 in that they indicate which model and Huffman table was used in the Run Length Coder for the particular block: #SOB1 Model 1 Chroma #SOB2 Model 1 Luma #SOB3 Model 2 Chroma #SOB4 Model 2 Luma #SOB5 Zero data block. All data after this delimiter and before the next start of block delimiter is ignored (if present at all) and assumed zero including the BW value. <BW> (16 bits, 8.8)This data code is not entropy coded, is always 16 bits in length and defines the Bin Width Quantizer control used on all data in the block subband. During decode, this value is used by the Quantizer. If this value is set to zero during decode, all Huffman data is presumed to be zero and is ignored, but must be included. During encode, this value is calculated by the external Host and is inserted into the bitstream by the ADV611/ADV612 (this value is not used by the quantizer). Another value calculated by the Host, 1/BW is actually used by the Quantizer during encode. <HUFF_DATA>(Modulo 32) This data is the quantized and entropy coded block subband data. The data’s length is dependent on block size and entropy coding so it is therefore variable in length. This field is filled with 1s making it Modulo 32 bits in length. Any Huffman decode process can be interrupted and reset by any unexpectedly received # delimiter following a bit error or synchronization problem. #EOS 0xffffffffc0ffffffThe host sends the #EOS (End of Sequence) to the ADV611/ADV612 during decode after the last field in a sequence to indicate that the field sequence is complete. The ADV611/ ADV612 does not append this code to the end of encoded field sequences; it must be added by the host.

–29–REV. 0 Table XVI. Video Data Bitstream for One Field In a Video Sequence 1 ffff ffff 4000 0000 0000 0000 0000 0000 0000 0000 8400 00ff df0d 8effffff ffff 8400 00ff df0c daffffff ffff 8300 00ff 609f ffffffff ffff 8300 00fe c5af ffff ffff ffff 8300 00ff 609f ffffffff ffff 8300 00fe c5af ffffffff ffff 8300 00ff 609f ffffffff ffff 8300 00fe c70f ffffffff ffff 8300 00ff 609f ffffffff ffff 8300 00fe c70f ffffffff ffff 8300 00ff 609f ffffffff ffff 8300 00fe c78f ffff ffff ffff 8300 00ff 609f ffffffff ffff 8300 00fe c78f ffffffff ffff 8300 00ff 6894 3fffffff ffff 811d 40f0 90ff ffffffff ffff 8300 00ff 6894 3fffffff ffff 811d 40f0 90ff ffffffff ffff 8300 00ff 68aa bfffffff ffff 8116 80f0 9bff ffff ffff ffff 8300 00ff 68aa bfffffff ffff 8116 80f0 9bff ffffffff ffff 8300 00ff 6894 3fffffff ffff 8116 80f0 9fff ffffffff ffff 8300 00ff 6894 3fffffff ffff 8116 80f0 9fff ffffffff ffff 8300 00ff fe62 a2ffffff ffff 8103 e6e9 d74d 75d7 5d75 d75a f8f9 74eb d7af 5ebd 7af5 ebf0 f8f8 f979 7979 7979 7979 79fd 5f5f c7e3 f1f8 fc7e 3f1f 8fc7 e5fa ff6f d5f6 7d9f 67d9 f67d 9f67 d9f6 7edf abec f87c 3e1f 0f87 c3e1 f0f8 fd9f 1f1f 2f2f 2f2f 2f2f 2f2f 2f1f 2ebd 7af5 ebd7 ae9d 74e9 a56d 6b5a d6b5 a2b0 d249 24a5 ce36 db6d b6db 6db7 c6fd fd3d 3d3d 3d3d 3d3d 3d3b 7a7b fbfb fbfb fbfb fbfb fcfd bdfe dfb7 edfb 7eef bbee fbbe dfbb dbe7 f6fd ff7f dff7 fdff 7fdf f7fd feff 3fbb effb feff bfef fbfe ffbf efff ffffffff ffff 8300 00ff fe62 a2ffffff ffff 8103 e6fd bfab f9bf 57d5 f2eb 18f4 f9fd ffb7 f5ff 3feb fafc 7431 e9f4 fbff 77eb fd3f b3ec f2d5 efeb f6fe 1fbb f67e afdb f0f3 aaed edf7 fe3f 57ed fd7f bbe3 d2d3 dfe7 f87e 5f57 eefd 9fbb e5d6 2fdf e7f8 7eff abf7 7ecf ddf2 eb17 eff3 fc3f 7fd5 fbbf 67ee f975 8bf7 f9fe 1fbf eafd dfb3 f77c bac5 fbfc ff0f dff5 7eef d9fb be5d 62fd fe7f 87ef fabf 77ec fddf 2eb1 7eff 3fc3 f7fd 5fbb f67e ef97 58bf 7f9f e1fb feaf ddfb 3f77 cbac 5fbf cff0 fdff 57ee fd9f bbe5 d62f dfe7 f87e ffaf f77e cfab e5d6 2fe9 f3fc 7f7f d9f5 7edf abc7 431e 9f4f c7f8 7fff ffff ffff ffff 8400 00ff dfb7 c5ff df0d 7fffffff ffff 8202 9afc 3eff b7e9 ede9 e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 e9e9 dbef fbbe 9efe 9dbb 76ed dbb7 6edd bb76 eddb b76e ddb7 fbbe df9f af6d b6db 6db6 db6d b6db 6db6 db6d aff6 fd3d bbed 7bde f7bd ef7b def7 bdef 75f4 f7f4 dee9 2492 4924 924c fa7b 77da 6991 f4f7 efb4 d323 e9ed df69 a647 d3db bed3 4c8f a7b7 7da6 991f 4f7e fb4d 323e 9edd f69a 647d 3dbb ed34 c8fa 7b77 da69 647c fd7b 6100 0000 0045 bdfd 37bb 8888 8888 8888 8888 8aff ffff ffff ffff 8400 00ff c9a7 1fffffff ffff 820f 00ff 7704 4fffffff ffff 8400 00ff c9a7 1fffffff ffff 820f 00ff 7704 bfffffff ffff 8400 00ff c9a7 1fffffff ffff 8213 80ff 7703 5fffffff ffff 8200 00ff 7743 1fffffff ffff 8200 00ff 7743 1fff ffff ffff 8200 00ff 7745 efffffff ffff 8400 00ff df0c daff NOTE 1This table shows ADV611/ADV612 compressed data for one field in a color ramp video sequence. The SOF# and SOB# codes in the dat a are in bold text. Bit Error Tolerance Bit error tolerance is ensured because a bit error within a Huffman coded stream does not cause #delimiter symbols to be misread by the ADV611/ADV612 in decode mode. The worst error that can occur is loss of a complete block of Huffman data. With the ADV611/ADV612, this type of error results only in some blurring of the decoded image, not complete loss of the image.

• Using the ADV611/ADV612 in computer applications
• Using the ADV611/ADV612 in stand-alone applications
• Configuring the host interface for 16- or 32-bit data paths
• Connecting the video interface to popular video encoders and decoders
• Getting the most out of the ADV611/ADV612 The following Analog Devices products should be considered in ADV611/ADV612 designs:
• ADV7175/ADV7176—Digital YUV to analog composite video encoder
• AD722—Analog RGB to analog composite video encoder
• AD1843—Audio codec with embedded video synchronization
• ADSP-21xx—Family of fixed-point digital signal processors
• AD8xxx—Family of video operational amplifiers Using the ADV611/ADV612 in Computer Applications Many key features of the ADV611/ADV612 were driven by the demanding cost and performance requirements of computer applications. The following ADV611/ADV612 features provide key advantages in computer applications, such as the one in Figure 15.
• Host Interface The 512 double word FIFO provides necessary buffering of compressed digital video to deal with PCI bus latency.
• Low Cost External DRAM Unlike many other real-time compression solutions, the ADV611/ADV612 does not require expensive external SRAM transform buffers or VRAM frame stores. D0–D7 D8–D15 D16–D23 D24–D31 A28 A29 A30 A31 HOST BUS RD WR DECODE 1 DECODE 2 VCLK VDATA [0–7] LLC XTAL SAA7111 27MHz PAL OR NTSC ADR0 ADR1 DQ0–DQ7 DQ8–DQ15 DQ16–DQ23 DQ24–DQ31 CS STATS R LCODE 24.576MHz XTAL A0–A8 D0–D15 A0–A8 DQ1–DQ16 NOTE: DECODE 1 ASSERTS CS ~ ON THE ADV611/ADV612 FOR HOST ADDRESSES 0X4000,0000 THROUGH 0X4000,0013 DECODE

2 IS HOST-SPECIFIC

Figure 15. A Suggested PC Application Design

–33–REV. 0 ADV611/ADV612 The ADV611/ADV612 Video Codec uses a Bi-Orthogonal (7, 9) Wavelet Transform. RECOMMENDED OPERATING CONDITIONS Parameter Description Min Max Unit VDD Supply Voltage 4.50 5.50 V TAMB Ambient Operating Temperature 0 +70 °C

ELECTRICAL CHARACTERISTICS

Parameter Description Test Conditions Min Max Unit VIH Hi-Level Input Voltage @ V DD = max 2.0 N/A V VIL Lo-Level Input Voltage @ V DD = min N/A 0.8 V VOH Hi-Level Output Voltage @ V DD = min, IOH = –0.5 mA 2.4 N/A V VOL Lo-Level Output Voltage @ V DD = min, IOL = 2 mA N/A 0.4 V IIH Hi-Level Input Current @ V DD = max, VIN = VDD max N/A 10 mA IIL Lo-Level Input Current @ V DD = max, VIN = 0 V N/A 10 mA IOZH Three-State Leakage Current @ V DD = max, VIN = VDD max N/A 10 mA IOZL Three-State Leakage Current @ V DD = max, VIN = 0 V N/A 10 mA CI Input Pin Capacitance @ V IN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C N/A 8* pF CO Output Pin Capacitance @ V IN = 2.5 V, fIN = 1.0 MHz, TAMB = +25°C N/A 8* pF *Guaranteed but not tested. ABSOLUTE MAXIMUM RATINGS* Parameter Description Min Max Unit VDD Supply Voltage –0.3 +7 V VIN Input Voltage N/A V DD – 0.3 V VOUT Output Voltage N/A V DD – 0.3 V TAMB (ADV611) Am bient Operating Temperature 0 +70 °C TAMB (ADV612) Am bient Operating Temperature –25 +85 °C TS Storage Temperature –65 +150 °C TL Lead Temperature (5 sec) PQFP N/A +280 °C *Stresses greater than those listed above under Absolute Maximum Ratings may cause permanent damage to the device. This is a st ress rating only; functional opera- tion of the device at these or any other conditions above those indicated in the Pin Definitions section of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. SUPPLY CURRENT AND POWER Parameter Description Test Conditions Min Max Unit IDD Supply Current (Dynamic) @ V DD = max, tVCLK_CYC = 37 ns (at 27 MHz VCLK) 0.11 0.27 A IDD Supply Current (Soft Reset) @ V DD = max, tVCLK_CYC = 37 ns (at 27 MHz VCLK) 0.08 0.17 A IDD Supply Current (Idle) @ V DD = max, tVCLK_CYC = None 0.01 0.02 A ENVIRONMENTAL CONDITIONS Parameter Description ADV611/ADV612 Max Unit qCA Case-to-Ambient Thermal Resistance 30 °C/W qJA Junction-to-Ambient Thermal Resistance 35 °C/W qJC Junction-to-Case Thermal Resistance 5 °C/W SPECIFICATIONS CAUTION The ADV611/ADV612 is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. Permanent damage may occur to devices subj ected to high energy electrostatic discharges. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. The ADV611/ADV612 latchup immunity has been demonstrated at ‡200 mA/–200 mA on all pins when tested to industry standard/JEDEC methods. WARNING! ESD SENSITIVE DEVICE

Figure 26. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLKO.

Figure 29. Multiplexed Philips Video–Line (Horizontal) and Frame (Vertical) Transfer Timing

Register Data and Interrupt Mask/Status registers, your system MUST observe ACK and RD or WR assertion timing. 1RD input must be asserted (low) until ACK is asserted (low). 2Maximum tDATA_D_RDD varies with VCLK according to the formula: t DATA_D_RDD (MAX) = 4 (VCLK Period) +16. 3During STATS_R deasserted (low) conditions, t DATA_D_RDD may be as long as 52 VCLK periods. 4Minimum tRD_D_WRT varies with VCLK according to the formula: t RD_D_WRT (MIN) = 1.5 (VCLK Period) –4.1. 5Maximum tACK_D_RDD varies with VCLK according to formula: t ACK_D_RDD (MAX) = 7 (VCLK Period) +14.8. 6During STATS_R deasserted (low) conditions, t ACK_D_RDD may be as long as 52 VCLK periods. Figure 32. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Read Transfer Timing

1WR input must be asserted (low) until ACK is asserted (low). 2Minimum tWR_D_RDT varies with VCLK according to the formula: t WR_D_RDT (MIN) = 0.8 (VCLK Period) +7.4. 3Maximum tWR_D_WRD varies with VCLK according to the formula: t ACK_D_WRD (MAX) = 4.3 (VCLK Period) +14.8. 4During STATS_R deasserted (low) conditions, t ACK_D_WRD may be as long as 52 VCLK periods. Figure 33. Host (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Write Transfer Timing

or WR signal assertion timing, your system does NOT have to wait for the ACK signal between new compressed data addresses. Figure 34. Host (Compressed Data) Read Transfer Timing

Figure 35. Host (Compressed Data) Write Transfer Timing

–44– REV. 0 Pin Pin Pin Name Type

81 VDATA4 I/O

82 GND GROUND

83 VDD POWER

84 VDATA3 I/O

85 VDATA2 I/O

86 VDATA1 I/O

87 VDATA0 I/O

88 NC* NC

89 NC* NC

90 GND GROUND

91 DATA31 I/O

92 DATA30 I/O

93 DATA29 I/O

94 DATA28 I/O

95 DATA27 I/O

96 DATA26 I/O

97 DATA25 I/O

98 DATA24 I/O

99 DATA23 I/O

100 DATA22 I/O

101 DATA21 I/O

102 DATA20 I/O

103 VDD POWER

104 DATA19 I/O

105 DATA18 I/O

106 DATA17 I/O

107 DATA16 I/O

108 GND GROUND

109 GND GROUND

110 DATA15 I/O

111 DATA14 I/O

112 DATA13 I/O

113 DATA12 I/O

114 DATA11 I/O

115 DATA10 I/O

116 DATA9 I/O

117 DATA8 I/O

118 DATA7 I/O

119 DATA6 I/O

120 DATA5 I/O

41 CAS O

42 WE O

43 VDD POWER

44 VDD POWER

45 DDAT15 I/O

46 DDAT14 I/O

47 DDAT13 I/O

48 DDAT12 I/O

49 DDAT11 I/O

50 DDAT10 I/O

51 DDAT9 I/O

52 DDAT8 I/O

53 DDAT7 I/O

54 DDAT6 I/O

55 DDAT5 I/O

56 DDAT4 I/O

57 DDAT3 I/O

58 DDAT2 I/O

59 DDAT1 I/O

60 DDAT0 I/O

61 GND GROUND

62 VDD POWER

63 GND GROUND

64 VDD POWER

65 STALL I

66 GND GROUND

67 ENC O

68 VCLKO O

69 VDD POWER

70 XTAL I

71 VCLK I

72 GND GROUND

73 FIELD I OR O

74 HSYNC I OR O

75 VSYNC I OR O

76 GND GROUND

77 VDD POWER

78 VDATA7 I/O

79 VDATA6 I/O

80 VDATA5 I/O

1 DATA4 I/O

2 DATA3 I/O

3 DATA2 I/O

4 DATA1 I/O

5 DATA0 I/O

6 VDD POWER

7 GND GROUND

8 RD I

9 WR I

10 CS I

11 ADR1 I

12 ADR0 I

13 GND GROUND

14 BE2–BE3 I

15 BE0–BE1 I

16 GND GROUND

17 RESET I

18 VDD POWER

19 ACK O

20 VDD POWER

21 GND GROUND

22 HIRQ O

23 LCODE O

24 FIFO_SRQ O

25 STATS_R O

26 VDD POWER

27 GND GROUND

28 GND GROUND

29 VDD POWER

30 DADR8 O

31 DADR7 O

32 DADR6 O

33 DADR5 O

34 DADR4 O

35 DADR3 O

36 DADR2 O

37 DADR1 O

38 DADR0 O

39 GND GROUND

40 RAS O

ADV611/ADV612 LQFP PINOUTS *Apply a 10 k W pull-down resistor to this pin.

–45–REV. 0 ADV611/ADV612 PIN CONFIGURATION PIN 1 IDENTIFIER TOP VIEW (Not to Scale) 112 113 114 115 116 117 118 119 120 111 103 110 109 108 107 106 104 102 101 100 105 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 GND GND DATA16 DATA17 DATA18 DATA19 VDD DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DADR7 DADR6 DADR5 DADR4 DADR3 DADR2 DADR1 DADR0 GND RAS CAS WE VDD VDD DDAT15 DDAT14 DDAT13 DDAT12 DDAT11 DDAT10 DDAT9 DDAT8 DDAT7 DDAT6 DDAT5 DDAT4 DDAT3 DDAT2 DDAT1 DDAT0 GND NC* NC* VDATA0 VDATA1 VDATA2 VDATA3 VDD GND VDATA4 VDATA5 VDATA6 VDATA7 VCLKO ENC GND STALL VDD GND VDD GND VDD GND VSYNC HSYNC FIELD GND VCLK XTAL VDD DATA4 DATA3 DATA2 DATA1 DATA0 VDD GND RD WR CS ADR1 ADR0 GND BE2–BE3 BE0–BE1 GND RESET VDD ACK VDD GND HIRQ LCODE FIFO SRQ STATS R VDD GND GND VDD DADR8 *APPLY A 10kV PULL DOWN RESISTOR TO THIS PIN ADV611/ADV612 LQFP

–46– REV. 0 120-Lead LQFP (ST-120) TOP VIEW (PINS DOWN) 120 91 0.457 (11.6) BSC SQ 0.638 (16.20) 0.630 (16.00) SQ 0.622 (15.80) 0.559 (14.20) 0.551 (14.00) SQ 0.543 (13.80) SEATING PLANE 0.063 (1.60) MAX COPLANARITY 0.003 (0.08) MAX 0.006 (0.15) 0.002 (0.05) 0.030 (0.75) 0.024 (0.60) 0.020 (0.50) 0.016 (0.40) BSC * 3.58 080.008 (0.20) 0.004 (0.09) 0.009 (0.23) 0.007 (0.18) 0.005 (0.13) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) * THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.07 mm LATERAL TO THE PINS TRUE POSITION. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED ORDERING GUIDE Part Number Ambient Temperature Range 1 Package Description Package Options 2 ADV611JST 0 °C to +70°C 120-Lead LQFP ST-120 ADV612BST3 –25°C to +85°C 120-Lead LQFP ST-120 NOTES 1J = Commercial temperature range (0 °C to +70°C). 2ST = Plastic Thin Quad Flatpack. 3B = Standard Industrial Temperature Range (–25 °C to +85°C). OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3399–3–1/99PRINTED IN U.S.A.