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750 MHz, 16 × 8
Data Sheet ADV3224/ADV3225 Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. O Tel: 781.329.4700 © 2010–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com
FEATURES
16 × 8 high speed, nonblocking switch array Pinout and functionally equivalent to the AD8110/AD8111 Drop-in compatible with the ADV3228/ADV3229 8 × 8 array Complete solution Buffered inputs Programmable high impedance outputs 8 output amplifiers, G = +1 (ADV3224), G = +2 (ADV3225) Drives 150 Ω loads Operates on ±5 V supplies Low power: 0.5 W Excellent ac performance −3 dB bandwidth 200 mV p-p: 1200 MHz (ADV3224), 900 MHz (ADV3225)
2 V p-p: 750 MHz (ADV3224), 850 MHz (ADV3225)
0.5 dB flatness (2 V p-p)
250 MHz (ADV3224), 235 MHz (ADV3225)
Slew rate: 2500 V/μs Serial or parallel programming of switch array 72-lead LFCSP (10 mm × 10 mm)
APPLICATIONS
Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications FUNCTIONAL BLOCK DIAGRAM ADV3224/ ADV3225 128 40-BIT SHIFT REGISTER WITH 4-BIT PARALLEL LOADING PARALLEL LATCH DECODE 8 × 5:16 DECODERS CLK DATAIN UPDATE CE RESET DATAOUT OUTPUTS INPUTS SER/PAR D0 D1 D2 D3 D4 SWITCH ENABLE/DISABLE MATRIX SET INDIVIDUAL OR RESET ALL OUTPUTS TO OFF OUTPUT BUFFER G = +1, G = +2 09317-001 F igure 1. GENERAL DESCRIPTION The ADV3224/ADV3225 are high speed 16 × 8 analog crosspoint switch matrices. They offer a −3 dB signal bandwidth of greater than 750 MHz and a high slew rate of greater than 2500 V/μs. The ADV3224/ADV3225 include eight independent output buffers that can be placed into a high impedance state for paralleling crosspoint outputs to prevent off channels from loading the output bus. The ADV3224 has a gain of +1 and the ADV3225 has a gain of +2, and they both operate on voltage supplies of ±5 V . Channel switching is performed via a serial digital control that can accommodate the daisy chaining of several devices or via a parallel control to allow updating of an individual output without reprogramming the entire array. The ADV3224/ADV3225 are available in the 72-lead LFCSP package over the extended industrial temperature range of −40°C to +85°C.
ADV3224/ADV3225 Data Sheet Rev. B | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
1/16—Rev. A to Rev. B Change to Maximum Potential Difference (DVCC − AVEE) 12/10—Rev. 0 to Rev. A 11/10—Revision 0: Initial Version
Data Sheet ADV3224/ADV3225 Rev. B | Page 3 of 24 SPECIFICATIONS VS = ±5 V , TA = 25°C, RL = 150 Ω, unless otherwise noted. Table 1. ADV3224 ADV3225 Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth 200 mV p-p 1200 900 MHz
2 V p-p 750 850 MHz
Gain Flatness 0.1 dB, 2 V p-p 55 50 MHz 0.5 dB, 2 V p-p 250 235 MHz Propagation Delay 2 V p-p 0.6 0.6 ns Settling Time 1%, 2 V step 3 3 ns Slew Rate 2 V step, peak 2500 2500 V/μs NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL 0.01 0.02 % Differential Phase Error NTSC or PAL 0.01 0.02 Degrees Crosstalk, All Hostile, RTO f = 100 MHz −45 −45 dB f = 5 MHz −87 −70 dB Off Isolation, Input to Output f = 100 MHz, one channel −80 −87 dB OIP2 f = 100 MHz, RL = 100 Ω 38 dBm f = 500 MHz, RL = 100 Ω 15 dBm OIP3 f = 100 MHz, RL = 100 Ω 32 dBm f = 500 MHz, RL = 100 Ω 7 dBm Output 1 dB Compression Point f = 100 MHz, R L = 100 Ω 19 dBm f = 500 MHz, RL = 100 Ω 10 dBm Input Voltage Noise Density 50 MHz 18 18 nV/√Hz DC PERFORMANCE Gain Error 0.1 0.5 0.2 1.5 % Gain Matching Channel-to-channel 0.5 1.5 % Gain Temperature Coefficient 0.5 5 ppm/°C OUTPUT CHARACTERISTICS Output Resistance DC, enabled 0.2 0.2 Ω DC, disabled 15 8 MΩ Output Disabled Capacitance 2.2 2.6 pF Output Leakage Current Output disabled 0.5 0.5 μA Output Voltage Range No load ±3 ±3 V R L = 150 Ω ±2.8 ±2.8 V Short-Circuit Current 55 55 mA INPUT CHARACTERISTICS Input Offset Voltage Worst case (all configurations) ±5 ±5 mV Input Offset Voltage Drift 5 5 μV/°C Input Voltage Range ±3 ±1.5 V Input Capacitance Any switch configuration 1.8 1.8 pF Input Resistance 2 2 MΩ Input Bias Current Any switch configuration ±1 ±1 μA SWITCHING CHARACTERISTICS Enable/Disable Time 50% UPDATE to 1% settling 20 20 ns Switching Time, 2 V Step 50% UPDATE to 1% settling 20 20 ns Switching Transient (Glitch) 25 50 mV p-p
ADV3224/ADV3225 Data Sheet Rev. B | Page 4 of 24 ADV3224 ADV3225 Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit POWER SUPPLIES Supply Current AVCC, outputs enabled, no load 52 70 58 70 mA AVCC, outputs disabled 12 18 13 18 mA AVEE, outputs enabled, no load 52 70 58 70 mA AVEE, outputs disabled 12 18 14 18 mA DVCC, outputs enabled, no load 6 6 mA Supply Voltage Range ±4.5 ±5 ±5.5 ±4.5 ±5 ±5.5 V PSRR DC to 50 kHz, AVCC, AVEE <−60 <−60 dB f = 100 kHz, AVCC, AVEE −60 −60 dB f = 10 MHz, AVCC −48 −35 dB f = 10 MHz, AVEE −35 −55 dB f = 100 MHz, AVCC −25 −15 dB f = 100 MHz, AVEE −15 −15 dB f = 100 kHz, DVCC −90 −90 dB OPERATING TEMPERATURE RANGE Temperature Range Operating (still air) −40 +85 −40 +85 °C θJA Operating (still air) 29 29 °C/W
Figure 2. Timing Diagram, Serial Mode Table 3. Logic Levels
Figure 3. Timing Diagram, Parallel Mode
soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance tions over the −40°C to +85°C ambient temperature range. current dropped on the die output transistors. Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature
- EXPOSED PADDLE. THE EXPOSED METAL PADDLE ON THE BOTTOM OF
Figure 5. Pin Configuration Table 7. Pin Function Descriptions AVCC Analog Positive Supply. AVEE Analog Negative Supply. 17, 56, 72 AGND Analog Ground. 37, 55 DVCC Digital Positive Supply. 39 D4 Parallel Data Input, Output Enable. 40 to 43 D3 to D0 Parallel Data Input. 44 to 46 A2 to A0 Parallel Output Address Input.
Data Sheet ADV3224/ADV3225 Rev. B | Page 9 of 24 Pin No. Mnemonic Description 47 SER/PAR Serial/Parallel Mode Select (Control Pin). 48 UPDATE Second Rank Write Strobe (Control Pin). 49 DATAIN Serial Data In (Control Pin). 50 CLK Serial Data Clock, Parallel First Rank Latch Enable (Control Pin). 51 DATAOUT Serial Data Out. 52 CE Chip Enable (Control Pin). 53 RESET Second Rank Reset (Control Pin). 57 IN0 Input Number 0. 59 IN1 Input Number 1. 61 IN2 Input Number 2. 63 IN3 Input Number 3. 65 IN4 Input Number 4. 67 IN5 Input Number 5. 69 IN6 Input Number 6. 71 IN7 Input Number 7. EPAD Exposed Paddle. The exposed metal paddle on the bottom of the LFCSP package must be soldered to the PCB AGND for proper heat dissipation and for noise and mechanical strength benefits.
Table 8. Operation Truth Table1 1 X X X X X X No change in logic.
0 X DataI2 DataI-80 X 0 The data on the serial DATAIN line is loaded into the serial
DATAOUT 40 clock cycles later.
0 X 0 D0…D4 Not applicable in
the 40-bit serial shift register location addressed at A0 to A2. latches that control the switch array. Latches are transparent. rank latches are cleared. Remainder of logic is unchanged. 3 DATAOUT remains active in parallel mode and always reflects the state of the MSB of the serial shift register.
3 TO 8 DECODER
Figure 6. Logic Diagram
Data Sheet ADV3224/ADV3225 Rev. B | Page 21 of 24 THEORY OF OPERATION The ADV3224 (G = +1) and ADV3225 (G = +2) are crosspoint arrays with eight outputs, each of which can be connected to any one of 16 inputs. Organized by output row, 16 switchable input transconductance stages are connected to each output buffer to form 16-to-1 multiplexers. There are eight of these multiplexers, each with its inputs wired in parallel, for a total array of 128 transconductance stages forming a multicast-capable crosspoint switch. Each input is buffered and is not loaded by the outputs, simplifying the construction of larger arrays using the ADV3224 or ADV3225 as a building block. Decoding logic for each output selects one (or none) of the transconductance stages to drive the output stage. The enabled transconductance stage drives the output stage, and feedback forms a closed-loop amplifier. A mask programmable feedback network sets the closed-loop signal gain. For the ADV3224, this gain is +1, and for the ADV3225, this gain is +2. The output stage of the ADV3224 or ADV3225 is designed for low differential gain and phase error when driving composite video signals. It also provides slew current for a fast pulse response when driving component video signals. Unlike many multiplexer designs, these requirements are balanced such that large signal bandwidth is very similar to small signal bandwidth. The design load is 150 Ω, but provisions are made to drive loads as low as 100 Ω when on-chip power dissipation limits are not exceeded. The outputs of the ADV3224/ADV3225 can be disabled to mini- mize on-chip power dissipation. When disabled, there is no feedback network loading the output. This high disabled output impedance allows multiple ICs to be bussed together without additional buffering. Take care to reduce output capacitance, which results in more overshoot and frequency domain peaking. A series of internal amplifiers drives internal nodes such that a wideband high impedance is presented at the disabled output, even while the output bus is under large signal swings. To keep these internal amplifiers in their linear range of operation when the outputs are disabled and driven externally, do not allow the voltage applied to them to exceed the valid output swing range for the ADV3224/ADV3225. If the disabled outputs are left floating, they may exhibit high enable glitches. If necessary, the disabled output can be kept from drifting out of range by applying an output load resistor to ground. The connection of the ADV3224/ADV3225 is controlled by a flexible TTL-compatible logic interface. Either parallel or serial loading into a first rank of latches preprograms each output. A global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. In serial mode, a serial output pin allows devices to be daisy-chained together for single pin programming of multiple ICs. A power- on reset pin is available to avoid bus conflicts by disabling all outputs. This power-on reset clears the second rank of latches but does not clear the first rank of latches. In serial mode, pre- programming individual inputs is not possible and the entire shift register must be flushed. To easily interface to ground referenced video signals, the ADV3224/ADV3225 operate on split ±5 V supplies. The logic inputs and output run on a single 5 V supply, and the logic inputs switch at approximately 1.6 V for compatibility with a variety of logic families. The serial output buffer is a rail-to- rail output stage with 5 mA of drive capability.
ADV3224/ADV3225 Data Sheet Rev. B | Page 22 of 24 APPLICATIONS INFORMATION The ADV3224/ADV3225 have two options for changing the programming of the crosspoint matrix. In the first option, a serial word of 40 bits can be provided, which updates the entire matrix each time the 40-bit word is shifted into the device. The second option allows for changing the programming of a single output via a parallel interface. The serial option requires fewer signals but more time (clock cycles) for changing the program- ming, whereas the parallel programming technique requires more signals but can change a single output at a time and requires fewer clock cycles to complete the programming. SERIAL PROGRAMMING The serial programming mode uses the CE, CLK, DATAIN, UPDATE, and SER/PAR pins. The first step is to assert a low on SER/PAR to enable the serial programming mode. CE must be low to allow data to be clocked into the device. The CE signal can be used to address an individual device when devices are connected in parallel. The UPDATE signal should be high during the time that data is shifted into the serial port of the device. Although the data still shifts in when UPDATE is low, the transparent, asynchronous latches allow the shifting data to reach the matrix, which causes the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATAIN is clocked in at every falling edge of CLK, and a total of 40 bits must be shifted in to complete the program- ming. For each of the eight outputs, there are four bits (D0 to D3) that determine the source of its input. The MSB is shifted in first. A fifth bit (D4) precedes the four input select bits and determines the enabled state of the output. If D4 is low (output disabled), the four associated bits (D0 to D3) do not matter because no input switches to that output. The most significant output address data is shifted in first, and the remaining addresses follow in sequence until the least signifi- cant output address data is shifted in. At this point, UPDATE can be taken low, which programs the device according to the data that was just shifted in. The update registers are asynchronous, and when UPDATE is low (and CE is low), they are transparent. If more than one ADV3224/ADV3225 device is to be serially programmed in a system, the DATAOUT signal from one device can be connected to the DATAIN of the next device to form a serial chain. Connect all of the CLK, CE, UPDATE, and SER/PAR pins in parallel and operate them as described previously in this section. The serial data is input to the DATAIN pin of the first device of the chain, and it ripples through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence (40 bits) is multiplied by the number of devices in the chain. PARALLEL PROGRAMMING When using the parallel programming mode, it is not necessary to reprogram the entire device when making changes to the matrix. Parallel programming allows the modification of a single output at a time. Because this takes only one CLK/UPDATE cycle, signifi- cant time savings can be realized by using parallel programming. An important consideration in using parallel programming is that the RESET signal does not reset all registers in the ADV3224/ ADV3225. When taken low, the RESET signal sets each output to the disabled state. This is helpful during power-up to ensure that two parallel outputs are not active at the same time. After initial power-up, the internal registers in the device generally contain random data, even though the RESET signal was asserted. If parallel programming is used to program one output, that output is properly programmed, but the rest of the device has a random program state depending on the internal register content at power-up. Therefore, when using parallel programming, it is essential that all outputs be programmed to a desired state after power-up to ensure that the programming matrix is always in a known state. From this point, parallel pro- gramming can be used to modify either a single output or multiple outputs at one time. Similarly, if both CE and UPDATE are taken low after initial power-up, the random power-up data in the shift register is programmed into the matrix. Therefore, to prevent programming the crosspoint into an unknown state, do not apply low logic levels to both CE and UPDATE after power is initially applied. To eliminate the possibility of programming the matrix to an unknown state, after initial power-up, program the full shift register one time to a desired state using either serial or parallel programming. To change the programming of an output via parallel program- ming, take the SER/PAR and UPDATE pins high, and take the CE pin low. The CLK signal should be in the high state. Place the 3-bit address of the output to be programmed on A0 to A2. The first four data bits (D0 to D3) contain the information that identifies the input that is programmed to the addressed output. The fifth data bit (D4) determines the enabled state of the out- put. If D4 is low (output disabled), the data on D0 to D3 does not matter. After the address and data signals are established, they can be latched into the shift register by pulling the CLK signal low; however, the matrix is not programmed until the UPDATE signal is taken low. In this way, it is possible to latch in new data for several or all of the outputs first via successive negative transi- tions of CLK while UPDATE is held high and then have all the new data take effect when UPDATE goes low. Use this technique when programming the device for the first time after power-up when using parallel programming. In parallel mode, the CLK pin is level sensitive, whereas in serial mode, it is edge triggered.
low, the RESET pin causes all outputs to be in the disabled state. each time; therefore, no special considerations apply. allowing full programming capability of the device. have very high impedance when their outputs are disabled. when paralleling additional outputs of other crosspoint devices. creating crosspoint arrays of dimensions larger than 16 × 8. +1 and gain of +2 options, are useful for creating larger arrays. determine the minimum number of devices that is required. compared to using multiples of these smaller 4 × 1 devices. when designing the overall system. Figure 65. A 32 × 16 Nonblocking Crosspoint Switch Array being enabled at the same time.
0.20 REF
0.80 MAX
0.05 MAX
0.02 NOM
8.50 REF
0.25 MIN
Figure 66. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] registered trademarks are the property of their respective owners.