ADV3222ARZ-R7

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800 MHz, 4:1 Analog Multiplexer

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

−3 dB bandwidth

800 MHz (200 mV p-p)

750 MHz (2 V p-p)

Slew rate: 2400 V/μs Low power: 75 mW, VS = ±5 V Excellent video performance 100 MHz, 0.1 dB gain flatness 0.02% differential gain error/0.02° differential phase error L = 150 Ω) ADV3221 is a pin-for-pin upgrade to the HA4344 Gain = +1 (ADV3221) or gain = +2 (ADV3222) Low all hostile crosstalk of −85 dB @ 5 MHz, and −58 dB @ 100 MHz Latched control lines for synchronous switching High impedance output disable allows connection of multiple devices without loading the output bus 16-lead SOIC

APPLICATIONS

Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications FUNCTIONAL BLOCK DIAGRAM DQ LATCH DQ LATCH DQ LATCH DQ LATCH DQ LATCH DQ LATCH DECODE 100kΩ 100kΩ CK1 CK2 CS IN0 IN1 IN2 IN3 G = +1 (G = +2) OUT ENABLE 08652-001 Figure 1. GENERAL DESCRIPTION The ADV3221 and ADV3222 are high speed, high slew rate, buffered 4:1 analog multiplexers. They offer a −3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With lower than −58 dB of crosstalk and −67 dB isolation (at 100 MHz), the ADV3221 and ADV3222 are useful in many high speed applications. The diffe- rential gain error of less than 0.02% and differential phase error of less than 0.02°, together with 0.1 dB gain flatness out to 100 MHz while driving a 75 Ω back terminated load, make the ADV3221 and ADV3222 ideal for all types of signal switching. The ADV3221/ADV3222 include an output buffer that can be placed into a high impedance state. This allows multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3221 has a gain of +1, and the ADV3222 has a gain of +2; they both operate on ±5 V supplies while consuming less than 7.5 mA of idle current. The channel switching is performed via latched control lines, allowing synchronous updating in a multiple ADV3221/ADV3222 envi- ronment. The ADV3221/ADV3222 are offered in a 16-lead SOIC package and are available over the extended industrial temperature range of −40°C to +85°C.

Rev. 0 | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

3/10—Revision 0: Initial Version

Rev. 0 | Page 3 of 20 SPECIFICATIONS VS = ±5 V , TA = 25°C, RL = 150 Ω, CL = 2 pF, ADV3221 at G = +1, ADV3222 at G = +2, unless otherwise noted. Table 1. ADV3221 ADV3222 Parameter Test Conditions/Comments Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth 200 mV p-p 1000 800 MHz

2 V p-p 750 750 MHz

Gain Flatness 0.1 dB, 200 mV p-p 100 100 MHz 0.1 dB, 2 V p-p 100 100 MHz Propagation Delay 2 V p-p 700 650 ps Settling Time 1%, 2 V step 5 5 ns Slew Rate 2 V step, peak 2400 2700 V/μs NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL 0.01 0.02 % Differential Phase Error NTSC or PAL 0.01 0.02 Degrees Crosstalk, All Hostile f = 100 MHz −87 −58 dB f = 5 MHz −100 −85 dB Off Isolation, Input to Output f = 100 MHz, one channel −67 −72 dB Input Second-Order Intercept (ADV3222 Only) f = 70 MHz, RL = 100 Ω 54 dBm Input Third-Order Intercept (ADV3222 Only) f = 70 MHz, RL = 100 Ω 17 dBm Output 1 dB Compression Point (ADV3222 Only) f = 70 MHz, RL = 100 Ω 18.5 dBm Input Voltage Noise 10 MHz to 100 MHz 16 17 nV/√Hz DC PERFORMANCE Gain Error No load 1 1 % R L = 150 Ω 0.75 0.75 % Gain Matching Channel-to-channel, no load 1 1 % OUTPUT CHARACTERISTICS Output Impedance DC, enabled 0.02 0.04 Ω Disabled 1 1 MΩ Output Disable Capacitance Disabled 2.8 3 pF Output Leakage Current Disabled 2 2 μA Output Voltage Range No load ±2.9 ±3 ±2.9 ±3 V R L = 150 Ω ±2.8 ±3 ±2.75 ±3 V Short-Circuit Current 50 50 mA INPUT CHARACTERISTICS Input Offset Voltage Worst case (all configurations) ±5 ±21 ±5 ±21 mV Input Offset Voltage Drift ±10 ±10 μV/°C Input Voltage Range ±3 ±1.5 V Input Capacitance Any switch configuration 1.8 1.8 pF Input Resistance Output enabled 1 10 1 10 MΩ Input Bias Current Output enabled 5 12 6 12 μA SWITCHING CHARACTERISTICS Enable On Time 15 15 ns Switching Time, 2 V Step 50% A0 to 1% settling 20 20 ns Switching Transient (Glitch) IN0 to IN1 switching 28 55 mV p-p

Table 3. Logic Levels

ADV3222 junction-to-ambient thermal impedance (θJA) is 81°C/W . do include the load current through the die output transistors. soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature

Figure 5. Pin Configuration Table 6. Pin Function Descriptions

1 IN0 Analog Input

2 GND Ground

3 IN1 Analog Input

4 GND Ground

5 IN2 Analog Input

6 GND Ground

7 IN3 Analog Input

8 GND Ground

9 V− Negative Power Supply

10 CK1 First Rank Clock

11 CK2 Second Rank Clock

12 OUT Analog Output

13 CS Chip Select (Output Enable)

14 A1 Select Address Most Significant Bit

15 A0 Select Address Least Significant Bit

16 V+ Positive Power Supply

Table 7. Truth Table

1 X 1 X 1 0 0 High-Z

ADV3222 ideal for constructing larger arrays. to realize gain-of-two operation (see Figure 60). Figure 60. Conceptual Diagram of ADV3222 system to create larger switching arrays. the level of the CK1 and CK2 signals, and it is not edge triggered.

Rev. 0 | Page 18 of 20 APPLICATIONS INFORMATION The ADV3221 and ADV3222 are high speed multiplexers used to switch video or RF signals. The low output impedance of the ADV3221/ADV3222 allows the output environment to be optimized for use in 75 Ω or 50 Ω systems by choosing the appropriate series termination resistor. For composite video applications, the ADV3222 (gain of +2) is typically used to provide compensation for the loss of the output termination. CK1/CK2 OPERATION The ADV3221/ADV3222 provide a double latched architecture for the A0, A1 (channel selection) and CS (output enable) logic. This allows for simultaneous update of multiple devices in bank switching applications or large multiplexer systems consisting of multiple devices connected to common output busses. Holding CK1 and CK2 low places the ADV3221/ADV3222 in a transparent mode. In transparent mode, all logic changes to A0, A1, and CS immediately affects the input selection and output enable/disable. CIRCUIT LAYOUT Use of proper high speed design techniques is important to ensure optimum performance. Use a low inductance ground plane for power supply bypassing and to provide high quality return paths for the input and output signals. For best performance, it is recommended that power supplies be bypassed with 0.1 μF ceramic capacitors as close to the body of the device as possible. To provide stored energy for lower frequency, high current output driving, place 10 μF tantalum capacitors farther from the device. The input and output signal paths should be stripline or micro- strip controlled impedance. Video systems typically use 75 Ω characteristic impedance, whereas RF systems typically use 50 Ω. Various calculators are available to calculate the trace geometry required to produce the proper characteristic impedance. TERMINATION For a controlled impedance situation, termination resistors are required at the inputs and output of the device. The input termination should be a shunt resistor to ground with a value matching the characteristic impedance of the input trace. To reduce reflections, place the input termination resistor as close to the device input pin as possible. To minimize the input-to- input crosstalk, it is important to utilize a low inductance shield between input traces to isolate each input. Consideration of ground current paths must be taken to minimize loop currents in the shields to prevent them from providing a coupling medium for crosstalk. For proper matching, the output series termination resistor should be the same value as the characteristic impedance of the output trace and placed as close to the output of the device as possible. This placement reduces the high frequency effect of series parasitic inductance, which can affect gain flatness and −3 dB bandwidth. CAPACITIVE LOAD A high frequency output can have difficulties when driving a large capacitive load, usually resulting in peaking in the frequency domain or overshoot in the time domain. If these effects become too large, oscillation can result. The response of the device under various capacitive loads is shown in Figure 6 through Figure 12, and in Figure 15. If a condition arises where excessive load capacitance is encoun- tered and the overshoot is too great or the device oscillates, a small series resistor of a few tens of ohms can be used to improve the performance.

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 61. 16-Lead Standard Small Outline Package [SOIC_N]

Rev. 0 | Page 20 of 20 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D08652-0-3/10(0)