ADV3219ACPZ-RL

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800 MHz, 2:1 Analog Multiplexers

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

−3 dB bandwidth

800 MHz (200 mV p-p)

730 MHz (2 V p-p)

Slew rate: 2800 V/μs Low power: 75 mW, VS = ±5 V Excellent video performance >100 MHz, 0.1 dB gain flatness 0.02% differential gain/0.02° differential phase error L = 150 Ω) Gain = +1 (ADV3219) or gain = +2 (ADV3220) Low crosstalk of −82 dB @ 5 MHz and −60 dB @ 100 MHz High impedance output disable allows connection of multiple devices without loading the output bus 8-lead LFCSP

APPLICATIONS

Routing of high speed signals including Video (NTSC, PAL, S, SECAM, YUV, and RGB) Compressed video (MPEG, wavelet) 3-level digital video (HDB3) Data communications Telecommunications FUNCTIONAL BLOCK DIAGRAM ADV3219 (ADV3220) 3IN1 4V+ 1IN0 2GND 6O U T 5V –

8 SELEC T

G = +1 (G = +2) 08649-001 Figure 1. GENERAL DESCRIPTION The ADV3219 and ADV3220 are high speed, high slew rate, buffered, 2:1 analog multiplexers. They offer a −3 dB signal bandwidth greater than 800 MHz and channel switch times of less than 20 ns with 1% settling. With −60 dB of crosstalk and −82 dB isolation (at 100 MHz), the ADV3219 and ADV3220 are useful in many high speed applications. The differential gain of less than 0.02% and the differential phase of less than 0.02°, together with 0.1 dB flatness beyond 100 MHz while driving a 75 Ω back terminated load, make the ADV3219 and ADV3220 ideal for all types of signal switching. The ADV3219/ADV3220 include an output buffer that can be placed into a high impedance state to allow multiple outputs to be connected together for cascading stages without the off channels loading the output bus. The ADV3219 has a gain of +1, and the ADV3220 has a gain of +2; they both operate on ±5 V supplies while consuming less than 7.5 mA of idle current. The ADV3219/ADV3220 are available in the 8-lead LFCSP package over the extended industrial temperature range of −40°C to +85°C.

Rev. 0 | Page 2 of 20 TABLE OF CONTENTS

REVISION HISTORY

4/10—Revision 0: Initial Version

Rev. 0 | Page 3 of 20 SPECIFICATIONS VS = ±5 V , TA = 25°C, RL = 150 Ω, CL = 4 pF, ADV3219 at G = +1, ADV3220 at G = +2, unless otherwise noted. Table 1. ADV3219 ADV3220 Parameter Conditions Min Typ Max Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth 200 mV p-p 840 800 MHz

2 V p-p 600 730 MHz

Gain Flatness 0.1 dB, 200 mV p-p 100 100 MHz 0.1 dB, 2 V p-p 100 100 MHz Propagation Delay 2 V p-p 700 650 ps Settling Time 1%, 2 V step 5 5 ns Slew Rate 2 V step, peak 2200 2800 V/μs NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL 0.02 0.02 % Differential Phase Error NTSC or PAL 0.02 0.02 Degrees Crosstalk f = 100 MHz −70 −60 dB f = 5 MHz −90 −82 dB Off Isolation, Input-Output f = 100 MHz, one channel −83 −82 dB Input Second-Order Intercept f = 70 MHz, ADV3220, RL = 100 Ω 47 dBm Input Third-Order Intercept f = 70 MHz, ADV3220, RL = 100 Ω 34 dBm Output 1 dB Compression Point f = 70 MHz, ADV3220, RL = 100 Ω 20 dBm Input Voltage Noise 10 MHz to 100 MHz 16 17 nV/√Hz DC PERFORMANCE Gain Error No load 1 1 % R L = 150 Ω 0.75 1.1 0.75 1.1 % Gain Matching Channel-to-channel, no load 1 1 % OUTPUT CHARACTERISTICS Output Impedance DC, enabled 0.02 0.04 Ω Disabled 1 1 MΩ Output Disable Capacitance Disabled 1.0 1.2 pF Output Leakage Current Disabled 2 2 μA Output Voltage Range No load 2.9 ±3 2.9 ±3 V Load 2.8 ±3 2.75 ±3 V Short-circuit current 50 50 mA INPUT CHARACTERISTICS Input Offset Voltage Worst case (all configurations) ±5 21 ±5 21 mV Input Offset Voltage Drift ±10 ±10 μV/°C Input Voltage Range No load ±3 ±1.5 V R L = 150 Ω ±3 ±1.5 V Input Capacitance Any switch configuration 0.6 0.6 pF Input Resistance Output enabled 1 10 1 10 MΩ Input Bias Current Output enabled 5 12 6 12 μA SWITCHING CHARACTERISTICS Enable On Time 15 15 ns Switching Time, 2 V Step 50% SELECT to 1% settling 20 20 ns Switching Transient (Glitch) IN0 to IN1 switching 70 100 mV p-p

Table 2. Logic Levels

load current through the die output transistors. soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Figure 2. Maximum Die Power Dissipation vs. Ambient Temperature

6 OUT

8 SELECT

Figure 3. Pin Configuration Table 5. Pin Function Descriptions 7 EN Output Enable (Low True). 8 SELECT Logic Input for Analog Input Selection. N/A1 EP Exposed Pad. Connect the exposed pad to ground. Table 6. Truth Table

Figure 10. ADV3219 Large Signal Pulse Response vs. Capacitive Load,

2 V p-p Output

Figure 11. ADV3219 Large Signal Rising Slew Rate with 4 pF Load, Figure 12. ADV3219 Large Signal Falling Slew Rate with 4 pF Load, Figure 13. ADV3220 Large Signal Pulse Response vs. Capacitive Load, Figure 14. ADV3220 Large Signal Rising Slew Rate with 4 pF Load, Figure 15. ADV3220 Large Signal Falling Slew Rate with 4 pF Load,

the ADV3219 and ADV3220 ideal for constructing larger arrays. for the ADV3220 is taken from the exposed pad of the package. to a low inductance, quiet ground plane. Figure 56. Conceptual Diagram of ADV3220 in a system to create larger switching arrays. of the two inputs depending on the state of the SELECT pin. impedance disabled mode via the EN logic input.

Rev. 0 | Page 17 of 20 APPLICATIONS INFORMATION The ADV3219 and ADV3220 are very high speed muxes that can be used to switch video or RF signals. The low output imped- ance of the ADV3219/ADV3220 allows the output environment to be optimized for use in 75 Ω or 50 Ω systems by choosing the appropriate series termination resistor. For composite video applications, the ADV3220 (gain of +2) is typically used to provide compensation for the loss of the output termination. CIRCUIT LAYOUT Use of proper high speed design techniques is important to ensure optimum performance. Use a low inductance ground plane for power supply bypassing and to provide high quality return paths for the input and output signals. For best performance, it is recommended that power supplies be bypassed with 0.1 μF ceramic capacitors placed as close to the body of the device as possible. To provide stored energy for lower frequency, high current output driving, place 10 μF tantalum capacitors farther from the device. The input and output signal paths should be stripline or micro- strip controlled impedance. Video systems typically use a 75 Ω characteristic impedance, whereas RF systems typically use 50 Ω. Various calculators are available to calculate the trace geometry that is required to produce the proper characteristic impedance. TERMINATION For a controlled impedance situation, termination resistors are required at the inputs and output of the device. The input ter- mination should be a shunt resistor to ground with a value matching the characteristic impedance of the input trace. To reduce reflections, place the input termination resistor as close to the device input pin as possible. To minimize the input-to- input crosstalk, it is important to use a low inductance shield between input traces to isolate each input. Consideration of ground current paths must be taken to minimize loop currents in the shields to prevent them from providing a coupling medium for crosstalk. For proper matching, the output series termination resistor should be the same value as the characteristic impedance of the output trace and placed as close to the output of the device as possible. This placement reduces the high frequency effect of series parasitic inductance, which can affect gain flatness and −3 dB bandwidth. CAPACITIVE LOAD A high frequency output generally has difficulty when driving a capacitive load. The usual response is some peaking in the fre- quency domain or some overshoot in the time domain. If these effects become too large, oscillation can result. The response of the device under various capacitive loads is shown in Figure 4 to Figure 10 and in Figure 13. If a condition arises wherein excessive load capacitance is encountered and the overshoot is too great or the part oscillates, use a small series resistor of a few tens of ohms to improve the performance.

0.203 REF

0.05 MAX

0.02 NOM

0.50 BSC

Figure 57. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

Rev. 0 | Page 19 of 20 NOTES

Rev. 0 | Page 20 of 20 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D08649-0-4/10(0)