ADV3200 AD | Alldatasheet
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Technical content
300 MHz, 32 × 32 Buffered
Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved.
FEATURES
Large, 32 × 32, nonblocking switch array G = +1 (ADV3200) or G = +2 (ADV3201) operation Pin-compatible 32 × 16 versions available (ADV3202/ADV3203) Single 5 V supply, dual ±2.5 V supply, or dual ±3.3 V supply (G = +2) Serial programming of switch array 2:1 OSD insertion mux per output Input sync-tip clamp High impedance output disable allows connection of multiple devices with minimal output bus load Excellent video performance 60 MHz, 0.1 dB gain flatness 0.1% differential gain error (R L = 150 Ω) 0.1° differential phase error (RL = 150 Ω) Excellent ac performance Bandwidth: >300 MHz Slew rate: >400 V/μs Low power: 1.25 W Low all hostile crosstalk of −48 dB @ 5 MHz Reset pin allows disabling of all outputs Connected through a capacitor to ground, provides power-on reset capability 176-lead exposed pad LQFP (24 mm × 24 mm)
APPLICATIONS
Routing of high speed signals including Composite video (NTSC, PAL, S, SECAM) RGB and component video routing Compressed video (MPEG, Wavelet) Video conferencing FUNCTIONAL BLOCK DIAGRAM DGNDDVCCVNEGVPOS DATA OUT ENABLE/ DISABLE 193-BIT SHIFT REGISTER PARALLEL LATCH 32 × 5:32 DECODERS ADV3200 (ADV3201) OUTPUT BUFFER G = +1 (G = +2) ENABLE/ BYPASS 193 192 1024 SYNC-TIP CLAMP SWITCH MATRIX OSD MUX OUTPUTS INPUTS 3232 REFERENCE CLK DATA IN VCLAMP VREFOSD INPUTS OSD SWITCHES 07176-001 UPDATE CS RESET Figure 1. GENERAL DESCRIPTION The ADV3200/ADV3201 are 32 × 32 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input for ac-coupled applications and an on-screen display (OSD) insertion mux. With −48 dB of crosstalk and −80 dB isolation at 5 MHz, the ADV3200/ADV3201 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3200/ADV3201 ideal for composite video switching. The 32 independent output buffers of the ADV3200/ADV3201 can be placed into a high impedance state for paralleling cross- point outputs so that off channels present minimal loading to an output bus if building a larger array. The part is available in a gain of +1 (ADV3200) or +2 (ADV3201) for ease of use in back-terminated load applications. A single 5 V supply, dual ±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used while consuming only 250 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control, which can accommodate daisy chaining of several devices. The ADV3200/ADV3201 are packaged in a 176-lead exposed pad LQFP (24 mm × 24 mm) and are available over the extended industrial temperature range of −40°C to +85°C.
Rev. 0 | Page 2 of 36 TABLE OF CONTENTS
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 3 of 36 SPECIFICATIONS OSD DISABLED VS = ±2.5 V (ADV3200), VS = ±3.3 V (ADV3201) at TA = 25°C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 Ω, all configurations, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE −3 dB Bandwidth 200 mV p-p 300 MHz
2 V p-p 120 MHz
Gain Flatness 0.1 dB, 200 mV p-p 60 MHz 0.1 dB, 2 V p-p 40 MHz Settling Time 1%, 2 V step 6 ns Slew Rate 2 V step, peak 400 V/μs NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL ADV3200 0.06 % ADV3201 0.1 % Differential Phase Error NTSC or PAL ADV3200 0.06 Degrees ADV3201 0.03 Degrees Crosstalk, All Hostile, RTI f = 5 MHz, RL = 150 Ω −48 dB f = 5 MHz, RL = 1 kΩ −65 dB f = 100 MHz, RL = 150 Ω −23 dB f = 100 MHz, RL = 1 kΩ −30 dB Off Isolation, Input-to-Output, RTI f = 5 MHz, one channel −80 dB Input Voltage Noise 0.1 MHz to 50 MHz ADV3200 25 nV/√Hz ADV3201 22 nV/√Hz DC PERFORMANCE Gain Error ADV3200 No load (broadcast mode) ±0.5 ±1.75 % Broadcast mode ±0.5 ±2.2 % ADV3201 No load (broadcast mode) ±0.5 ±2.2 % Broadcast mode ±0.5 ±2.7 % Gain Matching No load, channel-to-channel ±0.5 ±2.8 % Channel-to-channel ±0.8 ±3.4 % OUTPUT CHARACTERISTICS Output Impedance DC, enabled 0.15 Ω ADV3200 DC, disabled 900 1000 kΩ ADV3201 DC, disabled 3.2 4 kΩ Output Capacitance Disabled 3.7 pF Output Voltage Range ADV3200 −1.1 to +1.1 −1.2 to +1.2 V ADV3201 −1.5 to +1.5 −1.6 to +2.0 V No output load −1.5 to +1.5 −2.0 to +2.0 V INPUT CHARACTERISTICS Input Offset Voltage ±5 ±30 mV Input Voltage Range ADV3200 −1.1 to +1.1 −1.2 to +1.2 V ADV3201 −0.75 to +0.75 −0.8 to +1.0 V No output load −0.75 to +0.75 −1.0 to +1.0 V
Rev. 0 | Page 4 of 36 Parameter Test Conditions/Comments Min Typ Max Unit Input Capacitance 3 pF Input Resistance 1 4 MΩ Input Bias Current Sync-tip clamp enabled, VIN = VCLAMP + 0.1 V 0.1 3 12 μA Sync-tip clamp enabled, VIN = VCLAMP − 0.1 V −2.9 −1 −0.25 mA Sync-tip clamp disabled −10 −3 μA SWITCHING CHARACTERISTICS Enable On Time 50% update to 1% settling 50 ns Switching Time, 2 V Step 50% update to 1% settling 40 ns Switching Transient (Glitch) IN00 to IN31, RTI 300 mV p-p POWER SUPPLIES Supply Current ADV3200 VPOS or VNEG, outputs enabled, no load 250 300 mA VPOS or VNEG, outputs disabled 120 155 mA ADV3201 VPOS or VNEG, outputs enabled, no load 260 310 mA VPOS or VNEG, outputs disabled 130 165 mA DVCC 2.5 3.5 mA Supply Voltage Range VPOS − VNEG 5 ± 10% to 6.6 ± 10% V PSR VNEG, VPOS, f = 1 MHz ADV3200 −50 dB ADV3201 −45 dB OPERATING TEMPERATURE RANGE Temperature Range Operating (still air) −40 to +85 °C θJA Operating (still air) 16 °C/W OSD ENABLED VS = ±2.5 V (ADV3200), VS = ±3.3 V (ADV3201) at TA = 25°C, G = +1 (ADV3200), G = +2 (ADV3201), RL = 150 Ω, all configurations, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min Typ Max Unit OSD DYNAMIC PERFORMANCE −3 dB Bandwidth ADV3200 200 mV p-p 170 MHz
2 V p-p 135 MHz
ADV3201 200 mV p-p 150 MHz
2 V p-p 130 MHz
Gain Flatness 0.1 dB, 200 mV p-p 35 MHz 0.1 dB, 2 V p-p 35 MHz Settling Time 1%, 2 V step 6 ns Slew Rate 2 V step, peak 400 V/μs OSD NOISE/DISTORTION PERFORMANCE Differential Gain Error NTSC or PAL ADV3200 0.12 % ADV3201 0.35 % Differential Phase Error NTSC or PAL ADV3200 0.06 Degrees ADV3201 0.04 Degrees Input Voltage Noise 0.5 MHz to 50 MHz ADV3200 27 nV/√Hz ADV3201 25 nV/√Hz
Figure 2. Timing Diagram, Serial Mode
Figure 3. Programming Example Table 4. Logic Levels, DVCC = 3.3 V
based on ambient temperature. Figure 4. Maximum Die Power Dissipation vs. Ambient Temperature Table 6. Thermal Resistance
90 OSD19
91 OSD18
92 OSD17
93 OSD16
94 VPOS
95 IN31
96 OSDS31
97 IN30
98 OSDS30
99 IN29
100 OSDS29
101 IN28
102 OSDS28
103 IN27
104 OSDS27
105 IN26
106 OSDS26
107 IN25
108 OSDS25
109 IN24
110 OSDS24
111 IN23
112 OSDS23
113 IN22
114 OSDS22
115 IN21
116 OSDS21
117 IN20
118 OSDS20
119 IN19
120 OSDS19
121 IN18
122 OSDS18
123 IN17
124 OSDS17
125 IN16
126 OSDS16
127 OSD15
128 OSD14
129 OSD13
130 OSD12
131 OSD11
132 VNEG
133 OSD10
134 OSD09
135 OSD08
136 VPOS
137 OUT15
138 VNEG
139 OUT14
140 VPOS
141 OUT13
142 VNEG
143 OUT12
144 VPOS
145 OUT11
146 VNEG
147 OUT10
148 VPOS
149 OUT09
150 VNEG
151 OUT08
152 VPOS
153 OUT07
154 VNEG
155 OUT06
156 VPOS
157 OUT05
158 VNEG
159 OUT04
160 VPOS
161 OUT03
162 VNEG
163 OUT02
164 VPOS
165 OUT01
166 VNEG
167 OUT00
168 VPOS
169 OSD07
170 OSD06
171 OSD05
172 OSD04
173 OSD03
174 OSD02
175 OSD01
176 DGND45OSD30
- OSDSxx: OSD SELECT FOR OUTxx
- THE EXPOSED PAD SHOULD BE
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions 1 DVCC Digital Positive Power Supply. 3 RESET Control Pin: First and Second Rank Reset. 4 CLK Control Pin: Serial Data Clock. 5 DATA IN Control Pin: Serial Data In. 6 DATA OUT Control Pin: Serial Data Out. 7 UPDATE Control Pin: Second Rank Write Strobe. 8 CS Control Pin: Chip Select. 9 OSDS15 Control Pin: OSD Select Number 15. 11 OSDS14 Control Pin: OSD Select Number 14. 13 OSDS13 Control Pin: OSD Select Number 13. 15 OSDS12 Control Pin: OSD Select Number 12. 17 OSDS11 Control Pin: OSD Select Number 11. 19 OSDS10 Control Pin: OSD Select Number 10. 21 OSDS09 Control Pin: OSD Select Number 9. 23 OSDS08 Control Pin: OSD Select Number 8. 25 OSDS07 Control Pin: OSD Select Number 7. 27 OSDS06 Control Pin: OSD Select Number 6. 29 OSDS05 Control Pin: OSD Select Number 5. 31 OSDS04 Control Pin: OSD Select Number 4. 33 OSDS03 Control Pin: OSD Select Number 3. 35 OSDS02 Control Pin: OSD Select Number 2. 37 OSDS01 Control Pin: OSD Select Number 1. 39 OSDS00 Control Pin: OSD Select Number 0. 41 VNEG Analog Negative Power Supply. Operation section for details. Theory of Operation section for details. 44 OSD31 OSD Input Number 31. 45 OSD30 OSD Input Number 30. 46 OSD29 OSD Input Number 29. 47 OSD28 OSD Input Number 28. 48 OSD27 OSD Input Number 27. 49 OSD26 OSD Input Number 26. 50 OSD25 OSD Input Number 25. 51 OSD24 OSD Input Number 24. 52 VPOS Analog Positive Power Supply. 54 VNEG Analog Negative Power Supply. 56 VPOS Analog Positive Power Supply. 58 VNEG Analog Negative Power Supply. 60 VPOS Analog Positive Power Supply. 62 VNEG Analog Negative Power Supply. 64 VPOS Analog Positive Power Supply. 66 VNEG Analog Negative Power Supply. 68 VPOS Analog Positive Power Supply. 70 VNEG Analog Negative Power Supply. 72 VPOS Analog Positive Power Supply. 74 VNEG Analog Negative Power Supply. 76 VPOS Analog Positive Power Supply. 78 VNEG Analog Negative Power Supply. 80 VPOS Analog Positive Power Supply. 82 VNEG Analog Negative Power Supply. 84 VPOS Analog Positive Power Supply. 85 OSD23 OSD Input Number 23. 86 OSD22 OSD Input Number 22. 87 OSD21 OSD Input Number 21. 88 OSD20 OSD Input Number 20. 89 VNEG Analog Negative Power Supply. 90 OSD19 OSD Input Number 19. 91 OSD18 OSD Input Number 18. 92 OSD17 OSD Input Number 17. 93 OSD16 OSD Input Number 16. 94 VPOS Analog Positive Power Supply. 96 OSDS31 Control Pin: OSD Select Number 31. 98 OSDS30 Control Pin: OSD Select Number 30. 100 OSDS29 Control Pin: OSD Select Number 29.
Rev. 0 | Page 10 of 36 Pin Mnemonic Description 101 IN28 Input Number 28. 102 OSDS28 Control Pin: OSD Select Number 28. 103 IN27 Input Number 27. 104 OSDS27 Control Pin: OSD Select Number 27. 105 IN26 Input Number 26. 106 OSDS26 Control Pin: OSD Select Number 26. 107 IN25 Input Number 25. 108 OSDS25 Control Pin: OSD Select Number 25. 109 IN24 Input Number 24. 110 OSDS24 Control Pin: OSD Select Number 24. 111 IN23 Input Number 23. 112 OSDS23 Control Pin: OSD Select Number 23. 113 IN22 Input Number 22. 114 OSDS22 Control Pin: OSD Select Number 22. 115 IN21 Input Number 21. 116 OSDS21 Control Pin: OSD Select Number 21. 117 IN20 Input Number 20. 118 OSDS20 Control Pin: OSD Select Number 20. 119 IN19 Input Number 19. 120 OSDS19 Control Pin: OSD Select Number 19. 121 IN18 Input Number 18. 122 OSDS18 Control Pin: OSD Select Number 18. 123 IN17 Input Number 17. 124 OSDS17 Control Pin: OSD Select Number 17. 125 IN16 Input Number 16. 126 OSDS16 Control Pin: OSD Select Number 16. 127 OSD15 OSD Input Number 15. 128 OSD14 OSD Input Number 14. 129 OSD13 OSD Input Number 13. 130 OSD12 OSD Input Number 12. 131 OSD11 OSD Input Number 11. 132 VNEG Analog Negative Power Supply. 133 OSD10 OSD Input Number 10. 134 OSD09 OSD Input Number 9. 135 OSD08 OSD Input Number 8. 136 VPOS Analog Positive Power Supply. 137 OUT15 Output Number 15. 138 VNEG Analog Negative Power Supply. 139 OUT14 Output Number 14. Pin Mnemonic Description 140 VPOS Analog Positive Power Supply. 141 OUT13 Output Number 13. 142 VNEG Analog Negative Power Supply. 143 OUT12 Output Number 12. 144 VPOS Analog Positive Power Supply. 145 OUT11 Output Number 11. 146 VNEG Analog Negative Power Supply. 147 OUT10 Output Number 10. 148 VPOS Analog Positive Power Supply. 149 OUT09 Output Number 9. 150 VNEG Analog Negative Power Supply. 151 OUT08 Output Number 8. 152 VPOS Analog Positive Power Supply. 153 OUT07 Output Number 7. 154 VNEG Analog Negative Power Supply. 155 OUT06 Output Number 6. 156 VPOS Analog Positive Power Supply. 157 OUT05 Output Number 5. 158 VNEG Analog Negative Power Supply. 159 OUT04 Output Number 4. 160 VPOS Analog Positive Power Supply. 161 OUT03 Output Number 3. 162 VNEG Analog Negative Power Supply. 163 OUT02 Output Number 2. 164 VPOS Analog Positive Power Supply. 165 OUT01 Output Number 1. 166 VNEG Analog Negative Power Supply. 167 OUT00 Output Number 0. 168 VPOS Analog Positive Power Supply. 169 OSD07 OSD Input Number 7. 170 OSD06 OSD Input Number 6. 171 OSD05 OSD Input Number 5. 172 OSD04 OSD Input Number 4. 173 OSD03 OSD Input Number 3. 174 OSD02 OSD Input Number 2. 175 OSD01 OSD Input Number 1. 176 DGND Digital Negative Power Supply. Exposed Pad Connect to analog ground.
Table 8. Operation Truth Table register is reset to all 0s. DATA OUT 193 clock cycles later. 1 X X X X 1 Chip is not selected. No change in logic. Figure 6. Logic Diagram
Figure 17. ADV3200 Small Signal Frequency Response, 200 mV p-p Figure 18. ADV3200 Large Signal Frequency Response, 2 V p-p Figure 19. ADV3200 Small Signal Frequency Response with Capacitive Loads, Figure 20. ADV3200 Large Signal Frequency Response with Capacitive Loads,
2 V p-p
Figure 21. ADV3200 OSD Small Signal Frequency Response Figure 22. ADV3200 OSD Large Signal Frequency Response with Capacitive
Figure 56. ADV3201 Small Signal Frequency Response, 200 mV p-p Figure 57. ADV3201 Large Signal Frequency Response, 2 V p-p Figure 58. ADV3201 Small Signal Frequency Response with Capacitive Loads, Figure 59. ADV3201 Large Signal Frequency Response with Capacitive Loads, Figure 60. ADV3201 OSD Small Signal Frequency Response Figure 61. ADV3201 OSD Large Signal Frequency Response with Capacitive
low impedance source to avoid crosstalk. Figure 98. Conceptual Diagram of Sync-Tip Clamp in an when driving component video signals. to be bussed together without additional buffering. Maximum Ratings section for guidelines). both the first and second rank of latches. video signals, split supply operation is possible with ±2.5 V . while the core remains on split supplies.
sync-tip clamps each time the part is programmed. itself to every intermediate state defined by the shifted-in data. The data at DATA IN is clocked in at every rising edge of CLK. matter because no input is switched to that output. disabled; otherwise, they are enabled. asynchronous and, when UPDATE is low, they are transparent. is 193 bits multiplied by the number of devices in the chain. RESET pin, when taken low, causes all outputs to be disabled. can be taken low to program the device. ming capability of the device. pin has a 25 kΩ pull-down resistor to DGND. operating from low supply voltages or from a single 5 V supply. Figure 99. Pathological Case for Input Dynamic Range
corresponding OSD mux (high = OSD, low = regular input). low switches the signal at INxx to the corresponding output. characters, or text, can be inserted to be displayed at the output. over the range of expected applied swing and load conditions. Figure 104. Maximum Die Power Dissipation vs. Ambient Temperature and supply conditions must not be allowed to exceed 6.5 W . by the load current over one period. where IOUTPUT,QUIESCENT = 0.95 mA for each single-ended output pin. VPOS and VNEG drops by approximately 4 mA.
Figure 105. Simplified Output Stage
- Calculate the power dissipation of the ADV3200 using data
- Calculate the power dissipation from the loads.
There are 32 outputs, therefore, 32 output currents.
- Subtract the quiescent output stage current for the number
counted only once (valid for output voltages > 0.5 V). There are 32 outputs, therefore, 32 output currents.
- Verify that the power dissipation does not exceed the
atures up to and including 85°C. section explains these effects. an unwanted crosstalk signal in any channel that receives it. two areas when attempting to minimize the effect of crosstalk.
Rev. 0 | Page 33 of 36 Measuring Crosstalk Crosstalk is measured by applying a signal to one or more channels and measuring the relative strength of that signal on a desired selected channel. The measurement is usually expressed as decibels below the magnitude of the test signal. The crosstalk is expressed by ) ( ) (log 2010 s A s AXT TEST SEL (4) where: s = jω (Laplace transform variable). ASEL(s) is the amplitude of the crosstalk induced signal in the selected channel. A TEST(s) is the amplitude of the test signal. It can be seen that crosstalk is a function of frequency but not a function of the magnitude of the test signal (to first order). In addition, the crosstalk signal has a phase relative to the test signal associated with it. A network analyzer is most commonly used to measure cross- talk over a frequency range of interest. It can provide both magnitude and phase information about the crosstalk signal. As a crosspoint system or device grows larger, the number of theoretical crosstalk combinations and permutations can become extremely large. For example, in the case of the 32 × 32 matrix of the ADV3200/ADV3201, note the number of crosstalk terms that can be considered for a single channel, for example, the IN00 input. IN00 is programmed to connect to one of the ADV3200/ ADV3201 outputs where the measurement can be made. First, the crosstalk terms associated with driving a test signal into each of the other 31 inputs can be measured one at a time, while applying no signal to IN00. Then the crosstalk terms associated with driving a parallel test signal into all 31 other inputs can be measured two at a time in all possible combina- tions, then three at a time, and so on until, finally, there is only one way to drive a test signal into all 31 other inputs in parallel. Each of these cases is legitimately different from the others and may yield a unique value, depending on the resolution of the measurement system, but it is hardly practical to measure all these terms and then specify them. In addition, this describes the crosstalk matrix for just one input channel. A similar cross- talk matrix can be proposed for every other input. In addition, if the possible combinations and permutations for connecting inputs to the other outputs (not used for measurement) are taken into consideration, the numbers quickly grow to astro- nomical proportions. If a larger crosspoint array of multiple ADV3200/ADV3201 devices is constructed, the numbers grow larger still. Obviously, some subset of all these cases must be selected as a guide for a practical measurement of crosstalk. One common method is to measure all hostile crosstalk; this means that the crosstalk to the selected channel is measured while all other system channels are driven in parallel. In general, this yields the worst crosstalk number, but this is not always the case due to the vector nature of the crosstalk signal. Other useful crosstalk measurements are those created by one nearest neighbor or by the two nearest neighbors on either side. These crosstalk measurements are generally higher than those of more distant channels; therefore, they can serve as a worst- case measure for any other one-channel or two-channel crosstalk measurements. Input and Output Crosstalk Capacitive coupling is voltage-driven (dV/dt) but is generally a constant ratio. Capacitive crosstalk is proportional to input or output voltage, but this ratio is not reduced by simply reducing signal swings. Attenuation factors must be changed by changing impedances (lowering mutual capacitance), or destructive canceling must be utilized by summing equal and out of phase components. For high input impedance devices such as the ADV3200/ADV3201, capacitances generally dominate input- generated crosstalk. Inductive coupling is proportional to current (dI/dt) and often scales as a constant ratio with signal voltage, but it also shows a dependence on impedances (load current). Inductive coupling can also be reduced by constructive canceling of equal and out of phase fields. In the case of driving low impedance video loads, output inductances contribute highly to output crosstalk. The flexible programming capability of the ADV3200/ADV3201 can be used to diagnose whether crosstalk is occurring more on the input side or the output side. Some examples are illustrative. A given input pair (IN07 in the middle for this example) can be programmed to drive OUT07 (also in the middle). The inputs to IN07 are terminated to ground (via 50 Ω or 75 Ω resistors) and no signal is applied. All the other inputs are driven in parallel with the same test signal (practically provided by a distribution amplifier), with all other outputs except OUT07 disabled. Because the grounded IN07 input is programmed to drive OUT07, no signal should be present. Any signal that is present can be attributed to the other 15 hostile input signals because no other outputs are driven (they are all disabled). Thus, this method measures all the hostile input contribution to crosstalk into IN07. Of course, this method can be used for other input channels and combinations of hostile inputs. For output crosstalk measurement, a single input channel is driven (IN00, for example) and all outputs other than a given output (IN07 in the middle) are programmed to connect to IN00. OUT07 is programmed to connect to IN15 (far away from IN00), which is terminated to ground. Thus OUT07 should not have a signal present because it is listening to a quiet input. Any signal measured at OUT07 can be attributed to the output crosstalk of the other 15 hostile outputs. Again, this method can be modified to measure other channels and other crosspoint matrix combinations.
Rev. 0 | Page 34 of 36 Effect of Impedances on Crosstalk Input side crosstalk can be influenced by the output impedance of the sources that drive the inputs. The lower the impedance of the drive source, the lower the magnitude of the crosstalk. The dominant crosstalk mechanism on the input side is capacitive coupling. The high impedance inputs do not have significant current flow to create magnetically induced crosstalk. However, significant current can flow through the input termination resistors and the loops that drive them. Thus, the PCB on the input side can contribute to magnetically coupled crosstalk. From a circuit standpoint, the input crosstalk mechanism looks like a capacitor coupling to a resistive load. For low frequencies, the magnitude of the crosstalk is given by [ s C RXT MS ×= ) ( log 2010 ] (5) where: RS is the source resistance. CM is the mutual capacitance between the test signal circuit and the selected circuit. s is the Laplace transform variable. From the preceding equation, it can be observed that this crosstalk mechanism has a high-pass nature; it can also be minimized by reducing the coupling capacitance of the input circuits and lowering the output impedance of the drivers. If the input is driven from a 75 Ω terminated cable, the input crosstalk can be reduced by buffering this signal with a low output impedance buffer. On the output side, the crosstalk can be reduced by driving a lighter load. Although the ADV3200/ADV3201 are specified with excellent differential gain and phase when driving a standard 150 Ω video load, the crosstalk will be higher than the minimum obtainable due to the high output currents. These currents induce crosstalk via the mutual inductance of the output pins and bond wires of the ADV3200/ADV3201. From a circuit standpoint, the output crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by L XY R sMXT 10log 20 (6) where: MXY is the mutual inductance of Output X to Output Y . RL is the load resistance on the measured output. s is the Laplace transform variable. This crosstalk mechanism can be minimized by keeping the mutual inductance low and increasing R L. The mutual inductance can be kept low by increasing the spacing of the conductors and minimizing their parallel length. PCB Layout Extreme care must be exercised to minimize additional crosstalk generated by system circuit boards. The areas that must be carefully detailed are grounding, shielding, signal routing, and supply bypassing. The input and output signals have minimum crosstalk if they are located between ground planes on layers above and below and are separated by ground in between. Locate vias as close to the IC as possible to carry the inputs and outputs to the inner layer. The input and output signals surface at the input termin- ation resistors and the output series back-termination resistors. To the extent possible, separate these signals as soon as they emerge from the IC package. PCB TERMINATION LAYOUT As frequencies of operation increase, proper routing of trans- mission line signals becomes more important. The bandwidth of the ADV3200/ADV3201 is large enough so that using high impedance routing does not provide a flat in-band frequency response for practical signal trace lengths. It is necessary for the user to choose a characteristic impedance suitable for the application and to properly terminate the input and output signals of the ADV3200/ADV3201. Traditionally, video applications use 75 Ω single-ended environments. For flexibility, the ADV3200/ADV3201 does not contain on- chip termination resistors. This flexibility in application comes with some board layout challenges. The distance between the termination of the input transmission line and the ADV3200/ ADV3201 die is a high impedance stub and causes reflections of the input signal. With some simplification, it can be shown that these reflections cause peaking of the input at regular intervals in frequency, dependent on the propagation speed (v of the signal in the chosen board material and the distance (d) between the termination resistor and the ADV3200/ADV3201. If the distance is great enough, these peaks can occur in band. In fact, practical experience shows that these peaks are not high-Q, and should be pushed out to three or four times the desired bandwidth in order to not have an effect on the signal. For a board designer using FR4 (v P = 144 × 106 m/s), this means that the ADV3200/ADV3201 input should be placed no farther than 2 cm after the termination resistors and, preferably, should be placed even closer. Therefore, 2 cm PCB routing equates to d = 2 × 10 −2 m in the calculations. ( ) d v nf P PEAK 1 2×+= (7) In some cases, it is difficult to place the termination close to the ADV3200/ADV3201 due to space constraints and large resistor footprints. A better solution in this case is to maintain a controlled transmission line past the ADV3200/ADV3201 inputs and to terminate the end of the line. This method is known as fly-by termination. The input impedance of the ADV3200/ADV3201 is large enough, and the stub length inside the package is small enough, that this works well in practice.
1.60 MAX
1.00 REF
21.50 REF
Figure 108. 176-Lead Low Profile Quad Flat Package [LQFP_EP] registered trademarks are the prop erty of their respective owners.