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Rev. A | Page 2 of 16 TABLE OF CONTENTS
REVISION HISTORY
6/2017—Rev. 0 to Rev. A 2/2008—Revision 0: Initial Version
Rev. A | Page 3 of 16 SPECIFICATIONS TA = 27°C, AVCC = 3.3 V , VTTI = 3.3 V , VTTO = 3.3 V , AVEE = 0 V , differential input swing = 1000 mV , pattern = PRBS 27 − 1, data rate = 2.25 Gbps, TMDS outputs terminated with external 50 Ω resistors to 3.3 V , unless otherwise noted. Table 1. Parameter Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel NRZ 2.25 Gbps Bit Error Rate (BER) PRBS 223 − 1 10 −9 Added Deterministic Jitter DR ≤ 2.25 Gbps, PRBS 27 − 1 25 ps (p-p) Added Random Jitter 1 ps (rms) Differential Intrapair Skew At output 1 ps Differential Interpair Skew1 At output 50 ps EQUALIZATION PERFORMANCE Receiver (Fixed Setting)2 Boost frequency = 1.125 GHz 12 dB Transmitter (Pre-Emphasis On)3 Boost frequency = 1.125 GHz 6 dB INPUT CHARACTERISTICS Input Voltage Swing Differential 150 1200 mV Input Common-Mode Voltage (VICM) AVCC − 800 AVCC mV OUTPUT CHARACTERISTICS4 High Voltage Level Single-ended high speed channel AVCC − 200 AVCC + 10 mV Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV Rise/Fall Time (20% to 80%) 75 178 ps TERMINATION Input Termination Resistance Single-ended 50 Ω Output Termination Resistance Single-ended 50 Ω POWER SUPPLY AVCC Operating range (3.3 V ± 10%) 3 3.3 3.6 V QUIESCENT CURRENT AVCC Output disabled 20 40 mA Output enabled, pre-emphasis off 32 50 mA Output enabled, pre-emphasis on 66 80 mA VTTI Input termination on5 40 54 mA VTTO Output termination on, pre-emphasis off 40 50 mA Output termination on, pre-emphasis on 80 100 mA Output disabled 0 1 mA POWER DISSIPATION6 Output disabled 66 148 mW Output enabled, pre-emphasis off 370 553 mW Output enabled, pre-emphasis on 686 937 mW PARALLEL CONTROL INTERFACE TX_EN, PE_EN Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V 1 Differential interpair skew is measured between the TMDS pairs of the HDMI/DVI link. 2 ADV3003 output meets the transmitter eye diagram mask as defined in the HDMI Standard Version 1.3a and the DVI Standard Version 1.0. 3 Cable output meets the receiver eye diagram mask as defined in the HDMI Standard Version 1.3a and the DVI Standard Version 1.0. 4 PE = 0 dB. 5 Typical value assumes the HDMI/DVI link is active with nominal signal swings. Minimum and maximum limits are measured at the extremes of input termination resistance and input voltage swing, respectively. 6 The total power dissipation excludes power dissipated in the 50 Ω off-chip loads.
Rev. A | Page 4 of 16 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Rating AVCC to AVEE 3.7 V VTTI AVCC + 0.6 V VTTO AVCC + 0.6 V Internal Power Dissipation 2.0 W High Speed Input Voltage AVCC − 1.4 V < VIN < AVCC + 0.6 V High Speed Differential Input Voltage 2.0 V Parallel Interface (TX_EN, PE_EN) AVEE − 0.3 V < VIN < AVCC + 0.6 V Storage Temperature Range −65°C to +125°C Operating Temperature Range −40°C to +85°C Junction Temperature 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a 4-layer JEDEC circuit board for surface-mount packages. JC is specified for the exposed pad soldered to the circuit board with no airflow. Table 3. Package Type θJA θJC Unit 40-Lead LFCSP 31.9 2.6 °C/W MAXIMUM POWER DISSIPATION The maximum power that can be safely dissipated by the ADV3003 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. To ensure proper operation, it is necessary to observe the maximum power derating as determined by the thermal resistance coefficients. ESD CAUTION
- THE ADV3003 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE
ELECTRICAL AND THERMAL SPECIFICATIONS. Figure 3. Pin Configuration Table 4. Pin Function Descriptions 1 IN0 HS, I High Speed Input Complement. 2 IP0 HS, I High Speed Input. 3 IN1 HS, I High Speed Input Complement. 4 IP1 HS, I High Speed Input. 5 VTTI Power Input Termination Supply. Nominally connected to AVCC. 6 IN2 HS, I High Speed Input Complement. 7 IP2 HS, I High Speed Input. 8 IN3 HS, I High Speed Input Complement. 9 IP3 HS, I High Speed Input. 10, 16, 22, 23, 25, 26, 30, 32 AVCC Power Positive Analog Supply. 3.3 V nominal. 11 ON0 HS, O High Speed Output Complement. 12 OP0 HS, O High Speed Output. 13 VTTO Power Output Termination Supply. Nominally connected to AVCC. 14 ON1 HS, O High Speed Output Complement. 15 OP1 HS, O High Speed Output. 17 ON2 HS, O High Speed Output Complement. 18 OP2 HS, O High Speed Output. 19 ON3 HS, O High Speed Output Complement. 20 OP3 HS, O High Speed Output. 24, 27, 37, ePAD AVEE Power Negative Analog Supply. 0 V nominal. 28 TX_EN Control High Speed Output Enable Parallel Interface. 29 PE_EN Control High Speed Pre-Emph asis Enable Parallel Interface. 1 HS = high speed, I = input, O = output.
low (0), in accordance with the logic values set forth in Table 1. that the link through the ADV3003 is inactive. Table 5. Transmitter Enable Setting
0 Off Off On
1 On On On
cable performance varies widely among manufacturers. Table 6. Pre-Emphasis Enable Setting 3.3 V through a 50 Ω resistor.
Rev. A | Page 12 of 16 APPLICATION NOTES The ADV3003 is a TMDS buffer featuring equalized inputs and pre-emphasized outputs. It is intended for use as a buffer in HDMI/DVI systems with long input cable runs, and is fully HDMI 1.3 receive-compliant. PINOUT The ADV3003 is designed to have an HDMI/DVI receiver pinout at its input and a transmitter pinout at its output. This makes the ADV3003 ideal for use in advanced TV front-panel connectors and AVR-type applications where a designer routes both the inputs and the outputs directly to HDMI/DVI connec- tors—all of the high speed signals can be routed on one side of the board. The ADV3003 provides 12 dB of input equalization, so it can compensate for the signal degradation of long input cables. In addition, the ADV3003 can also provide up to 6 dB of pre-emphasis that boosts the output TMDS signals and allows the ADV3003 to precompensate when driving long PCB traces or high loss output cables. The net effect of the input equalization and output pre-emphasis is that the ADV3003 can compensate for signal degradation of both the input and output cables; it acts to reopen a closed input data eye and transmit a full-swing HDMI signal to an end receiver. CABLE LENGTHS AND EQUALIZATION The 12 dB equalizer of the ADV3003 is optimized for video data rates of 2.25 Gbps and can equalize more than 20 meters of 24 AWG HDMI cable at the input at 2.25 Gbps, the data rate corresponding to the video format 1080p with 12-bit deep color. The length of cable that can be used in a typical HDMI/DVI application depends on a large number of factors including
- Cable quality: The quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors have lower signal degradation per unit length.
- Data rate: The data rate being sent over the cable. The signal degradation over HDMI cables increases with data rate.
- Edge rates: The edge rates of the source. Slower input edges result in more significant data eye closure at the end of a cable.
- Receiver sensitivity: The sensitivity of the terminating receiver. Because of these considerations, specific cable types and lengths are not recommended for use with this equalizer. The ADV3003 equalizer does not degrade signal integrity, even for short input cables. PRE-EMPHASIS The pre-emphasis of the ADV3003 acts to boost the initial voltage swing of the output signals. Pre-emphasis provides a distinct advantage in systems where the ADV3003 is driving either high loss cables or long PCB traces, because the added boost helps to ensure that the data eye at the far end of the output cables or PCB traces meets the HDMI receive mask. The use of pre-emphasis in a system is highly application specific. PCB LAYOUT GUIDELINES The ADV3003 is a 4-channel TMDS buffer, targeted for use in HDMI and DVI video applications. Although the HDMI/DVI link consists of four differential, high speed channels and four single-ended, low speed auxiliary control signals, the ADV3003 buffers only the high speed signals. The high speed signals carry the audiovisual (A V) data, which is encoded by a technique called TMDS. For HDMI, the TMDS data is further encrypted in accordance with the high bandwidth digital content protection (HDCP) standard. The TMDS signals are differential, unidirectional, and high speed (up to 2.25 Gbps). The channels that carry the video data must have a controlled impedance, be terminated at the receiver, and be capable of operating up to at least 2.25 Gbps. It is especially important to note that the PCB traces that carry the TMDS signals should be designed with a controlled differential impedance of 100 Ω. The ADV3003 provides single-ended 50 Ω terminations on chip for both its inputs and outputs. Transmitter termination is not fully specified by the HDMI standard, but its inclusion in the ADV3003 improves the overall system signal integrity. TMDS Signals In the HDMI/DVI standard, four differential pairs carry the TMDS signals. In DVI, three of these pairs are dedicated to carrying RGB video and sync data. For HDMI, audio data is also interleaved with the video data; the DVI standard does not incorporate audio information. The fourth high speed differential pair is used for the AV data-word clock, which runs at one-tenth the speed of the video data channels. The four high speed channels of the ADV3003 are identical. No concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any TMDS signal; the user chooses which signal is routed over which channel. In addition, the TMDS channels are symmetric; therefore, the p and n of a given differential pair are inter- changeable, provided the inversion is consistent across all inputs and outputs of the ADV3003.
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5. Figure 29. 40-Lead Lead Frame Chip Scale Package [LFCSP]
Rev. A | Page 16 of 16 NOTES ©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07212-0-6/17(A)