ADV3000 AD | Alldatasheet
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3:1 HDMI/DVI Switch with Equalization ADV3000 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved.
FEATURES
3 inputs, 1 output HDMI/DVI links Enables HDMI 1.3-compliant receiver
4 TMDS channels per link
Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs for operation with long HDMI cables (20 meters at 2.25 Gbps) Fully buffered unidirectional inputs/outputs Globally switchable, 50 Ω on-chip terminations Pre-emphasized outputs Low added jitter Single-supply operation (3.3 V) 4 auxiliary channels per link Bidirectional unbuffered inputs/outputs Flexible supply operation (3.3 V to 5 V) HDCP standard compatible Allows switching of DDC bus and 2 additional signals Output disable feature Reduced power dissipation Removable output termination Allows building of larger arrays Two ADV3000s support HDMI/DVI dual-link Standards compatible: HDMI receiver, HDCP , DVI Serial (I2C slave) and parallel control interface 80-lead, 14 mm × 14 mm LQFP , Pb-free package
APPLICATIONS
Advanced television (HDTV) sets ADV3000 HDMI RECEIVER HDTV SET DVD PLAYER 01:18 NameBrand Power DVD SET-TOP BOX GAME CONSOLE 06712-001 Figure 1. Typical HDTV Application the construction of larger arrays using the wire-OR technique.
- Supports data rates up to 2.25 Gbps, enabling 1080p deep
UXGA (1600 × 1200) DVI resolutions.
- Input cable equalizer enables use of long cables at the input
(more than 20 meters of 24 AWG cable at 2.25 Gbps).
- Auxiliary switch routes a DDC bus and two additional signals
for a single-chip, HDMI 1.3 receive-compliant solution.
Rev. 0 | Page 2 of 28 TABLE OF CONTENTS
REVISION HISTORY
8/07—Revision 0: Initial Version
Rev. 0 | Page 3 of 28 SPECIFICATIONS TA = 27°C, AVCC = 3.3 V , VTTI = 3.3 V , VTTO = 3.3 V , DVCC = 3.3 V , AMUXVCC = 5 V , AVEE = 0 V , DVEE = 0 V , differential input swing = 1000 mV , TMDS outputs terminated with external 50 Ω resistors to 3.3 V , unless otherwise noted. Table 1. Parameter Conditions/Comments Min Typ Max Unit DYNAMIC PERFORMANCE Maximum Data Rate (DR) per Channel NRZ 2.25 Gbps Bit Error Rate (BER) PRBS 223 − 1 10−9 Added Deterministic Jitter DR ≤ 2.25 Gbps, PRBS 27 − 1, EQ = 12 dB 25 ps (p-p) Added Random Jitter 1 ps (rms) Differential Intrapair Skew At output 1 ps Differential Interpair Skew1 At output 40 ps EQUALIZATION PERFORMANCE Receiver (Highest Setting)2 Boost frequency = 825 MHz 12 dB Transmitter (Highest Setting)3 Boost frequency = 825 MHz 6 dB INPUT CHARACTERISTICS Input Voltage Swing Differential 150 1200 mV Input Common-Mode Voltage (VICM) AVCC − 800 AVCC mV OUTPUT CHARACTERISTICS High Voltage Level Single-ended high speed channel AVCC − 10 AVCC + 10 mV Low Voltage Level Single-ended high speed channel AVCC − 600 AVCC − 400 mV Rise/Fall Time (20% to 80%) 75 135 175 ps INPUT TERMINATION Resistance Single-ended 50 Ω AUXILIARY CHANNELS On Resistance, RAUX 100 Ω On Capacitance, CAUX DC bias = 2.5 V, ac voltage = 3.5 V, f = 100 kHz 8 pF Input/Output Voltage Range DVEE AMUXVCC V POWER SUPPLY AVCC Operating range 3 3.3 3.6 V QUIESCENT CURRENT AVCC Outputs disabled 30 40 44 mA Outputs enabled, no pre-emphasis 52 60 66 mA Outputs enabled, maximum pre-emphasis 95 110 122 mA VTTI Input termination on4 5 40 54 mA VTTO Output termination on, no pre-emphasis 35 40 46 mA Output termination on, maximum pre-emphasis 72 80 90 mA DVCC 3.2 7 8 mA AMUXVCC 0.01 0.1 mA POWER DISSIPATION Outputs disabled 115 271 361 mW Outputs enabled, no pre-emphasis 384 574 671 mW Outputs enabled, maximum pre-emphasis 704 910 1050 mW TIMING CHARACTERISTICS Switching/Update Delay High speed switching register: HS_CH 200 ms All other configuration registers 1.5 ms RESET Pulse Width 50 ns
Rev. 0 | Page 4 of 28 Parameter Conditions/Comments Min Typ Max Unit SERIAL CONTROL INTERFACE5 Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V Output High Voltage, VOH 2.4 V Output Low Voltage, VOL 0.4 V PARALLEL CONTROL INTERFACE Input High Voltage, VIH 2 V Input Low Voltage, VIL 0.8 V 1 Differential interpair skew is measured between the TMDS pairs of a single link. 2 ADV3000 output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 4 Typical value assumes only the selected HDMI/DVI link is active with nominal signal swings and that the unselected HDMI/DVI links are deactivated. Minimum and maximum limits are measured at the respective extremes of input termination resistance and input voltage swing. 5 The ADV3000 is an I2C slave and its serial control interface is based on the 3.3 V I2C bus specification.
in a 4-layer JEDEC circuit board for surface-mount packages. θJC is specified for no airflow. Table 3. Thermal Resistance the stresses exerted on the die by the package. by the coefficients in Table 3.
Figure 3. Pin Configuration Table 4. Pin Function Descriptions 1, 45, 48, 60 AVCC Power Positive Analog Supply. 3.3 V nominal. 2 IN_B0 HS I High Speed Input Complement. 3 IP_B0 HS I High Speed Input. 4 IN_B1 HS I High Speed Input Complement. 5 IP_B1 HS I High Speed Input. 6, 15, 46, 54 VTTI Power Input Termination Supply. Nominally connected to AVCC. 7 IN_B2 HS I High Speed Input Complement. 8 IP_B2 HS I High Speed Input. 9 IN_B3 HS I High Speed Input Complement. 10 IP_B3 HS I High Speed Input. 11 IN_A0 HS I High Speed Input Complement. 12 IP_A0 HS I High Speed Input. 13 IN_A1 HS I High Speed Input Complement. 14 IP_A1 HS I High Speed Input. 16 IN_A2 HS I High Speed Input Complement. 17 IP_A2 HS I High Speed Input. 18 IN_A3 HS I High Speed Input Complement. 19 IP_A3 HS I High Speed Input. 20, 44, 47, 51, 57 AVEE Power Negative Analog Supply. 0 V nominal. 21 I2C_ADDR0 Control I2C Address LSB. 22, 76 DVEE Power Negative Digital and Auxiliary Multiplexer Power Supply. 0 V nominal. 23 PP_CH0 Control High Speed Source Selection Parallel Interface LSB. 24 PP_CH1 Control High Speed Source Selection Parallel Interface MSB.
Rev. 0 | Page 7 of 28 Pin No. Mnemonic Type 1 Description 25, 31, 40 DVCC Power Positive Digital Power Supply. 3.3 V nominal. 26 ON0 HS O High Speed Output Complement. 27 OP0 HS O High Speed Output. 28, 34 VTTO Power Output Termination Supply. Nominally connected to AVCC. 29 ON1 HS O High Speed Output Complement. 30 OP1 HS O High Speed Output. 32 ON2 HS O High Speed Output Complement. 33 OP2 HS O High Speed Output. 35 ON3 HS O High Speed Output Complement. 36 OP3 HS O High Speed Output. 37 RESET Control Configuration Registers Reset. Normally pulled up to AVCC. 38 PP_PRE0 Control High Speed Pre-Emphasis Selection Parallel Interface LSB. 39 PP_PRE1 Control High Speed Pre-Emphasis Selection Parallel Interface MSB. 40 DVCC Power Positive Digital Supply. 3.3 V nominal. 41 PP_OCL Control High Speed Output Current Level Parallel Interface. 42 I2C_SCL Control I2C Clock. 43 I2C_SDA Control I2C Data. 49 IN_C0 HS I High Speed Input Complement. 50 IP_C0 HS I High Speed Input. 52 IN_C1 HS I High Speed Input Complement. 53 IP_C1 HS I High Speed Input. 55 IN_C2 HS I High Speed Input Complement. 56 IP_C2 HS I High Speed Input. 58 IN_C3 HS I High Speed Input Complement. 59 IP_C3 HS I High Speed Input. 61 PP_EN Control High Speed Output Enable Parallel Interface. 62 PP_EQ Control High Speed Equalization Selection Parallel Interface. 63 AMUXVCC Power Positive Auxiliary Multiplexer Supply. 5 V typical. 64 AUX_C3 LS I/O Low Speed Input/Output. 65 AUX_C2 LS I/O Low Speed Input/Output. 66 AUX_C1 LS I/O Low Speed Input/Output. 67 AUX_C0 LS I/O Low Speed Input/Output. 68 AUX_COM3 LS I/O Low Speed Common Input/Output. 69 AUX_COM2 LS I/O Low Speed Common Input/Output. 70 AUX_COM1 LS I/O Low Speed Common Input/Output. 71 AUX_COM0 LS I/O Low Speed Common Input/Output. 72 AUX_B3 LS I/O Low Speed Input/Output. 73 AUX_B2 LS I/O Low Speed Input/Output. 74 AUX_B1 LS I/O Low Speed Input/Output. 75 AUX_B0 LS I/O Low Speed Input/Output. 77 AUX_A3 LS I/O Low Speed Input/Output. 78 AUX_A2 LS I/O Low Speed Input/Output. 79 AUX_A1 LS I/O Low Speed Input/Output. 80 AUX_A0 LS I/O Low Speed Input/Output. 1 HS = high speed, LS = low speed, I = input, O = output.
(manually) select among a number of fixed settings. ADV3000 through the parallel control interface. Figure 25. High Speed Input Simplified Schematic than 20 meters of 24 AWG cable at 2.25 Gbps.
3.3 V VTTO power supply through two 50 Ω on-chip resistors
transmitter settings register through the serial control interface. quality of the output signal. arrays can be constructed using the ADV3000 in this mode. Figure 26. High Speed Output Simplified Schematic
Rev. 0 | Page 16 of 28 PARALLEL CONTROL INTERFACE The ADV3000 can be controlled through the parallel interface using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], and PP_OCL pins. Logic levels for the parallel interface pins are set in accordance with the specifications listed in Table 1. Setting these pins updates the parallel control interface registers, as listed in Table 18. Following a reset, the ADV3000 can be controlled through the parallel control interface until the first serial control event occurs. As soon as any serial control event occurs, the serial programming values override any prior parallel programming values, and the parallel control interface is disabled until the part is subsequently reset. The default serial programming values correspond to the state of the serial interface configuration registers, as listed in Table 5.
The serial interface configuration registers can be read and written using the I2C serial control interface, Pin I2C_SDA, and Pin I2C_SCL. Table 5. Serial (I2C) Interface Register Map Table 6. HS_EN Description
0 High speed channels off, low power/standby mode
1 High speed channels on
Table 7. HS_EN Mapping
00 A[3:0] High Speed Source A switched to output
01 B[3:0] High Speed Source B switched to output
10 C[3:0] High Speed Source C switched to output
11 Illegal value
Table 8. AUX_EN Description
0 Auxiliary switch off, no low speed input/output to
1 Auxiliary switch on
Table 9. AUX_CH Mapping
00 AUX_A[3:0] Auxiliary Source A switched
01 AUX_B[3:0] Auxiliary Source B switched
10 AUX_C[3:0] Auxiliary Source C switched
Table 10. RX_TO Description
0 Input termination off
1 Input termination on (can be pulsed on and off accord-
Table 11. RX_PT[X] Description
0 Input termination for TMDS Channel X always
1 Input termination for TMDS Channel X
Table 12. RX_PT[X] Mapping Table 13. RX_EQ[X] Description
0 Low equalization (6 dB)
1 High equalization (12 dB)
Table 14. RX_EQ[X] Mapping Table 15. TX_PE[1:0] Description
00 No pre-emphasis (0 dB)
01 Low pre-emphasis (2 dB)
10 Medium pre-emphasis (4 dB)
11 High pre-emphasis (6 dB)
Table 16. TX_PTO Description
0 Output termination off
1 Output termination on
Table 17. TX_OCL Description
0 Output current set to 10 mA
1 Output current set to 20 mA
The parallel interface configuration registers can be directly set using the PP_EN, PP_CH[1:0], PP_EQ, PP_PRE[1:0], and PP_OCL pins. each pin is set by tying it to 3.3 V (Logic 1) or 0 V (Logic 0). Table 18. Parallel Interface Register Map Table 19. PP_EN Description Table 20. High Speed Switch Mode Mapping Table 21. Auxiliary Switch Mode Mapping
when using the parallel interface. fixed to off when using the parallel interface. Table 22. PP_EQ Description Table 23. PP_PE[1:0] Description Table 24. TX_OCL Description
Rev. 0 | Page 22 of 28 CABLE LENGTHS AND EQUALIZATION The ADV3000 offers two levels of programmable equalization for the high speed inputs: 6 dB and 12 dB. The equalizer of the ADV3000 supports video data rates of up to 2.25 Gbps, and as shown in Figure 14, it can equalize more than 20 meters of 24 AWG HDMI cable at 2.25 Gbps, which corresponds to the video format, 1080p with deep color. The length of cable that can be used in a typical HDMI/DVI application depends on a large number of factors, including:
- Cable quality: the quality of the cable in terms of conductor wire gauge and shielding. Thicker conductors have lower signal degradation per unit length.
- Data rate: the data rate being sent over the cable. The signal degradation of HDMI cables increases with data rate.
- Edge rates: the edge rates of the source input. Slower input edges result in more significant data eye closure at the end of a cable.
- Receiver sensitivity: the sensitivity of the terminating receiver. As such, specific cable types and lengths are not recommended for use with a particular equalizer setting. In nearly all applica- tions, the ADV3000 equalization level can be set to high, or 12 dB, for all input cable configurations at all data rates, without degrading the signal integrity. PCB LAYOUT GUIDELINES The ADV3000 is used to switch two distinctly different types of signals, both of which are required for HDMI and DVI video. These signal groups require different treatment when laying out a PC board. The first group of signals carries the audiovisual (AV) data. HDMI/ DVI video signals are differential, unidirectional, and high speed (up to 2.25 Gbps). The channels that carry the video data must be controlled impedance, terminated at the receiver, and capable of operating at the maximum specified system data rate. It is especially important to note that the differential traces that carry the TMDS signals should be designed with a controlled differential impedance of 100 Ω. The ADV3000 provides single- ended, 50 Ω terminations on-chip for both its inputs and outputs, and both the input and output terminations can be enabled or disabled through the serial control interface. The output terminations can also be enabled or disabled through the parallel control interface. Transmitter termination is not required by the HDMI 1.3 standard, but its inclusion improves the overall system signal integrity. The audiovisual (AV) data carried on these high speed channels is encoded by a technique called transmission minimized differ- ential signaling (TMDS) and in the case of HDMI, is also encrypted according to the high bandwidth digital copy protection (HDCP) standard. The second group of signals consists of low speed auxiliary control signals used for communication between a source and a sink. Depending upon the application, these signals can include the DDC bus (this is an I2C bus used to send EDID information and HDCP encryption keys between the source and the sink), the consumer electronics control (CEC) line, and the hot plug detect (HPD) line. These auxiliary signals are bidirectional, low speed, and transferred over a single-ended transmission line that does not need to have controlled impedance. The primary concern with laying out the auxiliary lines is ensuring that they conform to the I 2C bus standard and do not have excessive capacitive loading. TMDS Signals In the HDMI/DVI standard, four differential pairs carry the TMDS signals. In DVI, three of these pairs are dedicated to carrying RGB video and sync data. For HDMI, audio data is interleaved with the video data; the DVI standard does not incorporate audio information. The fourth high speed differ- ential pair is used for the AV data-word clock, and runs at one-tenth the speed of the TMDS data channels. The four high speed channels of the ADV3000 are identical. No concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any TMDS signal. The user chooses which signal is routed over which channel. Additionally, the TMDS channels are symmetrical; therefore, the p and n of a given differential pair are inter- changeable, provided the inversion is consistent across all inputs and outputs of the ADV3000. However, the routing between inputs and outputs through the ADV3000 is fixed. For example, Output Channel 0 always switches between Input A0, Input B0, Input C0, and so forth. The ADV3000 buffers the TMDS signals and the input traces can be considered electrically independent of the output traces. In most applications, the quality of the signal on the input TMDS traces is more sensitive to the PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the ADV3000, all four high speed signals should be routed on a PCB in accordance with the same RF layout guidelines. Layout for the TMDS Signals The TMDS differential pairs can be either microstrip traces, routed on the outer layer of a board, or stripline traces, routed on an internal layer of the board. If microstrip traces are used, there should be a continuous reference plane on the PCB layer directly below the traces. If stripline traces are used, they must be sandwiched between two continuous reference planes in the PCB stack-up. Additionally, the p and n of each differential pair must have a controlled differential impedance of 100 Ω. The characteristic impedance of a differential pair is a function of several variables including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the PC board binder material. Interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path, therefore, it is preferable to route the TMDS lines exclusively on one layer of the
Figure 36. 80-Lead Low Profile Quad Flat Package [LQFP]
Rev. 0 | Page 27 of 28 NOTES
Rev. 0 | Page 28 of 28 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06712-0-8/07(0)