ADV212BBCZ-150

ADV212 AD | Alldatasheet

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Technical content

Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.

FEATURES

Complete single-chip JPEG 2000 compression and decompression solution for video and still images Identical in pinout and footprint to the ADV202 and supports all the functionality of the ADV202 Power reduction of at least 30% compared with ADV202 JTAG/boundary scan support Patented SURF® (spatial ultraefficient recursive filtering) technology enables low power, low cost wavelet-based compression Supports both 9/7 and 5/3 wavelet transforms with up to 6 levels of transform Video interface directly supporting ITU-R BT.656, SMPTE 125M PAL/NTSC, SMPTE 274M, SMPTE 293M (525p), and ITU-R BT.1358 (625p), or any video format with a maximum input rate of 65 MSPS for irreversible mode or

40 MSPS for reversible mode

Programmable tile/image size with widths up to 4096 pixels in single-component mode; maximum tile/image height: 4096 pixels 2 or more ADV212s can be combined to support full-frame SMPTE 274M HDTV (1080i) or SMPTE 296M (720p) Flexible, asynchronous SRAM-style host interface allows glue- less connection to most 16-/32-bit microcontrollers and ASICs 2.5 V or 3.3 V input/output and 1.5 V core supply 12 mm × 12 mm, 121-ball CSPBGA with a speed grade of

115 MHz, or 13 mm × 13 mm, 144-ball CSPBGA with a

APPLICATIONS

Networked video and image distribution systems Wireless video and image distribution Image archival/retrieval Digital CCTV and surveillance systems Digital cinema systems Professional video editing and recording Digital still cameras Digital camcorders GENERAL DESCRIPTION The ADV212 is a single-chip JPEG 2000 codec targeted for video and high bandwidth image compression applications that can benefit from the enhanced quality and features provided by the JPEG 2000 (J2K)—ISO/IEC15444-1 image compression standard. The part implements the computationally intensive operations of the JPEG 2000 image compression standard and provides fully compliant code-stream generation for most applications. The dedicated video port of the ADV212 provides glueless con- nection to common digital video standards such as ITU-R BT.656, SMPTE 125M, SMPTE 293M (525p), ITU-R BT.1358 (625p), SMPTE 274M (1080i), or SMPTE 296M (720p). A variety of other high speed, synchronous pixel and video formats can also be supported by using the programmable framing and validation signals. The ADV212 is an upgrade version of the ADV202 that is identical in pinout and footprint. It supports all the functionality of the ADV202 and has the following additional options:

• JTAG/boundary scan support
• Power reduction of at least 30% compared with the ADV202 FUNCTIONAL BLOCK DIAGRAM PIXEL I/F EXTERNAL DMA CTRL WAVELET ENGINE INTERNAL BUS AND DMA ENGINE PIXEL I/F EC1 EC2 EC3 EMBEDDED RISC PROCESSOR SYSTEM RAM ROM ADV212 CODE FIFO PIXEL FIFO ATTR FIFO HOST I/F 06389-001 Figure 1.

Rev. 0 | Page 2 of 44 TABLE OF CONTENTS DREQ/DACK DMA Mode—Single FIFO Write Operation .. 8 DREQ/DACK DMA Mode—Single FIFO Read Operation . 10

REVISION HISTORY

10/06—Revision 0: Initial Version

Rev. 0 | Page 3 of 44 The ADV212 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV212 contains a dedicated wavelet transform engine, three entropy codecs, an on-board memory system, and an embedded reduced instruction set computer (RISC) processor that can provide a complete JPEG 2000 compression/decompression solution. The wavelet processor supports the 9/7 irreversible wavelet transform and the 5/3 wavelet transform in reversible and irreversible modes. The entropy codecs support all features in the JPEG 2000 Part 1 specification, except maximum shift region of interest (ROI). The ADV212 operates on a rectangular array of pixel samples called a tile. A tile can contain a complete image, up to the maximum supported size, or some portion of an image. The maximum horizontal tile size supported depends on the wavelet transform selected and the number of samples in the tile. Images larger than the ADV212’s maximum tile size can be broken into individual tiles and then sent sequentially to the chip while maintaining a single, fully compliant JPEG 2000 code stream for the entire image. JPEG 2000 FEATURE SUPPORT The ADV212 supports a broad set of features that are included in Part 1 of the JPEG 2000 standard (ISO/IEC 15444). See ADV212 User’s Guide for information on the JPEG 2000 features that the ADV212 currently supports. Depending on the particular application requirements, the ADV212 can provide varying levels of JPEG 2000 compression support. It can provide raw code block and attribute data output, which allows the host software to have complete control over the generation of the JPEG 2000 code stream and other aspects of the compression process such as bit-rate control. Otherwise, the ADV212 can create a complete, fully compliant JPEG 2000 code stream (J2C) and enhanced file formats such as JP2.

Rev. 0 | Page 4 of 44 SPECIFICATONS Specifications apply to IOVDD = 2.5 V or 3.3 V over operating temperature range, unless otherwise specified. SUPPLY VOLTAGES AND CURRENT Table 1. Parameter Mnemonic Min Typ Max Unit DC Supply Voltage, Core VDD 1.425 1.5 1.575 V DC Supply Voltage, Input/Output IOVDD 2.375 2.5 2.625 V DC Supply Voltage, Input/Output IOVDD 3.135 3.3 3.465 V Input Range V IN −0.3 V DDI/O + 0.3 V Operating Ambient Temperature Range in Free Air T −40 +25 +85 °C Static Current1 I DD 15 30 mA Dynamic Current, Core (JCLK Frequency = 150 MHz)2 380 440 mA Dynamic Current, Core (JCLK Frequency = 108 MHz) 280 320 mA Dynamic Current, Core (JCLK Frequency = 81 MHz) 210 290 mA Dynamic Current, Input/Output 40 50 mA 1 No clock or input/output activity. 2 ADV212-150 only. INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter Mnemonic Min Typ Max Unit Test Conditions High Level Input Voltage V IH (3.3 V) 2.2 V VDD = maximum High Level Input Voltage V IH (2.5 V) 1.9 V VDD = maximum Low Level Input Voltage V IL (3.3 V, 2.5 V) 0.6 V VDD = minimum High Level Output Voltage V OH (3.3 V) 2.4 V VDD = minimum, I OH = −0.5 mA High Level Output Voltage V OH (2.5 V) 2.0 V VDD = minimum, I OH = −0.5 mA Low Level Output Voltage V OL (3.3 V, 2.5 V) 0.4 V VDD = minimum, I OL = +2 mA High Level Input Current I IH 1.0 μA VDD = maximum, V IN = VDD Low Level Input Current I IL 1.0 μA VDD = maximum, V IN = 0 V High Level Three-State Leakage Current I OZH 1.0 μA VDD = maximum, V IN = VDD Low Level Three-State Leakage Current I OZL 1.0 μA VDD = maximum, V IN = 0V Input Pin Capacitance C I 8 pF Output Pin Capacitance C O 8 pF

1 For a definition of MCLK, see Figure 32. Figure 2. Input Clock

1 For a definition of JCLK, see Figure 32. Figure 3. Normal Host Mode—Write Operation

minimum of three JCLK cycles is recommended between ACK assert and RD deassert. 2 For a definition of JCLK, see Figure 32. Figure 4. Normal Host Mode—Read Operation

Figure 28. Raw Pixel Modes

Figure 29. JTAG Timing

soldered in a circuit board for surface-mount packages. Table 15. Thermal Resistance

Table 16. Pin Function Descriptions 119 L9 132 L12 MCLK 1 I System Input Clock. See the PLL section. 117 L7 131 L11 RESET 1 I Reset. Causes the ADV212 to immediately reset. must be held high when a RESET is applied. 4 I Address Bus for the Host Interface. ADV212 using the host interface. 95 J7 94 H10 WE1 1 I Write Enable Used with the Host Interface. RDFB2 Read Enable When Fly-By DMA Is Enabled. 86 H9 84 G12 RD1 1 I Read Enable Used with the Host Interface. WEFB3 Write Enable When Fly-By DMA Is Enabled. 85 H8 83 G11 ACK 1 O Acknowledge. Used for direct register accesses. and the PLL_HI register, Bit 4, must be set to 1. requires the attention of the host processor. enabled via the bits in register EIRQIE.

Rev. 0 | Page 22 of 44 121-Ball Package 144-Ball Package Pin No. Location Pin No. Location Mnemonic Pins Used Type Description 63 F8 72 F12 DREQ0 1 O Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 0. FSRQ0 O FIFO Service Request. Used in DCS-DMA Mode. Service request from the FIFO assigned to Channel 0 (asynchronous mode). VALID O Valid Indication for JDATA Input/Output Stream. Polarity of this pin is programmable in the EDMOD0 register. VALID is always an output. CFG1 I Boot Mode Configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to IOVDD or DGND through a 10 kΩ resistor. 64 F9 71 F11 DACK0 1 I Data Acknowledge for External DMA Interface. Signal from the host CPU, which indicates that the data transfer request (DREQ0 ) has been acknowledged and that the data transfer can proceed. This pin must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled. HOLD I External Hold Indication for JDATA Input/Output Stream. Polarity is programmable in the EDMOD0 register. This pin is always an input. FCS0 I FIFO Chip Select. Used in DCS-DMA Mode. Chip select for the FIFO assigned to Channel 0 (asynchronous mode). 65 F10 70 F10 DREQ1 1 O Data Request for External DMA Interface. Indicates that the ADV212 is ready to send/receive data to/from the FIFO assigned to DMA Channel 1. FSRQ1 O FIFO Service Request. Used in DCS-DMA Mode. Service request from the FIFO assigned to Channel 1 (asynchronous mode). CFG2 I Boot Mode Configuration. This pin is read on reset to determine the boot configuration of the on-board processor. The pin should be tied to IOVDD or DGND through a 10 kΩ resistor. 75 G9 69 F9 DACK1 1 I Data Acknowledge for External DMA Interface. Signal from the host CPU, which indicates that the data transfer request (DREQ1) has been acknowledged and data transfer can proceed. This pin must be held high at all times unless a DMA or JDATA access is occurring. This pin must be held high at all times if the DMA interface is not used, even if the DMA channels are disabled. FCS1 I FIFO Chip Select. Used in DCS-DMA Mode. Chip select for the FIFO assigned to Channel 1 (asynchronous mode). 90 to 92, 78 J2 to J4, H1 111,97 to 99 K3, J1 to J3 HDATA [31:28] 4 I/O Host Expansion Bus. JDATA [7:4] I/O JDATA Bus (JDATA Mode). 79 to 81, 70 H2 to H4, G4 100, 85 to 87 J4, H1 to H3 HDATA [27:24] 4 I/O Host Expansion Bus. JDATA [3:0] I/O JDATA Bus (JDATA Mode).

Rev. 0 | Page 23 of 44 121-Ball Package 144-Ball Package Pin No. Location Pin No. Location Mnemonic Pins Used Type Description 69, 68, 59, 58 G3, G2, F4, F3 88,73 to 75 H4, G1 to G3 HDATA [23:20] 4 I/O Host Expansion Bus. 57, 46 to 48 F2, E2, E3, 76, 61 to 63 G4, F1 to F3 HDATA [19:16] 4 I/O Host Expansion Bus. VDATA [15:12] I/O Video Data. Only used for raw pixel video mode. Unused pins should be pulled down via a 10 kΩ resistor. 112 L2 134 M2 SCOMM7 8 I/O Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. 113 L3 135 M3 SCOMM6 I/O Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. 114 L4 136 M4 SCOMM5 I/O Serial Communication. This pin must be used in multiple chip mode to align the outputs of two or more ADV212s. For details, see the Applications section and the AN-796 Application Note. When not used, this pin should be tied low via a 10 kΩ resistor. 100 K1 121 L1 SCOMM4 O LCODE Output in Encode Mode. When LCODE is enabled, the output on this pin indicates on a high transition that the last data-word for a field has been read from the FIFO. For an 8-bit interface, such as JDATA, LCODE is asserted for four consecutive bytes and is enabled by default. 101 K2 122 L2 SCOMM3 I Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. 115 L5 123 L3 SCOMM2 O Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. 103 K4 109 K1 SCOMM1 I Serial Communication. For internal use only. This pin should be tied low via a 10 kΩ resistor. 102 K3 110 K2 SCOMM0 O Serial Communication. This pin should be tied low via a10 kΩ resistor. 53 E9 60 E12 VCLK 1 I Video Data Clock. This pin must be supplied if video data is input/output on the VDATA bus. 44, 43, 29, 31, 32, 18 to 20, 22, 21, 7, D11, D10, C7, C9, C10, B7, B8, B9, B11, B10, A7, A10 46 to 48, 34 to 36, 22 to 24, 9 to 11 D10 to D12, C10 to C12, B10 to B12, A9 to A11 VDATA [11:0] 12 I/O Video Data. Unused pins should be pulled down via a 10 kΩ resistor. 41 D8 58 E10 VSYNC 1 I/O Vertical Sync for Video Mode. VFRM Raw Pixel Mode Framing Signal. When this pin is asserted high, it indicates the first sample of a tile. 42 D9 59 E11 HSYNC 1 I/O Horizontal Sync for Video Mode. VRDY O Raw Pixel Mode Ready Signal. 54 E10 57 E9 FIELD 1 I/O Field Sync for Video Mode. VSTRB I Raw Pixel Mode Transfer Strobe. 94 J6 120 K12 TCK 1 I JTAG Clock. If not used, this pin should be connected to ground via a pull-down resistor. 108 K9 119 K11 TRS 1 I JTAG Reset. If the JTAG is used, this pin must be toggled low to high. If JTAG is not used, this pin must be held low.

Rev. 0 | Page 24 of 44 121-Ball Package 144-Ball Package Pin No. Location Pin No. Location Mnemonic Pins Used Type Description 98 J10 118 K10 TMS 1 I JTAG Mode Select. If JTAG is used, connect 10 kΩ pull-up resistor to this pin. If not used, this pin should be connected to ground via a pull-down resistor. 116 L6 141 M9 TDI 1 I JTAG Serial Data Input. If JTAG is used, connect a 10 kΩ pull-up resistor to this pin. If JTAG is not used, this pin should be connected to ground via a pull-down resistor. 109 K10 130 L10 TDO 1 O JTAG Serial Data Output. If this pin is not used, do not connect it. 3, 8, 40, 84, 120 A3, A8, D7, H7, L10 18, 19, 30, 31, 42, 43, 102, 103, 114, 115, 126, 127, 142 B6, B7, C6, C7, D6, D7, J6, J7, K6, K7, L6, L7, M10 VDD V Positive Supply for Core. 1, 4, 9,11, 23, 33, 39, 45, 49 to 51, 55, 56, 60 to 62, 66, 67, 71 to 73, 77, 83, 89,99, 110, 111, 118, 121 A1, A4, A9, A11, C1, C11, D6, E1, E5 to E7, E11, F1, F5 to F7, F11, G1, G5 to G7, G11, H6, J1, J11, K11, L1, L8, L11 1, 5 to 8, 12, 17, 20, 29, 32, 41, 44, 52 to 56, 65 to 68, 77 to 81, 89 to 93, 101, 104, 105, 113, 116, 125, 128, 133, 137 to 140, 143, 144 A1, A5 to A8, A12, B5, B8, C5, C8, D5, D8, E4 to E8, F5 to F8, G5 to G9, H5 to H9, J5, J8, J9, K5, K8, L5, L8, M1, M5 to M8, M11, M12 DGND GND Ground. 17, 28, 30, 38, 52, 74, 82, 93, 104 to 106 B6, C6, C8, D5, E8, G8, H5, J5, K5 to 16, 21, 28, 33, 40, 45, 112, 117, 124, 129 B4, B9, C4, C9, D4, D9, K4, K9, L4, IOVDD V Positive Supply for Input/Output. 1 In fly-by mode DMA, the function of the RD and WE signals (for DMA only) are reversed. This allows a host to move data between an external device and the ADV212 with the use of a single strobe. 2 In encode mode with fly-by DMA, the host can use the RDFB signal (WE pin) to simultaneously read from the ADV212 and write to an external device like memory. 3 In decode mode with fly-by DMA, the host can use the WEFB signal (RD pin) to simultaneously read from the external device and write to the ADV212.

Rev. 0 | Page 25 of 44 THEORY OF OPERATION The input video or pixel data is passed on to the ADV212’s pixel interface, and samples are deinterleaved and passed on to the wavelet engine, which decomposes each tile or frame into subbands using the 5/3 or 9/7 filters. The resultant wavelet coefficients are then written to the internal memory. The entropy codecs code the image data so that it conforms to the JPEG 2000 standard. An internal DMA provides high bandwidth memory-to-memory transfers, as well as high performance transfers between functional blocks and memory. WAVELET ENGINE The ADV212 provides a dedicated wavelet transform processor based on the Analog Devices proven and patented SURF technology. This processor can perform up to six wavelet decomposition levels on a tile. In encode mode, the wavelet transform processor takes in uncompressed samples, performs the wavelet transform and quantization, and writes the wavelet coefficients in all frequency subbands to the internal memory. Each of these subbands is further broken down into code blocks. The code-block dimensions can be user defined and are used by the wavelet transform processor to organize the wavelet coefficients into code blocks when writing to the internal memory. Each completed code block is then entropy coded by one of the entropy codecs. In decode mode, wavelet coefficients are read from internal memory and recomposed into uncompressed samples. ENTROPY CODECS The entropy codec block performs context modeling and arithmetic coding on a code block of the wavelet coefficients. Additionally, this block also performs the distortion metric calculations during compression that are required for optimal rate and distortion performance. Because the entropy coding process is the most computationally intensive operation in the JPEG 2000 compression process, three dedicated hardware entropy codecs are provided on the ADV212. EMBEDDED PROCESSOR SYSTEM The ADV212 incorporates an embedded 32-bit RISC processor. This processor is used for configuration, control, and manage- ment of the dedicated hardware functions, as well as for parsing and generation of the JPEG 2000 code stream. The processor system includes memory for both the program and data memory, the interrupt controller, the standard bus interfaces, and other hardware functions such as timers and counters. MEMORY SYSTEM The main function of the memory system is to manage wavelet coefficient data, interim code-block attribute data, and temporary workspace for creating, parsing, and storing the JPEG 2000 code stream. The memory system can also be used for the program and data memory for the embedded processor. INTERNAL DMA ENGINE The internal DMA engine provides high bandwidth memory- to-memory transfers, as well as high performance transfers between memory and functional blocks. This function is critical for high speed generation and parsing of the code stream.

the VDATA bus and the HDATA bus or the HDATA bus alone. requiring very high throughput, such as live video capture. supported using two or more ADV212 devices. single input mode. YCbCr data must be in 4:2:2 format. the pixel clock must be input on the VCLK pin. Table 17. Video Input/Output Modes the YCbCr data is interleaved onto a single bus. Raw Video Used for still picture data and nonstandard video. interface, DMA accesses, or streaming mode (JDATA) interface. 8-/16-/32-bit buses for data transfer. can be used for uncompressed data transfers in certain modes. data streams in addition to control and status communications.

• Uncompressed tile data (for example, still image data)
• Fully encoded JPEG 2000 code stream (or unpackaged code blocks)
• Code-block attributes The ADV212 uses big endian byte alignment for 16- and 32-bit transfers. All data is left-justified (MSB). Pixel Input on the Host Interface Pixel input on the host interface supports 8-/10-/12-/14-/16-bit raw pixel data formats. It can be used for pixel (still image) input/output or compressed video output. Because there are no timing codes or sync signals associated with the input data on the host interface, dimension registers and internal counters are used and must be programmed to indicate the start and end of the frame. Refer to the ADV202 in HIPI Mode technical note for information about using the ADV212 in this mode. Host Bus Configuration For maximum flexibility, the host interface provides several configurations to meet particular system requirements. The default bus mode uses the same pins to transfer control, status, and data to and from the ADV212. In this mode, the ADV212 can support 16- and 32-bit control transfers and 8-/16-/32-bit data transfers. The size of these buses can be selected independently, allowing, for example, a 16-bit microcontroller to configure and control the ADV212 while still providing 32-bit data transfers to an ASIC or external memory system. DIRECT AND INDIRECT REGISTERS To minimize pin count and cost, the number of address pins is limited to four, which yields a total direct address space of 16 locations. These locations are most commonly used by the external controller and are, therefore, accessible directly. All other registers in the ADV212 can be accessed indirectly through the IADDR and IDATA registers.

Rev. 0 | Page 27 of 44 CONTROL ACCESS REGISTERS With the exception of the indirect address and data registers (IADDR and IDATA), all control/status registers in the ADV212 are 16 bits wide and are half-word (16-bit) addressable only. When 32-bit host mode is enabled, the upper 16 bits of the HDATA bus are ignored on writes and return all zeros on reads of 16-bit registers. PIN CONFIGURATION AND BUS SIZES/MODES The ADV212 provides a wide variety of control and data configurations, which allows it to be used in many applications with little or no glue logic. The modes described in this section are configured using the BUSMODE register. In this section, host refers to normal addressed accesses (CS/RD/WE/ADDR) and data refers to external DMA accesses (DREQ/DACK). 32-Bit Host/32-Bit Data In this mode, the HDATA<31:0> pins provide full 32-bit wide data access to PIXEL, CODE, ATTR FIFOs. 16-Bit Host/32-Bit Data This mode allows a 16-bit host to configure and communicate with the ADV212 while allowing 32-bit accesses to the PIXEL, CODE, ATTR FIFOs using the external DMA capability. All addressed host accesses are 16 bits and, therefore, use only the HDATA<15:0> pins. The HDATA<31:16> pins provide the additional 16 bits necessary to support the 32-bit external DMA transfers to and from the FIFOs only. 16-Bit Host/16-Bit Data This mode uses 16-bit transfers if used for host or external DMA data transfers. 16-Bit Host/8-Bit Data (JDATA Bus Mode) This mode provides separate data input/output and host control interface pins. Host control accesses are 16 bits and use HDATA<15:0>, whereas the dedicated data bus uses JDATA<7:0>. JDATA uses a valid/hold synchronous transfer protocol. The direction of the JDATA bus is determined by the mode of the ADV212. If the ADV212 is encoding (compression), JDATA<7:0> is an output. If the ADV212 is decoding (decompression), JDATA<7:0> is an input. Host control accesses remain asynchronous. See also JDATA section below. STAGE REGISTER Because the ADV212 contains both 16-bit and 32-bit registers and its internal memory is mapped as 32-bit data, a mechanism has been provided to allow 16-bit hosts to access these registers and memory locations using the stage register (STAGE). STAGE is accessed as a 16-bit register using HDATA [15:0]. Prior to writing to the desired register, the stage register must be written with the upper (most significant) half-word. When the host subsequently writes the lower half-word to the desired control register, HDATA is combined with the previously staged value to create the required 32-bit value that is written. When a register is read, the upper (most significant) half-word is returned immediately on HDATA and the lower half-word can be retrieved by reading the stage register on a subsequent access. For details on using the stage register, see the ADV212 User’s Guide. Note that the stage register does not apply to the three data channels (PIXEL, CODE, ATTR). These channels are always accessed at the specified data width and do not require the use of the stage register. JDATA MODE JDATA mode is typically used only when the dedicated video interface (VDATA) is also enabled. This mode allows code stream data (compressed data compliant with JPEG 2000) to be input or output on a single dedicated 8-bit bus (JDATA<7:0>). The bus is always an output during compression operations, and is an input during decompression. A 2-pin handshake is used to transfer data over this synchronous interface. V ALID is used to indicate that the ADV212 is ready to provide or accept data and is always an output. HOLD is always an input and is asserted by the host if it cannot accept/provide data. For example, JDATA mode allows real-time applications, in which pixel data is input over the VDATA bus while the compressed data stream is output over the JDATA bus. EXTERNAL DMA ENGINE The external DMA interface is provided to enable high bandwidth data input/output between an external DMA controller and the ADV212 data FIFOs. Two independent DMA channels can each be assigned to any one of the three data stream FIFOs (PIXEL, CODE, ATTR). The controller supports asynchronous DMA using a data-request/data-acknowledge (DREQ/DACK) protocol in either single or burst access modes. Additional functionality is provided for single address compatibility (fly-by) and dedicated chip select (DCS) modes.

This section describes the internal registers of the ADV212. application-specific operation can be implemented. registers, see the ADV212 User’s Guide. Table 18. Direct Registers

register address space starts at Internal Address 0xFFFF0000. Both 32-bit and 16-bit hosts can access the indirect registers. hosts use the IADDR, the IDATA, and the stage register. Table 19. Indirect Registers

• JCLK > 50 MHz and < 150 MHz (144-pin version).
• JCLK > 50 MHz and < 115 MHz (121-pin version).
• HCLK < 81 MHz (121-pin version), or HCLK < 108 MHz (144-pin version).
• JCLK ≥ 2 × VCLK for single-component input.
• JCLK ≥ 2 × VCLK for YCbCr [4:2:2] input.
• In JDATA mode (JDATA), JCLK must be 4 × MCLK or higher.
• The maximum burst frequency for external DMA modes is ≤ 0.36 JCLK.
• For MCLK frequencies greater than 50 MHz, the input clock divider must be enabled, that is, IPD must be set to 1.
• IPD cannot be enabled for MCLK frequencies below 20 MHz.
• Deinterlace modes require JCLK ≥ 4 × MCLK.
• It is not recommended to use an LLC output from a video decoder as a clock source for MCLK. To achieve the lowest power consumption, an MCLK frequency of 27 MHz is recommended for a standard definition CCIR 656 input. The PLL circuit is recommended to have a multiplier of 3. This sets JCLK and HCLK to 81 MHz. LPFPHASE DETECT VCO JCLK HCLK÷2 HCLKD ÷PLLMULT÷2 LFB ÷2÷2 IPD BYPASS MCLK 06389-009

Figure 32. PLL Architecture and Control Functions Table 20. Recommended PLL Register Settings Table 21. Recommended Values for PLL_HI and PLL_LO Registers

The boot mode can be configured via hardware using the CFG pins or via software. The first boot mode after power-up is set by the CFG pins. Table 22. Hardware Boot Modes memory are accessible through normal host input/output operations. Hardware Boot Mode 4 CFG<1> tied low, CFG<2> tied high Reserved. Hardware Boot Mode 6 CFG<1> and CFG<2> tied high Reserved.

samples transferred with each access. Table 25 to determine the maximum data input rate. Table 23. Maximum Pixel Data Input Rates (144-Ball Package) 1 Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. 2 Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate]. 3 Maximum peak output rate; an output rate above this value is not possible. Table 24. Maximum Pixel Data Input Rates (121-Ball Package) 1 Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. 2 Minimum guaranteed sustained output rate or minimum sustainable compression rate [input rate/minimum peak output rate]. 3 Maximum peak output rate; an output rate above this value is not possible.

Table 25. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses

each SCOMM[5] pin is connected to the same GPIO on the host. SCOMM[5] is connected to the same GPIO output on the host. unmasked on both devices to enable multichip mode. Figure 34. Decode—Multichip Master/Slave Application

EXCEPTION TO PACKAGE HEIGHT AND THICKNESS.

0.50 NOM

0.30 MIN

Figure 40. 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

0.20 MAX

1.00 BSC

EXCEPTION TO PACKAGE HEIGHT AND THICKNESS. Figure 41. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Rev. 0 | Page 42 of 44 ORDERING GUIDE Model Temperature Range Speed Grade Operating Voltage Package Description Package Option ADV212BBCZ-1151 −40°C to +85°C 115 MHz 1.5 V Internal, 2.5 V or 3.3 V I/O 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC- 121-1 ADV212BBCZRL-1151 −40°C to +85°C 115 MHz 1.5 V Internal, 2.5 V or 3.3 V I/O 121-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC- 121-1 ADV212BBCZ-1501 −40°C to +85°C 150 MHz 1.5 V Internal, 2.5 V or 3.3 V I/O 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC- 144-3 ADV212BBCZRL-1501 −40°C to +85°C 150 MHz 1.5 V Internal, 2.5 V or 3.3 V I/O 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC- 144-3 1 Z = Pb-free part.

Rev. 0 | Page 43 of 44 NOTES

Rev. 0 | Page 44 of 44 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the prop erty of their respective owners. D06389-0-10/06(0)